IN90LS2323D_技术文档

IN90S2323D, IN90LS2323D

8-BIT MICROCONTROLLER WITH 2K BYTES BUILD-IN

PROGRAMMABLE FLASH

Description

The IN90S2323D and IN90LS2323D is a low-power

CMOS 8-bit microcontrollers based on the AVR

enhanced RISC architecture. By executing powerful

instructions in a single clock cycle, the IN90S2323D and

IN90LS2323D achieves throughputs approaching 1 MIPS

per MHz allowing the system designer to optimize power

consumption versus processing speed.

8

1

The AVR core combines a rich instruction set with

32 general purpose working registers. All the 32 registers

are directly connected to the Arithmetic Logic Unit (ALU),

allowing two independent registers to be accessed in one

single instruction executed in one clock cycle. The

resulting architecture is more code efficient while

achieving throughputs up to ten times faster than

conventional CISC microcontrollers.

Features

• Utilizes the AVR ^®Enhanced RISC Architecture

• AVR - High Performance and Low Power RISC Architecture

• 118 Powerful Instructions - Most Single Clock Cycle Execution

• 2K bytes of In-System Programmable ISP Flash

– SPI Serial Interface for In-System Programming

– Endurance: 1,000 Write/Erase Cycles

• 128 bytes EEPROM

– Endurance: 100,000 Write/Erase Cycles

• 128 bytes Internal RAM

• 32 x 8 General Purpose Working Registers

– 3 Programmable I/O Lines

• V_CC: 4.0 - 6.0V IN90S2323D

• V_CC: 2.7 - 6.0V IN90LS2323D

• Power-On Reset Circuit

• Speed Grades: 0 - 10 MHz IN90S2323D

• Speed Grades: 0 - 4 MHz IN90LS2323D

• Up to 10 MIPS Throughput at 10 MHz

• One 8-Bit Timer/Counter with Separate Prescaler

• External and Internal Interrupt Sources

• Programmable Watchdog Timer with On-Chip Oscillator

• Low Power Idle and Power Down Modes

• Programming Lock for Flash Program and EEPROM Data Security

• Selectable On-Chip RC Oscillator

•

8-Pin Device

1

IN90S2323D, IN90LS2323D

Block Diagram

2

IN90S2323D, IN90LS2323D

Pin Descriptions

VCC

Supply voltage pin.

GND

Ground pin.

Port B (PB2..PB0)

Port B is a 3-bit bi-directional I/O port. Port pins can provide

internal pull-up resistors (selected for each bit).

RESET

Reset input. A low on this pin for two machine cycles while the

oscillator is running resets the device.

XTAL1

Input to the inverting oscillator amplifier and input to the internal

clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier.

Clock Sources

The IN90S2313D and IN90LS2313D contains an inverting amplifier which can be configured for use as

an on-chip oscillator. XTAL1 and XTAL2 are input and output respectively. Either a quartz crystal or a

ceramic resonator may be used.

External Clock Drive Configuration

Oscillator Connection

Architectural Overview

The fast-access register file concept contains 32 x 8-bit general purpose working registers with a single

clock cycle access time. This means that during one single clock cycle, one ALU (Arithmetic Logic Unit)

operation is executed. Two operands are output from the register file, the operation is executed, and the

result is stored back in the register file -in one clock cycle.

Six of the 32 registers can be used as three 16-bits indirect address register pointers for Data Space

addressing-enabling efficient address calculations. One of the three address pointers is also used as the

address pointer for the constant table look up function. These added function registers are the 16-bit X-

3

IN90S2323D, IN90LS2323D

register, Y-register and Z-register. The ALU supports arithmetic and logic functions between registers or

between a constant and a register. Single register operations are also executed in the ALU. In addition to

the register operation, the conventional memory addressing modes can be used on the register file as

well. This is enabled by the fact that the register file is assigned the 32 lowermost Data Space addresses

($00 -$1F), allowing them to be accessed as though they were ordinary memory locations.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers,

Timer/Counters, A/D-converters, and other I/O functions. The I/O memory can be accessed directly, or as

the Data Space locations following those of the register file, $20 - $5F.

The AVR has Harvard architecture - with separate memories and buses for program and data. The

program memory is accessed with a two stage pipeline. While one instruction is being executed, the next

instruction is pre-fetched from the program memory. This concept enables instructions to be executed in

every clock cycle. The program memory is in-system downloadable Flash memory.

With the relative jump and call instructions, the whole 1K address space is directly accessed. Most AVR

instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit

instruction.

During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack.

The stack is effectively allocated in the general data SRAM, and consequently the stack size is only

limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the

reset routine (before subroutines or interrupts are executed). The 8-bit stack pointer SP is read/write

accessible in the I/O space.

The 128 bytes data SRAM + register file and I/O registers can be easily accessed through the five

different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

AVR Architecture

4

IN90S2323D, IN90LS2323D

Memory Maps

5

IN90S2323D, IN90LS2323D

REGISTER SUMMARY

Address

$3F ($5F)

$3E ($5E)

$3D ($5D)

$3C ($5C)

$3B ($5B)

$3A ($5A)

$39 ($59)

$38 ($58)

$37 ($57)

$36 ($56)

$35 ($55)

$34 ($54)

$33 ($53)

$32 ($52)

$31 ($51)

$30 ($50)

$2F ($4F)

$2E ($4E)

$2D ($4D)

$2C ($4C)

$2B ($4B)

$2A ($4A)

$29 ($49)

$28 ($48)

$27 ($47)

$26 ($46)

$25 ($45)

$24 ($44)

$23 ($43)

$22 ($42)

$21 ($41)

$20 ($40)

$1F ($3F)

$1E ($3E)

$1D ($3D)

Name

SREG

Bit 7 Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

I

T

H

S

V

N

Z

C

page 13

Reserved

SPL

SP7

SP6

SP5

-

SP4

-

SP3

-

SP2

-

SP1

-

SP0

-

page 13

Reserved

GIMSK

-

INT0

page 17

page 15

page 16

GIFR

INTF0

TIMSK

-

TOIE0

TOV0

-

TIFR

Reserved

MCUCR

MCUSR

TCCR0

-

SE

SM

-

ISC01

EXTRF

CS01

ISC00

PORF

CS00

page 16

page 14

page 20

-

CS02

TCNT0

Timer/Counter0 (8 Bit)

Reserved

WDTCR

Reserved

EEAR

-

WDTO

WDE

WDP2

EEMW

WDP1

EEWE

WDP0

EERE

page 21

EEPROM Address Register

page 22

EEDR

EEPROM Data

register

$1C ($3C)

$1B ($3B)

$1A ($3A)

$19 ($39)

$18 ($38)

$17 ($37)

$16 ($36)

$15 ($35)

$14 ($34)

$13 ($33)

$12 ($32)

$11 ($31)

$10 ($30)

$0F ($2F)

$0E ($2E)

$0D ($2D)

$0C ($2C)

$0B ($2B)

$0A ($2A)

$09 ($29)

$08 ($28)

…

EECR

-

page 22

Reserved

PORTB

-

PORTB PORTB PORTB

PORTB

DDB1

PORTB

DDB0

page 23

DDRB

DDB4

PINB4

DDB3

PINB3

DDB2

PINB2

PINB

PINB1

PINB0

Reserved

$00 ($20)

6

IN90S2323D, IN90LS2323D

Instruction Set Summary

ARITHMETIC AND LOGIC INSTRUCTIONS

Mnemonics Operands Description

Operation

Flags

#Clock

ADD

ADC

ADIW

SUB

SUBI

SBIW

SBC

SBCI

AND

ANDI

OR

Rd, Rr

Rdl,K

Rd, Rr

Rd, K

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd

Add two Registers

Rd ← Rd + Rr

Rd ← Rd + Rr + C

Rdh:Rdl ← Rdh:Rdl + K

Rd ← Rd - Rr

Z,C,N,V,H

Z,C,N,V,S

Z,C,N,V,H

Z,C,N,V,S

Z,C,N,V,H

Z,N,V

1

2

1

2

1

Add with Carry two Registers

Add Immediate to Word

Subtract two Registers

Subtract Constant from Register

Subtract Immediate from Word

Subtract with Carry two Registers

Subtract with Carry Constant from Reg.

Logical AND Registers

Logical AND Register and Constant

Logical OR Registers

Rd ← Rd - K

Rdh:Rdl ← Rdh:Rdl - K

Rd ← Rd - Rr – C

Rd ← Rd - K - C

Rd ← Rd • Rr

Rd ← Rd • K

Z,N,V

Rd ← Rd v Rr

Rd ← Rd v K

Z,N,V

ORI

Logical OR Register and Constant

Exclusive OR Registers

One’s Complement

Z,N,V

EOR

COM

NEG

SBR

CBR

INC

Rd ← Rd ⊕ Rr

Rd ← $FF - Rd

Rd ← $00 - Rd

Rd ← Rd v K

Z,N,V

Z,C,N,V

Z,C,N,V,H

Z,N,V

Rd

Two’s Complement

Rd,K

Rd

Set Bit(s) in Register

Clear Bit(s) in Register

Increment

Rd ← Rd • ($FF - K)

Rd ← Rd + 1

Z,N,V

DEC

TST

Rd

Decrement

Rd ← Rd - 1

Z,N,V

Rd

Test for Zero or Minus

Clear Register

Rd ← Rd • Rd

Rd ← Rd ⊕ Rd

Rd ← $FF

Z,N,V

CLR

SER

Rd

Z,N,V

Rd

Set Register

None

BRANCH INSTRUCTIONS

RJMP

IJMP

k

Relative Jump

PC ← PC + k + 1

None

I

2

Indirect Jump to (Z)

PC ← Z

2

RCALL

ICALL

RET

Relative Subroutine Call

Indirect Call to (Z)

PC ← PC + k + 1

3

PC ← Z

3

Subroutine Return

PC ← STACK

4

RETI

Interrupt Return

PC ← STACK

4

CPSE

CP

Rd,Rr

Compare, Skip if Equal

Compare

if (Rd = Rr) PC ← PC + 2 or 3

Rd - Rr

None

Z, N,V,C,H

None

1 / 2

1

Rd,Rr

CPC

Rd,Rr

Compare with Carry

Rd - Rr - C

1

CPI

Rd,K

Compare Register with Immediate

Skip if Bit in Register Cleared

Skip if Bit in Register is Set

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register is Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Rd - K

1

SBRC

SBRS

SBIC

SBIS

Rr, b

if (Rr(b)=0) PC ← PC + 2 or 3

if (Rr(b)=1) PC ← PC + 2 or 3

if (P(b)=0) PC ← PC + 2 or 3

if (R(b)=1) PC ← PC + 2 or 3

if (SREG(s) = 1) then PC←PC + k + 1

if (SREG(s) = 0) then PC←PC + k + 1

if (Z = 1) then PC ← PC + k + 1

if (Z = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (C = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (N = 1) then PC ← PC + k + 1

if (N = 0) then PC ← PC + k + 1

if (N ⊕ V= 0) then PC ← PC + k + 1

if (N ⊕ V= 1) then PC ← PC + k + 1

if (H = 1) then PC ← PC + k + 1

if (H = 0) then PC ← PC + k + 1

if (T = 1) then PC ← PC + k + 1

if (T = 0) then PC ← PC + k + 1

if (V = 1) then PC ← PC + k + 1

if (V = 0) then PC ← PC + k + 1

if ( I = 1) then PC ← PC + k + 1

if ( I = 0) then PC ← PC + k + 1

1 / 2

Rr, b

P, b

s, k

k

BRBS

BRBC

BREQ

BRNE

BRCS

BRCC

BRSH

BRLO

BRMI

BRPL

BRGE

BRLT

BRHS

BRHC

BRTS

BRTC

BRVS

BRVC

BRIE

BRID

k

Branch if Not Equal

k

Branch if Carry Set

k

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

k

Branch if Minus

k

Branch if Plus

k

Branch if Greater or Equal, Signed

Branch if Less Than Zero, Signed

Branch if Half Carry Flag Set

Branch if Half Carry Flag Cleared

Branch if T Flag Set

k

Branch if T Flag Cleared

Branch if Overflow Flag is Set

Branch if Overflow Flag is Cleared

Branch if Interrupt Enabled

Branch if Interrupt Disabled

k

7

IN90S2323D, IN90LS2323D

Instruction Set Summary (Continued)

Mnemonics Operands Description

DATA TRANSFER INSTRUCTIONS

Operation

Flags

#Clock

MOV

LDI

LD

Rd, Rr

Rd, K

Move Between Registers

Load Immediate

Rd ← Rr

None

1

2

3

1

2

Rd ← K

None

Rd, X

Load Indirect

Rd ← (X)

LD

Rd, X+

Rd, - X

Rd, Y

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect

Rd ← (X), X ← X + 1

X ← X 1, Rd ← (X)

Rd ← (Y)

LD

Rd, Y+

Rd, - Y

Rd,Y+q

Rd, Z

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Indirect

Rd ← (Y), Y ← Y + 1

Y ← Y - 1, Rd ← (Y)

Rd ← (Y + q)

Rd ← (Z)

LD

LDD

LD

Rd, Z+

Rd, -Z

Rd, Z+q

Rd, k

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Direct from SRAM

Store Indirect

Rd ← (Z), Z ← Z+1

Z ← Z - 1, Rd ← (Z)

Rd ← (Z + q)

Rd ← (k)

LD

LDD

LDS

ST

X, Rr

(X) ← Rr

ST

X+, Rr

- X, Rr

Y, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect

(X) ← Rr, X ← X + 1

X ← X - 1, (X) ← Rr

(Y) ← Rr

ST

Y+, Rr

- Y, Rr

Y+q,Rr

Z, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Indirect

(Y) ← Rr, Y ← Y + 1

Y ← Y - 1, (Y) ← Rr

(Y + q) ← Rr

(Z) ← Rr

ST

STD

ST

Z+, Rr

-Z, Rr

Z+q,Rr

k, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Direct to SRAM

Load Program Memory

In Port

(Z) ← Rr, Z ← Z + 1

Z ← Z - 1, (Z) ← Rr

(Z + q) ← Rr

(k) ← Rr

ST

STD

STS

LPM

IN

R0 ← (Z)

Rd, P

P, Rr

Rr

Rd ← P

OUT

PUSH

POP

Out Port

P ← Rr

Push Register on Stack

Pop Register from Stack

STACK ← Rr

Rd ← STACK

Rd

BIT AND BIT-TEST INSTRUCTIONS

SBI

CBI

P,b

Rd

s

Set Bit in I/O Register

Clear Bit in I/O Register

Logical Shift Left

I/O(P,b) ← 1

None

2

1

3

1

I/O(P,b) ← 0

None

LSL

Rd(n+1) ← Rd(n), Rd(0) ← 0

Z,C,N,V

LSR

ROL

ROR

ASR

SWAP

BSET

BCLR

BST

BLD

SEC

CLC

SEN

CLN

SEZ

CLZ

Logical Shift Right

Rotate Left Through Carry

Rotate Right Through Carry

Arithmetic Shift Right

Swap Nibbles

Rd(n) ← Rd(n+1), Rd(7) ← 0

Z,C,N,V

Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)

Z,C,N,V

Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)

Z,C,N,V

Rd(n) ← Rd(n+1), n=0..6

Z,C,N,V

Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)

None

Flag Set

SREG(s) ← 1

SREG(s) ← 0

T ← Rr(b)

Rd(b) ← T

C ← 1

SREG(s)

s

Flag Clear

SREG(s)

Rr, b

Rd, b

Bit Store from Register to T

Bit load from T to Register

Set Carry

T

None

C

Clear Carry

C ← 0

C

Set Negative Flag

N ← 1

N

Clear Negative Flag

Set Zero Flag

N ← 0

N

Z ← 1

Z

Clear Zero Flag

Z ← 0

Z

SEI

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

Clear Signed Test Flag

Set Twos Complement Overflow

Clear Twos Complement Overflow

Set T in SREG

I ← 1

I

CLI

I ← 0

I

S

SES

CLS

SEV

CLV

SET

CLT

S ← 1

S ← 0

S

V ← 1

V

V ← 0

V

T ← 1

T

Clear T in SREG

T ← 0

T

SEH

CLH

NOP

SLEEP

WDR

Set Half Carry Flag in SREG

Clear Half Carry Flag in SREG

No Operation

H ← 1

H

H ← 0

H

None

Sleep

(see specific descr. for Sleep

Watchdog Reset

(see specific descr. for WDR/timer)

8

IN90S2323D, IN90LS2323D

MS-012AA Package dimensions

D

8

1

5

4

H

E1

hx45

c

A1

C

Mounting

plate

α

e

L

b

M

0,25 (0,010)

C

D

E1

H

b

e

A

A1

c

L

h

α

mm

min

max

4.80

5.00

3.80

4.00

5.80

6.20

0.33

0.51

1.35

1.75

0.10

0.25

0.19

0.25

0.41

1.27

0.25

0.50

0°

8°

1.27

inches

min

max

0.1890 0.1497 0.2284 0.013

0.1968 0.1574 0.2440 0.020 0.100

0.0532 0.0040 0.0075 0.016 0.0099

0.0688 0.0090 0.0098 0.050 0.0196

0°

8°

9


型号：	IN90LS2323D
厂家：	INTEGRAL CORP.
描述：	8-BIT MICROCONTROLLER WITH 2K BYTES BUILD-IN PROGRAMMABLE FLASH 带2K字节的8位单片机内置的可编程闪存闪存
文件：	总9页 (文件大小：189K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IN90LS2323D [INTEGRAL]

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