IN90S2313DW_技术文档

IN90S2313DW,

8-BIT MICROCONTROLLER WITH 2K BYTES BUILD-IN

PROGRAMMABLE FLASH

Description

The IN90S2313 is a low-power CMOS 8-bit

microcontroller based on the AVR enhanced RISC

architecture. By executing powerful instructions in a single

clock cycle, the IN90S2313 achieves throughputs

approaching 1 MIPS per MHz allowing the system

designer to optimize power consumption versus

processing speed. The AVR core combines a rich

instruction set with 32 general purpose working registers.

All the 32 registers are directly connected to the

Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction

executed in one clock cycle. The resulting architecture is

more code efficient while achieving throughputs up to ten

times faster than conventional CISC microcontrollers.

The IN90S2313 provides the following features: 2K bytes of In-System Programmable

Flash, 128 bytes EEPROM, 128 bytes SRAM, 15 general purpose I/O lines, 32 general

purpose working registers, flexible timer/counters with compare modes, internal and

external interrupts, a programmable serial UART, programmable Watchdog Timer with

internal oscillator, an SPI serial port for Flash Memory downloading and two software

selectable power saving modes. The Idle Mode stops the CPU while allowing the SRAM,

timer/counters, SPI port and interrupt system to continue functioning. The power down

mode saves the register contents but freezes the oscillator, disabling all other chip

functions until the next interrupt or hardware reset. The device is manufactured using

Atmel’s high density non-volatile memory technology. The on-chip In-System

Programmable Flash allows the program memory to be reprogrammed in-system

through an SPI serial interface or by a conventional nonvolatile memory programmer. By

combining an enhanced RISC 8-bit CPU with In-System Programmable Flash on a

monolithic chip, the Atmel IN90S2313 is a powerful microcontroller that provides a highly

flexible and cost effective solution to many embedded control applications.

The IN90S2313 AVR is supported with a full suite of program and system development

tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit

emulators, and evaluation kits.

1

IN90S2313DW,

Features

• AVR - High Performance and Low Power RISC Architecture

• 118 Powerful Instructions - Most Single Clock Cycle Execution

• 2K bytes of In-System Reprogrammable Flash

– SPI Serial Interface for Program Downloading

– Endurance: 1,000 Write/Erase Cycles

• 128 bytes EEPROM

– Endurance: 100,000 Write/Erase Cycles

• 128 bytes Internal RAM

• 32 x 8 General Purpose Working Registers

• 15 Programmable I/O Lines

•

V_CC: 2.7 - 6.0V

• Fully Static Operation

– 0 - 10 MHz, 4.0 - 6.0V

– 0 - 4 MHz, 2.7 - 6.0V

• Up to 10 MIPS Throughput at 10 MHz

• One 8-Bit Timer/Counter with Separate Prescaler

• One 16-Bit Timer/Counter with Separate Prescaler and

Compare and Capture Modes

• Full Duplex UART

• Selectable 8, 9 or 10 bit PWM

• External and Internal Interrupt Sources

• Programmable Watchdog Timer with On-Chip Oscillator

• On-Chip Analog Comparator

• Low Power Idle and Power Down Modes

• Programming Lock for Software Security

•

20-Pin Device

2

IN90S2313DW,

Block Diagram

3

IN90S2313DW,

Pin Descriptions

VCC

Supply voltage pin.

GND

Ground pin.

Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port. Port pins can provide

internal pull-up resistors (selected for each bit). PB0 and PB1

also serve as the positive input (AIN0) and the negative input

(AIN1), respectively, of the on-chip analog comparator. The Port

B output buffers can sink 20mA and can drive LED displays directly. When pins PB0 to PB7 are used as

inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated.

Port B also serves the functions of various special features of the IN90S2313 as listed on page 38.

Port D (PD6..PD0)

Port D has seven bi-directional I/O pins with internal pull-up resistors, PD6..PD0. The Port D output

buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source current if the pull-

up resistors are activated.

Port D also serves the functions of various special features of the IN90S2313 as listed on page 43.

RESET

Reset input. A low on this pin for two machine cycles while the oscillator is running resets the device.

XTAL1

Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier

Crystal Oscillator

XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for

use as an on-chip oscillator. Either a quartz crystal or a ceramic resonator may be used. To drive the

device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven.

Oscillator Connections

External Clock Drive Configuration

4

IN90S2313DW,

Architectural Overview

The fast-access register file concept contains 32 x 8-bit general purpose working registers with a single

clock cycle access time. This means that during one single clock cycle, one ALU (Arithmetic Logic Unit)

operation is executed. Two operands are output from the register file, the operation is executed, and the

result is stored back in the register file -in one clock cycle.

Six of the 32 registers can be used as three 16-bits indirect address register pointers for Data Space

addressing -enabling efficient address calculations. One of the three address pointers is also used as the

address pointer for the constant table look up function. These added function registers are the 16-bits X-

register, Y-register and Z-register. The ALU supports arithmetic and logic functions between registers or

between a constant and a register. Single register operations are also executed in the ALU.

In addition to the register operation, the conventional memory addressing modes can be used on the

register file as well. This is enabled by the fact that the register file is assigned the 32 lowermost Data

Space addresses ($00 -$1F), allowing them to be accessed as though they were ordinary memory

locations.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers,

Timer/Counters, A/D-converters, and other I/O functions. The I/O memory can be accessed directly, or as

the Data Space locations following those of the register file, $20 - $5F.

The AVR has Harvard architecture - with separate memories and buses for program and data. The

program memory is accessed with a two stage pipeline. While one instruction is being executed, the next

instruction is pre-fetched from the program memory. This concept enables instructions to be executed in

every clock cycle. The program memory is In-system Programmable Flash memory.

With the relative jump and call instructions, the whole 1K address space is directly accessed. Most AVR

instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit

instruction.

During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack.

The stack is effectively allocated in the general data SRAM, and consequently the stack size is only

limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the

reset routine (before subroutines or interrupts are executed). The 8-bit stack pointer SP is read/write

accessible in the I/O space.

The 128 bytes data SRAM + register file and I/O registers can be easily accessed through the five

different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

5

IN90S2313DW,

AVR Enhanced RISC Architecture

Memory Maps

6

IN90S2313DW,

REGISTER SUMMARY

Address

$3F ($5F)

$3E ($5E)

$3D ($5D)

$3C ($5C)

$3B ($5B)

$3A ($5A)

$39 ($59)

$38 ($58)

$37 ($57)

$36 ($56)

$35 ($55)

$34 ($54)

$33 ($53)

$32 ($52)

$31 ($51)

$30 ($50)

$2F ($4F)

$2E ($4E)

$2D ($4D)

$2C ($4C)

$2B ($4B)

$2A ($4A)

$29 ($49)

$28 ($48)

$27 ($47)

$26 ($46)

$25 ($45)

$24 ($44)

$23 ($43)

$22 ($42)

$21 ($41)

$20 ($40)

$1F ($3F)

$1E ($3E)

$1D ($3D)

$1C ($3C)

$1B ($3B)

$1A ($3A)

$19 ($39)

$18 ($38)

$17 ($37)

$16 ($36)

$15 ($35)

$14 ($34)

$13 ($33)

$12 ($32)

$11 ($31)

$10 ($30)

Name

Bit 7

Bit 6

T

Bit 5

Bit 4

S

Bit 3

V

Bit 2

Bit 1

Bit 0

Page

SREG

I

H

N

Z

C

17

Reserved

SPL

Reserved

GIMSK

GIFR

SP7

SP6

SP5

-

SP4

-

SP3

-

SP2

-

SP1

-

SP0

-

18

INT1

INTF1

TOIE1

TOV1

INT0

INTF0

OCIE1A

OCF1A

23

24

TIMSK

TIFR

-

TICIE1

ICF1

-

TOIE0

TOV0

-

Reserved

MCUCR

Reserved

TCCR0

TCNT0

Reserved

TCCR1A

TCCR1B

-

SE

-

SM

-

ISC11

-

ISC10

CS02

ISC01

CS01

ISC00

CS00

25

28

29

Timer/Counter0 (8 Bit)

COM1A1

ICNC1

COM1A0

ICES1

-

.

-

PWM11

CS11

PWM10

CS10

30

31

32

CTC1

CS12

TCNT1H Timer/Counter1 - Counter Register High Byte

TCNT1L Timer/Counter1 - Counter Register Low Byte

OCR1AH Timer/Counter1 - Compare Register High Byte

OCR1AL Timer/Counter1 - Compare Register Low Byte

Reserved

ICR1H

ICR1L

Reserved

WDTCR

Reserved

EEAR

Timer/Counter1 - Input Capture Register High Byte

Timer/Counter1 - Input Capture Register Low Byte

33

-

WDTOE

WDE

WDP2

WDP1

EEWE

WDP0

EERE

35

-

EEPROM Address Register

36

37

EEDR

EECR

EEPROM Data register

-

EEMWE

Reserved

PORTB

DDRB

PORTB7

DDB7

PINB7

PORTB6

DDB6

PINB6

PORTB5

DDB5

PINB5

PORTB4

DDB4

PINB4

PORTB3

DDB3

PINB3

PORTB2

DDB2

PINB2

PORTB1

DDB1

PINB1

PORTB0

DDB0

PINB0

46

PINB

Reserved

PORTD

DDRD

-

PORTD6

DDD6

PIND6

PORTD5

DDD5

PIND5

PORTD4

DDD4

PIND4

PORTD3

DDD3

PIND3

PORTD2

DDD2

PIND2

PORTD1

DDD1

PIND1

PORTD0

DDD0

PIND0

51

PIND

7

IN90S2313DW,

REGISTER SUMMARY (Continued)

Address

$0F ($2F)

$0E ($2E)

$0D ($2D)

$0C ($2C)

$0B ($2B)

$0A ($2A)

$09 ($29)

$08 ($28)

…

Name

Reserved

UDR

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

UART I/O Data Register

40

41

43

44

USR

UCR

UBRR

ACSR

Reserved

RXC

TXC

UDRE

UDRIE

FE

RXEN

OR

TXEN

-

RXCIE

TXCIE

CHR9

RXB8

TXB8

UART Baud Rate Register

ACD

-

ACO

ACI

ACIE

ACIC

ACIS1

ACIS0

$00 ($20)

Instruction Set Summary

Mnemonics Operands Description

ARITHMETIC AND LOGIC INSTRUCTIONS

Operation

Flags

#Clocks

Rd ← Rd + Rr

Rd ← Rd + Rr + C

Rdh:Rdl ← Rdh:Rdl + K

Rd ← Rd - Rr

ADD

ADC

ADIW

SUB

SUBI

SBIW

SBC

SBCI

AND

ANDI

OR

Rd, Rr

Rdl,K

Rd, Rr

Rd, K

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd

Add two Registers

Z,C,N,V,H

Z,C,N,V,S

Z,C,N,V,H

Z,C,N,V,S

Z,C,N,V,H

Z,N,V

Z,C,N,V

Z,C,N,V,H

Z,N,V

None

1

2

1

2

1

Add with Carry two Registers

Add Immediate to Word

Subtract two Registers

Subtract Constant from Register

Subtract Immediate from Word

Subtract with Carry two Registers

Subtract with Carry Constant from Reg.

Logical AND Registers

Logical AND Register and Constant

Logical OR Registers

Logical OR Register and Constant

Exclusive OR Registers

One’s Complement

Two’s Complement

Set Bit(s) in Register

Rd ← Rd - K

Rdh:Rdl ← Rdh:Rdl - K

Rd ← Rd - Rr - C

Rd ← Rd - K - C

Rd ← Rd • Rr

Rd ← Rd • K

Rd ← Rd v Rr

Rd ← Rd v K

ORI

Rd ← Rd ⊕ Rr

Rd ← $FF - Rd

Rd ← $00 - Rd

Rd ← Rd v K

EOR

COM

NEG

SBR

CBR

INC

DEC

TST

CLR

SER

Rd

Rd,K

Rd

Rd ← Rd • ($FF - K)

Rd ← Rd + 1

Clear Bit(s) in Register

Increment

Decrement

Test for Zero or Minus

Clear Register

Set Register

Rd ← Rd - 1

Rd ← Rd • Rd

Rd ← Rd ⊕ Rd

Rd ← $FF

Rd

BRANCH INSTRUCTIONS

PC ← PC + k + 1

PC ← Z

RJMP

IJMP

RCALL

ICALL

RET

RETI

CPSE

CP

CPC

CPI

SBRC

SBRS

SBIC

k

Relative Jump

Indirect Jump to (Z)

Relative Subroutine Call

Indirect Call to (Z)

Subroutine Return

Interrupt Return

Compare, Skip if Equal

Compare

None

2

3

4

1 / 2

1

PC ← PC + k + 1

PC ← Z

k

PC ← STACK

I

if (Rd = Rr) PC ← PC + 2 or 3

Rd,Rr

Rd,K

Rr, b

P, b

None

Rd - Rr

Rd - Rr - C

Rd K

Z, N,V,C,H

None

Compare with Carry

Compare Register with Immediate

Skip if Bit in Register Cleared

Skip if Bit in Register is Set

Skip if Bit in I/O Register Cleared

if (Rr(b)=0) PC ← PC + 2 or 3

if (Rr(b)=1) PC ← PC + 2 or 3

if (P(b)=0) PC ← PC + 2 or 3

1 / 2

8

IN90S2313DW,

Instruction Set Summary (Continued)

Mnemonics Operands Description

Operation

Flags

None

#Clocks

1 / 2

if (R(b)=1) PC ← PC + 2 or 3

SBIS

P, b

s, k

k

Skip if Bit in I/O Register is Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Branch if Not Equal

Branch if Carry Set

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

Branch if Minus

Branch if Plus

Branch if Greater or Equal, Signed

Branch if Less Than Zero, Signed

Branch if Half Carry Flag Set

Branch if Half Carry Flag Cleared

Branch if T Flag Set

Branch if T Flag Cleared

Branch if Overflow Flag is Set

Branch if Overflow Flag is Cleared

Branch if Interrupt Enabled

Branch if Interrupt Disabled

if (SREG(s) = 1) then PC←PC + k + 1

if (SREG(s) = 0) then PC←PC + k + 1

if (Z = 1) then PC ← PC + k + 1

if (Z = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (C = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (N = 1) then PC ← PC + k + 1

if (N = 0) then PC ← PC + k + 1

if (N ⊕ V= 0) then PC ← PC + k + 1

if (N ⊕ V= 1) then PC ← PC + k + 1

if (H = 1) then PC ← PC + k + 1

if (H = 0) then PC ← PC + k + 1

if (T = 1) then PC ← PC + k + 1

if (T = 0) then PC ← PC + k + 1

if (V = 1) then PC ← PC + k + 1

if (V = 0) then PC ← PC + k + 1

if (I = 1) then PC ← PC + k + 1

if (I = 0) then PC ← PC + k + 1

BRBS

BRBC

BREQ

BRNE

BRCS

BRCC

BRSH

BRLO

BRMI

BRPL

BRGE

BRLT

BRHS

BRHC

BRTS

BRTC

BRVS

BRVC

BRIE

k

BRID

k

DATA TRANSFER INSTRUCTIONS

MOV

LDI

LD

LDD

LD

LDD

LDS

ST

STD

ST

STD

STS

LPM

Rd, Rr

Rd, K

Rd, X

Rd, X+

Rd, - X

Rd, Y

Rd, Y+

Rd, - Y

Rd,Y+q

Rd, Z

Move Between Registers

Load Immediate

Load Indirect

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Indirect

Rd ← Rr

Rd ← K

Rd ← (X)

None

1

2

3

Rd ← (X), X ← X + 1

X ← X 1, Rd ← (X)

Rd ← (Y)

Rd ← (Y), Y ← Y + 1

Y ← Y 1, Rd ← (Y)

Rd ← (Y + q)

Rd ← (Z)

Rd, Z+

Rd, -Z

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Rd ← (Z), Z ← Z+1

Z ← Z - 1, Rd ← (Z)

Rd ← (Z + q)

Rd, Z+q Load Indirect with Displacement

Rd, k

X, Rr

X+, Rr

- X, Rr

Y, Rr

Y+, Rr

- Y, Rr

Y+q,Rr

Z, Rr

Load Direct from SRAM

Store Indirect

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Indirect

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Direct to SRAM

Rd ← (k)

(X) ← Rr

(X) ← Rr, X ← X + 1

X ← X - 1, (X) ← Rr

(Y) ← Rr

(Y) ← Rr, Y ← Y + 1

Y ← Y - 1, (Y) ← Rr

(Y + q) ← Rr

(Z) ← Rr

Z+, Rr

-Z, Rr

Z+q,Rr

k, Rr

(Z) ← Rr, Z ← Z + 1

Z ← Z - 1, (Z) ← Rr

(Z + q) ← Rr

(k) ← Rr

R0 ← (Z)

Load Program Memory

9

IN90S2313DW,

Instruction Set Summary (Continued)

Mnemonics Operands Description

Operation

Rd ← P

P ← Rr

STACK ← Rr

Rd ← STACK

Flags

None

#Clocks

IN

Rd, P

P, Rr

Rr

In Port

Out Port

Push Register on Stack

Pop Register from Stack

1

2

OUT

PUSH

POP

Rd

BIT AND BIT-TEST INSTRUCTIONS

SBI

P,b

Rd

Set Bit in I/O Register

Clear Bit in I/O Register

Logical Shift Left

Logical Shift Right

Rotate Left Through Carry

I/O(P,b) ← 1

I/O(P,b) ← 0

Rd(n+1) ← Rd(n), Rd(0) ← 0

Rd(n) ← Rd(n+1), Rd(7) ← 0

None

Z,C,N,V

2

1

CBI

LSL

LSR

ROL

Rd(0)←C,Rd(n+1)←

Rd(n),C←Rd(7)

ROR

Rd

Rotate Right Through Carry

Rd(7)←C,Rd(n)←

Rd(n+1),C←Rd(0)

Z,C,N,V

1

ASR

SWAP

Rd

Arithmetic Shift Right

Swap Nibbles

Rd(n) ← Rd(n+1), n=0..6

Z,C,N,V

None

1

Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3.

.0)

BSET

BCLR

BST

BLD

SEC

CLC

SEN

CLN

SEZ

CLZ

SEI

s

Flag Set

Flag Clear

Bit Store from Register to T

Bit load from T to Register

Set Carry

SREG(s) ← 1

SREG(s) ← 0

T ← Rr(b)

Rd(b) ← T

C ← 1

SREG(s)

T

None

1

3

Rr, b

Rd, b

C

N

Z

I

S

V

T

H

None

Clear Carry

C ← 0

N ← 1

N ← 0

Z ← 1

Z ← 0

I ← 1

I ← 0

S ← 1

S ← 0

V ← 1

V ← 0

T ← 1

T ← 0

H ← 1

H ← 0

Set Negative Flag

Clear Negative Flag

Set Zero Flag

Clear Zero Flag

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

Clear Signed Test Flag

Set Twos Complement Overflow

Clear Twos Complement Overflow

Set T in SREG

CLI

SES

CLS

SEV

CLV

SET

CLT

SEH

CLH

NOP

SLEEP

Clear T in SREG

Set Half Carry Flag in SREG

Clear Half Carry Flag in SREG

No Operation

Sleep

(see specific descr. for Sleep

function)

WDR

Watchdog Reset

(see specific descr. for

None

1

WDR/timer)

10

IN90S2313DW,

MS-013AC Package dimensions

D

20

11

e₁

H

E

1

10

T

e

h x 45°

C

A

A₁

-T-

α

B

L

0.25 (0.010) M

C

M

A

A₁

C

D

E

e

e₁

H

h

L

B

α

°

mm

min 2.35 0.10 0.33

max 2.65 0.30 0.51

0.23

0.32

12.60

13.00

7.40

7.60

1.27

9.53 10.00 0.25 0.40

10.65 0.75 1.27

0

8

(nom) (nom)

11


型号：	IN90S2313DW
厂家：	INTEGRAL CORP.
描述：	8-BIT MICROCONTROLLER WITH 2K BYTES BUILD-IN PROGRAMMABLE FLASH 带2K字节的8位单片机内置的可编程闪存闪存
文件：	总11页 (文件大小：212K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IN90S2313DW [INTEGRAL]

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