XC836T [INFINEON]
8-Bit Single-Chip Microcontroller; 8位单芯片微控制器
| 型号： | XC836T |
| 厂家： | 
Infineon |
| 描述： | 8-Bit Single-Chip Microcontroller |
| 文件： | 总56页 (文件大小：1355K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
XC835/836
8-Bit Single-Chip Microcontroller
Data Sheet
V1.2 2011-03
Microcontrollers
Edition 2011-03
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2011 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
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be endangered.
XC835/836
8-Bit Single-Chip Microcontroller
Data Sheet
V1.2 2011-03
Microcontrollers
XC835/836
XC835/836 Data Sheet
Revision History: V1.2 2011-03
Previous Versions: V 1.1
Page
Subjects (major changes since last revision)
Page 3,
Page 46,
Page 49
TSSOP-28-9 package for Automotive has been updated to TSSOP-28-12.
We Listen to Your Comments
Is there any information in this document that you feel is wrong, unclear or missing?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
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Data Sheet
V1.2, 2011-03
XC835/836
Table of Contents
Table of Contents
1
Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2
General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
JTAG ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Chip Identification Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.1
2.2
2.3
2.4
2.5
2.6
2.7
3
Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Absolute Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Operating Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Input/Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Supply Threshold Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
ADC Conversion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Out of Range Comparator Characteristics . . . . . . . . . . . . . . . . . . . . . 32
Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Output Rise/Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Oscillator Timing and Wake-up Timing . . . . . . . . . . . . . . . . . . . . . . . . . 40
On-Chip Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
SSC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
SSC Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
SSC Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
SPD Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.1
3.1.1
3.1.2
3.1.3
3.2
3.2.1
3.2.2
3.2.3
3.2.3.1
3.2.3.2
3.2.4
3.2.5
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.3.5.1
3.3.5.2
3.3.6
4
Package and Quality Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Quality Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.1
4.2
4.3
Data Sheet
1
V1.2, 2011-03
XC835/836
Summary of Features
1
Summary of Features
The XC835/836 has the following features:
• High-performance XC800 Core
– compatible with standard 8051 processor
– two clocks per machine cycle architecture (for memory access without wait state)
– two data pointers
• On-chip memory
– 8 Kbytes of Boot ROM, Library ROM and User routines
– 256 bytes of RAM
– 256 bytes of XRAM
– 4/8 Kbytes of Flash (includes memory protection strategy)
• I/O port supply at 2.5 V - 5.5 V and core logic supply at 2.5 V (generated by
embedded voltage regulator)
8/4K Bytes
On-Chip Debug Support
XC800 Core
IIC
UART
SSC
Port 0
Port 1
Port 2
Port 3
8-bit Digital I/O
6-bit Digital I/O
Flash
Boot ROM
8K Bytes
Capture/Compare Unit
16-bit
XRAM
Compare Unit
16-bit
8-bit Digital/
Analog Input
256 Bytes
ADC
10-bit
RAM
3-bit Digital I/O
LED and Touch Sense Controller
256 Bytes
8-channel
Timer 0
16-bit
Timer 1
16-bit
Timer 2
16-bit
Real-Time Watchdog
Clock Timer
MDU
CORDIC
Figure 1
XC835/836 Functional Units
• Power-on reset generation
• Brownout detection for IO supply and core logic supply
• 48 MHz on-chip OSC for clock generation
– Loss-of-Clock detection
(more features on next page)
Data Sheet
1
V1.2, 2011-03
XC835/836
Summary of Features
Features: (continued)
• Power saving modes
– idle mode
– power-down mode with wake-up capability via real-time clock event
– clock gating control to each peripheral
• Programmable 16-bit Watchdog Timer (WDT) running on independent oscillator with
programmable window feature for refresh operation and warning prior to overflow
• Three general purpose I/O ports
– 4 high current I/O
– 2 high sink I/O
– Up to 25 pins as digital I/O
– Up to 8 pins as digital/analog input
• Up to 8 channels, 10-bit A/D Converter
– support up to 7 differential input channel
– results filtering by data reduction or digital low-pass filter, for up to 13-bit results
• Up to 8 channels, Out of range comparator
• Three 16-bit timers
– Timer 0 and Timer 1 (T0 and T1)
– Timer 2 (T2)
• Real-time clock with 32.768 kHz crystal pad
• 16-bit Vector Computer for Field-Oriented Control (FOC)
– Multiplication/Division Unit (MDU) for arithmetic calculation
– CORDIC Unit for trigonometric calculation
• Capture and Compare unit for PWM signal generation (CCU6)
• A full-duplex or half-duplex serial interface (UART)
• Synchronous serial channel (SSC)
• Inter-IC (IIC) serial interface
• LED and Touch-sense Controller (LEDTSCU)
• Software libraries to support fixed-point control and EEPROM emulation
• On-chip debug support via single pin DAP interface (SPD)
• Packages:
– PG-DSO-24
– PG-TSSOP-28
• Temperature range TA:
– SAF (-40 to 85 °C)
Data Sheet
2
V1.2, 2011-03
XC835/836
Summary of Features
XC835/836 Variant Devices
The XC835/836 product family features devices with different configurations, program
memory sizes, packages options and temperature profiles, to offer cost-effective
solutions for different application requirements.
The list of XC835/836 device configurations are summarized in Table 1. The type of
packages available are DSO-24 for XC835 and TSSOP-28 for XC836.
Table 1
Device Configuration
MDU and CORDIC Module
Device Name
XC835/836
XC835/836M
XC835/836T
XC835/836MT
LEDTSCU Module
No
No
Yes
Yes
No
Yes
No
Yes
Table 2 shows the device sales type available, based on above device.
Table 2
Device Profile
Sales Type
Device Program Temp-
Package
Type
Quality
Profile
Type
Memory erature
(Kbytes) Profile
(°C)
SAF-XC835MT-2FGI Flash
8
8
8
8
4
8
8
4
8
4
-40 to 85 PG-DSO-24-1
Industrial
SAF-XC836-2FRI
SAF-XC836T-2FRI
SAF-XC836M-2FRI
SAF-XC836M-1FRI
Flash
Flash
Flash
Flash
-40 to 85 PG-TSSOP-28-1 Industrial
-40 to 85 PG-TSSOP-28-1 Industrial
-40 to 85 PG-TSSOP-28-1 Industrial
-40 to 85 PG-TSSOP-28-1 Industrial
-40 to 85 PG-TSSOP-28-1 Industrial
-40 to 85 PG-TSSOP-28-12 Automotive
-40 to 85 PG-TSSOP-28-12 Automotive
-40 to 125 PG-TSSOP-28-12 Automotive
-40 to 125 PG-TSSOP-28-12 Automotive
SAF-XC836MT-2FRI Flash
SAF-XC836MT-2FRA Flash
SAF-XC836MT-1FRA Flash
SAK-XC836MT-2FRA Flash
SAK-XC836MT-1FRA Flash
As this document refers to all the derivatives, some description may not apply to a
specific product. For simplicity, all versions are referred to by the term XC835/836
throughout this document.
Data Sheet
3
V1.2, 2011-03
XC835/836
Summary of Features
Ordering Information
The ordering code for Infineon Technologies microcontrollers provides an exact
reference to the required product. This ordering code identifies:
• The derivative itself, i.e. its function set, the temperature range, and the supply
voltage
• The package and the type of delivery
For the available ordering codes for the XC835/836, please refer to your responsible
sales representative or your local distributor.
Data Sheet
4
V1.2, 2011-03
XC835/836
General Device Information
2
General Device Information
Chapter 2 contains the block diagram, pin configurations, definitions and functions of the
XC835/836.
2.1
Block Diagram
The block diagram of the XC835/836 is shown in Figure 2.
XC83x
Internal Bus
8-Kbyte
Boot ROM1)
XC800 Core
P0.0 - P0.7
P1.0 - P1.5
256-byte RAM
+
T0 & T1
UART
64-byte monitor
RAM
Vector Computer
CORDIC
MDU
VDDP
VSSP
VSSC
256-byte XRAM
P2.0 – P2.7
P3.0 - P3.2
RTC
IIC
4/8-Kbyte
Flash
WDT
SSC
CCU6
OCDS
SCU
ADC
Clock Generator
Timer 2
48 MHz
On-chip OSC
75 KHz
On-chip OSC
EVR
LED and Touch
Sense Controller
1) Includes 1-Kbyte monitor ROM
Figure 2
XC835/836 Block Diagram
Data Sheet
5
V1.2, 2011-03
XC835/836
General Device Information
2.2
Logic Symbol
The logic symbol of the XC835/836 is shown in Figure 3.
VDDP VDDC VSSP
VDDP VDDC VSSP
Port 0 8-Bit
Port 1 6-Bit
Port 0 8-Bit
Port 1 6-Bit
XC836
XC835
Port 2 8-Bit
Port 3 3-Bit
Port 2 4-Bit
Port 3 3-Bit
Figure 3
XC835/836 Logic Symbol
Data Sheet
6
V1.2, 2011-03
XC835/836
General Device Information
2.3
Pin Configuration
The pin configuration of the XC835 in Figure 4.
P3.2/SPD_0/RXD_3/SDA_2/MTSR_5/
1
24
23
22
21
20
19
18
17
16
15
14
13
P3.0/XTAL4/SCL_2/SCK_1/EXINT2_1/COL6
MRST_5/EXINT0_6/T2EX_7/TXD_3
P0.7/SCL_3/LINE7/TSIN7/TXD_5/COUT63_0/
P3.1/XTAL3/RXD_4/RTCCLK/MTSR_4/
MRST_4/EXINT0_5/COLA_0/EXF2_1
2
COL3_1/COLA_3
P2.3/CCPOS0_2/CTRAP_2/T2_2/EXINT3/AN3
3
P0.3/CC60_1/SDA_1/CTRAP_0/LINE3/TSIN3
P2.2/CCPOS2_1/T12HR_3/T13HR_3/SCK_3/
T1_1/EXINT2_0/AN2
4
P0.2/T1_0/CC62_1/SCL_1/CCPOS2_0/LINE2/TSIN2
P0.1/T0_0/CC61_1/MTSR_3/MRST_2/T13HR_0/
CCPOS1_0/LINE1/TSIN1
P0.0/T2_0/T13HR_1/MTSR_2/MRST_3/T12HR_0/
CCPOS0_0/LINE0/TSIN0/COUT61_1
P2.1/CCPOS1_1/RXD_5/MTSR_6/T0_1/EXINT1_1/AN1
5
P2.0/CCPOS0_1/T12HR_2/T13HR_2/T2EX_3/
T2_1/EXINT0_3/AN0
6
XC835
P0.6/SPD_1/RXD_1/SDA_0/MTSR_1/MRST_0/EXINT0_1/
T2EX_0/LINE6/TSIN6/TXD_0/COL2_1/COLA_2
7
P1.5/CC62_0/COL5/COLA_1
P0.5/RXD_0/MTSR_0/MRST_1/EXINT0_0/LINE5/TSIN5/
COUT62_1/TXD_4/COL1_1/EXF2_3
8
P1.4/EXINT5/COL4/COUT62_0/COUT63_2
P0.4/T2EX_1/SCL_0/SCK_0/EXINT1_0/CTRAP_1/
LINE4/TSIN 4/EXF2_0/COL0_1/COL3_2/COLA_4
9
VDDC
VSSP
VDDP
10
11
12
P1.0/SPD_2/RXD_2/T2EX_2/EXINT0_2/COL0_0/
COUT60_0/TXD_1
P1.3/CC61_0/COL3_0/CC61_0/EXF2_2
P1.2/EXINT4/COL2_0/COUT61_0/COUT63_1
P1.1/CC60_0/COL1_0/TXD_2
Figure 4
XC835 Pin Configuration, PG-DSO-24 Package (top view)
Data Sheet
7
V1.2, 2011-03
XC835/836
General Device Information
The pin configuration of the XC836 in Figure 5.
P0.7/SCL_3/LINE7/TSIN7/TXD_5/COUT63_0/
COL3_1/COLA_3
P2.7/RXD_6/T2EX_6/MTSR_7/EXINT0_4/AN7
P2.6/SCK_2/EXINT6/AN6
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
P3.2/SPD_0/RXD_3/SDA_2/MTSR_5/MRST_5/
EXINT0_6/T2EX_7/TXD_3
2
P2.5/T12HR_7/T13HR_7/AN5
3
P3.0/XTAL4/SCL_2/SCK_1/EXINT2_1/COL6
P3.1/XTAL3/RXD_4/RTCCLK/MTSR_4/
MRST_4/EXINT0_5/COLA_0/EXF2_1
P2.4/T12HR_5/T13HR_5/T2_3/AN4
P2.3/CCPOS0_2/CTRAP_2/T2_2/EXINT3/AN3
4
5
P0.3/CC60_1/SDA_1/CTRAP_0/LINE3/TSIN3
P2.2/CCPOS2_1/T12HR_3/T13HR_3/SCK_3/
T1_1/EXINT2_0/AN2
6
P0.2/T1_0/CC62_1/SCL_1/CCPOS2_0/LINE2/TSIN2
P2.1/CCPOS1_1/RXD_5/MTSR_6/T0_1/
P0.1/T0_0/CC61_1/MTSR_3/MRST_2/T13HR_0/
CCPOS1_0/LINE1/TSIN1
7
XC836
EXINT1_1/AN1
P0.0/T2_0/T13HR_1/MTSR_2/MRST_3/T12HR_0/
P2.0/CCPOS0_1/T12HR_2/T13HR_2/T2EX_3/
T2_1/EXINT0_3/AN0
8
CCPOS0_0/LINE0/TSIN0/COUT61_1
P0.6/SPD_1/RXD_1/SDA_0/MTSR_1/MRST_0/EXINT0_1/
9
P1.5/CC62_0/COL5/COLA_1
T2EX_0/LINE6/TSIN6/TXD_0/COL2_1/COLA_2
P0.5/RXD_0/MTSR_0/MRST_1/EXINT0_0/LINE5/
TSIN5/COUT62_1/TXD_4/COL1_1/EXF2_3
10
11
12
13
14
P1.4/EXINT5/COL4/COUT62_0/COUT63_2
P0.4/T2EX_1/SCL_0/SCK_0/EXINT1_0/CTRAP_1/
VDDC
VSSP
LINE4/TSIN4/EXF2_0/COL0_1/COL3_2/COLA_4
VDDP
P1.0/SPD_2/RXD_2/T2EX_2/EXINT0_2/
P1.3/CC61_0/COL3_0/CC61_0/EXF2_2
COL0_0/COUT60_0/TXD_1
P1.2/EXINT4/COL2_0/COUT61_0/COUT63_1
P1.1/CC60_0/COL1_0/TXD_2
Figure 5
XC836 Pin Configuration, PG-TSSOP-28 Package (top view)
Data Sheet
8
V1.2, 2011-03
XC835/836
General Device Information
2.4
Pin Definitions and Functions
The functions and default states of the XC835/836 external pins are provided in Table 3.
Table 3
Symbol Pin
Pin Definitions and Functions for XC835/836
Type Reset Function
Number
State
TSSOP28/
DS024
P0
I/O
Port 0
Port 0 is a bidirectional general purpose I/O port.
It can be used as alternate functions for
LEDTSCU, Timer 0, 1 and 2, SSC, CCU6, IIC,
SPD and UART.
P0.0
21/19
Hi-Z
T2_0
Timer 2 Input
T13HR_1
CCU6 Timer 13 Hardware Run
Input
MTSR_2
SSC Master Transmit Output/
Slave Receive Input
MRST_3
T12HR_0
SSC Master Receive Input
CCU6 Timer 12 Hardware Run
Input
CCPOS0_0 CCU6 Hall Input 0
TSIN0
LINE0
Touch-sense Input 0
LED Line 0
COUT61_1 Output of Capture/Compare
Channel 1
Data Sheet
9
V1.2, 2011-03
XC835/836
General Device Information
Table 3
Pin Definitions and Functions for XC835/836 (cont’d)
Symbol Pin
Type Reset Function
State
Number
TSSOP28/
DS024
P0.1
22/20
Hi-Z
T0_0
Timer 0 Input
CC61_1
Input/Output of Capture/Compare
channel 1
MTSR_3
MRST_2
SSC Slave Receive Input
SSC Master Receive Input/
Slave Transmit Output
T13HR_0
CCU6 Timer 13 Hardware Run
Input
CCPOS1_0 CCU6 Hall Input 1
TSIN1
LINE1
T1_0
Touch-sense Input 1
LED Line 1
Timer 1 Input
Input/Output of Capture/Compare
channel 2
IIC Clock Line
P0.2
P0.3
23/21
24/22
Hi-Z
Hi-Z
CC62_1
SCL_1
CCPOS2_0 CCU6 Hall Input 2
TSIN2
LINE2
Touch-sense Input 2
LED Line 2
Input/Output of Capture/Compare
channel 0
CC60_1
SDA_1
CTRAP_0
TSIN3
IIC Data Line
CCU6 Trap Input
Touch-sense Input 3
LED Line 3
LINE3
Data Sheet
10
V1.2, 2011-03
XC835/836
General Device Information
Table 3
Pin Definitions and Functions for XC835/836 (cont’d)
Symbol Pin
Type Reset Function
State
Number
TSSOP28/
DS024
P0.4
11/9
PD
T2EX_1
SCK_0
SCL_0
Timer 2 External Trigger Input
SSC Clock Input/Output
IIC Clock Line
CTRAP_1
EXINT1_0
TSIN4
CCU6 Trap Input
External Interrupt Input 1
Touch-sense Input 4
LED Line 4
LINE4
EXF2_0
COL0_1
COL3_2
COLA_4
RXD_0
Timer 2 Overflow Flag
LED Column 0
LED Column 3
LED Column A
UART Receive Input
P0.5
10/8
Hi-Z
MTSR_0
SSC Master Transmit Output/
Slave Receive Input
MRST_1
EXINT0_0
TSIN5
SSC Master Receive Input
External Interrupt Input 0
Touch-sense Input 5
LED Line 5
LINE5
COUT62_1 Output of Capture/Compare
Channel 2
TXD_4
COL1_1
EXF2_3
UART Transmit Output
LED Column 1
Timer 2 Overflow Flag
Data Sheet
11
V1.2, 2011-03
XC835/836
General Device Information
Table 3
Pin Definitions and Functions for XC835/836 (cont’d)
Symbol Pin
Type Reset Function
State
Number
TSSOP28/
DS024
P0.6
9/7
PU
SPD_1
RXD_1
SDA_0
SPD Input/Output
UART Receive Input
IIC Data Line
MTSR_1
MRST_0
SSC Slave Receive Input
SSC Master Receive Input/
Slave Transmit Output
EXINT0_1
T2EX_0
TSIN6
External Interrupt Input 0
Timer 2 External Trigger Input
Touch-sense Input 6
LED Line 6
LINE6
TXD_0
COL2_1
COLA_2
SCL_3
TSIN7
UART Transmit Output
LED Column 2
LED Column A
IIC Clock Line
Touch-sense Input 7
LED Line 7
P0.7
28/2
Hi-Z
LINE7
TXD_5
UART Transmit Output/
2-wire UART BSL Transmit Output
COUT63_0 Output of Capture/Compare
Channel 3
COL3_1
COLA_3
Port 1
LED Column 3
LED Column A
P1
I/O
Port 1 is a bidirectional general purpose I/O port.
It can be used as alternate functions for CCU6,
LEDTSCU, SPD, UART and Timer 2
Data Sheet
12
V1.2, 2011-03
XC835/836
General Device Information
Table 3
Pin Definitions and Functions for XC835/836 (cont’d)
Symbol Pin
Type Reset Function
State
Number
TSSOP28/
DS024
P1.0
16/14
Hi-Z
SPD_2
SPD Input/Output
RXD_2
UART Receive Input
Timer 2 External Trigger Input
External Interrupt Input 0
LED Column 0
T2EX_2
EXINT0_2
COL0_0
COUT60_0 Output of Capture/Compare
Channel 0
TXD_1
UART Transmit Output
P1.1
P1.2
15/13
14/12
Hi-Z
Hi-Z
CC60_0
Input/Output of Capture/Compare
channel 0
LED Column 1
UART Transmit Output
External Interrupt Input 4
LED Column 2
COL1_0
TXD_2
EXINT4
COL2_0
COUT61_0 Output of Capture/Compare
channel 1
COUT63_1 Output of Capture/Compare
channel 3
P1.3
P1.4
13/11
19/17
Hi-Z
Hi-Z
CC61_0
Input/Output of Capture/Compare
channel 1
LED Column 3
Timer 2 Overflow Flag
External Interrupt Input 5
LED Column 4
COL3_0
EXF2_2
EXINT5
COL4
COUT62_0 Output of Capture/Compare
channel 2
COUT63_2 Output of Capture/Compare
channel 3
Data Sheet
13
V1.2, 2011-03
XC835/836
General Device Information
Table 3
Pin Definitions and Functions for XC835/836 (cont’d)
Symbol Pin
Type Reset Function
State
Number
TSSOP28/
DS024
P1.5
20/18
Hi-Z
CC62_0
Input/Output of Capture/Compare
channel 2
COL5
COLA_1
Port 2
LED Column 5
LED Column A
P2
I
Port 2 is a general purpose input-only port. It can
be used as inputs for A/D Converter and out of
range comparator, CCU6, Timer 2, SSC and
UART.
P2.0
8/6
Hi-Z
CCPOS0_1 CCU6 Hall Input 0
T12HR_2
CCU6 Timer 12 Hardware Run
Input
T13HR_2
CCU6 Timer 13 Hardware Run
Input
T2EX_3
T2_1
Timer 2 External Trigger Input
Timer 2 Input
EXINT0_3
AN0
External Interrupt Input 0
Analog Input 0 /
Out of range comparator channel 0
P2.1
7/5
Hi-Z
CCPOS1_1 CCU6 Hall Input 1
RXD_5
MTSR_6
T0_1
UART Receive Input
SSC Slave Receive Input
Timer 0 Input
EXINT1_1
AN1
External Interrupt Input 1
Analog Input 1 /
Out of range comparator channel 1
Data Sheet
14
V1.2, 2011-03
XC835/836
General Device Information
Table 3
Pin Definitions and Functions for XC835/836 (cont’d)
Symbol Pin
Type Reset Function
State
Number
TSSOP28/
DS024
P2.2
6/4
Hi-Z
CCPOS2_1 CCU6 Hall Input 2
T12HR_3
CCU6 Timer 12 Hardware Run
Input
T13HR_3
CCU6 Timer 13 Hardware Run
Input
SCK_3
T1_1
SSC Clock Input/Output
Timer 1 Input
EXINT2_0
AN2
External Interrupt Input 2
Analog Input 2 /
Out of range comparator channel 2
P2.3
P2.4
5/3
4/-
Hi-Z
Hi-Z
CCPOS0_2 CCU6 Hall Input 0
CTRAP_2
T2_2
CCU6 Trap Input
Timer 2 Input
EXINT3
AN3
External Interrupt Input 3
Analog Input 3 /
Out of range comparator channel 3
T12HR_5
T13HR_5
CCU6 Timer 12 Hardware Run
Input
CCU6 Timer 13 Hardware Run
Input
T2_3
AN4
Timer 2 Input
Analog Input 4 /
Out of range comparator channel 4
P2.5
3/-
Hi-Z
T12HR_7
T13HR_7
AN5
CCU6 Timer 12 Hardware Run
Input
CCU6 Timer 13 Hardware Run
Input
Analog Input 5 /
Out of range comparator channel 5
Data Sheet
15
V1.2, 2011-03
XC835/836
General Device Information
Table 3
Pin Definitions and Functions for XC835/836 (cont’d)
Symbol Pin
Type Reset Function
State
Number
TSSOP28/
DS024
P2.6
P2.7
2/-
Hi-Z
Hi-Z
SCK_2
EXINT6
AN6
SSC Clock Input/Output
External Interrupt Input 6
Analog Input 6 /
Out of range comparator channel 6
1/-
RXD_6
T2EX_6
MTSR_7
EXINT0_4
AN7
UART Receive Input
Timer 2 External Trigger Input
SSC Slave Receive Input
External Interrupt Input 0
Analog Input 7 /
Out of range comparator channel 7
P3
I/O
Port 3
Port 3 is a bidirectional general purpose I/O port.
It can be used as alternate functions for IIC,
LEDTSCU, UART, Timer 2, SSC, SPD and
32.768 kHz crystal pad.
P3.0
26/24
PU
SCL_2
SCK_1
EXINT2_1
COL6
IIC Clock Line
SSC Clock Input/Output
External Interrupt Input 2
LED Column 6
XTAL4
32.768 kHz External Oscillator
Output
Data Sheet
16
V1.2, 2011-03
XC835/836
General Device Information
Table 3
Pin Definitions and Functions for XC835/836 (cont’d)
Symbol Pin
Type Reset Function
State
Number
TSSOP28/
DS024
P3.1
25/23
PU
RXD_4
UART Receive Input
RTCCLK
MTSR_4
RTC External Clock Input
SSC Master Transmit Output/
Slave Receive Input
MRST_4
EXINT0_5
COLA_0
XTAL3
SSC Master Receive Input
External Interrupt Input 0
LED Column A
32.768 kHz External oscillator
Input
EXF2_1
SPD_0
RXD_3
Timer 2 Overflow Flag
SPD Input/Output
UART Receive Input/
UART BSL Receive Input
P3.2
27/1
PU
SDA_2
IIC Data Line
MTSR_5
MRST_5
SSC Slave Receive Input
SSC Master Receive Input/
Slave Transmit Output
EXINT0_6
T2EX_7
TXD_3
External Interrupt Input 0
Timer 2 External Trigger Input
UART Transmit Output/
1-wire UART BSL Transmit Output
VDDP
VDDC
12/10
18/16
17/15
–
–
–
–
–
–
I/O Port Supply (2.5 V - 5.5 V)
Core Supply Monitor (2.5 V)
I/O Port Ground/
Core Supply Ground
VSSP
/
VSSC
Data Sheet
17
V1.2, 2011-03
XC835/836
General Device Information
2.5
Memory Organization
The XC835/836 CPU operates in the following five address spaces:
• 8 Kbytes of Boot ROM, Library ROM and User routines
• 256 bytes of internal RAM
• 256 bytes of XRAM
(XRAM can be read/written as program memory or external data memory)
• A 128-byte Special Function Register area
• 4/8 Kbytes of Flash
Figure 6 illustrates the memory address spaces of the 4 Kbyte Flash devices. Figure 7
illustrates the memory address spaces of the 8 Kbyte Flash devices.
FFFFH
FFFFH
F100H
F000H
F100H
F000H
XRAM
XRAM
256 Bytes
256 Bytes
E000H
Boot ROM
8 KBytes
C000H
B000H
Flash Bank 0
4 KBytes 1)
A000H
Indirect
Direct
Address
Address
FFH
80H
Special Function
Registers
Internal RAM
1000H
0000H
7FH
40H
Internal RAM
Flash Bank 0
4 KBytes
In Debug Mode, this 64-byte address area
is replaced by a 64-byte Monitor RAM.
00H
0000H
Code Space
External Data Space
Internal Data Space
1) Physically one 4-Kbyte Flash bank, mapped to both address range .
Memory Map User Mode
Figure 6
Memory Map of XC835/836 with 4 Kbytes of Flash memory
Data Sheet
18
V1.2, 2011-03
XC835/836
General Device Information
FFFFH
FF80H
FF40H
FFFFH
User BSL Flash Sector
64 Bytes2)
F100H
F000H
F100H
F000H
XRAM
XRAM
256 Bytes
256 Bytes
E000H
Boot ROM
8 KBytes
C000H
B000H
Flash Bank 1
4 KBytes 1)
A000H
Indirect
Direct
Address
Address
FFH
Special Function
Internal RAM
2000H
1000H
Registers
Flash Bank 1
4 KBytes 1)
80H
7FH
40H
Internal RAM
Flash Bank 0
4 KBytes
In Debug Mode, this 64-byte address area
is replaced by a 64-byte Monitor RAM.
00H
0000H
0000H
Code Space
External Data Space
Internal Data Space
1) Physically one 4-Kbyte Flash bank, mapped to both address range . Flash Bank 1 is only available in 8-Kbyte Flash Variant.
2) User BSL Flash sector is only available in 8-Kbyte Flash Variant .
Memory Map User Mode
Figure 7
Memory Map of XC835/836 with 8 Kbytes of Flash memory
Data Sheet
19
V1.2, 2011-03
XC835/836
General Device Information
2.6
JTAG ID
JTAG ID register is a read-only register located inside the JTAG module, and is used to
recognize the device(s) connected to the JTAG interface. Its content is shifted out when
INSTRUCTION register contains the IDCODE command (opcode 04H), and the same is
also true immediately after reset.
The JTAG ID register contents for the XC835/836 Flash devices are given in Table 4.
Table 4
Device Type
Flash
JTAG ID Summary
Device Name
XC835*-2FG
JTAG ID
101B A083H
XC836*-2FR
XC836*-1FR
101B B083H
Note: The asterisk (*) above denotes all possible device configurations.
Data Sheet
20
V1.2, 2011-03
XC835/836
General Device Information
2.7
Chip Identification Number
The XC835/836 identity (ID) register is located at Page 1 of address B3H. The value of
ID register is 59H. However, for easy identification of product variants, the Chip
Identification Number, which is an unique number assigned to each product variant, is
available. The differentiation is based on the product and variant type information.
Two methods are provided to read a device’s Chip Identification number:
• In-application subroutine, GET_CHIP_INFO
• Boot-loader (BSL) mode A
Table 5 lists the Chip Identification numbers of XC835/836 device variants.
Table 5
Chip Identification Number
Product Variant
XC835MT-2FG
XC836-2FR
Chip Identification Number
59080001H
59080060H
XC836T-2FR
XC836M-2FR
XC836M-1FR
XC836MT-2FR
XC836MT-1FR
59080040H
59080020H
59080120H
59080000H
59080100H
Data Sheet
21
V1.2, 2011-03
XC835/836
Electrical Parameters
3
Electrical Parameters
Chapter 3 provides the characteristics of the electrical parameters which are
implementation-specific for the XC835/836.
3.1
General Parameters
The general parameters are described here to aid the users in interpreting the
parameters mainly in Section 3.2 and Section 3.3.
3.1.1
Parameter Interpretation
The parameters listed in this section represent partly the characteristics of the
XC835/836 and partly its requirements on the system. To aid interpreting the parameters
easily when evaluating them for a design, they are indicated by the abbreviations in the
“Symbol” column:
• CC
– These parameters indicate Controller Characteristics, which are distinctive
features of the XC835/836 and must be regarded for a system design.
• SR
– These parameters indicate System Requirements, which must be provided by the
microcontroller system in which the XC835/836 is designed in.
Data Sheet
22
V1.2, 2011-03
XC835/836
Electrical Parameters
3.1.2
Absolute Maximum Rating
Maximum ratings are the extreme limits to which the XC835/836 can be subjected to
without permanent damage.
Table 6
Absolute Maximum Rating Parameters
Parameter
Symbol
Limit Values
Unit Notes
Min.
-40
-65
-40
-0.5
Max.
125
150
150
6
Ambient temperature
Storage temperature
Junction temperature
TA
TST
TJ
°C
°C
°C
V
under bias
–
under bias
Voltage on power supply pin with VDDP
respect to VSS
Maximum current per pin for
P1[3:0]
Input current on any pin during
overload condition
IM
-115
-10
–
115
10
mA
mA
mA
IIN
Absolute sum of all input currents Σ|IIN|
50
during overload condition
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
During absolute maximum rating overload conditions (VIN > VDDP or VIN < VSS) the
voltage on VDDP pin with respect to ground (VSS) must not exceed the values
defined by the absolute maximum ratings.
Data Sheet
23
V1.2, 2011-03
XC835/836
Electrical Parameters
3.1.3
Operating Condition
The following operating conditions must not be exceeded in order to ensure correct
operation of the XC835/836. All parameters mentioned in the following tables refer to
these operating conditions, unless otherwise noted.
Table 7
Parameter
Operating Condition Parameters
Symbol Limit Values
Unit Notes/
Conditions
Min.
3.0
2.5
Max.
5.5
3.0
Digital power supply voltage VDDP
Digital core supply voltage2) VDDC
V
V
V
1)
2.3
2.7
CPU Clock Frequency
fCCLK
22.5
7.5
25.6
8.5
MHz typ. 24 MHz
MHz typ. 8 MHz
Ambient temperature
TA
-40
85
°C
SAF-XC835/836...
1) In this voltage range, limited operations are available in active mode. Operations in power save modes are
fully supported.
2) VDDC is supplied by the on-chip EVR. The limits are verified by design and production testing.
Data Sheet
24
V1.2, 2011-03
XC835/836
Electrical Parameters
3.2
DC Parameters
The electrical characteristics of the DC Parameters are detailed in this section.
3.2.1
Input/Output Characteristics
Table 8 provides the characteristics of the input/output pins of the XC835/836.
Table 8
Parameter
Input/Output Characteristics (Operating Conditions apply)
Symbol Limit Values Unit Test Conditions
Min.
Max.
Outputlowvoltageon VOLP CC –
1.0
V
V
V
IOL = 25 mA (5 V)
port pins
IOL = 13 mA (3.3 V)
(all except P1)
–
0.4
1.0
IOL = 10 mA (5 V)
IOL = 5 mA (3.3 V)
Outputlowvoltageon VOLP1 CC –
IOL = 50 mA (5 V)
P1[3:0]
IOL = 25 mA (3.3 V)
–
–
0.32
0.4
1.0
V
V
V
IOL = 20 mA (5 V)
IOL = 10 mA (3.3 V )
Outputlowvoltageon VOLP2 CC –
IOL = 50 mA (5 V)
P1[5:4]
IOL = 25 mA (3.3 V)
–
0.4
V
V
V
V
V
V
V
V
IOL = 20 mA (5 V)
IOL = 10 mA (3.3 V)
Output high voltage VOHP CC VDDP - –
I
OH = -15 mA (5 V)
OH = -8 mA (3.3 V )
on port pins
1.0
I
(all except P1)
V
DDP - –
I
I
OH = -5 mA (5 V)
OH = -2.5 mA (3.3 V)
0.4
Output high voltage VOHP1 CC VDDP - –
I
I
I
OH = -20 mA (5 V)
OH = -25 mA (3.3 V)
OH = -10 mA (3.3 V)
on P1[3:0] 0.32
V
DDP - –
1.0
V
DDP - –
0.4
Output high voltage VOHP2 CC VDDP - –
I
I
OH = -30 mA (5 V)
OH = -16 mA (3.3 V)
on P1[5:4]
1.0
V
DDP - –
I
OH = -10 mA (5 V)
OH =- 5 mA (3.3 V)
0.4
I
Data Sheet
25
V1.2, 2011-03
XC835/836
Electrical Parameters
Table 8
Input/Output Characteristics (Operating Conditions apply) (cont’d)
Parameter
Symbol
Limit Values Unit Test Conditions
Min.
SR –
Max.
0.3 ×
VDDP
Input low voltage on VILP
V
V
V
V
V
CMOS Mode
(5 & 3.3 V)
CMOS Mode
(5 V & 3.3 V)
CMOS Mode (5 V)
CMOS Mode (3.3 V)
CMOS Mode (2.5 V)
port pins
Input high voltage on VIHP
SR 0.7 ×
–
port pins
VDDP
Input Hysteresis1)
HYS CC 0.08 × –
VDDP
0.03 × –
VDDP
0.01 × –
VDDP
Pull-up current
IPUP
SR –
-20
–
-5
–
20
–
5
µA
µA
µA
µA
µA
µA
µA
µA
V
V
V
V
V
V
V
V
IH,min (5 V)
-150
–
-100
IL,max (5 V)
IH,min (3.3 V)
IL,max (3.3 V)
IL,max (5 V)
IH,min (5 V)
Pull-down current
IPDP
SR –
150
–
100
IL,max (3.3 V)
IH,min (3.3 V)
–
Input leakage current IOZP
on port pins2)
(all except P1)
CC -1
1
µA 0 < VIN < VDDP
,
TA ≤ 125 °C
Input leakage current IOZP1 CC -3
3
µA 0 < VIN < VDDP
TA ≤ 125 °C
,
,
on P1[3:0]2)
Input leakage current IOZP2 CC -2
2
µA 0 < VIN < VDDP
on P1[5:4]2)
TA ≤ 125 °C
Overcurrent
|IOCP1| SR 60
115
mA VDDP = 5 V
threshold per pin for
P1[3:0]3)
4)
Overload current on IOVP
SR -5
5
mA
any pin
4)
Absolute sum of
overload currents
Σ|IOV| SR –
25
mA
Data Sheet
26
V1.2, 2011-03
XC835/836
Electrical Parameters
Table 8
Input/Output Characteristics (Operating Conditions apply) (cont’d)
Parameter
Symbol
Limit Values Unit Test Conditions
Min.
SR –
Max.
0.3
5)
Voltage on any pin
during VDDP power off
VPO
V
Maximum current per IMP
SR -15
25
mA
–
pin (excluding P1,
V
DDP and VSS)
Maximum current per IMP1A SR -50
50
mA
mA
mA
mA
–
pin for P1[3:0]
Maximum current per IMP1B SR -30
50
–
pin for P1[5:4]
4)
Maximum current
into VDDP
IMVDDP SR –
130
130
4)
Maximum current out IMVSS SR –
of VSS
1) Not subjected to production test, verified by design/characterization. Hysteresis is implemented to avoid meta
stable states and switching due to internal ground bounce. It cannot be guaranteed that it suppresses switching
due to external system noise.
2) An additional error current (IINJ) will flow if an overload current flows through an adjacent pin.
3) Over current detection is available for 5V application only.
4) Not subjected to production test, verified by design/characterization.
5) Not subjected to production test, verified by design/characterization. However, for applications with strict low
power-down current requirements, it is mandatory that no active voltage source is supplied at any GPIO pin
when VDDP is powered off.
Data Sheet
27
V1.2, 2011-03
XC835/836
Electrical Parameters
3.2.2
Supply Threshold Characteristics
Table 9 provides the characteristics of the supply threshold in the XC835/836.
5.0V
VDDPPW/VDDPBOPD
VDDPBOA
VDDPSRR
VDDP
VDDC
2.5V
VDDCPW
VDDCBOA
VDDCBOPD
VDDCSRR
VDDCRDR
Figure 8
Supply Threshold Parameters
Supply Threshold Parameters (Operating Conditions apply)
Table 9
Parameters
Symbol
Limit Values
Unit
Min. Typ. Max.
V
V
V
DDP prewarning voltage1)2)
VDDPPW
CC 3.0
3.6 4.5
V
DDP brownout voltage in active mode2)3)
DDP brownout voltage in all power down
VDDPBOA CC 2.65 2.75 2.87 V
3.0 3.6 4.5
VDDPBOPD
V
mode2)3)
V
V
V
V
V
DDP system reset release voltage2)4)
DDC prewarning voltage2)5)
VDDPSRR CC 2.7
VDDCPW CC 2.3
2.8 2.92 V
2.4 2.48 V
DDC brownout voltage in active mode2)
VDDCBOA CC 2.25 2.3 2.42 V
DDC brownout voltage in power down mode2) VDDCBOPD CC 1.35 1.5 1.95 V
DDC system reset release voltage2)4)
VDDCSRR CC 2.28 2.3 2.47 V
VDDCRDR CC 1.1
RAM data retention voltage
–
–
V
1) Detection is enabled via SDCON register in active mode. It is automatically disabled in power down mode.
Detection should be disabled for VDDP less than maximum of VDDPPW
.
2) This parameter has a hysteresis of 50 mV.
3) Detection is enabled via SDCON register. Detection must be disabled for application with V
specified values.
less than the
DDP
4) V
and V
must be met before the system reset is released.
DDPSRR
DDCSRR
5) Detection is enabled via SDCON register in active mode. It is automatically disabled in power down mode.
Data Sheet
28
V1.2, 2011-03
XC835/836
Electrical Parameters
3.2.3
ADC Characteristics
The values in Table 10 are given for an analog power supply of 5.0 V. The ADC can be
used with an analog power supply down to 3 V. But in this case, analog parameters may
show a reduced performance. In the reduced voltage mode (2.5 V < VDDP < 3 V), the
ADC is not recommended to be used.
Table 10
ADC Characteristics (Operating Conditions apply; VDDP = 5 V;
f
ADCI <= 12 MHz)
Parameter
Symbol
Limit Values
Min. Typ. Max.
Unit
Test
Conditions /
Remarks
Analog reference
voltage
Analog reference
ground
Alternate analog
reference ground
VAREF
VAGND
–
–
VDDP
VSSP
–
V
V
V
Connect
internally to VDDP
–
Connect
internally to VSSP
Connect to AN0
in differential
mode, See
Figure 9.
4)
VAGNDALT SR VSSP - –
2.51)
0.1
Internal voltage
reference
VINTREF SR 1.19 1.23 1.28
V
Analog input voltage VAIN
SR VAGND
–
–
VAREF
V
–
range
ADC clock
fADCI
tS
8
16
MHz
internal analog
clock
–
Sample time
CC (2 + INPCR0.STC) × µs
tADCI
Conversion time
tC
CC See Section 3.2.3.1 µs
–
2)
Set-uptimebetween tSETUP
conversions using
internal voltage
SR –
35
–
µs
reference
Data Sheet
29
V1.2, 2011-03
XC835/836
Electrical Parameters
Table 10
ADC Characteristics (Operating Conditions apply; VDDP = 5 V;
f
ADCI <= 12 MHz) (cont’d)
Parameter
Symbol
Limit Values
Min. Typ. Max.
Unit
Test
Conditions /
Remarks
Total unadjusted
error
TUE3)
CC –
–
±1
LSB8 8-bit conversion
with internal
reference4)
–
–
+4/-2
LSB10 10-bit
conversion with
internal
reference4)5)
–
–
+14/-2 LSB12 12-bit
conversionusing
the Low Pass
Filter 4)
Differential
EADNL
CC –
CC –
CC –
CC –
CC –
–
+1.5/ -1 LSB
10-bit
Nonlinearity
conversion4)
Integral Nonlinearity EAINL
–
±1.5
LSB
LSB
LSB
pF
10-bit
conversion4)
Offset
Gain
EAOFF
EAGAIN
CAINSW
+4
-4
2
–
–
3
10-bit
conversion4)
10-bit
conversion4)
4)6)
Switched
capacitance at an
analog input
4)6)
4)
Total capacitance at CAINT
CC –
CC –
–
12
2
pF
an analog input
Input resistance of RAIN
1.5
kΩ
an analog input
1) 1.2 V at VDDP = 3.0 V.
2) Not subject to production test, verified at CPU clock (fSCLK, CCLK ) = 8 MHz, TA = + 25 °C and VDDP = 5 V.
3) TUE is tested at VAREF = VDDP = 5.0 V and CPU clock (fSCLK, CCLK ) = 8 MHz.
4) Not subject to production test, verified by design/characterization.
5) If a reduced positive reference voltage is used, TUE will increase. If the positive reference is reduced by a
factor of K, the TUE will increased by 1/K. Example:K = 0.8, 1/K = 1.25; 1.25 X TUE = 2.5 LSB10.
6) The sampling capacity of the conversion C-Network is pre-charged to VAREF/2 before connecting the input to
the C-Network. Because of the parasitic elements, the voltage measured at ANx is lower than VAREF/2.
Data Sheet
30
V1.2, 2011-03
XC835/836
Electrical Parameters
ADC kernel
V1.2VREF
va_altref
va_altgnd
V1.2VGND
AIN CH0
AIN CH1
result
handling
AD
converter
conversion
control
AIN CH7
request
control
Interrupt
generation
Figure 9
Differential like measurement with internal 1.2V voltage reference,
and CH0 gnd.
Analog Input Circuitry
REXT
RAIN, On
ANx
CAINSW
CAINT - CAINSW
VAIN
CEXT
VSSP
Figure 10
ADC Input Circuits
Data Sheet
31
V1.2, 2011-03
XC835/836
Electrical Parameters
3.2.3.1 ADC Conversion Timing
Conversion time, tC = tADC × (1 + r × (3 + n + STC)), where
• r = CTC + 3,
• CTC = Conversion Time Control (GLOBCTR.CTC),
• STC = Sample Time Control (INPCR0.STC),
• n = 8 or 10 (for 8-bit and 10-bit conversion respectively),
• tADC = 1 / fADC
3.2.3.2 Out of Range Comparator Characteristics
Table 11 below shows the Out of Range Comparator characteristics.
Table 11
Out of Range Comparator Characteristics (Operating Conditions
apply)
Parameter
Symbol
Limit Values
Unit Remarks
Min. Typ. Max.
DC Switching
Level
DC Hysteresis
Pulse Width
VSenseDC SR 60
125 270 mV Above VDDP
1)
VSenseHys CC 30
tSensePW SR 300
–
–
–
–
mV
ns
1)
ANx > VDDP
ANx >= VDDP + 350 mV1)
Switching Delay tSenseSD CC –
Pulse Switching tSensePSL SR –
–
250
60
400 ns
–
–
mV @ 300 nsec1)
mV @ 800 usec1)
Level
SR –
1) Not subject to production test, verified by design/characterization.
Data Sheet
32
V1.2, 2011-03
XC835/836
Electrical Parameters
3.2.4
Flash Memory Parameters
The XC835/836 is delivered with all Flash sectors erased (read all zeros).
The data retention time of the XC835/836’s Flash memory (i.e. the time after which
stored data can still be retrieved) depends on the number of times the Flash memory has
been erased and programmed.
Note: Flash memory parameters are not subject to production test but verified by design
and/or characterization.
Table 12
Flash Timing Parameters (Operating Conditions apply)
Parameter
Symbol
Limit Values
Unit Remarks
Min. Typ. Max.
Read access time
(per byte)
Programming time
(per wordline)
Erase time
(one or more sectors)
tACC
tPR
CC –
CC –
CC –
125
–
–
–
ns
2.2
ms
ms
tER
120
Flash wait states
NWSFLASH CC
0
1
CPU clock = 8 MHz
CPU clock = 24 MHz
Table 13
Retention
20 years
5 years
2 years
2 years
Flash Data Retention and Endurance (Operating Conditions apply)
Endurance1)
1,000 cycles
10,000 cycles
70,000 cycles
100,000 cycles
Size
up to 8 Kbytes
1 Kbyte
512 bytes
128 bytes
Remarks
1) One cycle refers to the programming of all wordlines in a sector and erasing of sector. The Flash endurance
data specified in Table 13 is valid only if the following conditions are fulfilled:
- the maximum number of erase cycles per Flash sector must not exceed 100,000 cycles.
- the maximum number of erase cycles per Flash bank must not exceed 300,000 cycles.
- the maximum number of program cycles per Flash bank must not exceed 2,500,000 cycles.
Data Sheet
33
V1.2, 2011-03
XC835/836
Electrical Parameters
Table 14
Emulated Flash Data Retention and Endurance based on EEPROM
Emulation ROM Library (Operating Conditions apply)
Retention
2 years
2 years
2 years
2 years
Endurance1)
Emulation Size
31 bytes
Remarks
1,600,000 cycles
1,400,000 cycles
1,200,000 cycles
1,000,000 cycles
62 bytes
93 bytes
124 bytes
1) These values show the maximum endurance. Maximum endurance is the maximum possible unique data write
if each data update is only 31 bytes. Minimum endurance cycle is the maximum possible unique data write if
each data update is the same as the emulation size. The minimum endurance cycle can be calculated using
the formulae [(max. endurance)*(31)/(emulation size)].
Data Sheet
34
V1.2, 2011-03
XC835/836
Electrical Parameters
3.2.5
Power Supply Current
Table 15 provides the characteristics of the power supply current in the XC835/836.
Table 15
Power Consumption Parameters1) 2)(Operating Conditions apply)
Parameter
Symbol
Limit Values
Typ. Max.
28
Unit Test Condition
Active Mode
IDDPA
23
16
–
mA
mA
mA
mA
mA
µA
µA
µA
µA
µA
µA
µA
µA
5 V / 3.3 V 3)
5 V / 3.3 V 4)
2.5 V5)
20
5
Idle Mode
IDDPI
IPDP1
IPDP2
IPDP3
IPDP4
18
–
25
5
5 V / 3.3 V 6)
2.5 V 5)
Power Down Mode 1
Power Down Mode 2
Power Down Mode 3
Power Down Mode 4
3
5
TA = 25° C7)
TA = 85° C7)8)9)
TA = 25° C7)8)
TA = 85° C7)8)9)
TA = 25° C7)8)
TA = 85° C7)8)9)
TA = 25° C7)
TA = 85° C7)8)9)
–
6
28
8
–
5
31
7
–
5
30
7
–
30
1) The typical IDDP values are measured at TA = + 25 °C and VDDP = 5 V and 3.3 V.
2) The maximum IDDC values are measured under worst case conditions (TA = + 125 °C and VDDC = 5 V).
3) IDDP (active mode) is measured with: CPU clock and input clock to all peripherals running at 24 MHz
(CLKMODE=0).
4) IDDP (active mode) is measured with: CPU clock and input clock to all peripherals running at 8 MHz
(CLKMODE=1).
5) This value is based on the maximum load capacity of EVR during VDDP = 2.5 V. Not subject to production test,
verified by design/characterisation.
6) IDDPI (idle mode) is measured with: CPU clock disabled, watchdog timer disabled, input clock to all peripherals
enabled and running at 24 MHz (CLKMODE=0).
7) IPDP1, IPDP2, IPDP3 and IPDP4 is measured at 5 V and 3.3 V with: wake-up port is programmed to be input with
either internal pull devices enabled or driven externally to ensure no floating inputs.
8) Not subject to production test, verified by design/characterisation.
9) IPDP1, IPDP2, IPDP3 and IPDP4 has a maximum values of 120 uA at TA = + 125 °C.
Data Sheet
35
V1.2, 2011-03
XC835/836
Electrical Parameters
Table 16 shows the maximum active current within the device in the reduced voltage
condition of 2.5 V < VDDP < 3.0 V. The active current consumption needs to be below the
specified values as according to the VDDP voltage. If the conditions are not met, a
brownout reset may be triggered.
Table 16
VDDP
Active Current Consumption in Reduced Voltage Condition
2.5 V
2.6 V
2.7 V
2.8 V
Maximum active current 7 mA
13 mA
20 mA
25 mA
Table 17 provides the active current consumption of some modules operating at 8 MHz
active mode, 3 V power supply at 25° C. The typical values shown are used as a
reference guide for device operating in reduced voltage conditions.
Table 17
Typical Active Current Consumption1) 2)
Active Current
Symbol
Limit Values Unit Test Condition
Typ.
Consumption
Baseload current3) ICPUDDC
6900
µA
Modules including Core,
memories, UART, T0, T1 and
EVR. Disable ADC analog
(GLOBCTR.ANON = 0).
ADC4)
IADCDDC
3760
µA
Set PMCON1.ADC_DIS to 0
and GLOBECTR. ANON to 1
SSC5)
ISSCDDC
ICCU6DDC
IT2DDC
IMDUDDC
ICORDICDDC 1880
460
3320
200
µA
µA
µA
µA
µA
µA
µA
Set PMCON1.SSC_DIS to 0
Set PMCON1.CCU_DIS to 0
Set PMCON1.T2_DIS to 0
Set PMCON1.MDU_DIS to 0
Set PMCON1.CDC_DIS to 0
Set PMCON1.LTS_DIS to 0
Set PMCON1.IIC_DIS to 0
CCU66)
Timer 27)
MDU8)
1260
CORDIC9)
LEDTSCU10)
IIC11)
ILEDDDC
IIICDDC
850
580
1) Modules that are controllable by programming the register PMCON1.
2) Not subject to production test, verified by design/characterisation.
3) Baseload current is measured when the device is running in user mode with an endless loop in the flash
memory. All modules in register PMCON1 are disabled.
4) ADC active current is measured with: module enable, ADC analog clock at 8MHz, running in parallel
conversion request in autoscan mode for 4 channels
5) SSC active curremt is measured with: module enabled, running in loop back mode at a baud rate of 1 MBaud
6) CCU6 active current is measured with: module enabled, all timers running in 8 MHz, 6 PWM outputs are
generated.
Data Sheet
36
V1.2, 2011-03
XC835/836
Electrical Parameters
7) Timer 2 active current is measured with: module enabled, timer running in 8 MHz
8) MDU active current is measured with: module enabled, division operation was performed.
9) CORDIC active mode is measured with: module enabled, circular mode was selected for the calculation.
10) LEDTSCU active curent is measured with: module enabled, counter running in 8 MHz.
11) IIC active current is measured with: module enabled, performing a master transmit with the master clock
running at 400 KHz.
Data Sheet
37
V1.2, 2011-03
XC835/836
Electrical Parameters
3.3
AC Parameters
The electrical characteristics of the AC Parameters are detailed in this section.
3.3.1
Testing Waveforms
The testing waveforms for rise/fall time, output delay and output high impedance are
shown in Figure 11, Figure 12 and Figure 13.
VDDP
90%
90%
10%
10%
VSS
tF
tR
Figure 11
Rise/Fall Time Parameters
VDDP
VDDE / 2
VDDE / 2
Test Points
VSS
Figure 12
Testing Waveform, Output Delay
VLoad + 0.1 V
VLoad - 0.1 V
VOH - 0.1 V
VOL - 0.1 V
Timing
Reference
Points
Figure 13
Testing Waveform, Output High Impedance
Data Sheet
38
V1.2, 2011-03
XC835/836
Electrical Parameters
3.3.2
Output Rise/Fall Times
Table 18 provides the characteristics of the output rise/fall times in the XC835/836.
Table 18
Parameter
Output Rise/Fall Times Parameters (Operating Conditions apply)
Symbol Limit Values Unit Test Conditions
Min.
Max.
Rise/fall times on High
Current Pad Type A1)2)
tHCPR
tHCPF
,
–
–
–
–
–
–
15
ns
ns
ns
ns
ns
ns
20 pF @ Fast edge
(5 V) 3).
150
25
20 pF @ Slow Edge
(5 V)3).
20 pF @ Fast edge
(3.3 V)4).
300
10
20 pF @ Slow edge
(3.3 V)4).
Rise/fall times on High
Current Pad Type B1)2)
tR, tF
tR, tF
20 pF3)4)
(5 V & 3.3 V).
Rise/fall times on
10
20 pF3)4)
Standard Pad1)2)
(5 V & 3.3 V).
1) Rise/Fall time parameters are taken with 10% - 90% of supply.
2) Not all parameters are 100% tested, but are verified by design/characterisation and test correlation.
3) Additional rise/fall time valid for CL = 20 pF - CL = 100 pF @ 0.125 ns/pF at 5 V supply voltage.
4) Additional rise/fall time valid for CL = 20 pF - CL = 100 pF.@ 0.225 ns/pF at 3.3 V supply voltage.
V
DDC
90%
90%
10%
10%
V
SS
t
t
F
R
Figure 14
Rise/Fall Times Parameters
Data Sheet
39
V1.2, 2011-03
XC835/836
Electrical Parameters
3.3.3
Oscillator Timing and Wake-up Timing
Table 19 provides the characteristics of the power-on reset, PLL and wake-up timings in
the XC835/836.
Table 19
Power-On Reset Wake-up Timing1) (Operating Conditions apply)
Parameter
Symbol
Limit Values
Unit Test Conditions
Min. Typ. Max.
48 MHz Oscillator
start-up time
t48MOSCST CC –
–
–
–
13
800
1
µs
µs
s
75 KHz Oscillator start- t75KOSCST CC –
up time
32 KHz external
oscillator start-up
time2)
t32KOSCST CC –
Flash initialization time tFINT
CC –
160
–
µs
1) Not subject to production test, verified by design/characterisation.
2) The external circuitry has to be optimized by the user and checked for negative resistance as recommended
and specified by the crystal supplier.
Data Sheet
40
V1.2, 2011-03
XC835/836
Electrical Parameters
3.3.4
On-Chip Oscillator Characteristics
Table 20 provides the characteristics of the 48 MHz oscillator in the XC835/836.
Table 20
48 MHz Oscillator Characteristics (Operating Conditions apply)
Parameter
Symbol
Limit Values
Min. Typ. Max.
Nominal frequency fNOM CC -0.5 % 48
Unit Test Conditions
+0.5% MHz under nominal
conditions1) after
trimming
Long term
∆fLT CC -2.0
-4.5
–
–
–
3.0
4.5
1
%
%
%
with respect to fNOM, over
lifetime and temperature
(0 °C to 85 °C)
with respect to fNOM, over
lifetime and temperature
(-40 °C to 125 °C)
frequency deviation
Short term
∆fST CC -1
with respect to fNOM,
frequency deviation
within one LIN message
(< 10 ms … 100 ms)
(over VDDC
)
1) Nominal condition: VDDC = 2.5 V, TA = + 25°C.
Data Sheet
41
V1.2, 2011-03
XC835/836
Electrical Parameters
Table 21 provides the characteristics of the 75 kHz oscillator in the XC835/836.
Table 21
75 kHz Oscillator Characteristics (Operating Conditions apply)
Parameter
Symbol
Limit Values
Unit Test Conditions
Min. Typ. Max.
Nominal frequency
fNOM CC -1% 75
+1% KHz under nominal
conditions1) after trimming
Long term frequency ∆fLT CC -4.5 –
4.5
1.5
%
%
with respect to fNOM, over
lifetime and temperature
(-40 °C to 125 °C)
deviation
Short term frequency ∆fST CC -1.5 –
with respect to fNOM, over
deviation
VDDC
1) Nominal condition: VDDC = 2.5 V, TA = + 25°C.
Data Sheet
42
V1.2, 2011-03
XC835/836
Electrical Parameters
3.3.5
SSC Timing
3.3.5.1 SSC Master Mode Timing
Table 22 provides the SSC master mode timing in the XC835/836.
Table 22
SSC Master Mode Timing1) (Operating Conditions apply; CL = 50 pF)
Parameter
Symbol
Limit Values
Unit
Min.
2 * TSSC
0
Max.
–
3
2)
SCLK clock period
MTSR delay from SCLK
t0
t1
CC
ns
ns
CC
SR
SR
MRST set-up to SCLK
MRST hold from SCLK
t2
t3
32
0
–
–
ns
ns
1) Not subject to production test, verified by design/characterisation.
2) TSSCmin = TCPU = 1/fCPU. When fCPU = 24 MHz, t0 = 83.3 ns. TCPU is the CPU clock period.
t0
SCLK1)
t1
t1
1)
MTSR
t2
t3
Data
MRST1)
valid
t1
1) This timing is based on the following setup: CON.PH = CON.PO = 0.
SSC_Tmg1
Figure 15
SSC Master Mode Timing
Data Sheet
43
V1.2, 2011-03
XC835/836
Electrical Parameters
3.3.5.2 SSC Slave Mode Timing
Table 23 provides the SSC slave mode timing in the XC835/836.
Table 23
SSC Slave Mode Timing1) (Operating Conditions apply; CL = 50 pF)
Parameter
Symbol
Limit Values
Unit
Min.
4 * TSSC
0
Max.
–
29
2)
SCLK clock period
MRST delay from SCLK
t0
t1
SR
ns
ns
CC
SR
SR
MTSR set-up to SCLK
MTSR hold from SCLK
t2
t3
32
0
–
–
ns
ns
1) Not subject to production test, verified by design/characterisation.
2) TSSCmin = TCPU = 1/fCPU. When fCPU = 24 MHz, t0 = 166.7 ns. TCPU is the CPU clock period.
t0
SCLK1)
t2
t3
Data Valid
MTSR1)
MRST1)
t1
1)
This timing is based on the following setup : CON.PH = CON.PO = 0.
Figure 16
SSC Slave Mode Timing
Data Sheet
44
V1.2, 2011-03
XC835/836
Electrical Parameters
3.3.6
SPD Timing
The SPD interface will work with standard SPD tools having a sample/output clock fre-
quency deviation of +/- 5% or less. For further details please refer to application note
AP24004 in section SPD Timing Requirements.
Note: These parameters are no subject to product test but verified by design and/or
characterization.
Note: Operating Conditions apply.
Data Sheet
45
V1.2, 2011-03
XC835/836
Package and Quality Declaration
4
Package and Quality Declaration
Chapter 4 provides the information of the XC835/836 package and reliability section.
4.1
Package Parameters
Table 24 provides the thermal characteristics of the packages used in XC835 and
XC836 respectively.
Table 24
Parameter
Thermal Characteristics of the Packages
Symbol Limit Values
Unit Package Types
Min.
Max.
30.8
27.0
20.2
30.5
195.3
41
Thermalresistancejunction RTJC CC -
K/W PG-DSO-24-1
case1)
-
-
K/W PG-TSSOP-28-1
K/W PG-TSSOP-28-12
K/W PG-DSO-24-1
K/W PG-TSSOP-28-1
K/W PG-TSSOP-28-12
Thermalresistancejunction RTJL CC -
lead1)
-
-
1) The thermal resistances between the case and the ambient (RTCA) , the lead and the ambient (RTLA) are to be
combined with the thermal resistances between the junction and the case (RTJC), the junction and the lead
(RTJL) given above, in order to calculate the total thermal resistance between the junction and the ambient
(RTJA). The thermal resistances between the case and the ambient (RTCA), the lead and the ambient (RTLA
)
depend on the external system (PCB, case) characteristics, and are under user responsibility.
The junction temperature can be calculated using the following equation: TJ=TA+RTJA × PD, where the RTJA is
the total thermal resistance between the junction and the ambient. This total junction ambient resistance RTJA
can be obtained from the upper four partial thermal resistances, by
a) simply adding only the two thermal resistances (junction lead and lead ambient), or
b) by taking all four resistances into account, depending on the precision needed.
Data Sheet
46
V1.2, 2011-03
XC835/836
Package and Quality Declaration
4.2
Package Outline
Figure 17 and Figure 18 shows the package outlines of the XC835 (DSO-24-1) and
XC836 (TSSOP-28-1 and TSSOP-28-12) devices respectively.
Figure 17
PG-DSO-24-1 Package Outline
Data Sheet
47
V1.2, 2011-03
XC835/836
Package and Quality Declaration
Figure 18
PG-TSSOP-28-1 Package Outline
Data Sheet
48
V1.2, 2011-03
XC835/836
Package and Quality Declaration
Figure 19
PG-TSSOP-28-12 Package Outline
Data Sheet
49
V1.2, 2011-03
XC835/836
Package and Quality Declaration
4.3
Quality Declaration
Table 25 shows the characteristics of the quality parameters in the XC835/836.
Table 25
Parameter
Quality Parameters
Symbol Limit Values
Unit Notes
Min.
Max.
1500
15000
1500
Operation Lifetime when tOP1
-
-
-
-
hours TJ = 150°C
hours TJ = 110°C
hours TJ = -40°C
the device is used at the
1)
three stated TJ
Operation Lifetime when tOP2
131400 hours TJ = 27°C
the device is used at the
1)
stated TJ
ESD susceptibility
according to Human Body
Model (HBM)
ESD susceptibility
according to Charged
Device Model (CDM) pins
VHBM
-
-
2000
500
V
V
Conforming to
EIA/JESD22-
A114-B2)
VCDM
Conforming to
JESD22-C101-C2)
1) This lifetime refers only to the time when device is powered-on.
2) Not all parameters are 100% tested, but are verified by design/characterisation and test correlation.
Data Sheet
50
V1.2, 2011-03
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
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