XC866-4RR [INFINEON]
8-Bit Single-Chip Microcontroller; 8位单芯片微控制器
| 型号： | XC866-4RR |
| 厂家： | 
Infineon |
| 描述： | 8-Bit Single-Chip Microcontroller |
| 文件： | 总108页 (文件大小：1533K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet, V1.0, Feb 2006
XC866
8-Bit Single-Chip Microcontroller
Microcontrollers
Edition 2006-02
Published by Infineon Technologies AG,
81726 München, Germany
© Infineon Technologies AG 2006.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Data Sheet, V1.0, Feb 2006
XC866
8-Bit Single-Chip Microcontroller
Microcontrollers
XC866 Data Sheet
Revision History:
2006-02
V1.0
Previous Version: V 0.1, 2005-01
Page
3
Subjects (major changes since last revision)
LIN support is elaborated in Table 1.
Section 3.2 is updated.
Section 3.3 is updated.
Section 3.4 is updated.
The power-on reset requirements are updated in Section 3.7.
Section 3.7 is updated.
Table 19 is updated with a new range of the fVCOFREE parameter.
Section 3.12 is updated.
Section 3.13 is updated.
Figure 34 is updated with the removal of OCDS interrupt.
Section 4.1.2 is updated.
Section 4.1.3 is updated.
Section 4.2.1 is updated.
Section 4.2.2 is updated.
Section 4.2.4 is updated.
“Testing Waveforms” is updated in Section 4.3.1.
Section 4.3.3 is updated.
Figure 40 is updated.
13
34
37
49
49
54
65
66
78
81
82
83
87
91
95
97
102
103
“Quality Declaration” is updated in Section 5.2.
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
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8-Bit Single-Chip Microcontroller
XC800 Family
XC866
1
Summary of Features
• High-performance XC800 Core
– compatible with standard 8051 processor
– two clocks per machine cycle architecture (for memory access without wait state)
– two data pointers
• On-chip memory
– 8 Kbytes of Boot ROM
– 256 bytes of RAM
– 512 bytes of XRAM
– 8/16 Kbytes of Flash; or
8/16 Kbytes of ROM, with additional 4 Kbytes of Flash
(includes memory protection strategy)
• I/O port supply at 3.3 V/5.0 V and core logic supply at 2.5 V (generated by embedded
voltage regulator)
(further features are on next page)
Flash or ROM1)
On-Chip Debug Support
XC800 Core
UART
SSC
Port 0
Port 1
Port 2
Port 3
6-bit Digital I/O
8K/16K x 8
Boot ROM
Capture/Compare Unit
16-bit
5-bit Digital I/O
8K x 8
XRAM
512 x 8
Compare Unit
16-bit
8-bit Digital/Analog Input
8-bit Digital I/O
ADC
Watchdog
10-bit
RAM
Timer 0
16-bit
Timer 1
16-bit
Timer 2
16-bit
256 x 8
Timer
8-channel
1) All ROM devices include 4K x 8 Flash
Figure 1
XC866 Functional Units
Data Sheet
1
V1.0, 2006-02
XC866
Summary of Features
Features (continued):
• Power-on reset generation
• Brownout detection for core logic supply
• On-chip OSC and PLL for clock generation
– PLL loss-of-lock detection
• Power saving modes
– slow-down mode
– idle mode
– power-down mode with wake-up capability via RXD or EXINT0
– clock gating control to each peripheral
• Programmable 16-bit Watchdog Timer (WDT)
• Four ports
– 19 pins as digital I/O
– 8 pins as digital/analog input
• 8-channel, 10-bit ADC
• Three 16-bit timers
– Timer 0 and Timer 1 (T0 and T1)
– Timer 2
• Capture/compare unit for PWM signal generation (CCU6)
• Full-duplex serial interface (UART)
• Synchronous serial channel (SSC)
• On-chip debug support
– 1 Kbyte of monitor ROM (part of the 8-Kbyte Boot ROM)
– 64 bytes of monitor RAM
• PG-TSSOP-38 pin package
• Temperature range TA:
– SAF (-40 to 85 °C)
– SAK (-40 to 125 °C)
Data Sheet
2
V1.0, 2006-02
XC866
Summary of Features
XC866 Variant Devices
The XC866 product family features eight devices with different configurations and
program memory sizes, offering cost-effective solution for different application
requirements.
The list of XC866 devices and their differences are summarized in Table 1.
Table 1
Device Summary
Device Type Device Name
Flash Size
ROM Size
LIN BSL
Support
Flash
ROM
XC866L-4FR
XC866-4FR
XC866L-2FR
XC866-2FR
XC866L-4RR
XC866-4RR
XC866L-2RR
XC866-2RR
16 Kbytes
16 Kbytes
8 Kbytes
8 Kbytes
4 Kbytes
4 Kbytes
4 Kbytes
4 Kbytes
–
–
–
–
Yes
No
Yes
No
Yes
No
Yes
No
16 Kbytes
16 Kbytes
8 Kbytes
8 Kbytes
Ordering Information
The ordering code for Infineon Technologies microcontrollers provides an exact
reference to the required product. This ordering code indentifies:
• The derivative itself, i.e. its function set
• the specified temperature range
• the package and the type of delivery
For the available ordering codes for the XC866, please refer to the “Product Catalog
Microcontrollers” which summarizes all available microcontroller variants.
Note: The ordering codes for the Mask-ROM versions are defined for each product after
verification of the respective ROM code.
Data Sheet
3
V1.0, 2006-02
XC866
General Device Information
2
General Device Information
2.1
Block Diagram
XC866
Internal Bus
8-Kbyte
Boot ROM1)
XC800 Core
P0.0 - P0.5
256-byte RAM
+
T0 & T1
UART
64-byte monitor
RAM
P1.0 - P1.1
P1.5-P1.7
TMS
MBC
RESET
VDDP
VSSP
VDDC
VSSC
CCU6
SSC
512-byte XRAM
P2.0 - P2.7
8/16-Kbyte
Flash or ROM2)
Timer 2
WDT
VAREF
VAGND
ADC
Clock Generator
XTAL1
XTAL2
10 MHz
On-chip OSC
P3.0 - P3.7
OCDS
PLL
1) Includes 1-Kbyte monitor ROM
2) Includes additional 4-Kbyte Flash
Figure 2
XC866 Block Diagram
Data Sheet
4
V1.0, 2006-02
XC866
General Device Information
2.2
Logic Symbol
VDDP
VSSP
VAREF
VAGND
Port 0 6-Bit
Port 1 5-Bit
Port 2 8-Bit
Port 3 8-Bit
RESET
MBC
XC866
TMS
XTAL1
XTAL2
VDDC
VSSC
Figure 3
XC866 Logic Symbol
Data Sheet
5
V1.0, 2006-02
XC866
General Device Information
2.3
Pin Configuration
MBC
1
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
RESET
P0.3/SCLK_1/COUT63_1
2
P3.5/COUT62_0
P3.4/CC62_0
P0.4/MTSR_1/CC62_1
3
P0.5/MRST_1/EXINT0_0/COUT62_1
4
P3.3/COUT61_0
P3.2/CCPOS2_2/CC61_0
P3.1/CCPOS0_2/CC61_2/COUT60_0
P3.0/CCPOS1_2/CC60_0
P3.7/EXINT4/COUT63_0
P3.6/CTRAP_0
XTAL2
5
XTAL1
6
VSSC
VDDC
7
8
P1.6/CCPOS1_1/T12HR_0/EXINT6
P1.7/CCPOS2_1/T13HR_0
9
10
11
12
13
14
15
16
17
18
19
P1.5/CCPOS0_1/EXINT5/EXF2_0/RXDO_0
P1.1/EXINT3/TDO_1/TXD_0
P1.0/RXD_0/T2EX
P2.7/AN7
XC866
TMS
P0.0/TCK_0/T12HR_1/CC61_1/CLKOUT/RXDO_1
P0.2/CTRAP_2/TDO_0/TXD_1
P0.1/TDI_0/T13HR_1/RXD_1/EXF2_1/COUT61_1
P2.0/CCPOS0_0/EXINT1/T12HR_2/TCK_1/CC61_3/AN0
P2.1/CCPOS1_0/EXINT2/T13HR_2/TDI_1/CC62_3/AN1
P2.2/CCPOS2_0/CTRAP_1/CC60_3/AN2
VDDP
VAREF
VAGND
P2.6/AN6
P2.5/AN5
P2.4/AN4
VSSP
P2.3/AN3
Figure 4
XC866 Pin Configuration, PG-TSSOP-38 Package (top view)
Data Sheet
6
V1.0, 2006-02
XC866
General Device Information
2.4
Pin Definitions and Functions
Pin Definitions and Functions
Table 2
Symbol Pin
Type Reset Function
Number
State
P0
I/O
Port 0
Port 0 is a 6-bit bidirectional general purpose I/O
port. It can be used as alternate functions for the
JTAG, CCU6, UART, and the SSC.
P0.0
12
14
13
Hi-Z
Hi-Z
PU
TCK_0
JTAG Clock Input
T12HR_1
CCU6 Timer 12 Hardware Run
Input
CC61_1
Input/Output of Capture/Compare
channel 1
CLKOUT
RXDO_1
TDI_0
T13HR_1
Clock Output
UART Transmit Data Output
P0.1
P0.2
JTAG Serial Data Input
CCU6 Timer 13 Hardware Run
Input
RXD_1
UART Receive Data Input
COUT61_1 Output of Capture/Compare
channel 1
EXF2_1
Timer 2 External Flag Output
CTRAP_2
TDO_0
TXD_1
CCU6 Trap Input
JTAG Serial Data Output
UART Transmit Data Output/
Clock Output
P0.3
P0.4
2
3
Hi-Z
Hi-Z
SCK_1
SSC Clock Input/Output
COUT63_1 Output of Capture/Compare
channel 3
MTSR_1
SSC Master Transmit Output/
Slave Receive Input
Input/Output of Capture/Compare
channel 2
CC62_1
P0.5
4
Hi-Z
MRST_1
SSC Master Receive Input/
Slave Transmit Output
EXINT0_0 External Interrupt Input 0
COUT62_1 Output of Capture/Compare
channel 2
Data Sheet
7
V1.0, 2006-02
XC866
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin
Type Reset Function
Number
State
P1
I/O
Port 1
Port 1 is a 5-bit bidirectional general purpose I/O
port. It can be used as alternate functions for the
JTAG, CCU6, UART, and the SSC.
P1.0
P1.1
27
28
PU
PU
RXD_0
T2EX
EXINT3
TDO_1
TXD_0
UART Receive Data Input
Timer 2 External Trigger Input
External Interrupt Input 3
JTAG Serial Data Output
UART Transmit Data Output/
Clock Output
P1.5
P1.6
P1.7
29
9
PU
PU
PU
CCPOS0_1 CCU6 Hall Input 0
EXINT5
EXF2_0
RXDO_0
External Interrupt Input 5
TImer 2 External Flag Output
UART Transmit Data Output
CCPOS1_1 CCU6 Hall Input 1
T12HR_0
CCU6 Timer 12 Hardware Run
Input
EXINT6
External Interrupt Input 6
10
CCPOS2_1 CCU6 Hall Input 2
T13HR_0 CCU6 Timer 13 Hardware Run
Input
P1.5 and P1.6 can be used as a software chip
select output for the SSC.
Data Sheet
8
V1.0, 2006-02
XC866
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin
Type Reset Function
Number
State
P2
I
Port 2
Port 2 is an 8-bit general purpose input-only port. It
can be used as alternate functions for the digital
inputs of the JTAG and CCU6. It is also used as the
analog inputs for the ADC.
P2.0
P2.1
P2.2
15
16
17
Hi-Z
CCPOS0_0 CCU6 Hall Input 0
EXINT1
External Interrupt Input 1
CCU6 Timer 12 Hardware Run
Input
T12HR_2
TCK_1
CC61_3
AN0
JTAG Clock Input
Input of Capture/Compare channel 1
Analog Input 0
Hi-Z
Hi-Z
CCPOS1_0 CCU6 Hall Input 1
EXINT2
External Interrupt Input 2
T13HR_2
CCU6 Timer 13 Hardware Run
Input
TDI_1
CC62_3
AN1
JTAG Serial Data Input
Input of Capture/Compare channel 2
Analog Input 1
CCPOS2_0 CCU6 Hall Input 2
CTRAP_1
CC60_3
AN2
CCU6 Trap Input
Input of Capture/Compare channel 0
Analog Input 2
P2.3
P2.4
P2.5
P2.6
P2.7
20
21
22
23
26
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
AN3
AN4
AN5
AN6
AN7
Analog Input 3
Analog Input 4
Analog Input 5
Analog Input 6
Analog Input 7
Data Sheet
9
V1.0, 2006-02
XC866
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin
Type Reset Function
Number
State
P3
I
Port 3
Port 3 is a bidirectional general purpose I/O port. It
can be used as alternate functions for the CCU6.
P3.0
P3.1
32
33
Hi-Z
Hi-Z
CCPOS1_2 CCU6 Hall Input 1
CC60_0
Input/Output of Capture/Compare
channel 0
CCPOS0_2 CCU6 Hall Input 0
CC61_2 Input/Output of Capture/Compare
channel 1
COUT60_0 Output of Capture/Compare
channel 0
P3.2
34
Hi-Z
CCPOS2_2 CCU6 Hall Input 2
CC61_0
Input/Output of Capture/Compare
channel 1
P3.3
P3.4
P3.5
35
36
37
Hi-Z
Hi-Z
Hi-Z
COUT61_0 Output of Capture/Compare
channel 1
CC62_0
Input/Output of Capture/Compare
channel 2
COUT62_0 Output of Capture/Compare
channel 2
P3.6
P3.7
30
31
PD
Hi-Z
CTRAP_0
EXINT4
CCU6 Trap Input
External Interrupt Input 4
COUT63_0 Output of Capture/Compare
channel 3
Data Sheet
10
V1.0, 2006-02
XC866
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin
Type Reset Function
Number
State
VDDP
VSSP
VDDC
VSSC
VAREF
18
19
8
7
25
–
–
–
–
–
–
I
–
–
–
–
–
–
Hi-Z
I/O Port Supply (3.3 V/5.0 V)
I/O Port Ground
Core Supply Monitor (2.5 V)
Core Supply Ground
ADC Reference Voltage
ADC Reference Ground
VAGND 24
XTAL1
XTAL2
TMS
RESET 38
MBC
6
External Oscillator Input
(NC if not needed)
5
O
Hi-Z
External Oscillator Output
(NC if not needed)
Test Mode Select
Reset Input
Monitor & BootStrap Loader Control
11
I
I
I
PD
PU
PU
1
Data Sheet
11
V1.0, 2006-02
XC866
Functional Description
3
Functional Description
3.1
Processor Architecture
The XC866 is based on a high-performance 8-bit Central Processing Unit (CPU) that is
compatible with the standard 8051 processor. While the standard 8051 processor is
designed around a 12-clock machine cycle, the XC866 CPU uses a 2-clock machine
cycle. This allows fast access to ROM or RAM memories without wait state. Access to
the Flash memory, however, requires an additional wait state (one machine cycle). The
instruction set consists of 45% one-byte, 41% two-byte and 14% three-byte instructions.
The XC866 CPU provides a range of debugging features, including basic stop/start,
single-step execution, breakpoint support and read/write access to the data memory,
program memory and SFRs.
Figure 5 shows the CPU functional blocks.
Internal Data
Memory
Core SFRs
Register Interface
External Data
Memory
External SFRs
16-bit Registers &
Memory Interface
ALU
Program Memory
Opcode &
Immediate
Registers
Multiplier / Divider
Opcode Decoder
Timer 0 / Timer 1
UART
fCCLK
Memory Wait
Reset
State Machine &
Power Saving
Legacy External Interrupts (IEN0, IEN1)
External Interrupts
Interrupt
Controller
Non-Maskable Interrupt
Figure 5
CPU Block Diagram
Data Sheet
12
V1.0, 2006-02
XC866
Functional Description
3.2
Memory Organization
The XC866 CPU operates in the following five address spaces:
• 8 Kbytes of Boot ROM program memory
• 256 bytes of internal RAM data memory
• 512 bytes of XRAM memory
(XRAM can be read/written as program memory or external data memory)
• a 128-byte Special Function Register area
• 8/16 Kbytes of Flash program memory (Flash devices); or
8/16 Kbytes of ROM program memory, with additional 4 Kbytes of Flash
(ROM devices)
Figure 6 illustrates the memory address spaces of the 16-Kbyte Flash devices. For the
8-Kbyte Flash devices, the shaded banks are not available.
FFFFH
FFFFH
F200H
F000H
F200H
F000H
XRAM
XRAM
512 bytes
512 bytes
E000H
Boot ROM
8 Kbytes
C000H
B000H
A000H
D-Flash Bank
4 Kbytes
Indirect
Direct
3000H
2000H
1000H
0000H
Address
Address
P-Flash Bank 2
4 Kbytes
FFH
80H
Special Function
Registers
Internal RAM
P-Flash Bank 1
4 Kbytes
7FH
00H
P-Flash Bank 0
4 Kbytes
Internal RAM
0000H
Program Space
External Data Space
Internal Data Space
Figure 6
Memory Map of XC866 Flash Device
Data Sheet
13
V1.0, 2006-02
XC866
Functional Description
3.2.1
Memory Protection Strategy
The XC866 memory protection strategy includes:
• Read-out protection: The user is able to protect the contents in the Flash (for Flash
devices) and ROM (for ROM devices) memory from being read
• Flash program and erase protection (for Flash devices only)
Flash memory protection modes are available only for Flash devices:
• Mode 0: Only the P-Flash is protected; the D-Flash is unprotected
• Mode 1: Both the P-Flash and D-Flash are protected
The selection of each protection mode and the restrictions imposed are summarized in
Table 3.
Table 3
Flash Protection Modes
Mode
0
1
Activation
Selection
Program a valid password via BSL mode 6
MSB of password = 0 MSB of password = 1
P-Flashcontents Read instructions in the
Read instructions in the
P-Flash or D-Flash
can be read by P-Flash
P-Flash program Not possible
Not possible
and erase
D-Flashcontents Read instructions in any program
Read instructions in the
P-Flash or D-Flash
can be read by
memory
D-Flash program Possible
D-Flash erase
Not possible
Not possible
Possible, on the condition that bit
DFLASHEN in register MISC_CON
is set to 1 prior to each erase
operation
BSL mode 6, which is used for enabling Flash protection, can also be used for disabling
Flash protection. Here, the programmed password must be provided by the user. A
password match triggers an automatic erase of the protected P-Flash and D-Flash
contents, including the programmed password. The Flash protection is then disabled
upon the next reset.
Although no protection scheme can be considered infallible, the XC866 memory
protection strategy provides a very high level of protection for a general purpose
microcontroller.
Note: If ROM read-out protection is enabled, only read instructions in the ROM memory
can target the ROM contents.
Data Sheet
14
V1.0, 2006-02
XC866
Functional Description
3.2.2
Special Function Register
The Special Function Registers (SFRs) occupy direct internal data memory space in the
range 80H to FFH. All registers, except the program counter, reside in the SFR area. The
SFRs include pointers and registers that provide an interface between the CPU and the
on-chip peripherals. As the 128-SFR range is less than the total number of registers
required, address extension mechanisms are required to increase the number of
addressable SFRs. The address extension mechanisms include:
• Mapping
• Paging
3.2.2.1 Address Extension by Mapping
Address extension is performed at the system level by mapping. The SFR area is
extended into two portions: the standard (non-mapped) SFR area and the mapped SFR
area. Each portion supports the same address range 80H to FFH, bringing the number
of addressable SFRs to 256. The extended address range is not directly controlled by
the CPU instruction itself, but is derived from bit RMAP in the system control register
SYSCON0 at address 8FH. To access SFRs in the mapped area, bit RMAP in SFR
SYSCON0 must be set. Alternatively, the SFRs in the standard area can be accessed
by clearing bit RMAP. The SFR area can be selected as shown in Figure 7.
SYSCON0
System Control Register 0
Reset Value: 00H
7
6
5
4
3
2
1
0
0
1
0
RMAP
r
rw
r
rw
Field
Bits
Type Description
RMAP
0
rw
Special Function Register Map Control
0
The access to the standard SFR area is
enabled.
1
The access to the mapped SFR area is
enabled.
1
0
2
rw
r
Reserved
Returns the last value if read; should be written
with 1.
1,[7:3]
Reserved
Returns 0 if read; should be written with 0.
Data Sheet
15
V1.0, 2006-02
XC866
Functional Description
Note: The RMAP bit must be cleared/set by ANL or ORL instructions. The rest bits of
SYSCON0 should not be modified.
As long as bit RMAP is set, the mapped SFR area can be accessed. This bit is not
cleared automatically by hardware. Thus, before standard/mapped registers are
accessed, bit RMAP must be cleared/set, respectively, by software.
Standard Area (RMAP = 0)
FFH
Module 1 SFRs
SYSCON0.RMAP
Module 2 SFRs
Module n SFRs
rw
80H
FFH
SFR Data
(to/from CPU)
Mapped Area (RMAP = 1)
Module (n+1) SFRs
Module (n+2) SFRs
Module m SFRs
80H
Direct
Internal Data
Memory Address
Figure 7
Address Extension by Mapping
Data Sheet
16
V1.0, 2006-02
XC866
Functional Description
3.2.2.2 Address Extension by Paging
Address extension is further performed at the module level by paging. With the address
extension by mapping, the XC866 has a 256-SFR address range. However, this is still
less than the total number of SFRs needed by the on-chip peripherals. To meet this
requirement, some peripherals have a built-in local address extension mechanism for
increasing the number of addressable SFRs. The extended address range is not directly
controlled by the CPU instruction itself, but is derived from bit field PAGE in the module
page register MOD_PAGE. Hence, the bit field PAGE must be programmed before
accessing the SFR of the target module. Each module may contain a different number
of pages and a different number of SFRs per page, depending on the specific
requirement. Besides setting the correct RMAP bit value to select the SFR area, the user
must also ensure that a valid PAGE is selected to target the desired SFR. A page inside
the extended address range can be selected as shown in Figure 8.
SFR Address
(from CPU)
PAGE 0
MOD_PAGE.PAGE
SFR0
rw
SFR1
SFRx
PAGE 1
SFR0
SFR Data
SFR1
(to/from CPU)
SFRy
PAGE q
SFR0
SFR1
SFRz
Module
Figure 8
Address Extension by Paging
Data Sheet
17
V1.0, 2006-02
XC866
Functional Description
In order to access a register located in a page different from the actual one, the current
page must be left. This is done by reprogramming the bit field PAGE in the page register.
Only then can the desired access be performed.
If an interrupt routine is initiated between the page register access and the module
register access, and the interrupt needs to access a register located in another page, the
current page setting can be saved, the new one programmed and finally, the old page
setting restored. This is possible with the storage fields STx (x = 0 - 3) for the save and
restore action of the current page setting. By indicating which storage bit field should be
used in parallel with the new page value, a single write operation can:
• Save the contents of PAGE in STx before overwriting with the new value
(this is done in the beginning of the interrupt routine to save the current page setting
and program the new page number); or
• Overwrite the contents of PAGE with the contents of STx, ignoring the value written to
the bit positions of PAGE
(this is done at the end of the interrupt routine to restore the previous page setting
before the interrupt occurred)
ST3
ST2
ST1
ST0
STNR
PAGE
value update
from CPU
Figure 9
Storage Elements for Paging
With this mechanism, a certain number of interrupt routines (or other routines) can
perform page changes without reading and storing the previously used page information.
The use of only write operations makes the system simpler and faster. Consequently,
this mechanism significantly improves the performance of short interrupt routines.
The XC866 supports local address extension for:
• Parallel Ports
• Analog-to-Digital Converter (ADC)
• Capture/Compare Unit 6 (CCU6)
• System Control Registers
Data Sheet
18
V1.0, 2006-02
XC866
Functional Description
The page register has the following definition:
MOD_PAGE
Page Register for module MOD
Reset Value: 00H
7
6
5
4
3
2
1
0
OP
STNR
0
PAGE
w
w
r
rw
Field
PAGE
Bits Type Description
[2:0] rw Page Bits
When written, the value indicates the new page.
When read, the value indicates the currently active
page.
STNR
[5:4]
w
Storage Number
This number indicates which storage bit field is the
target of the operation defined by bit field OP.
If OP = 10 ,
B
the contents of PAGE are saved in STx before being
overwritten with the new value.
If OP = 11 ,
B
the contents of PAGE are overwritten by the
contents of STx. The value written to the bit positions
of PAGE is ignored.
00
01
10
11
ST0 is selected.
ST1 is selected.
ST2 is selected.
ST3 is selected.
Data Sheet
19
V1.0, 2006-02
XC866
Functional Description
Field
OP
Bits Type Description
[7:6] w Operation
0X Manual page mode. The value of STNR is
ignored and PAGE is directly written.
10
New page programming with automatic page
saving. The value written to the bit positions of
PAGE is stored. In parallel, the previous
contents of PAGE are saved in the storage bit
field STx indicated by STNR.
11
Automatic restore page action. The value
written to the bit positions PAGE is ignored
and instead, PAGE is overwritten by the
contents of the storage bit field STx indicated
by STNR.
0
3
r
Reserved
Returns 0 if read; should be written with 0.
Data Sheet
20
V1.0, 2006-02
XC866
Functional Description
3.2.3
Bit Protection Scheme
The bit protection scheme prevents direct software writing of selected bits (i.e., protected
bits) using the PASSWD register. When the bit field MODE is 11 , writing 10011 to the
B
B
bit field PASS opens access to writing of all protected bits, and writing 10101 to the bit
B
field PASS closes access to writing of all protected bits. Note that access is opened for
maximum 32 CCLKs if the “close access” password is not written. If “open access”
password is written again before the end of 32 CCLK cycles, there will be a recount of
32 CCLK cycles. The protected bits include NDIV, WDTEN, PD, and SD.
PASSWD
Password Register
Reset Value: 07H
7
6
5
4
3
2
1
0
PROTECT
PASS
MODE
_S
wh
rh
rw
Field
Bits Type Description
MODE
[1:0] rw
Bit Protection Scheme Control bits
00
11
Scheme Disabled
Scheme Enabled (default)
Others: Scheme Enabled
These two bits cannot be written directly. To change
the value between 11 and 00 , the bit field PASS
B
B
must be written with 11000 ; only then, will the
B
MODE[1:0] be registered.
PROTECT_S
PASS
2
rh
Bit Protection Signal Status bit
This bit shows the status of the protection.
0
1
Software is able to write to all protected bits.
Software is unable to write to any protected
bits.
[7:3] wh
Password bits
The Bit Protection Scheme only recognizes three
patterns.
11000 Enables writing of the bit field MODE.
B
10011 Opens access to writing of all protected bits.
B
10101 Closes access to writing of all protected bits.
B
Data Sheet
21
V1.0, 2006-02
XC866
Functional Description
3.2.4
XC866 Register Overview
The SFRs of the XC866 are organized into groups according to their functional units. The
contents (bits) of the SFRs are summarized in Table 4 to Table 12, with the addresses
of the bitaddressable SFRs appearing in bold typeface.
The CPU SFRs can be accessed in both the standard and mapped memory areas
(RMAP = 0 or 1).
Table 4
CPU Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 0 or 1
81
82
83
87
88
89
SP
Reset: 07
Reset: 00
Reset: 00
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
SP
rw
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Stack Pointer Register
DPL
DPL7 DPL6 DPL5 DPL4 DPL3 DPL2 DPL1 DPL0
rw rw rw rw rw rw rw rw
DPH7 DPH6 DPH5 DPH4 DPH3 DPH2 DPH1 DPH0
Data Pointer Register Low
DPH
Data Pointer Register High
rw
SMOD
rw
TF1
rwh
rw
rw
0
r
TF0
rwh
rw
rw
GF1
rw
IE1
rwh
rw
GF0
rw
IT1
rw
0
rw
0
r
IE0
rwh
rw
IDLE
rw
IT0
rw
PCON
Reset: 00
Power Control Register
TCON
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
TR1
rw
0
TR0
rw
Timer Control Register
TMOD
GATE1
rw
T1M
rw
GATE0
rw
VAL
rwh
VAL
rwh
VAL
rwh
VAL
rwh
T0M
rw
Timer Mode Register
r
r
8A
8B
TL0
H
Timer 0 Register Low
TL1
H
Timer 1 Register Low
8C
8D
TH0
H
Timer 0 Register High
TH1
H
Timer 1 Register High
98
SCON
SM0
rw
SM1
rw
SM2
rw
REN
rw
TB8
rw
RB8
rwh
TI
rwh
RI
rwh
H
Serial Channel Control Register
99
SBUF
Reset: 00
VAL
rwh
TRAP_
H
Serial Data Buffer Register
A2
EO
Reset: 00
Bit Field
0
0
DPSEL
0
rw
EX0
rw
PX0
rw
H
Extended Operation Register
EN
rw
ES
rw
PS
rw
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
r
0
r
r
A8
B8
IEN0
Reset: 00
EA
rw
ET2
rw
PT2
rw
ET1
rw
PT1
rw
EX1
rw
PX1
rw
ET0
rw
PT0
rw
H
H
H
H
Interrupt Enable Register 0
IP
Reset: 00
0
H
Interrupt Priority Register
r
0
r
B9
D0
IPH
Reset: 00
PT2H PSH PT1H PX1H PT0H PX0H
H
H
H
H
Interrupt Priority Register High
rw
F0
rwh
rw
RS1
rw
rw
RS0
rw
rw
OV
rwh
rw
F1
rwh
rw
P
rh
PSW
Reset: 00
CY
rw
AC
rwh
H
H
H
Program Status Word Register
E0
E8
ACC
Reset: 00
ACC7 ACC6 ACC5 ACC4 ACC3 ACC2 ACC1 ACC0
rw rw rw rw rw rw rw rw
EX2 ESSC EADC
Accumulator Register
IEN1
Reset: 00
Bit Field
ECCIP ECCIP ECCIP ECCIP EXM
Interrupt Enable Register 1
3
2
1
0
Type
rw
rw
rw
rw
rw
rw
rw
rw
Data Sheet
22
V1.0, 2006-02
XC866
Functional Description
Table 4
CPU Register Overview (cont’d)
Addr Register Name
Bit
7
B7
rw
6
B6
rw
5
B5
rw
4
B4
rw
3
2
1
0
F0
B
Reset: 00
Bit Field
Type
B3
rw
B2
rw
B1
rw
B0
rw
H
H
H
B Register
F8
IP1
Reset: 00
Bit Field
PCCIP PCCIP PCCIP PCCIP PXM
PX2 PSSC PADC
H
Interrupt Priority Register 1
3
2
1
0
Type
rw
rw
rw
rw
rw
rw rw rw
F9
IPH1
Reset: 00
Bit Field
PCCIP PCCIP PCCIP PCCIP PXMH PX2H PSSCH PADC
H
H
Interrupt Priority Register 1 High
3H
rw
2H
rw
1H
rw
0H
rw
H
Type
rw
rw
rw
rw
The system control SFRs can be accessed in the standard memory area (RMAP = 0).
Table 5
System Control Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 0 or 1
8F
SYSCON0
Reset: 00
Bit Field
Type
0
r
RMAP
rw
H
H
H
System Control Register 0
RMAP = 0
BF
SCU_PAGE
Reset: 00
Bit Field
Type
OP
w
STNR
w
0
r
PAGE
rw
H
Page Register for System Control
RMAP = 0, Page 0
B3
B4
B5
B7
MODPISEL
Reset: 00
Bit Field
0
r
JTAG JTAG
TDIS TCKS
0
r
EXINT URRIS
0IS
H
H
H
H
H
H
H
Peripheral Input Select Register
Type
Bit Field
rw
rw
rw
rw
IRCON0
Reset: 00
0
r
EXINT EXINT EXINT EXINT EXINT EXINT EXINT
Interrupt Request Register 0
6
rwh
0
5
4
3
rwh
2
rwh
RIR
1
0
Type
Bit Field
rwh
rwh
rwh
TIR
rwh
EIR
IRCON1
Reset: 00
ADCS ADCS
Interrupt Request Register 1
RC1
rwh
RC0
rwh
Type
Bit Field
Type
Bit Field
Type
Bit Field
r
rwh
rwh
rwh
EXICON0
Reset: 00
EXINT3
rw
0
EXINT2
EXINT1
EXINT0
H
H
H
External Interrupt Control Register 0
rw
EXINT6
rw
rw
EXINT5
rw
rw
EXINT4
rw
BA
EXICON1
Reset: 00
H
H
External Interrupt Control Register 1
r
BB
NMICON
Reset: 00
Reset: 00
Reset: 00
0
NMI
ECC VDDP VDD OCDS FLASH PLL
rw rw rw rw rw rw
NMI
NMI
NMI
NMI
NMI
NMI
NMI Control Register
WDT
Type
Bit Field
r
0
rw
BC
BD
NMISR
FNMI FNMI FNMI FNMI FNMI FNMI FNMI
H
H
NMI Status Register
ECC VDDP VDD OCDS FLASH PLL
WDT
rwh
R
Type
Bit Field
Type
Bit Field
Type
Bit Field
r
rwh
rwh
0
r
rwh
BREN
rw
rwh
rwh
BRPRE
rw
rwh
BCON
BGSEL
rw
H
H
H
H
H
H
Baud Rate Control Register
rw
BE
BG
Reset: 00
BR_VALUE
rw
Baud Rate Timer/Reload Register
E9
FDCON
Reset: 00
BGS SYNEN ERRSY EOFSY BRK NDOV FDM FDEN
Fractional Divider Control Register
N
N
Type
rw
rw
rwh
rwh
rwh
rwh
rw
rw
EA
EB
FDSTEP
Reset: 00
Bit Field
Type
Bit Field
Type
STEP
H
H
Fractional Divider Reload Register
rw
RESULT
rh
FDRES Reset: 00
H
H
Fractional Divider Result Register
RMAP = 0, Page 1
Data Sheet
23
V1.0, 2006-02
XC866
Functional Description
Table 5
System Control Register Overview (cont’d)
Addr Register Name
Bit
7
6
5
4
3
2
1
VERID
r
0
B3
ID
Reset: 01
Bit Field
Type
Bit Field
PRODID
r
WDT WKRS WK
H
H
H
Identity Register
B4
PMCON0
Reset: 00
0
r
SD
rw
PD
WS
H
Power Mode Control Register 0
RST
rwh
SEL
rw
Type
rwh
rwh
rw
B5
B6
B7
PMCON1
Reset: 00
Bit Field
0
r
T2_DIS CCU
SSC
_DIS
rw
ADC
_DIS
rw
H
H
H
H
H
H
H
H
Power Mode Control Register 1
_DIS
Type
Bit Field
rw
rw
OSC_CON
Reset: 08
0
r
OSC
PD
rw
XPD
OSC
ORD OSCR
OSC Control Register
SS
RES
Type
Bit Field
rw
rw
rwh
rh
PLL_CON
Reset: 20
Reset: 00
Reset: 07
Reset: 00
NDIV
rw
VCO
OSC RESLD LOCK
PLL Control Register
BYP
DISC
Type
Bit Field
rw
rw
rwh
rh
BA
BB
CMCON
VCO
SEL
rw
0
r
CLKREL
H
Clock Control Register
Type
Bit Field
rw
PASSWD
PASS
PROTE
MODE
rw
H
Password Register
CT_S
rh
Type
Bit Field
Type
Bit Field
Type
Bit Field
wh
BC
BD
FEAL
ECCERRADDR[7:0]
rh
ECCERRADDR[15:8]
rh
H
H
H
H
H
H
Flash Error Address Register Low
FEAH
Reset: 00
Flash Error Address Register High
BE
COCON Reset: 00
0
r
TLEN COUT
COREL
rw
Clock Output Control Register
S
rw
0
Type
Bit Field
rw
E9
MISC_CON
Reset: 00
DFLAS
H
H
H
Miscellaneous Control Register
HEN
rwh
Type
r
RMAP = 0, Page 3
B3 XADDRH
Reset: F0
Bit Field
Type
ADDRH
rw
H
On-Chip XRAM Address Higher Order
The WDT SFRs can be accessed in the mapped memory area (RMAP = 1).
Table 6
WDT Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 1
BB
WDTCON
Reset: 00
Bit Field
0
r
WINB WDT
0
WDT
EN
rw
WDT
RS
rwh
WDT
IN
rw
H
H
Watchdog Timer Control Register
EN
rw
PR
rh
Type
r
BC
BD
WDTREL
Reset: 00
Bit Field
Type
Bit Field
WDTREL
rw
WDTWINB
H
H
H
Watchdog Timer Reload Register
WDTWINB
Reset: 00
H
Watchdog Window-Boundary Count
Register
Type
Bit Field
Type
rw
WDT[7:0]
rh
BE
WDTL
Reset: 00
H
H
Watchdog Timer Register Low
BF
WDTH
Reset: 00
Bit Field
Type
WDT[15:8]
rh
H
H
Watchdog Timer Register High
Data Sheet
24
V1.0, 2006-02
XC866
Functional Description
The Port SFRs can be accessed in the standard memory area (RMAP = 0).
Table 7
Port Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 0
B2
PORT_PAGE
Reset: 00
Bit Field
Type
OP
w
STNR
w
0
r
PAGE
rw
H
H
Page Register for PORT
RMAP = 0, Page 0
80
86
90
91
P0_DATA
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
0
r
0
r
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P4
rw
P4
rw
P3
rw
P3
rw
0
r
0
r
P3
rw
P3
rw
P3
rw
P3
rw
P2
rw
P2
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
H
H
H
H
H
H
H
H
H
H
H
H
P0 Data Register
P0_DIR
P0 Direction Register
P1_DATA
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P1 Data Register
P1_DIR
P1 Direction Register
A0
P2_DATA
P4
rw
P4
rw
P4
rw
P4
rw
P2
rw
P2
rw
P2
rw
P2
rw
H
P2 Data Register
A1
B0
P2_DIR
H
P2 Direction Register
P3_DATA
H
P3 Data Register
B1
P3_DIR
H
P3 Direction Register
RMAP = 0, Page 1
80
86
90
91
P0_PUDSEL
Reset: FF
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
0
r
0
r
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P4
rw
P4
rw
P3
rw
P3
rw
0
r
0
r
P3
rw
P3
rw
P3
rw
P3
rw
P2
rw
P2
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
H
H
H
H
H
P0 Pull-Up/Pull-Down Select Register
P0_PUDEN
Reset: C4
H
P0 Pull-Up/Pull-Down Enable Register
P1_PUDSEL
Reset: FF
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
H
P1 Pull-Up/Pull-Down Select Register
P1_PUDEN Reset: FF
H
P1 Pull-Up/Pull-Down Enable Register
P2_PUDSEL Reset: FF
A0
P4
rw
P4
rw
P4
rw
P4
rw
P2
rw
P2
rw
P2
rw
P2
rw
H
H
P2 Pull-Up/Pull-Down Select Register
P2_PUDEN Reset: 00
A1
H
H
P2 Pull-Up/Pull-Down Enable Register
P3_PUDSEL Reset: BF
B0
H
H
P3 Pull-Up/Pull-Down Select Register
P3_PUDEN Reset: 40
B1
H
H
P3 Pull-Up/Pull-Down Enable Register
RMAP = 0, Page 2
80
86
90
91
P0_ALTSEL0
Reset: 00
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
0
r
0
r
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P4
rw
P4
rw
P3
rw
P3
rw
0
r
0
r
P3
rw
P2
rw
P2
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
H
H
H
H
H
H
H
H
H
P0 Alternate Select 0 Register
P0_ALTSEL1
Reset: 00
P0 Alternate Select 1 Register
P1_ALTSEL0
Reset: 00
P7
rw
P7
rw
P7
rw
P6
rw
P6
rw
P6
rw
P1 Alternate Select 0 Register
P1_ALTSEL1
Reset: 00
P1 Alternate Select 1 Register
B0
P3_ALTSEL0
Reset: 00
Bit Field
Type
P4
rw
P2
rw
H
P3 Alternate Select 0 Register
Data Sheet
25
V1.0, 2006-02
XC866
Functional Description
Table 7
Port Register Overview (cont’d)
Addr Register Name
Bit
7
P7
rw
6
P6
rw
5
P5
rw
4
P4
rw
3
2
1
0
B1
P3_ALTSEL1
Reset: 00
Bit Field
Type
P3
rw
P2
rw
P1
rw
P0
rw
H
H
P3 Alternate Select 1 Register
RMAP = 0, Page 3
80
P0_OD
Reset: 00
Bit Field
Type
Bit Field
Type
Bit Field
Type
0
r
P5
rw
P5
rw
P5
rw
P4
rw
P3
rw
0
r
P3
rw
P2
rw
P1
rw
P1
rw
P1
rw
P0
rw
P0
rw
P0
rw
H
H
H
H
P0 Open Drain Control Register
90
P1_OD
Reset: 00
P7
rw
P7
rw
P6
rw
P6
rw
H
P1 Open Drain Control Register
B0
P3_OD
Reset: 00
P4
rw
P2
rw
H
P3 Open Drain Control Register
The ADC SFRs can be accessed in the standard memory area (RMAP = 0).
Table 8
ADC Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 0
D1
ADC_PAGE
Reset: 00
Bit Field
Type
OP
w
STNR
w
0
r
PAGE
rw
H
H
Page Register for ADC
RMAP = 0, Page 0
CA
ADC_GLOBCTR
Reset: 30
Reset: 00
Bit Field
Type
Bit Field
ANON DW
rw rw
CTC
rw
CHNR
0
r
H
H
Global Control Register
CB
ADC_GLOBSTR
0
0
r
SAM BUSY
PLE
H
H
Global Status Register
Type
r
rh
rh
rh
CC
CD
ADC_PRAR
Reset: 00
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
ASEN1 ASEN0
rw rw
0
r
ARBM CSM1 PRIO1 CSM0 PRIO0
rw rw rw rw rw
BOUND0
H
H
H
H
H
H
H
H
Priority and Arbitration Register
ADC_LCBR
Reset: B7
BOUND1
rw
Limit Check Boundary Register
rw
CE
CF
ADC_INPCR0
Reset: 00
STC
rw
Input Class Register 0
ADC_ETRCR
Reset: 00
SYNEN SYNEN
ETRSEL1
ETRSEL0
rw
External Trigger Control Register
1
0
Type
rw
rw
rw
RMAP = 0, Page 1
CA
ADC_CHCTR0
Reset: 00
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
0
r
0
r
0
r
0
r
0
r
0
r
0
r
0
r
LCC
rw
LCC
rw
LCC
rw
LCC
rw
LCC
rw
LCC
rw
LCC
rw
LCC
rw
0
r
0
r
0
r
0
r
0
r
0
r
0
r
0
r
RESRSEL
rw
RESRSEL
rw
RESRSEL
rw
RESRSEL
rw
RESRSEL
rw
RESRSEL
rw
RESRSEL
rw
RESRSEL
rw
H
H
H
H
H
H
H
H
H
Channel Control Register 0
CB
ADC_CHCTR1
Reset: 00
H
Channel Control Register 1
CC
CD
ADC_CHCTR2
Reset: 00
H
H
H
H
H
H
Channel Control Register 2
ADC_CHCTR3
Reset: 00
Channel Control Register 3
CE
CF
ADC_CHCTR4
Reset: 00
Channel Control Register 4
ADC_CHCTR5
Reset: 00
Channel Control Register 5
D2
D3
ADC_CHCTR6
Reset: 00
Channel Control Register 6
ADC_CHCTR7
Reset: 00
Channel Control Register 7
RMAP = 0, Page 2
Data Sheet
26
V1.0, 2006-02
XC866
Functional Description
Table 8
ADC Register Overview (cont’d)
Addr Register Name
Bit
7
6
5
0
r
4
VF
rh
3
DRC
rh
2
1
CHNR
rh
0
CA
ADC_RESR0L
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
RESULT[1:0]
rh
H
H
H
H
H
H
H
H
H
Result Register 0 Low
CB
ADC_RESR0H
RESULT[9:2]
rh
VF
rh
RESULT[9:2]
rh
VF
rh
RESULT[9:2]
rh
VF
rh
RESULT[9:2]
rh
H
Result Register 0 High
CC
CD
ADC_RESR1L
RESULT[1:0]
rh
0
r
DRC
rh
CHNR
rh
H
H
H
H
H
H
Result Register 1 Low
ADC_RESR1H
Result Register 1 High
CE
CF
ADC_RESR2L
RESULT[1:0]
rh
0
r
DRC
rh
CHNR
rh
Result Register 2 Low
ADC_RESR2H
Result Register 2 High
D2
D3
ADC_RESR3L
RESULT[1:0]
rh
0
r
DRC
rh
CHNR
rh
Result Register 3 Low
ADC_RESR3H
Result Register 3 High
RMAP = 0, Page 3
CA
ADC_RESRA0L
Reset: 00
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
RESULT[2:0]
VF
rh
DRC
rh
CHNR
rh
H
H
H
H
H
H
H
H
H
Result Register 0, View A Low
rh
CB
ADC_RESRA0H
Reset: 00
RESULT[10:3]
rh
VF
rh
RESULT[10:3]
rh
VF
rh
RESULT[10:3]
rh
VF
rh
RESULT[10:3]
rh
H
Result Register 0, View A High
CC
CD
ADC_RESRA1L
Reset: 00
RESULT[2:0]
rh
DRC
rh
CHNR
rh
H
H
H
H
H
H
Result Register 1, View A Low
ADC_RESRA1H
Reset: 00
Result Register 1, View A High
CE
CF
ADC_RESRA2L
Reset: 00
RESULT[2:0]
rh
DRC
rh
CHNR
rh
Result Register 2, View A Low
ADC_RESRA2H
Reset: 00
Result Register 2, View A High
D2
D3
ADC_RESRA3L
Reset: 00
RESULT[2:0]
rh
DRC
rh
CHNR
rh
Result Register 3, View A Low
ADC_RESRA3H
Reset: 00
Result Register 3, View A High
RMAP = 0, Page 4
CA
ADC_RCR0
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Bit Field
VFCTR WFR
0
IEN
0
DRCT
R
rw
H
H
H
H
H
H
Result Control Register 0
Type
Bit Field
rw
rw
r
0
rw
IEN
r
0
CB
ADC_RCR1
VFCTR WFR
DRCT
H
Result Control Register 1
R
Type
Bit Field
rw
rw
r
0
rw
IEN
r
0
rw
CC
CD
ADC_RCR2
VFCTR WFR
DRCT
H
H
H
Result Control Register 2
R
Type
Bit Field
rw
rw
r
0
rw
IEN
r
0
rw
ADC_RCR3
VFCTR WFR
DRCT
Result Control Register 3
R
Type
Bit Field
Type
rw
rw
r
rw
r
rw
CE
ADC_VFCR
0
r
VFC3 VFC2 VFC1 VFC0
Valid Flag Clear Register
w
w
w
w
RMAP = 0, Page 5
Data Sheet
27
V1.0, 2006-02
XC866
Functional Description
Table 8
ADC Register Overview (cont’d)
Addr Register Name
Bit
7
6
5
4
3
2
1
0
CA
ADC_CHINFR
Reset: 00
Bit Field
CHINF CHINF CHINF CHINF CHINF CHINF CHINF CHINF
H
H
H
H
H
H
H
H
H
Channel Interrupt Flag Register
7
6
rh
5
rh
4
rh
3
rh
2
rh
1
rh
0
rh
Type
rh
CB
ADC_CHINCR
Reset: 00
Bit Field
CHINC CHINC CHINC CHINC CHINC CHINC CHINC CHINC
H
Channel Interrupt Clear Register
7
6
w
5
w
4
w
3
w
2
w
1
w
0
w
Type
w
CC
CD
ADC_CHINSR
Reset: 00
Bit Field
CHINS CHINS CHINS CHINS CHINS CHINS CHINS CHINS
H
H
H
H
H
H
Channel Interrupt Set Register
7
6
w
5
w
4
w
3
w
2
w
1
w
0
w
Type
w
ADC_CHINPR
Reset: 00
Bit Field
CHINP CHINP CHINP CHINP CHINP CHINP CHINP CHINP
Channel Interrupt Node Pointer
Register
7
6
rw
5
rw
4
rw
3
rw
2
rw
1
rw
0
rw
Type
rw
CE
ADC_EVINFR
Reset: 00
Bit Field
EVINF EVINF EVINF EVINF
0
EVINF EVINF
Event Interrupt Flag Register
7
6
rh
5
rh
4
rh
1
rh
0
rh
Type
rh
r
0
CF
ADC_EVINCR
Reset: 00
Bit Field
EVINC EVINC EVINC EVINC
EVINC EVINC
Event Interrupt Clear Flag Register
7
6
w
5
w
4
w
1
w
0
w
Type
w
r
0
D2
D3
ADC_EVINSR
Reset: 00
Bit Field
EVINS EVINS EVINS EVINS
EVINS EVINS
Event Interrupt Set Flag Register
7
6
w
5
w
4
w
1
w
0
w
Type
w
r
0
ADC_EVINPR
Reset: 00
Bit Field
EVINP EVINP EVINP EVINP
EVINP EVINP
Event Interrupt Node Pointer Register
7
6
5
4
1
0
Type
rw
rw
rw
rw
r
rw
rw
RMAP = 0, Page 6
CA
ADC_CRCR1
Reset: 00
Bit Field
CH7
rwh
CH6
rwh
CH5
rwh
CH4
rwh
0
H
H
Conversion Request Control Register 1
Type
r
CB
ADC_CRPR1
Reset: 00
Bit Field
CHP7 CHP6 CHP5 CHP4
0
H
H
Conversion Request Pending
Register 1
Type
Bit Field
rwh
Rsv
rwh
rwh
rwh
r
CC
CD
ADC_CRMR1
Reset: 00
LDEV CLR SCAN ENSI ENTR
ENGT
H
H
Conversion Request Mode Register 1
PND
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
r
w
w
rw
rw
rw
rw
ENGT
rw
ADC_QMR0
Reset: 00
Reset: 20
Reset: 00
Reset: 00
Reset: 00
CEV TREV FLUSH CLRV TRMD ENTR
H
H
H
H
H
H
H
H
H
H
Queue Mode Register 0
w
Rsv
r
EXTR ENSI
rh rh
EXTR ENSI
rh rh
EXTR ENSI
w
0
r
w
w
rw
rw
CE
CF
ADC_QSR0
EMPTY EV
0
r
Queue Status Register 0
rh
RF
rh
RF
rh
rh
V
rh
V
ADC_Q0R0
0
r
0
r
REQCHNR
Queue 0 Register 0
rh
REQCHNR
rh
REQCHNR
w
D2
D2
ADC_QBUR0
Queue Backup Register 0
rh
ADC_QINR0
RF
w
0
r
Queue Input Register 0
w
w
The Timer 2 SFRs can be accessed in the standard memory area (RMAP = 0).
Table 9
Timer 2 Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
C0
T2_T2CON
Reset: 00
Bit Field
TF2
EXF2
0
r
EXEN2 TR2
0
CP/
H
H
Timer 2 Control Register
RL2
rw
Type
rwh
rwh
rw rwh
r
Data Sheet
28
V1.0, 2006-02
XC866
Functional Description
Table 9
Timer 2 Register Overview (cont’d)
C1
T2_T2MOD
Reset: 00
Bit Field
T2
REGS RHEN SEL
rw rw rw
T2
EDGE PREN
T2PRE
rw
DCEN
rw
H
H
Timer 2 Mode Register
Type
rw
RC2[7:0]
rwh
RC2[15:8]
rwh
THL2[7:0]
rwh
THL2[15:8]
rwh
C2
C3
C4
C5
T2_RC2L
Reset: 00
Bit Field
Type
H
H
H
H
H
Timer 2 Reload/Capture Register Low
T2_RC2H
Reset: 00
Bit Field
Type
H
Timer 2 Reload/Capture Register High
T2_T2L
Reset: 00
Reset: 00
Bit Field
Type
Bit Field
Type
H
H
Timer 2 Register Low
T2_T2H
Timer 2 Register High
The CCU6 SFRs can be accessed in the standard memory area (RMAP = 0).
Table 10
CCU6 Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 0
A3
CCU6_PAGE
Reset: 00
Bit Field
Type
OP
w
STNR
w
0
r
PAGE
rw
H
H
H
Page Register for CCU6
RMAP = 0, Page 0
9A
CCU6_CC63SRL
Reset: 00
Bit Field
CC63SL
H
H
Capture/Compare Shadow Register for
Channel CC63 Low
Type
Bit Field
rw
9B
CCU6_CC63SRH
Reset: 00
CC63SH
H
Capture/Compare Shadow Register for
Channel CC63 High
Type
rw
9C
9D
CCU6_TCTR4L
Reset: 00
Bit Field
T12
T12
0
r
DTRES T12 T12RS T12RR
H
H
H
H
H
H
H
Timer Control Register 4 Low
STD
STR
RES
Type
Bit Field
w
w
w
w
w
w
CCU6_TCTR4H
Reset: 00
T13
T13
0
r
T13 T13RS T13RR
Timer Control Register 4 High
STD
STR
RES
Type
Bit Field
w
w
0
w
w
w
9E
CCU6_MCMOUTSL
Reset: 00
STRM
MCMPS
Multi-Channel Mode Output Shadow
Register Low
CM
Type
Bit Field
Type
w
STRHP
w
r
0
r
rw
9F
CCU6_MCMOUTSH
Reset: 00
CURHS
rw
EXPHS
rw
H
Multi-Channel Mode Output Shadow
Register High
A4
A5
A6
A7
CCU6_ISRL
Reset: 00
Bit Field
RT12P RT12O RCC62 RCC62 RCC61 RCC61 RCC60 RCC60
H
H
H
H
H
H
H
Capture/Compare Interrupt Status
Reset Register Low
M
w
M
w
F
R
w
F
w
0
R
w
F
R
w
Type
Bit Field
w
w
CCU6_ISRH
Reset: 00
RSTR RIDLE RWHE RCHE
RTRPF RT13 RT13
Capture/Compare Interrupt Status
Reset Register High
PM
w
CM
w
Type
Bit Field
w
0
w
w
w
0
r
w
CCU6_CMPMODIFL
Reset: 00
MCC63
MCC62 MCC61 MCC60
Compare State Modification Register
Low
S
S
w
S
w
S
w
Type
Bit Field
r
w
r
CCU6_CMPMODIFH
Reset: 00
0
MCC63
0
MCC62 MCC61 MCC60
H
Compare State Modification Register
High
R
R
w
R
w
R
w
Type
r
w
r
FA
CCU6_CC60SRL
Reset: 00
Bit Field
CC60SL
H
H
Capture/Compare Shadow Register for
Channel CC60 Low
Type
rwh
Data Sheet
29
V1.0, 2006-02
XC866
Functional Description
Table 10
CCU6 Register Overview (cont’d)
Addr Register Name
Bit
7
6
5
4
3
2
1
0
FB
CCU6_CC60SRH
Reset: 00
Bit Field
CC60SH
H
H
Capture/Compare Shadow Register for
Channel CC60 High
Type
rwh
FC
FD
CCU6_CC61SRL
Reset: 00
Bit Field
CC61SL
H
H
H
H
H
Capture/Compare Shadow Register for
Channel CC61 Low
Type
Bit Field
rwh
CC61SH
CCU6_CC61SRH
Reset: 00
H
Capture/Compare Shadow Register for
Channel CC61 High
Type
Bit Field
rwh
CC62SL
FE
CCU6_CC62SRL
Reset: 00
H
Capture/Compare Shadow Register for
Channel CC62 Low
Type
Bit Field
rwh
CC62SH
FF
CCU6_CC62SRH
Reset: 00
H
Capture/Compare Shadow Register for
Channel CC62 High
Type
rwh
RMAP = 0, Page 1
9A
CCU6_CC63RL
Reset: 00
Bit Field
CC63VL
H
H
Capture/Compare Register for Channel
CC63 Low
Type
rh
9B
CCU6_CC63RH
Reset: 00
Bit Field
CC63VH
H
H
Capture/Compare Register for Channel
CC63 High
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
rh
T12PVL
rwh
T12PVH
rwh
T13PVL
rwh
T13PVH
rwh
9C
9D
CCU6_T12PRL
Reset: 00
H
H
H
H
H
H
H
H
H
Timer T12 Period Register Low
CCU6_T12PRH
Reset: 00
Timer T12 Period Register High
9E
9F
CCU6_T13PRL
Reset: 00
Timer T13 Period Register Low
CCU6_T13PRH
Reset: 00
Timer T13 Period Register High
A4
CCU6_T12DTCL
Reset: 00
DTM
rw
H
H
Dead-Time Control Register for Timer
T12 Low
A5
CCU6_T12DTCH
Reset: 00
Bit Field
0
r
DTR2 DTR1 DTR0
rh rh rh
0
r
DTE2 DTE1 DTE0
H
Dead-Time Control Register for Timer
T12 High
Type
rw
rw
rw
A6
A7
CCU6_TCTR0L
Reset: 00
Bit Field
CTM CDIR STE12 T12R
T12
T12CLK
H
H
H
H
Timer Control Register 0 Low
PRE
Type
Bit Field
rw
rh
rh
rh
rw
rw
T13CLK
CCU6_TCTR0H
Reset: 00
0
r
STE13 T13R
T13
H
Timer Control Register 0 High
PRE
Type
Bit Field
rh
rh
rw
rw
FA
FB
CCU6_CC60RL
Reset: 00
CC60VL
H
H
Capture/Compare Register for Channel
CC60 Low
Type
Bit Field
rh
CCU6_CC60RH
Reset: 00
CC60VH
H
Capture/Compare Register for Channel
CC60 High
Type
rh
FC
CCU6_CC61RL
Reset: 00
Bit Field
CC61VL
H
H
Capture/Compare Register for Channel
CC61 Low
Type
rh
Data Sheet
30
V1.0, 2006-02
XC866
Functional Description
Table 10
CCU6 Register Overview (cont’d)
Addr Register Name
Bit
7
6
5
4
3
2
1
0
FD
CCU6_CC61RH
Reset: 00
Bit Field
CC61VH
H
H
H
H
Capture/Compare Register for Channel
CC61 High
Type
rh
FE
CCU6_CC62RL
Reset: 00
Bit Field
CC62VL
H
Capture/Compare Register for Channel
CC62 Low
Type
rh
FF
CCU6_CC62RH
Reset: 00
Bit Field
CC62VH
H
Capture/Compare Register for Channel
CC62 High
Type
rh
RMAP = 0, Page 2
9A
CCU6_T12MSELL
Reset: 00
Bit Field
MSEL61
MSEL60
H
H
H
H
H
H
H
H
T12 Capture/Compare Mode Select
Register Low
Type
Bit Field
rw
HSYNC
rw
MSEL62
9B
CCU6_T12MSELH
Reset: 00
DBYP
rw
H
T12 Capture/Compare Mode Select
Register High
Type
Bit Field
rw
rw
9C
9D
CCU6_IENL
Reset: 00
ENT12 ENT12 ENCC ENCC ENCC ENCC ENCC ENCC
H
H
H
H
Capture/Compare Interrupt Enable
Register Low
PM
rw
OM
rw
62F
rw
62R
rw
61F
rw
0
61R
rw
60F
rw
60R
rw
Type
Bit Field
CCU6_IENH
Reset: 00
ENSTR EN
EN
EN
EN
ENT13 ENT13
Capture/Compare Interrupt Enable
Register High
IDLE
WHE
CHE
TRPF
PM
rw
CM
rw
Type
Bit Field
rw
rw
rw
rw
r
rw
9E
CCU6_INPL
Reset: 40
INPCHE
INPCC62
INPCC61
INPCC60
Capture/Compare Interrupt Node
Pointer Register Low
Type
Bit Field
rw
0
rw
rw
rw
9F
CCU6_INPH
Reset: 39
INPT13
INPT12
INPERR
Capture/Compare Interrupt Node
Pointer Register High
Type
Bit Field
r
rw
rw
rw
A4
A5
CCU6_ISSL
Reset: 00
ST12P ST12O SCC62 SCC62 SCC61 SCC61 SCC60 SCC60
H
Capture/Compare Interrupt Status Set
Register Low
M
w
M
w
F
w
R
w
F
w
R
w
F
w
R
w
Type
Bit Field
CCU6_ISSH
Reset: 00
SSTR SIDLE SWHE SCHE SWHC STRPF ST13 ST13
H
H
Capture/Compare Interrupt Status Set
Register High
PM
w
CM
w
Type
Bit Field
Type
Bit Field
Type
w
w
0
r
w
w
w
w
A6
A7
CCU6_PSLR
Reset: 00
PSL63
rwh
PSL
rwh
H
H
Passive State Level Register
CCU6_MCMCTR Reset: 00
0
r
SWSYN
rw
0
r
SWSEL
rw
H
H
Multi-Channel Mode Control Register
FA
FB
CCU6_TCTR2L
Reset: 00
Bit Field
0
r
T13TED
T13TEC
T13
T12
H
H
H
Timer Control Register 2 Low
SSC
SSC
Type
Bit Field
Type
rw
0
r
rw
rw
rw
CCU6_TCTR2H
Reset: 00
T13RSEL
rw
T12RSEL
rw
H
Timer Control Register 2 High
FC
FD
CCU6_MODCTRL
Reset: 00
Bit Field
MC
0
T12MODEN
H
H
H
H
Modulation Control Register Low
MEN
Type
Bit Field
rw
r
0
rw
CCU6_MODCTRH
Reset: 00
ECT13
T13MODEN
H
H
Modulation Control Register High
O
Type
Bit Field
Type
rw
r
rw
FE
CCU6_TRPCTRL
Reset: 00
0
r
TRPM2 TRPM1 TRPM0
rw rw rw
Trap Control Register Low
Data Sheet
31
V1.0, 2006-02
XC866
Functional Description
Table 10
CCU6 Register Overview (cont’d)
Addr Register Name
Bit
7
6
5
4
3
2
1
0
FF
CCU6_TRPCTRH
Reset: 00
Bit Field
TRPPE TRPEN
TRPEN
H
H
Trap Control Register High
N
13
rw
Type
rw
rw
RMAP = 0, Page 3
9A
CCU6_MCMOUTL
Reset: 00
Bit Field
0
r
R
MCMP
rh
H
H
Multi-Channel Mode Output Register
Low
Type
rh
9B
CCU6_MCMOUTH
Reset: 00
Bit Field
0
r
CURH
rh
EXPH
rh
H
H
Multi-Channel Mode Output Register
High
Type
9C
9D
CCU6_ISL
Reset: 00
Bit Field
T12PM T12OM ICC62F ICC62 ICC61F ICC61 ICC60F ICC60
H
H
H
Capture/Compare Interrupt Status
Register Low
R
R
R
Type
Bit Field
rh
rh
rh
rh
rh
rh
rh
rh
CCU6_ISH
Reset: 00
STR
IDLE
WHE
CHE TRPS TRPF T13PM T13CM
H
Capture/Compare Interrupt Status
Register High
Type
rh
rh
rh
rh
rh
rh
rh
rh
9E
CCU6_PISEL0L
Reset: 00
Bit Field
Type
ISTRP
rw
ISCC62
rw
ISCC61
rw
ISCC60
rw
H
H
Port Input Select Register 0 Low
9F
CCU6_PISEL0H
Reset: 00
Bit Field
IST12HR
ISPOS2
ISPOS1
ISPOS0
H
H
Port Input Select Register 0 High
Type
Bit Field
Type
rw
rw
0
r
rw
rw
IST13HR
rw
A4
CCU6_PISEL2
Reset: 00
H
H
H
H
H
H
H
Port Input Select Register 2
FA
FB
CCU6_T12L
Reset: 00
Bit Field
Type
T12CVL
rwh
H
H
Timer T12 Counter Register Low
CCU6_T12H
Reset: 00
Bit Field
Type
T12CVH
rwh
Timer T12 Counter Register High
FC
FD
CCU6_T13L
Reset: 00
Bit Field
Type
T13CVL
rwh
H
H
H
Timer T13 Counter Register Low
CCU6_T13H
Reset: 00
Bit Field
Type
T13CVH
rwh
Timer T13 Counter Register High
FE
CCU6_CMPSTATL
Reset: 00
Bit Field
0
r
CC63 CCPO CCPO CCPO CC62 CC61 CC60
Compare State Register Low
ST
rh
S2
rh
S1
rh
S0
rh
ST
rh
ST
rh
ST
rh
Type
FF
CCU6_CMPSTATH
Reset: 00
Bit Field
T13IM COUT COUT CC62 COUT CC61 COUT CC60
H
H
Compare State Register High
63PS 62PS
rwh rwh
PS
61PS
rwh
PS
60PS
rwh
PS
Type
rwh
rwh
rwh
rwh
The SSC SFRs can be accessed in the standard memory area (RMAP = 0).
Table 11
SSC Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 0
A9
SSC_PISEL
Reset: 00
Reset: 00
Bit Field
Type
Bit Field
Type
0
r
PH
rw
CIS
rw
SIS
rw
MIS
rw
H
H
Port Input Select Register
AA
SSC_CONL
LB
rw
PO
rw
HB
rw
BM
rw
H
H
Control Register Low
Programming Mode
Operating Mode
Bit Field
Type
0
r
BC
rh
Data Sheet
32
V1.0, 2006-02
XC866
Functional Description
Table 11
SSC Register Overview
AB
SSC_CONH
Reset: 00
Bit Field
EN
MS
0
AREN BEN
PEN
REN
TEN
H
H
Control Register High
Programming Mode
Type
Bit Field
Type
rw
EN
rw
rw
MS
rw
r
0
r
rw
BSY
rh
rw
BE
rwh
rw
PE
rwh
rw
RE
rwh
rw
TE
rwh
Operating Mode
AC
AD
SSC_TBL
Reset: 00
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
TB_VALUE
H
H
H
H
H
H
H
Transmitter Buffer Register Low
rw
SSC_RBL
Reset: 00
RB_VALUE
Receiver Buffer Register Low
rh
AE
AF
SSC_BRL
Reset: 00
BR_VALUE[7:0]
Baudrate Timer Reload Register Low
SSC_BRH Reset: 00
rw
BR_VALUE[15:8]
rw
H
Baudrate Timer Reload Register High
The OCDS SFRs can be accessed in the mapped memory area (RMAP = 1).
Table 12
OCDS Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 1
E9
MMCR2
Reset: 0U
Bit Field
EXBC_ EXBC MBCO MBCO MMEP MMEP MMOD JENA
H
H
H
H
H
H
H
H
H
H
H
Monitor Mode Control Register 2
P
w
N_P
w
N
_P
w
E
Type
Bit Field
rw
rwh
rwh
rh
rh
F1
F2
F3
F4
F5
MMCR
Reset: 00
MEXIT MEXIT MSTEP MSTEP MRAM MRAM TRF
RRF
Monitor Mode Control Register
_P
w
_P
w
S_P
w
S
Type
Bit Field
rwh
rw
rwh
rh
rh
MMSR
Reset: 00
MBCA MBCIN EXBF SWBF HWB3 HWB2 HWB1 HWB0
Monitor Mode Status Register
M
rw
F
rwh
F
rwh
F
rwh
F
rwh
Type
Bit Field
rh
rwh
rwh
MMBPCR
Reset: 00
SWBC
HWB3C
HWB2C
HWB1
HWB0C
BreakPoints Control Register
C
Type
Bit Field
rw
rw
rw
rw
rw
MMICR
Reset: 00
DVECT DRETR
0
r
MMUIE MMUIE RRIE_ RRIE
Monitor Mode Interrupt Control Register
_P
w
P
w
Type
Bit Field
rwh
rwh
rw
rw
MMDR
Reset: 00
MMRR
H
Monitor Mode Data Register
Receive
Type
Bit Field
Type
rh
MMTR
w
Transmit
F6
F7
HWBPSR
Reset: 00
Bit Field
0
r
BPSEL
BPSEL
rw
H
H
Hardware Breakpoints Select Register
_P
w
Type
Bit Field
Type
HWBPDR
Reset: 00
HWBPxx
rw
H
H
Hardware Breakpoints Data Register
Data Sheet
33
V1.0, 2006-02
XC866
Functional Description
3.3
Flash Memory
The Flash memory provides an embedded user-programmable non-volatile memory,
allowing fast and reliable storage of user code and data. It is operated from a single 2.5 V
supply from the Embedded Voltage Regulator (EVR) and does not require additional
programming or erasing voltage. The sectorization of the Flash memory allows each
sector to be erased independently.
Features:
• In-System Programming (ISP) via UART
• In-Application Programming (IAP)
• Error Correction Code (ECC) for dynamic correction of single-bit errors
• Background program and erase operations for CPU load minimization
• Support for aborting erase operation
1)
• 32-byte minimum program width
• 1-sector minimum erase width
• 1-byte read access
2)
• 121.6 ns minimum read access time (3 × t
• Operating supply voltage: 2.5 V ± 7.5 %
@ f
= 26.7 MHz ± 7.5 % )
CCLK
CCLK
3)
• Program time: 2.3 ms
3)
• Erase time: 120 ms
Table 13
Flash Data Retention and Endurance Targets
Retention up to
Endurance up to
Programming
Size
Temperature
4)
5)
20 years
5 years
2 years
1,000 cycles
0 – 100°C
15 Kbytes
896 bytes
512 bytes
128 bytes
4)
5)
10,000 cycles
-40 – 125°C
-40 – 125°C
-40 – 125°C
4)
5)
70,000 cycles
4)
5)
2 years
100,000 cycles
1)
P-Flash: 32-byte wordline can only be programmed once, i.e., one gate disturb allowed.
D-Flash: 32-byte wordline can be programmed twice, i.e., two gate disturbs allowed.
2)
3)
f
f
= 80 MHz ± 7.5% (f
= 26.7 MHz ± 7.5 %) is the maximum frequency range for Flash read access.
CCLK
sys
sys
= 80 MHz ± 7.5% is the only frequency range for Flash programming and erasing. f
is used for
sysmin
obtaining the worst case timing.
4)
5)
Specification with 0.2ppm error rate.
One cycle refers to the programming of all wordlines in a sector and erasing of the sector.
Data Sheet
34
V1.0, 2006-02
XC866
Functional Description
3.3.1
Flash Bank Sectorization
The XC866 product family offers four Flash devices with either 8 Kbytes or 16 Kbytes of
embedded Flash memory. These Flash memory sizes are made up of two or four
4-Kbyte Flash banks, respectively. Each Flash device consists of Program Flash
(P-Flash) bank(s) and a single Data Flash (D-Flash) bank with different sectorization
shown in Figure 10. Both types can be used for code and data storage. The label “Data”
neither implies that the D-Flash is mapped to the data memory region, nor that it can only
be used for data storage. It is used to distinguish the different Flash bank sectorizations.
The XC866 ROM devices offer a single 4-Kbyte D-Flash bank.
Sector 2: 128-byte
Sector 1: 128-byte
Sector 9: 128-byte
Sector 8: 128-byte
Sector 7: 128-byte
Sector 6: 128-byte
Sector 5: 256-byte
Sector 4: 256-byte
Sector 3: 512-byte
Sector 2: 512-byte
Sector 0: 3.75-Kbyte
Sector 1: 1-Kbyte
Sector 0: 1-Kbyte
P-Flash
D-Flash
Figure 10
Flash Bank Sectorization
The internal structure of each Flash bank represents a sector architecture for flexible
erase capability. The minimum erase width is always a complete sector, and sectors can
be erased separately or in parallel. Contrary to standard EPROMs, erased Flash
memory cells contain 0s.
The D-Flash bank is divided into more physical sectors for extended erasing and
reprogramming capability; even numbers for each sector size are provided to allow
greater flexibility and the ability to adapt to a wide range of application requirements.
Data Sheet
35
V1.0, 2006-02
XC866
Functional Description
3.3.2
Flash Programming Width
For the P-Flash banks, a programmed wordline (WL) must be erased before it can be
reprogrammed as the Flash cells can only withstand one gate disturb. This means that
the entire sector containing the WL must be erased since it is impossible to erase a
single WL.
For the D-Flash bank, the same WL can be programmed twice before erasing is required
as the Flash cells are able to withstand two gate disturbs. Hence, it is possible to
program the same WL, for example, with 16 bytes of data in two times (see Figure 11).
32 bytes (1 WL)
0000 ….. 0000 H
16 bytes
16 bytes
Program 1
Program 2
0000 ….. 0000 H
1111 ….. 1111 H
1111 ….. 1111 H
0000 ….. 0000 H
1111 ….. 1111H
0000 ….. 0000 H
1111 ….. 0000 H
1111 ….. 0000 H
0000 ….. 0000H
Note: A Flash memory cell can be programmed
from 0 to 1, but not from 1 to 0.
Flash memory cells
Figure 11 D-Flash Programming
32-byte write buffers
Note: When programming a D-Flash WL the second time, the previously programmed
Flash memory cells (whether 0s or 1s) should be reprogrammed with 0s to retain
its original contents and to prevent “over-programming”.
Data Sheet
36
V1.0, 2006-02
XC866
Functional Description
3.4
Interrupt System
The XC800 Core supports one non-maskable interrupt (NMI) and 14 maskable interrupt
requests. In addition to the standard interrupt functions supported by the core, e.g.,
configurable interrupt priority and interrupt masking, the XC866 interrupt system
provides extended interrupt support capabilities such as the mapping of each interrupt
vector to several interrupt sources to increase the number of interrupt sources
supported, and additional status registers for detecting and determining the interrupt
source.
3.4.1
Interrupt Source
Figure 12 to Figure 16 give a general overview of the interrupt sources and illustrates
the request and control flags.
WDT Overflow
FNMIWDT
NMIISR.0
NMIWDT
NMICON.0
PLL Loss of Lock
FNMIPLL
NMIISR.1
NMIPLL
NMICON.1
Flash Operation
Complete
FNMIFLASH
NMIISR.2
NMIFLASH
>=1
Non
Maskable
Interrupt
0073
FNMIVDD
NMIISR.4
H
VDD Pre-Warning
VDDP Pre-Warning
Flash ECC Error
NMIVDD
NMICON.4
FNMIVDDP
NMIISR.5
NMIVDDP
NMICON.5
FNMIECC
NMIISR.6
NMIECC
NMICON.6
Figure 12
Non-Maskable Interrupt Request Sources
Data Sheet
37
V1.0, 2006-02
XC866
Functional Description
Highest
Timer 0
TF0
Lowest
Overflow
Priority Level
TCON.5
000B
001B
ET0
H
H
IP.1/
IPH.1
IEN0.1
Timer 1
Overflow
TF1
P
o
l
TCON.7
ET1
IP.3/
IPH.3
IEN0.3
l
i
n
g
RI
SCON.0
>=1
UART
S
e
q
u
e
n
c
0023
0003
TI
ES
IEN0.4
H
H
IP.4/
SCON.1
IPH.4
EINT0
EXINT0
IE0
TCON.1
e
IRCON0.0
EX0
IT0
IP.0/
IPH.0
IEN0.0
EXINT0
TCON.0
EXICON0.0/1
EINT1
EXINT1
IE1
IRCON0.1
TCON.3
0013
EA
EX1
H
IT1
IP.2/
IEN0.2
IPH.2
EXINT1
TCON.2
EXICON0.2/3
IEN0.7
Bit-addressable
Request flag is cleared by hardware
Figure 13
Interrupt Request Sources (Part 1)
Data Sheet
38
V1.0, 2006-02
XC866
Functional Description
Timer 2
Overflow
Highest
TF2
T2CON.7
Lowest
T2EX
EXF2
Priority Level
002B
ET2
IEN0.5
H
T2CON.6
EXEN2
IP.5/
IPH.5
T2CON.3
EDGES
EL
T2MOD.5
>=1
Normal Divider
Overflow
NDOV
FDCON.2
End of
Syn Byte
EOFSYN
FDCON.4
SYNEN
FDCON.6
Syn Byte Error
ERRSYN
FDCON.5
P
o
l
l
EXINT2
EINT2
i
IRCON0.2
0043
n
g
EX2
IEN1.2
H
IP1.2/
IPH1.2
EXINT2
EXICON0.4/5
S
e
q
u
e
n
c
EXINT3
EINT3
EINT4
IRCON0.3
EXINT3
e
EXICON0.6/7
EXINT4
IRCON0.4
004B
EXM
IEN1.3
H
IP1.3/
IPH1.3
EXINT4
>=1
EXICON1.0/1
EXINT5
EINT5
EINT6
IRCON0.5
EXINT5
EXICON1.2/3
EA
IEN0.7
EXINT6
IRCON0.6
Bit-addressable
Request flag is cleared by hardware
EXINT6
EXICON1.4/5
Bit-addressable
Request flag is cleared by hardware
Figure 14
Interrupt Request Sources (Part 2)
Data Sheet
39
V1.0, 2006-02
XC866
Functional Description
Highest
ADC_SRC0
ADC_SRC1
ADCSRC0
IRCON1.3
>=1
Lowest
Priority Level
0033
003B
EADC
IEN1.0
H
ADCSRC1
IRCON1.4
IP1.0/
IPH1.0
SSC_EIR
SSC_TIR
SSC_RIR
EIR
IRCON1.0
TIR
IRCON1.1
>=1
P
o
l
ESSC
IEN1.1
H
IP1.1/
IPH1.1
RIR
IRCON1.2
l
i
n
g
Capture/Compare
interrupt node 0
0053
005B
0063
H
H
S
e
q
u
e
n
c
ECCIP0
IEN1.4
IP1.4/
IPH1.4
Capture/Compare
interrupt node 1
ECCIP1
IEN1.5
e
IP1.5/
IPH1.5
Capture/Compare
interrupt node 2
H
H
ECCIP2
IEN1.6
IP1.6/
IPH1.6
Capture/Compare
interrupt node 3
006B
ECCIP3
IEN1.7
IP1.7/
IPH1.7
EA
IEN0.7
Bit-addressable
Request flag is cleared by hardware
Figure 15
Interrupt Request Sources (Part 3)
Data Sheet
40
V1.0, 2006-02
XC866
Functional Description
ICC60R
ISL.0
ENCC60R
IENL.0
CC60
CC61
>=1
>=1
ICC60F
ISL.1
ENCC60F
IENL.1
INPL.1
INPL.3
INPL.0
INPL.2
ICC61R
ISL.2
ENCC61R
IENL.2
ICC61F
ISL.3
ENCC61F
IENL.3
ICC62R
ISL.4
ENCC62R
IENL.4
CC62
>=1
ICC62F
ISL.5
ENCC62F
IENL.5
INPL.5
INPL.4
T12
One match
T12OM
ISL.6
ENT12OM
IENL.6
>=1
>=1
T12
T12PM
ISL.7
Period match
ENT12PM
IENL.7
INPH.3 INPH.2
INPH.5 INPH.4
T13
T13CM
ISH.0
Compare match
ENT13CM
IENH.0
T13
Period match
T13PM
ISH.1
ENT13PM
IENH.1
TRPF
ISH.2
CTRAP
ENTRPF
IENH.2
>=1
>=1
Wrong Hall
Event
WHE
ISH.5
ENWHE
IENH.5
INPH.1 INPH.0
Correct Hall
Event
CHE
ISH.4
ENCHE
IENH.4
Multi-Channel
Shadow
Transfer
STR
ISH.7
ENSTR
IENH.7
INPL.7
INPL.6
CCU6 Interrupt node 0
CCU6 Interrupt node 1
CCU6 Interrupt node 2
CCU6 Interrupt node 3
Figure 16
Interrupt Request Sources (Part 4)
Data Sheet
41
V1.0, 2006-02
XC866
Functional Description
3.4.2
Interrupt Source and Vector
Each interrupt source has an associated interrupt vector address. This vector is
accessed to service the corresponding interrupt source request. The interrupt service of
each interrupt source can be individually enabled or disabled via an enable bit. The
assignment of the XC866 interrupt sources to the interrupt vector addresses and the
corresponding interrupt source enable bits are summarized in Table 14.
Table 14
Interrupt Vector Addresses
Interrupt
Source
Vector
Assignment for XC866
Enable Bit
SFR
Address
NMI
0073
Watchdog Timer NMI
PLL NMI
Flash NMI
VDDC Prewarning NMI
VDDP Prewarning NMI
Flash ECC NMI
External Interrupt 0
Timer 0
NMIWDT
NMIPLL
NMIFLASH
NMIVDD
NMIVDDP
NMIECC
EX0
ET0
EX1
ET1
ES
NMICON
H
XINTR0
XINTR1
XINTR2
XINTR3
XINTR4
XINTR5
0003
IEN0
H
000B
H
H
0013
External Interrupt 1
Timer 1
UART
001B
H
H
0023
002B
T2
ET2
H
Fractional Divider
(Normal Divider Overflow)
LIN
Data Sheet
42
V1.0, 2006-02
XC866
Functional Description
Table 14
Interrupt Vector Addresses (cont’d)
XINTR6
XINTR7
XINTR8
XINTR9
0033
003B
0043
004B
ADC
SSC
EADC
ESSC
EX2
IEN1
H
H
H
External Interrupt 2
External Interrupt 3
External Interrupt 4
External Interrupt 5
External Interrupt 6
CCU6 INP0
CCU6 INP1
CCU6 INP2
CCU6 INP3
EXM
H
XINTR10
XINTR11
XINTR12
XINTR13
0053
005B
0063
006B
ECCIP0
ECCIP1
ECCIP2
ECCIP3
H
H
H
H
Data Sheet
43
V1.0, 2006-02
XC866
Functional Description
3.4.3
Interrupt Priority
Each interrupt source, except for NMI, can be individually programmed to one of the four
possible priority levels. The NMI has the highest priority and supersedes all other
interrupts. Two pairs of interrupt priority registers (IP and IPH, IP1 and IPH1) are
available to program the priority level of each non-NMI interrupt vector.
A low-priority interrupt can be interrupted by a high-priority interrupt, but not by another
interrupt of the same or lower priority. Further, an interrupt of the highest priority cannot
be interrupted by any other interrupt source.
If two or more requests of different priority levels are received simultaneously, the
request of the highest priority is serviced first. If requests of the same priority are
received simultaneously, then an internal polling sequence determines which request is
serviced first. Thus, within each priority level, there is a second priority structure
determined by the polling sequence shown in Table 15.
Table 15
Source
Priority Structure within Interrupt Level
Level
Non-Maskable Interrupt (NMI)
External Interrupt 0
Timer 0 Interrupt
External Interrupt 1
Timer 1 Interrupt
(highest)
1
2
3
4
5
UART Interrupt
Timer 2,Fractional Divider, LIN Interrupts 6
ADC Interrupt
7
SSC Interrupt
8
External Interrupt 2
9
External Interrupt [6:3]
CCU6 Interrupt Node Pointer 0
CCU6 Interrupt Node Pointer 1
CCU6 Interrupt Node Pointer 2
CCU6 Interrupt Node Pointer 3
10
11
12
13
14
Data Sheet
44
V1.0, 2006-02
XC866
Functional Description
3.5
Parallel Ports
The XC866 has 27 port pins organized into four parallel ports, Port 0 (P0) to Port 3 (P3).
Each pin has a pair of internal pull-up and pull-down devices that can be individually
enabled or disabled. Ports P0, P1 and P3 are bidirectional and can be used as general
purpose input/output (GPIO) or to perform alternate input/output functions for the on-chip
peripherals. When configured as an output, the open drain mode can be selected. Port
P2 is an input-only port, providing general purpose input functions, alternate input
functions for the on-chip peripherals, and also analog inputs for the Analog-to-Digital
Converter (ADC).
Bidirectional Port Features:
• Configurable pin direction
• Configurable pull-up/pull-down devices
• Configurable open drain mode
• Transfer of data through digital inputs and outputs (general purpose I/O)
• Alternate input/output for on-chip peripherals
Input Port Features:
• Configurable input driver
• Configurable pull-up/pull-down devices
• Receive of data through digital input (general purpose input)
• Alternate input for on-chip peripherals
• Analog input for ADC module
Data Sheet
45
V1.0, 2006-02
XC866
Functional Description
Px_PUDSEL
Pull-up/Pull-down
Select Register
Internal Bus
Px_PUDEN
Pull-up/Pull-down
Enable Register
Px_OD
Open Drain
Control Register
Px_DIR
Direction Register
Px_ALTSEL0
Alternate Select
Register 0
VDDP
Px_ALTSEL1
Alternate Select
Register 1
Pull
Up
enable
Device
AltDataOut 3
AltDataOut 2
AltDataOut1
enable
11
Output
Driver
10
01
00
Pin
enable
Out
In
Input
Px_Data
Driver
Data Register
Schmitt Trigger
AltDataIn
Pull
enable
Down
Device
Pad
Figure 17
General Structure of Bidirectional Port
Data Sheet
46
V1.0, 2006-02
XC866
Functional Description
Internal Bus
Px_PUDSEL
Pull-up/Pull-down
Select Register
Px_PUDEN
Pull-up/Pull-down
Enable Register
Px_DIR
Direction Register
VDDP
Pull
enable
Up
Device
enable
Input
In
Driver
Px_DATA
Pin
Data Register
Schmitt Trigger
AltDataIn
AnalogIn
Pull
enable
Down
Device
Pad
Figure 18
General Structure of Input Port
Data Sheet
47
V1.0, 2006-02
XC866
Functional Description
3.6
Power Supply System with Embedded Voltage Regulator
The XC866 microcontroller requires two different levels of power supply:
• 3.3 V or 5.0 V for the Embedded Voltage Regulator (EVR) and Ports
• 2.5 V for the core, memory, on-chip oscillator, and peripherals
Figure 19 shows the XC866 power supply system. A power supply of 3.3 V or 5.0 V
must be provided from the external power supply pin. The 2.5 V power supply for the
logic is generated by the EVR. The EVR helps to reduce the power consumption of the
whole chip and the complexity of the application board design.
The EVR consists of a main voltage regulator and a low power voltage regulator. In
active mode, both voltage regulators are enabled. In power-down mode, the main
voltage regulator is switched off, while the low power voltage regulator continues to
function and provide power supply to the system with low power consumption.
CPU &
On-chip
OSC
Peripheral
logic
Memory
ADC
FLASH
PLL
VDDC (2.5V)
XTAL1&
XTAL2
GPIO Ports
(P0-P3)
EVR
VDDP (3.3V/5.0V)
VSSP
Figure 19
XC866 Power Supply System
EVR Features:
• Input voltage (V
): 3.3 V/5.0 V
DDC
DDP
• Output voltage (V
): 2.5 V ± 7.5%
• Low power voltage regulator provided in power-down mode
• V
• V
and V
prewarning detection
DDC
DDC
DDP
brownout detection
Data Sheet
48
V1.0, 2006-02
XC866
Functional Description
3.7
Reset Control
The XC866 has five types of reset: power-on reset, hardware reset, watchdog timer
reset, power-down wake-up reset, and brownout reset.
When the XC866 is first powered up, the status of certain pins (see Table 17) must be
defined to ensure proper start operation of the device. At the end of a reset sequence,
the sampled values are latched to select the desired boot option, which cannot be
modified until the next power-on reset or hardware reset. This guarantees stable
conditions during the normal operation of the device.
In order to power up the system properly, the external reset pin RESET must be asserted
until V
reaches 0.9*V
. The delay of external reset can be realized by an external
DDC
DDC
capacitor at RESET pin. This capacitor value must be selected so that V
reaches
RESET
0.4 V, but not before V
reaches 0.9* V
DDC
DDC.
A typical application example is shown in Figure 20. For a voltage regulator with IDD
max
= 100 mA, the V
capacitor value is 10 µF. V
capacitor value is 220 nF. The
DDP
DDC
capacitor connected to RESET pin is 100 nF.
Typically, the time taken for V to reach 0.9*V
is less than 50 µs once V
DDP
DDC
DDC
reaches 2.3V. Hence, based on the condition that 10% to 90% V
(slew rate) is less
DDP
than 500 µs, the RESET pin should be held low for 500 µs typically. See Figure 21.
3.3V/5V
/
Vin
e.g. 100mA
VR
220nF
e.g. 10uF
VDDC
VSSC
VSSP VDDP
RESET
typ.
100nF
EVR
30k
XC866
Figure 20
Reset Circuitry
Data Sheet
49
V1.0, 2006-02
XC866
Functional Description
Voltage
5V
VDDP
VDDC
2.5V
2.3V
0.9*VDDC
Time
Voltage
5V
RESET with
capacitor
< 0.4V
0V
Time
typ. < 50 us
Figure 21
VDDP, VDDC and VRESET during Power-on Reset
The second type of reset in XC866 is the hardware reset. This reset function can be used
during normal operation or when the chip is in power-down mode. A reset input pin
RESET is provided for the hardware reset.
The Watchdog Timer (WDT) module is also capable of resetting the device if it detects
a malfunction in the system.
Another type of reset that needs to be detected is a reset while the device is in
power-down mode (wake-up reset). While the contents of the static RAM are undefined
after a power-on reset, they are well defined after a wake-up reset from power-down
mode.
Data Sheet
50
V1.0, 2006-02
XC866
Functional Description
3.7.1
Module Reset Behavior
Table 16 shows how the functions of the XC866 are affected by the various reset types.
A “ ” means that this function is reset to its default state.
Table 16
Effect of Reset on Device Functions
Module/
Wake-Up
Reset
Watchdog Hardware
Reset Reset
Power-On
Reset
Brownout
Reset
Function
CPU Core
Peripherals
On-Chip
Not affected, Not affected, Not affected, Affected, un- Affected, un-
Static RAM
reliable
reliable
reliable
reliable
reliable
Oscillator,
Not affected
PLL
Port Pins
EVR
The voltage Not affected
regulator is
switched on
FLASH
NMI
Disabled
Booting Scheme
Disabled
3.7.2
When the XC866 is reset, it must identify the type of configuration with which to start the
different modes once the reset sequence is complete. Thus, boot configuration
information that is required for activation of special modes and conditions needs to be
applied by the external world through input pins. After power-on reset or hardware reset,
the pins MBC, TMS and P0.0 collectively select the different boot options. Table 17
shows the available boot options in the XC866.
Table 17
XC866 Boot Selection
MBC TMS P0.0 Type of Mode
PC Start Value
1
0
0
0
0
1
x
x
0
User Mode; on-chip OSC/PLL non-bypassed 0000
BSL Mode; on-chip OSC/PLL non-bypassed 0000
H
H
H
OCDS Mode; on-chip OSC/PLL non-
bypassed
Standalone User (JTAG) Mode ; on-chip
OSC/PLL non-bypassed (normal)
0000
1)
1
1
0
0000
H
1)
Normal user mode with standard JTAG (TCK,TDI,TDO) pins for hot-attach purpose.
Data Sheet
51
V1.0, 2006-02
XC866
Functional Description
3.8
Clock Generation Unit
The Clock Generation Unit (CGU) allows great flexibility in the clock generation for the
XC866. The power consumption is indirectly proportional to the frequency, whereas the
performance of the microcontroller is directly proportional to the frequency. During user
program execution, the frequency can be programmed for an optimal ratio between
performance and power consumption. Therefore the power consumption can be
adapted to the actual application state.
Features:
• Phase-Locked Loop (PLL) for multiplying clock source by different factors
• PLL Base Mode
• Prescaler Mode
• PLL Mode
• Power-down mode support
The CGU consists of an oscillator circuit and a PLL.In the XC866, the oscillator can be
from either of these two sources: the on-chip oscillator (10 MHz) or the external oscillator
(3 MHz to 12 MHz). The term “oscillator” is used to refer to both on-chip oscillator and
external oscillator, unless otherwise stated. After the reset, the on-chip oscillator will be
used by default.The external oscillator can be selected via software. In addition, the PLL
provides a fail-safe logic to perform oscillator run and loss-of-lock detection. This allows
emergency routines to be executed for system recovery or to perform system shut down.
osc fail
OSCR
detect
lock
detect
LOCK
OSC
P:1
fsys
PLL
core
fvco
fosc
K:1
fp
fn
N:1
PLLBYP
OSCDISC
VCOBYP
NDIV
Figure 22
CGU Block Diagram
Data Sheet
52
V1.0, 2006-02
XC866
Functional Description
Direct Drive (PLL Bypass Operation)
During PLL bypass operation, the system clock has the same frequency as the external
clock source. For the XC866, the PLL bypass cannot be set active. Hence, the direct
drive mode is not available for use.
fSYS = fOSC
PLL Base Mode
The system clock is derived from the VCO base frequency clock divided by the K factor.
Both VCO bypass and PLL bypass must be inactive for this PLL mode.
1
---
fSYS = fVCObase
×
K
Prescaler Mode (VCO Bypass Operation)
In VCO bypass operation, the system clock is derived from the oscillator clock, divided
by the P and K factors.
1
-------------
fSYS = fOSC
×
P × K
PLL Mode
The system clock is derived from the oscillator clock, multiplied by the N factor, and
divided by the P and K factors. Both VCO bypass and PLL bypass must be inactive for
this PLL mode. The PLL mode is used during normal system operation. .
N
-------------
fSYS = fOSC
×
P × K
System Frequency Selection
For the XC866, the values of P and K are fixed to “1” and “2”, respectively. In order to
obtain the required system frequency, f , the value of N can be selected by bit NDIV
sys
for different oscillator inputs. Table 18 provides examples on how f = 80 MHz can be
sys
obtained for the different oscillator sources.
Table 18
Oscillator
On-chip
System frequency (fsys = 80 MHz)
fosc
N
P
K
2
fsys
80 MHz
10 MHz
16
1
Data Sheet
53
V1.0, 2006-02
XC866
Functional Description
Table 18
Oscillator
External
System frequency (fsys = 80 MHz)
fosc
N
P
1
1
1
K
2
2
2
fsys
10 MHz
8 MHz
5 MHz
16
20
32
80 MHz
80 MHz
80 MHz
Table 19 shows the VCO range for the XC866.
Table 19
fVCOmin
150
VCO Range
fVCOmax
200
fVCOFREEmin
20
10
fVCOFREEmax
80
80
Unit
MHz
MHz
100
150
3.8.1
Resonator Circuitry
Figure 23 shows the recommended ceramic resonator circuitry. When using an external
resonator, its frequency can be within the range of 3 MHz to 12 MHz. A resonator load
circuitry must be used, connected to both pins, XTAL1 and XTAL2. It normally consists
of two load capacitances C and C , and in some cases, a feedback (R ) and/or damp
1
2
f
(R ) resistor might be necessary.
d
C1
XTAL1
Ceramic
Rf
XC866
Resonator
C2
Rd
XTAL2
Figure 23
External Ceramic Resonator Circuitry
Note: The manufacturer of the ceramic resonator should check the resonator circuitry
and make recommendations for the C1, C2, Rf and Rd values to be used for stable
start-up behavior.
Data Sheet
54
V1.0, 2006-02
XC866
Functional Description
3.8.2
Clock Management
The CGU generates all clock signals required within the microcontroller from a single
clock, f . During normal system operation, the typical frequencies of the different
sys
modules are as follow:
• CPU clock: CCLK, SCLK = 26.7 MHz
• CCU6 clock: FCLK = 26.7 MHz
• Other peripherals: PCLK = 26.7 MHz
• Flash Interface clock: CCLK3 = 80 MHz and CCLK = 26.7 MHz
In addition, different clock frequency can output to pin CLKOUT(P0.0). The clock output
frequency can further be divided by 2 using toggle latch (bit TLEN is set to 1), the
resulting output frequency has 50% duty cycle. Figure 24 shows the clock distribution of
the XC866.
CLKREL
FCLK
CCU6
PCLK
fosc
fsys
Peripherals
CORE
PLL
OSC
/3
SCLK
CCLK
N,P,K
FLASH
CCLK3
Interface
COREL
COUTS
TLEN
Toggle
Latch
CLKOUT
Figure 24
Clock Generation from fsys
Data Sheet
55
V1.0, 2006-02
XC866
Functional Description
For power saving purposes, the clocks may be disabled or slowed down according to
Table 20.
Table 20
System frequency (fsys = 80 MHz)
Power Saving Mode Action
Idle
Clock to the CPU is disabled.
Slow-down
Clocks to the CPU and all the peripherals, including CCU6, are
divided by a common programmable factor defined by bit field
CMCON.CLKREL.
Power-down
Oscillator and PLL are switched off.
Data Sheet
56
V1.0, 2006-02
XC866
Functional Description
3.9
Power Saving Modes
The power saving modes of the XC866 provide flexible power consumption through a
combination of techniques, including:
• Stopping the CPU clock
• Stopping the clocks of individual system components
• Reducing clock speed of some peripheral components
• Power-down of the entire system with fast restart capability
After a reset, the active mode (normal operating mode) is selected by default (see
Figure 25) and the system runs in the main system clock frequency. From active mode,
different power saving modes can be selected by software. They are:
• Idle mode
• Slow-down mode
• Power-down mode
ACTIVE
any interrupt
& SD=0
EXINT0/RXD pin
& SD=0
set PD
bit
set IDLE
bit
set SD
bit
clear SD
bit
POWER-DOWN
IDLE
set IDLE
bit
set PD
bit
any interrupt
& SD=1
EXINT0/RXD pin
& SD=1
SLOW-DOWN
Figure 25
Transition between Power Saving Modes
Data Sheet
57
V1.0, 2006-02
XC866
Functional Description
3.10
Watchdog Timer
The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and
recover from software or hardware failures. The WDT is reset at a regular interval that is
predefined by the user. The CPU must service the WDT within this interval to prevent the
WDT from causing an XC866 system reset. Hence, routine service of the WDT confirms
that the system is functioning properly. This ensures that an accidental malfunction of
the XC866 will be aborted in a user-specified time period. In debug mode, the WDT is
suspended and stops counting. Therefore, there is no need to refresh the WDT during
debugging.
Features:
• 16-bit Watchdog Timer
• Programmable reload value for upper 8 bits of timer
• Programmable window boundary
• Selectable input frequency of f
/2 or f
/128
PCLK
PCLK
• Time-out detection with NMI generation and reset prewarning activation (after which
a system reset will be performed)
The WDT is a 16-bit timer incremented by a count rate of f
/2 or f
/128. This
PCLK
PCLK
16-bit timer is realized as two concatenated 8-bit timers. The upper 8 bits of the WDT
can be preset to a user-programmable value via a watchdog service access in order to
modify the watchdog expire time period. The lower 8 bits are reset on each service
access. Figure 26 shows the block diagram of the WDT unit.
WDT
WDTREL
Control
Clear
WDT Low Byte
1:2
MUX
WDT High Byte
fPCLK
1:128
Overflow/Time-out Control &
Window-boundary control
WDTTO
WDTRST
WDTIN
ENWDT
Logic
ENWDT_P
WDTWINB
Figure 26
WDT Block Diagram
Data Sheet
58
V1.0, 2006-02
XC866
Functional Description
If the WDT is not serviced before the timer overflow, a system malfunction is assumed.
As a result, the WDT NMI is triggered (assert WDTTO) and the reset prewarning is
entered. The prewarning period lasts for 30 count, after which the system is reset
H
(assert WDTRST).
The WDT has a “programmable window boundary” which disallows any refresh during
the WDT’s count-up. A refresh during this window boundary constitutes an invalid
access to the WDT, causing the reset prewarning to be entered but without triggering the
WDT NMI. The system will still be reset after the prewarning period is over. The window
boundary is from 0000 to the value obtained from the concatenation of WDTWINB and
H
00 .
H
8
After being serviced, the WDT continues counting up from the value (<WDTREL> * 2 ).
The time period for an overflow of the WDT is programmable in two ways:
• the input frequency to the WDT can be selected to be either f
/2 or f
/128
PCLK
PCLK
• the reload value WDTREL for the high byte of WDT can be programmed in register
WDTREL
The period, P
, between servicing the WDT and the next overflow can be determined
WDT
by the following formula:
2
(1 + WDTIN × 6) × (216 – WDTREL × 28)
PWDT = -----------------------------------------------------------------------------------------------------
fPCLK
If the Window-Boundary Refresh feature of the WDT is enabled, the period P
WDT
between servicing the WDT and the next overflow is shortened if WDTWINB is greater
than WDTREL, see Figure 27. This period can be calculated using the same formula by
replacing WDTREL with WDTWINB. For this feature to be useful, WDTWINB should not
be smaller than WDTREL.
Count
FFFFH
WDTWINB
WDTREL
time
No refresh
Refresh allowed
allowed
Figure 27
WDT Timing Diagram
Data Sheet
59
V1.0, 2006-02
XC866
Functional Description
Table 21 lists the possible watchdog time range that can be achieved for different
module clock frequencies . Some numbers are rounded to 3 significant digits.
Table 21
Watchdog Time Ranges
Reload value
in WDTREL
Prescaler for fPCLK
2 (WDTIN = 0)
26.7 MHz
19.2 µs
2.48 ms
128 (WDTIN = 1)
26.7 MHz
1.23 ms
159 ms
315 ms
FF
H
H
H
7F
00
4.92 ms
Data Sheet
60
V1.0, 2006-02
XC866
Functional Description
3.11
Universal Asynchronous Receiver/Transmitter
The Universal Asynchronous Receiver/Transmitter (UART) provides a full-duplex
asynchronous receiver/transmitter, i.e., it can transmit and receive simultaneously. It is
also receive-buffered, i.e., it can commence reception of a second byte before a
previously received byte has been read from the receive register. However, if the first
byte still has not been read by the time reception of the second byte is complete, one of
the bytes will be lost.
Features:
• Full-duplex asynchronous modes
– 8-bit or 9-bit data frames, LSB first
– fixed or variable baud rate
• Receive buffered
• Multiprocessor communication
• Interrupt generation on the completion of a data transmission or reception
The UART can operate in four asynchronous modes as shown in Table 22. Data is
transmitted on TXD and received on RXD.
Table 22
UART Modes
Operating Mode
Baud Rate
f /2
PCLK
Mode 0: 8-bit shift register
Mode 1: 8-bit shift UART
Mode 2: 9-bit shift UART
Mode 3: 9-bit shift UART
Variable
/32 or f
f
/64
PCLK
PCLK
Variable
There are several ways to generate the baud rate clock for the serial port, depending on
the mode in which it is operating. In mode 0, the baud rate for the transfer is fixed at
f
/2. In mode 2, the baud rate is generated internally based on the UART input clock
PCLK
and can be configured to either f
/32 or f
/64. The variable baud rate is set by
PCLK
PCLK
either the underflow rate on the dedicated baud-rate generator, or by the overflow rate
on Timer 1.
Data Sheet
61
V1.0, 2006-02
XC866
Functional Description
3.11.1
Baud-Rate Generator
The baud-rate generator is based on a programmable 8-bit reload value, and includes
divider stages (i.e., prescaler and fractional divider) for generating a wide range of baud
rates based on its input clock f
, see Figure 28.
PCLK
Fractional Divider
8-Bit Reload Value
FDSTEP
1
FDEN&FDM
FDM
1
0
Adder
fDIV
00
01
0
1
fBR
8-Bit Baud Rate Timer
0
11
10
fMOD
FDRES
(overflow)
FDEN
R
fDIV
fPCLK
Prescaler
clk
11
10
NDOV
01
00
‘0’
Figure 28
Baud-rate Generator Circuitry
The baud rate timer is a count-down timer and is clocked by either the output of the
fractional divider (f
) if the fractional divider is enabled (FDCON.FDEN = 1), or the
DIV
MOD
output of the prescaler (f ) if the fractional divider is disabled (FDEN = 0). For baud rate
generation, the fractional divider must be configured to fractional divider mode
(FDCON.FDM = 0). This allows the baud rate control run bit BCON.R to be used to start
or stop the baud rate timer. At each timer underflow, the timer is reloaded with the 8-bit
reload value in register BG and one clock pulse is generated for the serial channel.
Enabling the fractional divider in normal divider mode (FDEN = 1 and FDM = 1) stops the
baud rate timer and nullifies the effect of bit BCON.R. See Section 3.12.
The baud rate (f ) value is dependent on the following parameters:
BR
• Input clock f
PCLK
BRPRE
• Prescaling factor (2
) defined by bit field BRPRE in register BCON
• Fractional divider (STEP/256) defined by register FDSTEP
(to be considered only if fractional divider is enabled and operating in fractional divider
mode)
Data Sheet
62
V1.0, 2006-02
XC866
Functional Description
• 8-bit reload value (BR_VALUE) for the baud rate timer defined by register BG
The following formulas calculate the final baud rate without and with the fractional divider
respectively:
fPCLK
where 2BRPRE × (BR_VALUE + 1) > 1
-----------------------------------------------------------------------------------
baud rate =
16 × 2BRPRE × (BR_VALUE + 1)
fPCLK
STEP
×
----------------------------------------------------------------------------------- --------------
baud rate =
16 × 2BRPRE × (BR_VALUE + 1)
256
The maximum baud rate that can be generated is limited to fPCLK/32. Hence, for a module
clock of 26.7 MHz, the maximum achievable baud rate is 0.83 MBaud.
Standard LIN protocal can support a maximum baud rate of 20kHz, the baud rate
accuracy is not critical and the fractional divider can be disabled. Only the prescaler is
used for auto baud rate calculation. For LIN fast mode, which supports the baud rate of
20kHz to 115.2kHz, the higher baud rates require the use of the fractional divider for
greater accuracy.
Table 23 lists the various commonly used baud rates with their corresponding parameter
settings and deviation errors. The fractional divider is disabled and a module clock of
26.7 MHz is used.
Table 23
Typical Baud rates for UART with Fractional Divider disabled
Baud rate
Prescaling Factor Reload Value
(2BRPRE
(BR_VALUE + 1)
1 (BRPRE=000 ) 87 (57 )
Deviation Error
)
19.2 kBaud
9600 Baud
4800 Baud
2400 Baud
-0.22 %
-0.22 %
-0.22 %
-0.22 %
B
H
1 (BRPRE=000 )
174 (AE )
H
B
2 (BRPRE=001 )
174 (AE )
H
B
4 (BRPRE=010 )
174 (AE )
H
B
The fractional divider allows baud rates of higher accuracy (lower deviation error) to be
generated. Table 24 lists the resulting deviation errors from generating a baud rate of
115.2 kHz, using different module clock frequencies. The fractional divider is enabled
(fractional divider mode) and the corresponding parameter settings are shown.
Data Sheet
63
V1.0, 2006-02
XC866
Functional Description
Table 24
fPCLK
Deviation Error for UART with Fractional Divider enabled
Prescaling Factor Reload Value
STEP
Deviation
Error
+0.03 %
+0.11 %
-0.16 %
(2BRPRE
)
(BR_VALUE + 1)
10 (A )
26.67 MHz
13.33 MHz
6.67 MHz
1
1
1
177 (B1 )
H
H
7 (7 )
248 (F8 )
H
H
3 (3 )
212 (D4 )
H
H
Data Sheet
64
V1.0, 2006-02
XC866
Functional Description
3.11.2
Baud Rate Generation using Timer 1
In UART modes 1 and 3, Timer 1 can be used for generating the variable baud rates. In
theory, this timer could be used in any of its modes. But in practice, it should be set into
auto-reload mode (Timer 1 mode 2), with its high byte set to the appropriate value for the
required baud rate. The baud rate is determined by the Timer 1 overflow rate and the
value of SMOD as follows:
[3.1]
2SMOD × fPCLK
Mode 1, 3 baud rate= ----------------------------------------------------
32 × 2 × (256 – TH1)
3.12
Normal Divider Mode (8-bit Auto-reload Timer)
Setting bit FDM in register FDCON to 1 configures the fractional divider to normal divider
mode, while at the same time disables baud rate generation (see Figure 28). Once the
fractional divider is enabled (FDEN = 1), it functions as an 8-bit auto-reload timer (with
no relation to baud rate generation) and counts up from the reload value with each input
clock pulse. Bit field RESULT in register FDRES represents the timer value, while bit
field STEP in register FDSTEP defines the reload value. At each timer overflow, an
overflow flag (FDCON.NDOV) will be set and an interrupt request generated. This gives
an output clock fMOD that is 1/n of the input clock fDIV, where n is defined by 256 - STEP.
The output frequency in normal divider mode is derived as follows:
[3.2]
1
-----------------------------
fMOD = fDIV
×
256 – STEP
Data Sheet
65
V1.0, 2006-02
XC866
Functional Description
3.13
LIN Protocol
The UART can be used to support the Local Interconnect Network (LIN) protocol for both
master and slave operations. The LIN baud rate detection feature provides the capability
to detect the baud rate within LIN protocol using Timer 2. This allows the UART to be
synchronized to the LIN baud rate for data transmission and reception.
LIN is a holistic communication concept for local interconnected networks in vehicles.
The communication is based on the SCI (UART) data format, a single-master/multiple-
slave concept, a clock synchronization for nodes without stabilized time base. An
attractive feature of LIN is self-synchronization of the slave nodes without a crystal or
ceramic resonator, which significantly reduces the cost of hardware platform. Hence, the
baud rate must be calculated and returned with every message frame.
The structure of a LIN frame is shown in Figure 29. The frame consists of the:
• header, which comprises a Break (13-bit time low), Synch Byte (55 ), and ID field
H
• response time
• data bytes (according to UART protocol)
• checksum
Frame slot
Frame
Inter-
frame
space
Response
space
Header
Response
Checksum
Data 2 Data N
Protected
identifier
Data 1
Synch
Figure 29
3.13.1
Structure of LIN Frame
LIN Header Transmission
LIN header transmission is only applicable in master mode. In the LIN communication,
a master task decides when and which frame is to be transferred on the bus. It also
identifies a slave task to provide the data transported by each frame. The information
needed for the handshaking between the master and slave tasks is provided by the
master task through the header portion of the frame.
The header consists of a break and synch pattern followed by an identifier. Among these
three fields, only the break pattern cannot be transmitted as a normal 8-bit UART data.
Data Sheet
66
V1.0, 2006-02
XC866
Functional Description
The break must contain a dominant value of 13 bits or more to ensure proper
synchronization of slave nodes.
In the LIN communication, a slave task is required to be synchronized at the beginning
of the protected identifier field of frame. For this purpose, every frame starts with a
sequence consisting of a break field followed by a synch byte field. This sequence is
unique and provides enough information for any slave task to detect the beginning of a
new frame and be synchronized at the start of the identifier field.
Upon entering LIN communication, a connection is established and the transfer speed
(baud rate) of the serial communication partner (host) is automatically synchronized in
the following steps:
STEP 1: Initialize interface for reception and timer for baud rate measurement
STEP 2: Wait for an incoming LIN frame from host
STEP 3: Synchronize the baud rate to the host
STEP 4: Enter for Master Request Frame or for Slave Response Frame
Note: Re-synchronization and setup of baud rate are always done for every Master
Request Header or Slave Response Header LIN frame.
Data Sheet
67
V1.0, 2006-02
XC866
Functional Description
3.14
High-Speed Synchronous Serial Interface
The High-Speed Synchronous Serial Interface (SSC) supports full-duplex and
half-duplex synchronous communication. The serial clock signal can be generated by
the SSC internally (master mode), using its own 16-bit baud-rate generator, or can be
received from an external master (slave mode). Data width, shift direction, clock polarity
and phase are programmable. This allows communication with SPI-compatible devices
or devices using other synchronous serial interfaces.
Features:
• Master and slave mode operation
– Full-duplex or half-duplex operation
• Transmit and receive buffered
• Flexible data format
– Programmable number of data bits: 2 to 8 bits
– Programmable shift direction: LSB or MSB shift first
– Programmable clock polarity: idle low or high state for the shift clock
– Programmable clock/data phase: data shift with leading or trailing edge of the shift
clock
• Variable baud rate
• Compatible with Serial Peripheral Interface (SPI)
• Interrupt generation
– On a transmitter empty condition
– On a receiver full condition
– On an error condition (receive, phase, baud rate, transmit error)
Data Sheet
68
V1.0, 2006-02
XC866
Functional Description
Data is transmitted or received on lines TXD and RXD, which are normally connected to
the pins MTSR (Master Transmit/Slave Receive) and MRST (Master Receive/Slave
Transmit). The clock signal is output via line MS_CLK (Master Serial Shift Clock) or input
via line SS_CLK (Slave Serial Shift Clock). Both lines are normally connected to the pin
SCLK. Transmission and reception of data are double-buffered.
Figure 30 shows the block diagram of the SSC.
PCLK
SS_CLK
MS_CLK
Baud-rate
Generator
Clock
Control
Shift
Clock
RIR
TIR
Receive Int. Request
Transmit Int. Request
Error Int. Request
SSC Control Block
Register CON
EIR
Status
Control
TXD(Master)
RXD(Slave)
Pin
Control
16-Bit Shift
Register
TXD(Slave)
RXD(Master)
Transmit Buffer
Register TB
Receive Buffer
Register RB
Internal Bus
Figure 30
SSC Block Diagram
Data Sheet
69
V1.0, 2006-02
XC866
Functional Description
3.15
Timer 0 and Timer 1
Timers 0 and 1 are count-up timers which are incremented every machine cycle, or in
terms of the input clock, every 2 PCLK cycles. They are fully compatible and can be
configured in four different operating modes for use in a variety of applications, see
Table 25. In modes 0, 1 and 2, the two timers operate independently, but in mode 3, their
functions are specialized.
Table 25
Mode
0
Timer 0 and Timer 1 Modes
Operation
13-bit timer
The timer is essentially an 8-bit counter with a divide-by-32 prescaler.
This mode is included solely for compatibility with Intel 8048 devices.
1
2
3
16-bit timer
The timer registers, TLx and THx, are concatenated to form a 16-bit
counter.
8-bit timer with auto-reload
The timer register TLx is reloaded with a user-defined 8-bit value in THx
upon overflow.
Timer 0 operates as two 8-bit timers
The timer registers, TL0 and TH0, operate as two separate 8-bit counters.
Timer 1 is halted and retains its count even if enabled.
Data Sheet
70
V1.0, 2006-02
XC866
Functional Description
3.16
Timer 2
Timer 2 is a 16-bit general purpose timer (THL2) that has two modes of operation, a
16-bit auto-reload mode and a 16-bit one channel capture mode. If the prescalar is
disabled, Timer 2 counts with an input clock of PCLK/12. Timer 2 continues counting as
long as it is enabled.
Table 26
Mode
Timer 2 Modes
Description
Auto-reload Up/Down Count Disabled
• Count up only
• Start counting from 16-bit reload value, overflow at FFFF
H
• Reload event configurable for trigger by overflow condition only, or by
negative/positive edge at input pin T2EX as well
• Programmble reload value in register RC2
• Interrupt is generated with reload event
Up/Down Count Enabled
• Count up or down, direction determined by level at input pin T2EX
• No interrupt is generated
• Count up
– Start counting from 16-bit reload value, overflow at FFFF
– Reload event triggered by overflow condition
– Programmble reload value in register RC2
• Count down
H
– Start counting from FFFF , underflow at value defined in register
H
RC2
– Reload event triggered by underflow condition
– Reload value fixed at FFFF
• Count up only
H
Channel
capture
• Start counting from 0000 , overflow at FFFF
H
H
• Reload event triggered by overflow condition
• Reload value fixed at 0000
H
• Capture event triggered by falling/rising edge at pin T2EX
• Captured timer value stored in register RC2
• Interrupt is generated with reload or capture event
Data Sheet
71
V1.0, 2006-02
XC866
Functional Description
3.17
Capture/Compare Unit 6
The Capture/Compare Unit 6 (CCU6) provides two independent timers (T12, T13), which
can be used for Pulse Width Modulation (PWM) generation, especially for AC-motor
control. The CCU6 also supports special control modes for block commutation and
multi-phase machines.
The timer T12 can function in capture and/or compare mode for its three channels. The
timer T13 can work in compare mode only.
The multi-channel control unit generates output patterns, which can be modulated by
T12 and/or T13. The modulation sources can be selected and combined for the signal
modulation.
Timer T12 Features:
• Three capture/compare channels, each channel can be used either as a capture or as
a compare channel
• Supports generation of a three-phase PWM (six outputs, individual signals for
highside and lowside switches)
• 16-bit resolution, maximum count frequency = peripheral clock frequency
• Dead-time control for each channel to avoid short-circuits in the power stage
• Concurrent update of the required T12/13 registers
• Generation of center-aligned and edge-aligned PWM
• Supports single-shot mode
• Supports many interrupt request sources
• Hysteresis-like control mode
Timer T13 Features:
• One independent compare channel with one output
• 16-bit resolution, maximum count frequency = peripheral clock frequency
• Can be synchronized to T12
• Interrupt generation at period-match and compare-match
• Supports single-shot mode
Additional Features:
• Implements block commutation for Brushless DC-drives
• Position detection via Hall-sensor pattern
• Automatic rotational speed measurement for block commutation
• Integrated error handling
• Fast emergency stop without CPU load via external signal (CTRAP)
• Control modes for multi-channel AC-drives
• Output levels can be selected and adapted to the power stage
Data Sheet
72
V1.0, 2006-02
XC866
Functional Description
The block diagram of the CCU6 module is shown in Figure 31.
module kernel
compare
channel 0
channel 1
channel 2
address
decoder
1
1
1
dead-
time
multi-
trap
T12
channel
control
control
control
clock
control
start
T13
channel 3
compare
interrupt
control
1
3
2
2
2
3
1
input / output control
port control
CCU6_block_diagram
Figure 31
CCU6 Block Diagram
Data Sheet
73
V1.0, 2006-02
XC866
Functional Description
3.18
Analog-to-Digital Converter
The XC866 includes a high-performance 10-bit Analog-to-Digital Converter (ADC) with
eight multiplexed analog input channels. The ADC uses a successive approximation
technique to convert the analog voltage levels from up to eight different sources. The
analog input channels of the ADC are available at Port 2.
Features:
• Successive approximation
• 8-bit or 10-bit resolution
(TUE of ± 1 LSB and ± 2 LSB, respectively)
• Eight analog channels
• Four independent result registers
• Result data protection for slow CPU access
(wait-for-read mode)
• Single conversion mode
• Autoscan functionality
• Limit checking for conversion results
• Data reduction filter
(accumulation of up to 2 conversion results)
• Two independent conversion request sources with programmable priority
• Selectable conversion request trigger
• Flexible interrupt generation with configurable service nodes
• Programmable sample time
• Programmable clock divider
• Cancel/restart feature for running conversions
• Integrated sample and hold circuitry
• Compensation of offset errors
• Low power modes
Data Sheet
74
V1.0, 2006-02
XC866
Functional Description
3.18.1
ADC Clocking Scheme
A common module clock f
generates the various clock signals used by the analog
ADC
and digital parts of the ADC module:
• f
is input clock for the analog part.
ADCA
ADCI
• f
is internal clock for the analog part (defines the time base for conversion length
and the sample time). This clock is generated internally in the analog part, based on
the input clock f
• f
to generate a correct duty cycle for the analog components.
ADCA
is input clock for the digital part.
ADCD
The internal clock for the analog part f
is limited to a maximum frequency of 10 MHz.
ADCI
Therefore, the ADC clock prescaler must be programmed to a value that ensures f
ADCI
does not exceed 10 MHz. The prescaler ratio is selected by bit field CTC in register
GLOBCTR. A prescaling ratio of 32 can be selected when the maximum performance of
the ADC is not required.
fADC = fPCLK
fADCD
arbiter
registers
interrupts
digital part
fADCA
CTC
MUX
÷32
÷ 4
÷3
fADCI
analog
components
÷ 2
clock prescaler
analog part
1
fADCI
Condition: fADCI 10 MHz, where t ADCI =
≤
Figure 32
ADC Clocking Scheme
Data Sheet
75
V1.0, 2006-02
XC866
Functional Description
For module clock f
= 26.7 MHz, the analog clock f
frequency can be selected as
ADCI
ADC
shown in Table 27.
Table 27
fADCI Frequency Selection
Module Clock fADC
26.7 MHz
CTC
Prescaling Ratio Analog Clock fADCI
00
01
10
÷ 2
÷ 3
13.3 MHz (N.A)
8.9 MHz
B
B
B
÷ 4
6.7 MHz
11 (default)
÷ 32
833.3 kHz
B
As f
cannot exceed 10 MHz, bit field CTC should not be set to 00 when f
is
ADC
ADCI
B
26.7 MHz. During slow-down mode where f
may be reduced to 13.3 MHz, 6.7 MHz
ADC
etc., CTC can be set to 00 as long as the divided analog clock f
10 MHz. However, it is important to note that the conversion error could increase due to
loss of charges on the capacitors, if f becomes too low during slow-down mode.
does not exceed
ADCI
B
ADC
3.18.2
ADC Conversion Sequence
The analog-to-digital conversion procedure consists of the following phases:
• Synchronization phase (t
)
SYN
• Sample phase (t )
S
• Conversion phase
• Write result phase (t
)
WR
conversion start
trigger
Source
Channel
interrupt
Result
interrupt
interrupt
Sample Phase
Conversion Phase
fADCI
BUSY Bit
SAMPLE Bit
tSYN
tS
Write Result Phase
tWR
tCONV
Figure 33
ADC Conversion Timing
Data Sheet
76
V1.0, 2006-02
XC866
Functional Description
3.19
On-Chip Debug Support
The On-Chip Debug Support (OCDS) provides the basic functionality required for the
software development and debugging of XC800-based systems.
The OCDS design is based on these principles:
• use the built-in debug functionality of the XC800 Core
• add a minimum of hardware overhead
• provide support for most of the operations by a Monitor Program
• use standard interfaces to communicate with the Host (a Debugger)
Features:
• Set breakpoints on instruction address and within a specified address range
• Set breakpoints on internal RAM address
• Support unlimited software breakpoints in Flash/RAM code region
• Process external breaks
• Step through the program code
The OCDS functional blocks are shown in Figure 34. The Monitor Mode Control (MMC)
block at the center of OCDS system brings together control signals and supports the
overall functionality. The MMC communicates with the XC800 Core, primarily via the
Debug Interface, and also receives reset and clock signals. After processing memory
address and control signals from the core, the MMC provides proper access to the
dedicated extra-memories: a Monitor ROM (holding the code) and a Monitor RAM (for
1)
work-data and Monitor-stack). The OCDS system is accessed through the JTAG ,
which is an interface dedicated exclusively for testing and debugging activities and is not
normally used in an application. The dedicated MBC pin is used for external
configuration and debugging control.
Note: All the debug functionality described here can normally be used only after XC866
has been started in OCDS mode.
1)
The pins of the JTAG port can be assigned to either Port 0 (primary) or Ports 1 and 2 (secondary).
User must set the JTAG pins (TCK and TDI) as input during connection with the OCDS system.
Data Sheet
77
V1.0, 2006-02
XC866
Functional Description
Memory
Control
Unit
JTAG Module
TMS
Primary
Debug
TCK
TDI
TCK
TDI
User
Boot/
JTAG
Program Monitor
Interface
TDO
TDO
Memory
ROM
Control
Reset
Monitor Mode Control
Monitor &
MBC
Bootstrap loader
Control line
User
Internal
RAM
Monitor
RAM
WDT
Suspend
System
Control
Unit
Reset
Clock
Reset Clock Debug PROG PROG Memory
Interface & IRAM Data Control
Addresses
- parts of
OCDS
XC800
OCDS_XC800-Block_Diagram-UM-v0.2
Figure 34
3.19.1
OCDS Block Diagram
JTAG ID Register
This is a read-only register located inside the JTAG module, and is used to recognize the
device(s) connected to the JTAG interface. Its content is shifted out when
INSTRUCTION register contains the IDCODE command (opcode 04 ), and the same is
H
also true immediately after reset.
The JTAG ID register contents for the XC866 Flash devices are given in Table 28.
Table 28
Device Type
Flash
JTAG ID Summary
Device Name
XC866L-4FR
XC866-4FR
JTAG ID
1010 0083
100F 5083
1010 2083
1010 1083
H
H
H
H
XC866L-2FR
XC866-2FR
Data Sheet
78
V1.0, 2006-02
XC866
Functional Description
3.20
Identification Register
The XC866 identity register is located at Page 1 of address B3 .
H
ID
Identity Register
Reset Value: 0000 0010B
7
6
5
4
3
2
1
0
PRODID
VERID
r
r
Field
Bits Type Description
VERID
[2:0]
r
Version ID
010
B
PRODID
[7:3]
r
Product ID
00000
B
Data Sheet
79
V1.0, 2006-02
XC866
Electrical Parameters
4
Electrical Parameters
4.1
General Parameters
4.1.1
Parameter Interpretation
The parameters listed in this section represent partly the characteristics of the XC866
and partly its requirements on the system. To aid interpreting the parameters easily
when evaluating them for a design, they are indicated by the abbreviations in the
“Symbol” column:
• CC
These parameters indicate Controller Characteristics, which are distinctive features of
the XC866 and must be regarded for a system design.
• SR
These parameters indicate System Requirements, which must be provided by the
microcontroller system in which the XC866 designed in.
Data Sheet
80
V1.0, 2006-02
XC866
Electrical Parameters
4.1.2
Absolute Maximum Rating
Maximum ratings are the extreme limits to which the XC866 can be subjected to without
permanent damage.
Table 29
Absolute Maximum Rating Parameters
Parameter
Symbol
Limit Values
Unit Notes
min.
-40
-65
-40
-0.5
max.
125
150
150
6
Ambient temperature
Storage temperature
Junction temperature
Voltage on power supply pin with VDDP
respect to VSS
TA
TST
TJ
°C
°C
°C
V
under bias
under bias
Voltage on core supply pin with VDDC
respect to VSS
Voltage on any pin with respect VIN
to VSS
-0.5
-0.5
3.25
V
V
VDDP
+
Whatever is
lower
0.5 or
max. 6
10
Input current on any pin during
overload condition
IIN
-10
–
mA
mA
Absolute sum of all input currents Σ|IIN|
during overload condition
50
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
During absolute maximum rating overload conditions (VIN > VDDP or VIN < VSS
)
the voltage on VDDP pin with respect to ground (VSS) must not exceed the values
defined by the absolute maximum ratings.
Data Sheet
81
V1.0, 2006-02
XC866
Electrical Parameters
4.1.3
Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct
operation of the XC866. All parameters mentioned in the following table refer to these
operating conditions, unless otherwise noted.
Table 30
Operating Condition Parameters
Symbol Limit Values
Parameter
Unit Notes/
Conditions
min.
4.5
max.
5.5
Digital power supply voltage VDDP
V
5V range
3.0
3.6
V
3.3V range
Digital ground voltage
Digital core supply voltage
System Clock Frequency
Ambient temperature
VSS
VDDC
fSYS
TA
0
V
V
MHz
°C
°C
2.3
74
-40
-40
2.7
86
85
1)
SAF-XC866...
SAK-XC866...
125
1)
f
is the PLL output clock. During normal operating mode, CPU clock is f
/ 3. Please refer to Figure 24
SYS
SYS
for detailed description.
Data Sheet
82
V1.0, 2006-02
XC866
Electrical Parameters
4.2
DC Parameters
4.2.1
Input/Output Characteristics
Table 31
Input/Output Characteristics (Operating Conditions apply)
Parameter
Symbol
Limit Values Unit Test Conditions
min.
max.
VDDP = 5V Range
Output low voltage
VOL CC
–
–
1.0
0.4
V
V
V
IOL = 15 mA
IOL = 5 mA
IOH = -15 mA
Output high voltage
VOH CC VDDP - –
1.0
VDDP - –
V
V
IOH = -5 mA
0.4
Input low voltage on
port pins
(all except P0.0 & P0.1)
VILP SR
–
0.3 ×
VDDP
CMOS Mode
Input low voltage on
P0.0 & P0.1
Input low voltage on
RESET pin
Input low voltage on
TMS pin
Input high voltage on
port pins
(all except P0.0 & P0.1)
VILP0 SR -0.2
0.3 ×
V
V
V
V
CMOS Mode
CMOS Mode
CMOS Mode
CMOS Mode
VDDP
VILR SR
VILT SR
–
–
0.3 ×
VDDP
0.3 ×
VDDP
VIHP SR 0.7 ×
–
VDDP
Input high voltage on
P0.0 & P0.1
Input high voltage on
RESET pin
VIHP0 SR 0.7 × VDDP
V
V
V
V
V
CMOS Mode
CMOS Mode
CMOS Mode
CMOS Mode
VDDP
VIHR SR 0.7 ×
–
–
–
VDDP
Input high voltage on
TMS pin
VIHT SR 0.75 ×
VDDP
1)
Input Hysteresis
HYS CC 0.08 ×
VDDP
Input low voltage at
XTAL1
VILX SR VSS
-
0.3 ×
VDDC
0.5
Data Sheet
83
V1.0, 2006-02
XC866
Electrical Parameters
Table 31
Parameter
Input/Output Characteristics (Operating Conditions apply)
Symbol Limit Values Unit Test Conditions
min. max.
Input high voltage at
XTAL1
VIHX SR 0.7 × VDDC
V
VDDC + 0.5
Pull-up current
IPU SR
IPD SR
–
-150
–
-10
–
10
–
µA VIH,min
µA VIL,max
µA VIL,max
µA VIH,min
Pull-down current
Input leakage current
150
2)
IOZ1 CC -1
1
µA 0 < VIN < VDDP
,
T
≤ 125°C
A
Input current at XTAL1 IILX CC -10
Overload currenton any IOV SR -5
pin
10
5
µA
mA
3)
Absolute sum of
overload currents
Σ|IOV
|
–
–
25
15
mA
mA
SR
SR
Maximum current per
IM
pin(excludingVDDP and
VSS
)
Maximum current for all Σ|IM|
pins (excluding VDDP
–
60
mA
SR
and VSS
)
Maximum current into
IMVDDP
–
–
80
80
mA
mA
VDDP
SR
Maximum current out of IMVSS
VSS
SR
VDDP = 3.3V Range
Output low voltage
VOL CC
–
–
1.0
0.4
V
V
V
IOL = 8 mA
IOL = 2.5 mA
IOH = -8 mA
Output high voltage
VOH CC VDDP - –
1.0
VDDP - –
0.4
V
IOH = -2.5 mA
Data Sheet
84
V1.0, 2006-02
XC866
Electrical Parameters
Table 31
Input/Output Characteristics (Operating Conditions apply)
Parameter
Symbol
Limit Values Unit Test Conditions
min.
max.
Input low voltage on
port pins
(all except P0.0 & P0.1)
VILP SR
–
0.3 ×
VDDP
V
CMOS Mode
Input low voltage on
P0.0 & P0.1
Input low voltage on
RESET pin
Input low voltage on
TMS pin
Input high voltage on
port pins
(all except P0.0 & P0.1)
VILP0 SR -0.2
0.3 ×
V
V
V
V
CMOS Mode
CMOS Mode
CMOS Mode
CMOS Mode
VDDP
VILR SR
VILT SR
–
–
0.3 ×
VDDP
0.3 ×
VDDP
VIHP SR 0.7 ×
–
VDDP
Input high voltage on
P0.0 & P0.1
Input high voltage on
RESET pin
Input high voltage on
TMS pin
Input Hysteresis1)
VIHP0 SR 0.7 × VDDP
V
V
V
V
V
V
CMOS Mode
CMOS Mode
CMOS Mode
CMOS Mode
VDDP
VIHR SR 0.7 ×
–
–
–
VDDP
VIHT SR 0.75 ×
VDDP
HYS CC 0.03 ×
VDDP
Input low voltage at
XTAL1
Input high voltage at
XTAL1
VILX SR VSS
-
0.3 ×
VDDC
0.5
VIHX SR 0.7 × VDDC
VDDC + 0.5
Pull-up current
IPU SR
–
-50
–
-5
–
5
µA VIH,min
µA VIL,max
µA VIL,max
Pull-down current
IPD SR
50
–
µA VIH,min
Input leakage current2) IOZ1 CC -1
1
µA 0 < VIN < VDDP
,
T
≤ 125°C
A
Input current at XTAL1 IILX CC - 10
Overload currenton any IOV SR -5
pin
10
5
µA
mA
Data Sheet
85
V1.0, 2006-02
XC866
Electrical Parameters
Table 31
Parameter
Input/Output Characteristics (Operating Conditions apply)
Symbol Limit Values Unit Test Conditions
min.
–
max.
25
3)
Absolute sum of
overload currents
Σ|IOV
|
mA
mA
SR
SR
Maximum current per
IM
–
–
15
60
pin(excludingVDDP and
VSS
)
Maximum current for all Σ|IM|
pins (excluding VDDP
mA
SR
and VSS
)
Maximum current into
IMVDDP
–
–
80
80
mA
mA
VDDP
SR
Maximum current out of IMVSS
VSS
SR
1)
Not subjected to production test, verified by design/characterization. Hysteresis is implemented to avoid meta
stable states and switching due to internal ground bounce. It cannot be guaranteed that it suppresses switching
due to external system noise.
2)
3)
An additional error current (I ) will flow if an overload current flows through an adjacent pin. TMS pin and
INJ
RESET pin have internal pull devices and are not included in the input leakage current characteristic.
Not subjected to production test, verified by design/characterization.
Data Sheet
86
V1.0, 2006-02
XC866
Electrical Parameters
4.2.2
Supply Threshold Characteristics
5.0V
VDDPPW
VDDP
2.5V
VDDCPW
VDDCBO
VDDCRDR
VDDCBOPD
VDDC
VDDCPOR
Figure 35
Supply Threshold Parameters
Table 32
Supply Threshold Parameters (Operating Conditions apply)
Symbol Limit Values
Parameters
Unit
min.
CC 2.2
CC 2.0
typ.
2.3
2.1
max.
2.4
2.2
1)
V
V
prewarning voltage
V
V
V
V
DDC
DDCPW
brownout voltage in
DDC
DDCBO
active mode1)
RAM data retention voltage
V
V
CC 0.9
CC 1.3
1.0
1.5
1.1
1.7
V
V
DDCRDR
V
brownout voltage in
DDC
DDCBOPD
2)
power-down mode
3)
V
prewarning voltage
V
V
CC 3.4
CC 1.3
4.0
1.5
4.6
1.7
V
V
DDP
DDPPW
Power-on reset voltage2)4)
DDCPOR
1)
Detection is disabled in power-down mode.
2)
3)
Detection is enabled in both active and power-down mode.
Detection is enabled for external power supply of 5.0V.
Detection must be disabled for external power supply of 3.3V.
4)
The reset of EVR is extended by 300 µs typically after the VDDC reaches the power-on reset voltage.
Data Sheet
87
V1.0, 2006-02
XC866
Electrical Parameters
4.2.3
ADC Characteristics
The values in the table below are given for an analog power supply between 4.5 V to
5.5 V. The ADC can be used with an analog power supply down to 3 V. But in this case,
the analog parameters may show a reduced performance. All ground pins (V ) must be
SS
externally connected to one single star point in the system. The voltage difference
between the ground pins must not exceed 200mV.
Table 33
Parameter
ADC Characteristics (Operating Conditions apply; VDDP = 5V Range)
Symbol
Limit Values
Unit
Test Conditions/
Remarks
min.
typ . max.
Analog reference
voltage
Analog reference
ground
Analog input
voltage range
V
V
V
V
V
V
–
V
DDP
V
V
V
AREF
AGND
AGND
DDP
SS
SR + 1
+ 0.05
V
V
AREF
- 1
V
AREF
SS
SR - 0.05
SR
V
AIN
AGND
ADC clocks
f
f
–
–
20
–
40
10
MHz module clock
ADC
MHz internal analog clock
ADCI
See Figure 32
Sample time
t
CC (2 + INPCR0.STC) ×
µs
S
t
ADCI
Conversion time
Total unadjusted
error
t
CC See Section 4.2.3.1
µs
C
1)
2)
TUE CC –
–
–
–
10
±1
±2
20
LSB
LSB
pF
8-bit conversion.
10-bit conversion.
2)3)
Switched
C
–
AREFSW
capacitance at the
reference voltage
input
CC
2)4)
Switched
C
–
5
7
pF
AINSW
capacitance at the
analog voltage
inputs
CC
2)
2)
Input resistance of
the reference input
Input resistance of
theselectedanalog
channel
R
R
CC –
CC –
1
1
2
kΩ
kΩ
AREF
1.5
AIN
Data Sheet
88
V1.0, 2006-02
XC866
Electrical Parameters
1)
2)
3)
TUE is tested at V
= 5.0 V, V
= 0 V , V
= 5.0 V.
DDP
AREF
AGND
Not subject to production test, verified by design/characterization.
This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage
at once. Instead of this, smaller capacitances are successively switched to the reference voltage.
4)
The sampling capacity of the conversion C-Network is pre-charged to V
/2 before connecting the input to
AREF
the C-Network. Because of the parasitic elements, the voltage measured at ANx is lower than V
/2.
AREF
Analog Input Circuitry
REXT
RAIN, On
ANx
VAIN
CEXT
CAINSW
VAGNDx
Reference Voltage Input Circuitry
RAREF, On
VAREFx
VAREF
CAREFSW
VAGNDx
Figure 36
ADC Input Circuits
Data Sheet
89
V1.0, 2006-02
XC866
Electrical Parameters
4.2.3.1 ADC Conversion Timing
Conversion time, t = t × ( 1 + r × (3 + n + STC) ) , where
C
ADC
r = CTC + 2 for CTC = 00 , 01 or 10 ,
B
B
B
r = 32 for CTC = 11 ,
B
CTC = Conversion Time Control (GLOBCTR.CTC),
STC = Sample Time Control (INPCR0.STC),
n = 8 or 10 (for 8-bit and 10-bit conversion respectively),
t
= 1 / f
ADC
ADC
Data Sheet
90
V1.0, 2006-02
XC866
Electrical Parameters
4.2.4
Power Supply Current
Table 34
Power Supply Current Parameters (Operating Conditions apply;
VDDP = 5V range )
Parameter
Symbol
Limit Values Unit Test Condition
typ.1) max.2)
VDDP = 5V Range
Active Mode
Idle Mode
Active Mode with slow-down
enabled
3)
IDDP
IDDP
IDDP
22.6
17.2
7.2
24.5
19.7
8.2
mA
mA
mA
4)
5)
6)
Idle Mode with slow-down
enabled
IDDP
7.1
8
mA
1)
The typical IDDP values are periodically measured at TA = + 25 °C and VDDP = 5.0 V.
The maximum IDDP values are measured under worst case conditions (TA = + 125 °C and VDDP = 5.5 V).
2)
3)
I
(active mode) is measured with: CPU clock and input clock to all peripherals running at 26.7 MHz(set by
DDP
on-chip oscillator of 10 MHz and NDIV in PLL_CON to 0010 ), RESET = VDDP
.
B
4)
5)
6)
I
(idle mode) is measured with: CPU clock disabled, watchdog timer disabled, input clock to all peripherals
DDP
enabled and running at 26.7 MHz, RESET = VDDP
(active mode with slow-down mode) is measured with: CPU clock and input clock to all peripherals
.
I
DDP
running at 833 KHz by setting CLKREL in CMCON to 0101 , RESET = VDDP
.
B
I
(idle mode with slow-down mode) is measured with: CPU clock disabled, watchdog timer disabled, input
DDP
clock to all peripherals enabled and running at 833 KHz by setting CLKREL in CMCON to 0101 ,
B
RESET = VDDP
.
Data Sheet
91
V1.0, 2006-02
XC866
Electrical Parameters
Table 35
Power Down Current (Operating Conditions apply; VDDP = 5V range )
Parameter
Symbol
Limit Values Unit Test Condition
typ.1) max.2)
VDDP = 5V Range
Power-Down Mode
3)
4)
IPDP
1
-
10
30
µA T = + 25 °C.
A
µA T = + 85 °C.4)5)
A
1)
The typical IPDP values are measured at VDDP = 5.0 V.
2)
3)
4)
The maximum IPDP values are measured at VDDP = 5.5 V.
I
I
(power-down mode) has a maximum value of 200 µA at TA = + 125 °C.
PDP
(power-down mode) is measured with: RESET = VDDP, VAGND= VSS, RXD/INT0 = VDDP; rest of the ports
PDP
are programmed to be input with either internal pull devices enabled or driven externally to ensure no floating
inputs.
5)
Not subject to production test, verified by design/characterization.
Data Sheet
92
V1.0, 2006-02
XC866
Electrical Parameters
Table 36
Power Supply Current Parameters (Operating Conditions apply;
VDDP = 3.3V range)
Parameter
Symbol
Limit Values Unit Test Condition
typ.1) max.2)
VDDP = 3.3V Range
Active Mode
Idle Mode
Active Mode with slow-down
enabled
3)
IDDP
IDDP
IDDP
21.5
16.4
6.8
23.3
18.9
8
mA
mA
mA
4)
5)
6)
Idle Mode with slow-down
enabled
IDDP
6.8
7.8
mA
1)
The typical IDDP values are periodically measured at TA = + 25 °C and VDDP = 3.3 V.
2)
3)
The maximum IDDP values are measured under worst case conditions (TA = + 125 °C and VDDP = 3.6 V).
(active mode) is measured with: CPU clock and input clock to all peripherals running at 26.7 MHz(set by
I
DDP
on-chip oscillator of 10 MHz and NDIV in PLL_CON to 0010 ), RESET = VDDP
.
B
4)
5)
I
(idle mode) is measured with: CPU clock disabled, watchdog timer disabled, input clock to all peripherals
DDP
enabled and running at 26.7 MHz, RESET = VDDP
.
I
(active mode with slow-down mode) is measured with: CPU clock and input clock to all peripherals
DDP
running at 833 KHz by setting CLKREL in CMCON to 0101 , RESET = VDDP
.
B
6)
I
(idle mode with slow-down mode) is measured with: CPU clock disabled, watchdog timer disabled, input
DDP
clock to all peripherals enable and running at 833 KHz by setting CLKREL in CMCON to 0101 ,,
B
RESET = VDDP
.
Data Sheet
93
V1.0, 2006-02
XC866
Electrical Parameters
Table 37
Power Down Current (Operating Conditions apply; VDDP = 3.3V
range )
Parameter
Symbol
Limit Values Unit Test Condition
typ.1) max.2)
VDDP = 3.3V Range
Power-Down Mode
3)
4)
IPDP
1
-
10
30
µA T = + 25 °C.
A
µA T = + 85 °C.4)5)
A
1)
2)
3)
4)
The typical IPDP values are measured at VDDP = 3.3 V.
The maximum IPDP values are measured at VDDP = 3.6 V.
I
I
(power-down mode) has a maximum value of 200 µA at TA = + 125 °C.
(power-down mode) is measured with: RESET = VDDP, VAGND= VSS, RXD/INT0= VDDP; rest of the ports
PDP
PDP
are programmed to be input with either internal pull devices enabled or driven externally to ensure no floating
inputs.
5)
Not subject to production test, verified by design/characterization.
Data Sheet
94
V1.0, 2006-02
XC866
Electrical Parameters
4.3
AC Parameters
4.3.1
Testing Waveforms
The testing waveforms for rise/fall time, output delay and output high impedance are
shown in Figure 37, Figure 38 and Figure 39.
VDDP
90%
90%
10%
10%
VSS
tF
tR
Figure 37
Rise/Fall Time Parameters
VDDP
VDDE / 2
VDDE / 2
Test Points
VSS
Figure 38
Testing Waveform, Output Delay
VLoad + 0.1 V
VLoad - 0.1 V
VOH - 0.1 V
VOL - 0.1 V
Timing
Reference
Points
Figure 39
Testing Waveform, Output High Impedance
Data Sheet
95
V1.0, 2006-02
XC866
Electrical Parameters
4.3.2
Output Rise/Fall Times
Output Rise/Fall Times Parameters (Operating Conditions apply)
Table 38
Parameter
Symbol
Limit
Unit Test Conditions
Values
min. max.
VDDP = 5V Range
Rise/fall times
1) 2)
3)
t , t
–
–
10
10
ns
ns
20 pF.
20 pF.
R
F
F
VDDP = 3.3V Range
1) 2)
4)
Rise/fall times
t , t
R
1)
Rise/Fall time measurements are taken with 10% - 90% of the pad supply.
2)
3)
4)
Not all parameters are 100% tested, but are verified by design/characterization and test correlation.
Additional rise/fall time valid for C = 20pF - 100pF @ 0.125 ns/pF.
L
Additional rise/fall time valid for C = 20pF - 100pF @ 0.225 ns/pF.
L
V
DDP
90%
90%
10%
10%
V
SS
t
t
R
F
Figure 40
Rise/Fall Times Parameters
Data Sheet
96
V1.0, 2006-02
XC866
Electrical Parameters
4.3.3
Power-on Reset and PLL Timing
Power-On Reset and PLL Timing (Operating Conditions apply)
Table 39
Parameter
Symbol
Limit Values
Unit Test Conditions
min. typ. max.
Pad operating voltage VPAD CC 2.3
–
–
–
500
V
ns
On-Chip Oscillator
start-up time
tOSCST
CC
–
Flash initialization time tFINIT CC
–
–
160
500
–
–
µs
µs
1)
RESET hold time
tRST SR
VDDP rise time
(10% – 90%) ≤ 500µs
PLL lock-in in time
PLL accumulated jitter
tLOCK CC
D
P
–
–
–
–
200
0.7
µs
ns
2)
1)
RESET signal has to be active (low) until VDDC has reached 90% of its maximum value (typ. 2.5V).
PLL lock at 80 MHz using a 4 MHz external oscillator. The PLL Divider settings are K = 2, N = 40 and P = 1.
2)
VDDP
VPAD
VDDC
tOSCST
OSC
PLL unlock
tLOCK
PLL lock
PLL
Flash State
tRST
Reset
Initialization
tFINIT
Ready to Read
RESET
Pads
3)
1)Pad state undefined 2)ENPS control 3)As Programmed
2)
1)
I)until EVR is stable
III) until Flash go IV) CPU reset is released; Boot
to Ready-to-Read ROM software begin execution
II)until PLL is locked
Figure 4-1
Power-on Reset Timing
Data Sheet
97
V1.0, 2006-02
XC866
Electrical Parameters
4.3.4
On-Chip Oscillator Characteristics
On-chip Oscillator Characteristics (Operating Conditions apply)
Table 40
Parameter
Symbol
Limit Values
Unit Test Conditions
min. typ. max.
Nominal frequency
fNOM CC –
10
–
MHz under nominal
1)
conditions after
IFX-backend trimming
Chip-to-chipfrequency ∆fCC CC -2.5
–
–
2.5
5.0
%
%
with respect to fNOM
deviation
Long term frequency
deviation
∆fLT CC -5.0
with respect to fNOM, over
lifetime and temperature,
for one given device after
trimming
Short term frequency ∆fST CC -1.0
–
1.0
%
with respect to fNOM,
deviation
within one LIN message
(<10 ms .... 100 ms)
1)
Nominal condition: V
= 2.5 V, T = + 25°C.
A
DDC
Data Sheet
98
V1.0, 2006-02
XC866
Electrical Parameters
4.3.5
JTAG Timing
TCK Clock Timing (Operating Conditions apply; CL = 50 pF)
Symbol Limits
Table 41
Parameter
Unit
min max
TCK clock period
TCK high time
TCK low time
TCK clock rise time
TCK clock fall time
tTCK SR 50
t1 SR 20
t2 SR 20
−
ns
ns
ns
ns
ns
−
−
t3 SR
t4 SR
−
0.4
0.4
−
0.9 V DDP
0.1 V DDP
0.5 V DDP
TCK
t1
t2
t4
t3
tTCK
Figure 41
TCK Clock Timing
Data Sheet
99
V1.0, 2006-02
XC866
Electrical Parameters
Table 42
JTAG Timing (Operating Conditions apply; CL = 50 pF)
Symbol Limits
min max
Parameter
Unit
TMS setup to TCK
TMS hold to TCK
TDI setup to TCK
TDI hold to TCK
TDO valid output from TCK
TDO high impedance to valid output from TCK
TDO valid output to high impedance from TCK
t1 SR 8.0
t2 SR 5.0
t1 SR 11.0
t2 SR 6.0
−
ns
ns
ns
ns
ns
ns
ns
−
−
−
t3 CC
t4 CC
t5 CC
−
−
−
13
15
18
TCK
t2
t1
TMS
TDI
t2
t1
t4
t3
t5
TDO
Figure 42
JTAG Timing
Data Sheet
100
V1.0, 2006-02
XC866
Electrical Parameters
4.3.6
SSC Master Mode Timing
SSC Master Mode Timing (Operating Conditions apply; CL = 50 pF)
Table 43
Parameter
Symbol
Limit Values
Unit
min.
CC 2*T
max.
1)
SCLK clock period
MTSR delay from SCLK
MRST setup to SCLK
t0
t1
t2
t3
–
8
–
–
ns
ns
ns
ns
SSC
CC
0
SR 22
MRST hold from SCLK
SR
0
1)
T
= T
= 1/f
. When f
= 26.7MHz, t = 74.9ns. T
is the CPU clock period.
SSCmin
CPU
CPU
CPU
CPU
0
t0
SCLK1)
t1
t1
1)
MTSR
t2
t3
Data
MRST1)
valid
t1
1) This timing is based on the following setup: CON.PH = CON.PO = 0.
SSC_Tmg1
Figure 43
SSC Master Mode Timing
Data Sheet
101
V1.0, 2006-02
XC866
Package and Quality Declaration
5
Package and Quality Declaration
5.1
Package Outline
Figure 44
PG-TSSOP-38-4 Package Outline
Data Sheet
102
V1.0, 2006-02
XC866
Package and Quality Declaration
5.2
Quality Declaration
Table 44 shows the characteristics of the quality parameters in the XC866.
Table 44
Parameter
Quality Parameters
Symbol
Limit Values Unit
Notes
Min.
Max.
ESD susceptibility
according to Human Body
Model (HBM)
ESD susceptibility
according to Charged
Device Model (CDM) pins
VHBM
–
2000
V
V
Conforming to
EIA/JESD22-
A114-B
Conforming to
JESD22-C101-C
VCDM
–
500
Data Sheet
103
V1.0, 2006-02
h t t p : / / w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
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