TLV4946-2K [INFINEON]
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| 型号： | TLV4946-2K |
| 厂家： | 
Infineon |
| 描述： | 暂无描述 锁存器 |
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| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV4946-2L
Value Optimized Hall Effect Latch for Industrial and Consumer
Applications
Datasheet
Rev1.1, 2010-08-02
Sense and Control
Edition 2010-08-02
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2010 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
TLV4946-2L
Value Optimized Hall Effect Latch for Industrial and Consumer Applications
Revision History: 2010-08-02, Rev1.1
Previous Revisions: none
Page
Subjects (major changes since last revision)
all
TLV4946K and TLV4946-2K removed
We Listen to Your Comments
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Datasheet
1
Rev1.1, 2010-08-02
TLV4946-2L
Table of Contents
Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1
Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Target Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1
1.2
1.3
2
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Operating Modes and States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Functional Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1
2.2
2.3
2.4
2.5
2.6
3
Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1
3.2
3.3
3.4
4
4.1
4.2
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
TLV4946K and TLV4946-2K Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
TLV4946-2L Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Datasheet
4
Rev1.1, 2010-08-02
TLV4946-2L
List of Figures
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Pin Configuration and sensitive area (Top view, figure not to scale) . . . . . . . . . . . . . . . . . . . . . . . . 8
TLV4946xy Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Definition of the Magnetic Field direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Output Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Marking of the TLV4946K and TLV4946-2K distance of the chip to the upper side. . . . . . . . . . . . 14
PG-SC59-3-4 Package Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Footprint PG-SC59-3-4 (SOT23 compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10 Marking of the TLV4946-2L and distance of the chip to the upper side . . . . . . . . . . . . . . . . . . . . . 15
Figure 11 PG-SSO-3-2 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Datasheet
5
Rev1.1, 2010-08-02
TLV4946-2L
List of Tables
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
PIN Definitions for the PG-SC59-3-4 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
PIN Definitions for the PG-SSO-3-2 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Magnetic Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Datasheet
6
Rev1.1, 2010-08-02
High Precision Hall Effect Latch
TLV4946-2L
1
Product Description
1.1
Overview
The TLV4946-2L is a high precision Hall Effect Latch with highly accurate
switching thresholds for ambient operating temperatures up to 85°C.
1.2
Features
•
•
•
•
•
•
•
•
•
•
2.7 V to 18 V supply voltage operation.
Operation from unregulated power supply.
High sensitivity and high stability of the magnetic switching points.
High resistance to mechanical stress by active error compensation.
Reverse battery protection (-18 V).
Superior temperature stability.
Low jitter (typically 1 µs).
High ESD performance (± 4 kV HBM).
Digital output signal (open-drain).
Not suitable for automotive applications
1.3
Target Applications
The TLV4946-2L is ideally suited to detect the rotor position in Brushless DC (BLDC) Motors used in industrial and
consumer applications, such as: air conditioning systems, pumps, washing machines, DVD players, rolling shutter,
etc. The sensor also provides a reliable switching for index counting with small pole wheels and large air gaps.
The TLV4946-2L can also be used for index counting.
Product Name
Product Type
Order Code
Package
TLV4946-2L
Hall Effect Latch
SP000604340
PG-SSO-3-2
Datasheet
7
Rev1.1, 2010-08-02
TLV4946-2L
Functional Description
2
Functional Description
2.1
General
Precise magnetic switching thresholds and high temperature stability are achieved by active compensation circuits
and chopper techniques on chip. Offset voltages generated by temperature-induced stress or overmolding are
canceled so that high accuracy is achieved. The IC has an open collector output stage with 20 mA current sink
capability. A wide operating voltage range from 2.7 V to 18 V with reverse polarity protection down to -18 V makes
the TLV4946-2L suitable for a wide range of applications. A magnetic south pole with a field strength above Bop
turns the output on. A magnetic north pole exceeding Brp turns it off.
2.2
Pin Configuration
2.08 ± 0.1
Center of
Sensitive Area
1.35 ± 0.1
1
2
3
PG-SSO-3-2
Figure 1
Pin Configuration and sensitive area (Top view, figure not to scale)
Datasheet
8
Rev1.1, 2010-08-02
TLV4946-2L
Functional Description
2.3
Pin Description
Table 1
PIN Definitions for the PG-SSO-3-2 package
PIN No.
Name
Vs
Function
Supply Voltage
Ground
1
2
3
GND
Q
Output
2.4
Block Diagram
VS
Voltage Regulator
reverse polarity protected
Bias and
Compensation
Circuits
Oscillator
and
Sequencer
Q
Ref
GND
Low
Pass
Filter
Comparator
with
Hysteresis
Amplifier
Chopped
Hall Probe
Figure 2
TLV4946-2L Block Diagram
Datasheet
9
Rev1.1, 2010-08-02
TLV4946-2L
Functional Description
2.5
Operating Modes and States
Field Direction and Definition
Positive magnetic fields correspond to the south pole of the magnet targeting the branded side of the package.
N
S
Branded Side
Figure 3
Definition of the Magnetic Field direction
VQ
B
Brp
0
Bop
Figure 4
Output Signal
2.6
Functional Block Description
The chopped Hall Effect Latch comprises a Hall probe, a bias generator, compensation circuits, an oscillator and
an output transistor. The bias generator provides currents to the Hall probe and the active circuits. Compensation
circuits stabilize response of the IC over temperature and reduce the impact of process variations.
The Active Error Compensation rejects offsets in the signal path and reduces the impact of mechanical stress in
the package caused by molding, soldering and thermal effects.
The chopper technique together with the threshold generator and the comparator ensure high accurate magnetic
switching points.
Datasheet
10
Rev1.1, 2010-08-02
TLV4946-2L
Specification
3
Specification
3.1
Application circuit
Q
Q
GND
GND
VS
200Ω
VS
Figure 5
Application circuit
It is recommended to use a resistor of 200 Ω in the supply line for current limitation in the case of an overvoltage
pulse. Two capacitors of 4.7 nF enhance the EMC performance. The pull-up of 1.2 kΩ limits the current through
the output transistor.
3.2
Absolute Maximum Ratings
Stress above the maximum values listed in this section may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods may affect the reliability of the device. Exceeding only
one of these values may cause irreversible damage to the device.
Table 2
Absolute Maximum Ratings
Symbol
Parameter
Values
Unit
Note / Test Condition
Min.
- 40
- 40
- 18
-50
Typ. Max.
Maximum Ambient Temperature TA
Maximum Junction Temperature TJ
–
–
–
–
125
150
18
°C
°C
V
Supply Voltage
VS
Supply current through protection IS
50
mA
device
Output Voltage
VOUT
- 0.7
- 40
–
–
–
–
–
18
V
Storage Temperature
Magnetic flux density
TS
150
°C
B
unlimited mT
4 kV
1)
ESD Robustness HBM:
1.5 kΩ, 100 pF
VESD,HBM
–
1) According to EIA/JESD22-A114-E
Datasheet
11
Rev1.1, 2010-08-02
TLV4946-2L
Specification
3.3
Operating Range
The following operating conditions must not be exceeded in order to ensure correct operation of the TLV4946xy.
All parameters specified in the following sections refer to these operating conditions unless otherwise mentioned.
Table 3
Operating Range
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
2.7
-0.7
0
Typ. Max.
Supply Voltage
Output Voltage
Output Current
VS
VQ
IQ
–
–
–
–
18
18
20
85
V
V
mA
°C
Maximum Ambient Temperature TA
-40
3.4
Electrical Characteristics
Product characteristics include the spread of values guaranteed within the specified voltage and ambient
temperature range. typical characteristics are the median of the production (at Vs=12V and TA=25°C).
Table 4
Electrical Characteristics
Symbol
Parameter
Values
Unit
Note / Test Condition
Min.
2
Typ. Max.
Supply Current
IS
4
6
mA
mA
V
VS=2.7 V...18 V
VS=-18 V
Reverse Current
Output Saturation Voltage
Output leakage current
Output fall time1)
Output rise time1)
Chopper frequency
Switching frequency
Delay time3)
ISR
VQSAT
IQLEAK
tf
0
0.2
0.3
0.05
0.02
0.4
320
–
1
–
0.6
10
1
IQ=20 mA
–
µA
VQ=18 V
–
µs
RL=1.2k Ω, CL=50 pF
tr
–
1
µs
fOSC
fSW
td
–
–
152)
kHz
kHz
µs
0
–
13
–
Output jitter4)
tQJ
–
1
–
µsRMS
Typical value for a 1 kHz
square wave signal
Power-on Time5)
tPON
Rthja
–
–
13
–
µs
VS > 2.7 V
Thermal Resistance junction to
ambient6)
190
K/W
TLV4946-2L
1) See Figure 6
2) To operate the sensor at maximum switching frequency, the value of the magnetic signal amplitude must be 1.4 times
higher than the static fields. This is due to the -3 dB corner frequency of the low pass filter in the signal path.
3) Systematic delay between magnetic threshold reached and output.
4) Jitter is the unpredictable deviation of the output switching delay.
5) Time from applying VS. > 2.7 V to the sensor until the output state is valid.
6) Relationship between junction and ambient temperature: TJ=Tamb + Rthja .(VS . IS + VQS . IQ).
Datasheet
12
Rev1.1, 2010-08-02
TLV4946-2L
Specification
Applied
Magnetic
Field
BOP
BRP
td
td
tf
tr
VQ
90%
10%
Figure 6
Timing Diagram
Table 5
Magnetic Characteristics1)
Symbol
Parameter
Values
Unit
Note / Test Condition
Min.
0.5
-3.5
1.0
-1.5
–
Typ. Max.
Operate point
Release point
Hysteresis
BOP
2.0
-2.0
4.0
0
3.5
-0.5
6.0
1.5
–
mT
BRP
BHYS
BOFF
TC
mT
mT
Magnetic offset2)
mT
Temperature compensation of
magnetic thresholds
-350
ppm/°C
Repeatability of magnetic
thresholds3)
BREP
–
20
–
µTRMS
typical value for
ΔΒ/Δt > 12mT/ms
1) Over all operating conditions
2) BOFF = (BOP + BRP) / 2.
3) BREP is equivalent to the noise constant.
Datasheet
13
Rev1.1, 2010-08-02
TLV4946-2L
Package Information
4
Package Information
4.1
TLV4946-2L Package Outline
Year (y) = 0...9
Calendar Week (ww) = 01...52
Figure 7
Marking of the TLV4946-2L and distance of the chip to the upper side
Datasheet
14
Rev1.1, 2010-08-02
TLV4946-2L
Package Information
±0.1
0.8
x 45˚
7˚
±0.05
±0.08
4.16
4.06
0.2
2
A
1.9 MAX.
±0.05
1.52
(0.79)
0.6 MAX.
0.2+0.1
±0.05
0.4
1
2
3
±0.25
±1
1.27
±0.25
1.27
12.7
Adhesive
Tape
A
Tape
±0.4
±0.3
0.25-0.15
6.35
4
±0.1
±0.3
0.39
12.7
Total tolerance at 10 pitches ±1
1) No solder function area
GPO05358
Figure 8
PG-SSO-3-2 Package Outline
Datasheet
15
Rev1.1, 2010-08-02
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
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