TLS820D0EL V50_技术文档

Low Dropout Linear Voltage Regulator

TLS820D0

TLS820D0ELV50

TLS820D0ELV33

Linear Voltage Regulator

Data Sheet

Rev. 1.0, 2016-02-08

Automotive Power

TLS820D0

Table of Contents

1

2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3

3.1

3.2

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin Assignment TLS820D0ELV50 and TLS820D0ELV33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin Definitions and Functions TLS820D0ELV50 and TLS820D0ELV33 . . . . . . . . . . . . . . . . . . . . . . . 6

4

General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.1

4.2

4.3

5

Block Description and Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Voltage Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Typical Performance Characteristics Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Typical Performance Characteristics Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Typical Performance Characteristics Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Typical Performance Characteristics Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.1

5.2

5.3

5.4

5.5

5.6

5.7

5.8

6

Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Selection of External Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Further Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.1

6.2

6.2.1

6.2.2

6.3

6.4

6.5

7

8

Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Data Sheet

2

Rev. 1.0, 2016-02-08

Low Dropout Linear Voltage Regulator

TLS820D0

1

Overview

Features

•

Wide Input Voltage Range from 3.0 V to 40 V

Fixed Output Voltage 5 V or 3.3 V

Output Voltage Precision ≤ ±2 %

Output Current Capability up to 200 mA

Ultra Low Current Consumption typ. 40 µA

Very Low Dropout Voltage typ. 70 mV @100 mA

Stable with Ceramic Output Capacitor of 1 µF

Figure 1

PG-SSOP-14

Delayed Reset at Power-On with 2 Programmable Delay Times 8.5 ms

/ 16.5 ms

•

Adjustable Reset Threshold down to 2.50 V

Enable, Undervoltage Reset, Overtemperature Shutdown

Output Current Limitation

Wide Temperature Range

Green Product (RoHS compliant)

AEC Qualified

Data Sheet

3

Rev. 1.0, 2016-02-08

TLS820D0

Overview

Functional Description

The TLS820D0 is a high performance very low dropout linear voltage regulator for 5 V (TLS820D0V50) or 3.3 V

(TLS820D0V33) supply in a PG-SSOP-14 package.

With an input voltage range of 3 V to 40 V and very low quiescent of only 40 µA, these regulators are perfectly

suitable for automotive or any other supply systems connected to the battery permanently. The TLS820D0

provides an output voltage accuracy of 2 % and a maximum output current up to 200 mA.

The new loop concept combines fast regulation and very good stability while requiring only one small ceramic

capacitor of 1 µF at the output. At currents below 100 mA the device will have a very low typical dropout voltage

of only 70 mV (for 5 V device) and 80 mV (for 3.3 V device). The operating range starts already at input voltages

of only 3 V (extended operating range). This makes the TLS820D0 also suitable to supply automotive systems

that need to operate during cranking condition.

The device can be switched on and off by the Enable feature as described in Chapter 5.5.

The output voltage is supervised by the Reset feature, including Undervoltage Reset, delayed Reset at Power-On

and an adjustable lower Reset Threshold, more details can be found in Chapter 5.7.

Internal protection features like output current limitation and overtemperature shutdown are implemented to

protect the device against immediate damage due to failures like output short circuit to GND, over-current and

over-temperatures.

Choosing External Components

An input capacitor C_Iis recommended to compensate line influences. The output capacitor C_Qis necessary for

the stability of the regulating circuit. TLS820D0 is designed to be also stable with low ESR ceramic capacitors.

Type

Package

Marking

TLS820D0ELV50

TLS820D0ELV33

PG-SSOP-14

820D0V50

820D0V33

Data Sheet

4

Rev. 1.0, 2016-02-08

TLS820D0

Block Diagram

2

Block Diagram

I

Q

Current

Limitation

RO

Reset

EN

RADJ

DT

Enable

Bandgap

Reference

Temperature

Shutdown

GND

Figure 2

Block Diagram TLS820D0ELV50 and TLS820D0ELV33

Data Sheet

5

Rev. 1.0, 2016-02-08

TLS820D0

Pin Configuration

3

Pin Configuration

3.1

Pin Assignment TLS820D0ELV50 and TLS820D0ELV33

SSOP-14

I

1

2

3

4

5

6

7

14

13

12

11

10

9

Q

n.c.

EN

n.c.

RO

n.c.

GND

n.c.

DT

RADJ

n.c.

8

Figure 3

Pin Configuration

3.2

Pin Definitions and Functions TLS820D0ELV50 and TLS820D0ELV33

Symbol

Function

1

I

Input

It is recommended to place a small ceramic capacitor (e.g. 100 nF) to GND, close

to the IC terminals, in order to compensate line influences. See also Chapter 6.2.1

2, 4, 6, n.c.

7

not connected

Leave open or connect to GND

3

EN

Enable (integrated pull-down resistor)

Enable the IC with high level input signal;

Disable the IC with low level input signal;

5

8

GND

Ground

RADJ

Reset Threshold Adjustment

Connect to GND to use standard value;

Connect an external voltage divider to adjust reset threshold

9

DT

Delay Timing (integrated pull-down resistor)

Connect to GND or Q to select Reset timing acc. to Table 8

11

RO

Reset Output (integrated pull-up resistor to Q)

Open collector output;

Leave open if the reset function is not needed

10, 12, n.c.

13

not connected

Leave open or connect to GND

14

Q

Output Voltage

Connect output capacitor C_Qto GND close to the IC’s terminals, respecting the

values specified for its capacitance and ESR in “Functional Range” on Page 8

Pad

–

Exposed Pad

Connect to heatsink area;

Connect to GND

Data Sheet

6

Rev. 1.0, 2016-02-08

TLS820D0

General Product Characteristics

4

General Product Characteristics

4.1

Absolute Maximum Ratings

Table 1

Absolute Maximum Ratings¹⁾

T_j= -40 °C to +150 °C; all voltages with respect to ground (unless otherwise specified)

Parameter

Symbol

Values

Unit Note /

Test Condition

Number

Min. Typ. Max.

Input I, Enable EN

Voltage

V_I, V_EN

-0.3

–

45

7

V

–

P_4.1.1

P_4.1.3

P_4.1.6

Output Q, Reset Output RO

Voltage

V_Q, V_RO

–

Delay Timing DT, Reset Threshold Adjustment RADJ

Voltage

V_DT, V_RADJ-0.3

7

Temperatures

Junction Temperature

Storage Temperature

ESD Absorption

T_j

-40

-55

–

150

°C

–

P_4.1.7

P_4.1.8

T_stg

ESD Susceptibility to GND

V_ESD

-2

–

2

kV

V

²⁾HBM

³⁾CDM

P_4.1.9

-500

500

750

P_4.1.10

P_4.1.11

ESD Susceptibility Pin 1, 7, 8, 14 (corner V_ESD1,7,8,14-750

pins) to GND

V

1) Not subject to production test, specified by design.

2) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS001 (1.5 kΩ, 100 pF)

3) ESD susceptibility, Charged Device Model “CDM” according JEDEC JESD22-C101

Note:

1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the

data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not

designed for continuous repetitive operation.

Data Sheet

7

Rev. 1.0, 2016-02-08

TLS820D0

General Product Characteristics

4.2

Functional Range

Table 2

Functional Range

T_j= -40 °C to +150 °C; all voltages with respect to ground (unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note /

Test Condition

Number

Min.

V

Max.

40

1)

Input Voltage Range

V_I

_Q,nom+ V_dr

–

V

–

P_4.2.1

P_4.2.3

P_4.2.5

P_4.2.6

2)

Extended Input Voltage Range

Enable Voltage Range

V_I,ext

V_EN

C_Q

3.0

0

40

V

40

V

–

3)4)

Output Capacitor’s

1

–

µF

–

Requirements for Stability

3)

ESR

ESR(C_Q) –

T_j-40

–

100

150

Ω

–

P_4.2.7

P_4.2.9

Junction Temperature

°C

–

1) Output current is limited internaly and depends on the input voltage, see Electrical Characteristics for more details.

2) When V_Iis between V_I,ext,minand V_Q,nom+ V_dr, V_Q= V_I- V_dr. When V_Iis below V_I,ext,min, V_Qcan drop down to 0 V.

3) Not subject to production test, specified by design.

4) The minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30%

Note:Within the functional or operating range, the IC operates as described in the circuit description. The electrical

characteristics are specified within the conditions given in the Electrical Characteristics table.

Data Sheet

8

Rev. 1.0, 2016-02-08

TLS820D0

General Product Characteristics

4.3

Thermal Resistance

Note:This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go

to www.jedec.org.

Table 3

Thermal Resistance

Parameter

Symbol

Values

Typ.

Unit

Note /

Test Condition

Number

Min.

Max.

Package Version PG-SSOP-14

Junction to Case

1)

R_thJC

R_thJA

–

9

–

K/W

–

P_4.3.1

P_4.3.2

P_4.3.3

Junction to Ambient

43

128

¹⁾²⁾2s2p board

¹⁾³⁾1s0p board,

Junction to Ambient

footprint only

Junction to Ambient

R_thJA

–

58

50

–

K/W

¹⁾³⁾1s0p board,

300 mm²heatsink

area on PCB

¹⁾³⁾1s0p board,

600 mm²heatsink

area on PCB

P_4.3.4

P_4.3.5

R_thJA

1) Not subject to production test, specified by design

2) Specified R_thJAvalue is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product

(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).

Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.

3) Specified R_thJAvalue is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product

(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm³board with 1 copper layer (1 x 70µm Cu).

Data Sheet

9

Rev. 1.0, 2016-02-08

TLS820D0

Block Description and Electrical Characteristics

5

Block Description and Electrical Characteristics

5.1

Voltage Regulation

The output voltage V_Qis divided by a resistor network. This fractional voltage is compared to an internal voltage

reference and the pass transistor is driven accordingly.

The control loop stability depends on the output capacitor C_Q, the load current, the chip temperature and the

internal circuit design. To ensure stable operation, the output capacitor’s capacitance and its equivalent series

resistor (ESR) requirements given in “Functional Range” on Page 8 have to be maintained. For details, also see

the typical performance graph “Output Capacitor Series Resistor ESR(CQ) versus Output Current IQ” on

Page 15. As the output capacitor also has to buffer load steps, it should be sized according to the application’s

needs.

An input capacitor C_Iis recommended to compensate line influences. In order to block influences like pulses and

HF distortion at input side, an additional reverse polarity protection diode and a combination of several capacitors

for filtering should be used. Connect the capacitors close to the component’s terminals.

In order to prevent overshoots during start-up, a smooth ramp up function is implemented. This ensures almost

no output voltage overshoots during start-up, mostly independent from load and output capacitance.

Whenever the load current exceeds the specified limit, e.g. in case of a short circuit, the output current is limited

and the output voltage decreases.

The overtemperature shutdown circuit prevents the IC from immediate destruction under fault conditions (e.g.

output continuously short-circuit) by switching off the power stage. After the chip has cooled down, the regulator

restarts. This leads to an oscillatory behavior of the output voltage until the fault is removed. However, junction

temperatures above 150 °C are outside the maximum ratings and therefore significantly reduce the IC’s lifetime.

Regulated

Output Voltage

Supply

I_Q

I_I

I

Q

Current

Limitation

RO

Reset

EN

RADJ

DT

C

Enable

C_I

V_I

V_Q

Bandgap

Reference

LOAD

ESR

Temperature

Shutdown

C_Q

GND

Figure 4

Voltage Regulation

V

V_I

V_dr

V_Q,nom

V_I,ext,min

V_Q

t

Figure 5

Output Voltage vs. Input Voltage

Data Sheet

10

Rev. 1.0, 2016-02-08

TLS820D0

Block Description and Electrical Characteristics

Table 4

Electrical Characteristics Voltage Regulator 5 V version

T_j= -40 °C to +150 °C, V_I= 13.5 V, all voltages with respect to ground (unless otherwise specified)

Typical values are given at T_j= 25 °C

Parameter

Symbol

Values

Unit Note / Test Condition

Number

Min. Typ. Max.

Output Voltage Precision

V_Q

4.9

5.0

7.5

5.1

18

V

0.05 mA < I_Q< 200 mA

5.44 V < V_I< 28 V

P_5.1.1

P_5.1.2

P_5.1.7

4.9

0.05 mA < I_Q< 100 mA

5.27 V < V_I< 40 V

Output Voltage Start-up

slew rate

dV_Q/dt 3.0

V/ms V_I> 18 V/ms

C_Q= 1 µF

0.5 V < V_Q< 4.5 V

350 550 mA 0 V < V_Q< 4.8 V

Output Current Limitation

I_Q,max

201

P_5.1.8

Load Regulation

steady-state

∆V_Q,load-15

-1.5

5

mV

I_Q= 0.05 mA to 200 mA

V_I= 6 V

P_5.1.10

Line Regulation

steady-state

∆V_Q,line-20

0

20

mV

V_I= 8 V to 32 V

I_Q= 1 mA

P_5.1.12

P_5.1.14

P_5.1.15

P_5.1.18

P_5.1.19

P_5.1.20

Dropout Voltage

V_dr= V_I- V_Q

V_dr

–

140 340 mV ¹⁾I_Q= 200 mA

Dropout Voltage

V_dr= V_I- V_Q

V_dr

–

70

59

–

170 mV ¹⁾I_Q= 100 mA

Power Supply Ripple Rejection

PSRR

T_j,sd

T_j,sdh

–

dB

²⁾f_ripple= 100 Hz

_ripple= 0.5 Vpp

V

Overtemperature Shutdown

Threshold

151

–

200 °C

²⁾T_jincreasing

Overtemperature Shutdown

Threshold Hysteresis

15

–

K

²⁾T_jdecreasing

1) Measured when the output voltage V_Qhas dropped 100 mV from the nominal value obtained at V_I= 13.5V

2) Not subject to production test, specified by design

Data Sheet

11

Rev. 1.0, 2016-02-08

TLS820D0

Block Description and Electrical Characteristics

Table 5

Electrical Characteristics Voltage Regulator 3.3 V version

T_j= -40 °C to +150 °C, V_I= 13.5 V, all voltages with respect to ground (unless otherwise specified)

Typical values are given at T_j= 25 °C

Parameter

Symbol

Values

Unit Note / Test Condition

Number

Min. Typ. Max.

Output Voltage Precision

V_Q

3.23 3.3

3.37

18

V

0.05 mA < I_Q< 200 mA

3.72 V < V_I< 28 V

P_5.1.21

P_5.1.22

P_5.1.27

3.23 3.3

0.05 mA < I_Q< 100 mA

3.55 V < V_I< 40 V

Output Voltage Start-up

slew rate

dV_Q/dt 3.0

7.5

V/ms V_I> 18 V/ms

C_Q= 1 µF

0.33 V < V_Q< 2.97 V

350 550 mA 0 V < V_Q< 3.1 V

Output Current Limitation

I_Q,max

201

P_5.1.28

P_5.1.30

Load Regulation

steady-state

∆V_Q,load-15

-1.5

5

mV

I_Q= 0.05 mA to 200 mA

V_I= 6 V

Line Regulation

steady-state

∆V_Q,line-15

0

15

mV

V_I= 8 V to 32 V

I_Q= 1 mA

P_5.1.32

P_5.1.34

P_5.1.35

P_5.1.38

P_5.1.39

P_5.1.40

Dropout Voltage

V_dr= V_I- V_Q

V_dr

–

160 350 mV ¹⁾I_Q= 200 mA

Dropout Voltage

V_dr= V_I- V_Q

V_dr

–

80

63

–

175 mV ¹⁾I_Q= 100 mA

Power Supply Ripple Rejection

PSRR

T_j,sd

T_j,sdh

–

dB

²⁾f_ripple= 100 Hz

_ripple= 0.5 Vpp

V

Overtemperature Shutdown

Threshold

151

–

200 °C

²⁾T_jincreasing

Overtemperature Shutdown

Threshold Hysteresis

15

–

K

²⁾T_jdecreasing

1) Measured when the output voltage V_Qhas dropped 100 mV from the nominal value obtained at V_I= 13.5V

2) Not subject to production test, specified by design

Data Sheet

12

Rev. 1.0, 2016-02-08

TLS820D0

Block Description and Electrical Characteristics

5.2

Typical Performance Characteristics Voltage Regulator

Typical Performance Characteristics

Output Voltage V_Qversus

Junction Temperature T_j(3.3 V version)

Junction Temperature T_j(5 V version)

3.5

I_Q= 100mA

3.45

3.4

5.15

5.1

5.05

5

3.35

3.3

3.25

3.2

4.95

4.9

3.15

3.1

4.85

4.8

0

50

100

150

0

50

100

150

T_j[°C]

Dropout Voltage V_drversus

Junction Temperature T_j(3.3 V version)

Junction Temperature T_j(5 V version)

300

I_Q= 100 mA

I_Q= 200 mA

250

200

150

100

50

250

200

150

100

50

V_Q= 3.3 V

V_Q= 5 V

0

50

100

150

0

50

100

150

T_j[°C]

Data Sheet

13

Rev. 1.0, 2016-02-08

TLS820D0

Block Description and Electrical Characteristics

Load Regulation ∆V_Q,loadversus

Output Current Change I_Q

Line Regulation ∆V_Q,lineversus

Input Voltage V_I

0

−0.5

−1

8

6

4

−1.5

−2

2

−2.5

−3

0

−2

−3.5

V_I= 6 V

−4

I_Q= 1 mA

−4

−4.5

−5

T_j= −40 °C

T_j= 25 °C

T_j= 150 °C

T_j= −40 °C

−6

T_j= 25 °C

T_j= 150 °C

−8

0

50

100

150

200

10

15

20

25

30

I_Q[mA]

V_I[V]

Output Voltage V_Qversus

Input Voltage V_I(3.3 V version)

Input Voltage V_I(5 V version)

4

6

T_j= −40 °C

T_j= 25 °C

3.5

5

T_j= 150 °C

I_Q= 100 mA

3

I_Q= 100 mA

4

2.5

2

3

2

1

0

1.5

1

0.5

0

1

2

3

4

5

6

0

1

2

3

4

5

6

V_I[V]

Data Sheet

14

Rev. 1.0, 2016-02-08

TLS820D0

Block Description and Electrical Characteristics

Power Supply Ripple Rejection PSRR versus

ripple frequency f

Output Capacitor Series Resistor ESR(C_Q) versus

Output Current I_Q

10³

80

V_Q= 3.3 V

V_Q= 5 V

70

Unstable Region

10²

60

50

40

30

10¹

Stable Region

10⁰

20

10

0

I_Q= 10 mA

_Q= 1 μF

_ripple= 0.5 V_PP

10⁻¹

C

V

T_j= 25 °C

C_Q= 1 μF

T_j= 25 °C

10⁻²

10⁻¹

10⁰

10¹

10²

10³

0.05

1

10

200

I_Q[mA]

f [kHz]

Maximum Output Current I_Qversus

Input Voltage V_I

Dropout Voltage V_drversus

Output Current I_Q

800

300

V_Q= 3.3 V

T_j= −40 °C

V_Q= 5 V

700

600

500

400

300

200

100

0

T_j= 25 °C

T_j= 150 °C

V_Q= 0 V

250

T_j= 25 °C

200

150

100

50

0

10

20

30

40

0

50

100

150

200

V_I[V]

I_Q[mA]

Data Sheet

15

Rev. 1.0, 2016-02-08

TLS820D0

Block Description and Electrical Characteristics

5.3

Current Consumption

Table 6

Electrical Characteristics Current Consumption

T_j= -40 °C to +150 °C, V_I= 13.5 V (unless otherwise specified)

Typical values are given at T_j= 25 °C

Conditions of other pins: DT = GND

Parameter

Symbol

Values

Unit Note / Test Condition

Number

Min. Typ. Max.

Current Consumption

I_q= I_I

I_q,off

I_q

–

1.3

5

µA

V

_EN= 0 V; T_j< 105 °C

_EN= 0.4 V; T_j< 125 °C

P_5.3.1

P_5.3.3

P_5.3.4

P_5.3.7

P_5.3.9

Current Consumption

I_q= I_I

–

8

Current Consumption

I_q= I_I- I_Q

40

62

52

77

80

I_Q= 0.05 mA

T_j= 25 °C

Current Consumption

I_q= I_I- I_Q

I_q

I_Q= 0.05 mA

T_j< 125 °C

¹⁾I_Q= 200 mA

T_j< 125 °C

Current Consumption

I_q= I_I- I_Q

I_q

1) Not subject to production test, specified by design

Data Sheet

16

Rev. 1.0, 2016-02-08

TLS820D0

Block Description and Electrical Characteristics

5.4

Typical Performance Characteristics Current Consumption

Typical Performance Characteristics

Current Consumption I_qversus

Output Current I_Q

Current Consumption I_qversus

Input Voltage V_I

100

200

T_j= 25 °C

T_j= −40 °C

90

80

70

60

50

40

30

20

10

0

180

T_j= 25 °C

T_j= 150 °C

160

V_EN= 5 V

I_Q= 50 uA

140

120

100

80

60

40

20

0

50

100

I_Q[mA]

150

200

5

10

15

20

V_I[V]

25

30

35

40

Data Sheet

17

Rev. 1.0, 2016-02-08

TLS820D0

Block Description and Electrical Characteristics

5.5

Enable

The TLS820D0 can be switched on and off by the Enable feature: Connect a HIGH level as specified below (e.g.

the battery voltage) to pin EN to enable the device; connect a LOW level as specified below (e.g. GND) to shut it

down. The enable has a built in hysteresis to avoid toggling between ON/OFF state, if signals with slow slopes are

applied to the EN input.

Table 7

Electrical Characteristics Enable

T_j= -40 °C to +150 °C, V_I= 13.5 V, all voltages with respect to ground (unless otherwise specified)

Typical values are given at T_j= 25 °C

Parameter

Symbol

Values

Unit

Note / Test Condition

Number

Min. Typ. Max.

High Level Input Voltage

Low Level Input Voltage

Enable Threshold Hysteresis

High Level Input Current

V_EN,H

V_EN,L

V_EN,Hy

I_EN,H

2

–

V

V_Qsettled

V_Q≤ 0.1 V

–

P_5.5.1

P_5.5.2

P_5.5.3

P_5.5.4

P_5.5.6

P_5.5.7

–

0.8

–

V

100

–

mV

µA

MΩ

3.5

22

2.6

V

–

_EN= 3.3 V

I_EN,H

–

_EN≤ 18 V

Enable internal pull-down resistor R_EN

0.95 1.5

Data Sheet

18

Rev. 1.0, 2016-02-08

TLS820D0

Block Description and Electrical Characteristics

5.6

Typical Performance Characteristics Enable

Typical Performance Characteristics

Input Current I_INversus

Input Voltage V_IN(condition: V_EN= 0 V)

Enabled Input Current I_ENversus

Enabled Input Voltage V_EN

30

50

T_j= −40 °C

45

T_j= 25 °C

25

T_j= 150 °C

40

35

30

25

20

15

10

5

V_EN= 0V

20

15

10

5

0

10

20

30

40

0

10

20

30

40

V_IN[V]

V_EN[V]

Output Voltage V_Qversus

time (EN switched ON, 5 V version)

time (EN switched ON, 3.3 V version)

6

5

4

3

2

5

4

3

2

I_Q= 100 mA

T_j= −40 °C

I_Q= 100 mA

T_j= −40 °C

T_j= 25 °C

T_j= 150 °C

V_EN

T_j= 25 °C

T_j= 150 °C

V_EN

1

0

1

0

500

1000

t [us]

1500

2000

0

500

1000

t [us]

1500

2000

Data Sheet

19

Rev. 1.0, 2016-02-08

TLS820D0

Block Description and Electrical Characteristics

5.7

Reset

The TLS820D0’s output voltage is supervised by the Reset feature, including Undervoltage Reset, delayed Reset

at Power-On and an adjustable Reset Threshold.

The Undervoltage Reset function sets the pin RO to LOW, in case V_Qis falling for any reason below the Reset

Threshold V_RT,low

.

When the regulator is powered on, the pin RO is held at LOW for the duration of the Power-On Reset Delay Time

t_rd.

Supply

I

Q

VDD

R_RO,int

C_Q

Control

RO

Reset

S

R

I_RO

Reference

OR

Q

OR

Micro-

Controller

R_ADJ,1

Timer

RADJ

I_RADJ

DT

GND

R_ADJ,2

Figure 6

Block Diagram Reset Circuit

Reset Delay Time

The pin DT is used to set the desired Reset Delay Time t_rd. Connect this pin either to GND or Q to select the timing

according to Table 8.

Table 8

Reset DelayTime Selection

DT connected to

t_rd

GND

Q

16.5 ms

8.5 ms

Power-On Reset Delay Time

The power-on reset delay time is defined by the parameter t_rdand allows a microcontroller and oscillator to start

up. This delay time is the time period from exceeding the upper reset switching threshold V_RT,highuntil the reset is

released by switching the reset output “RO” from “LOW” to “HIGH”.

Undervoltage Reset Delay Time

Unlike the power-on reset delay time, the undervoltage reset delay time is defined by the parameter t_rdand

considers an output undervoltage event where the output voltage V_Qtrigger the V_RT,lowthreshold.

Reset Blanking Time

The reset blanking time t_rr,blankavoids that short undervoltage spikes trigger an unwanted reset “low” signal.

Data Sheet

20

Rev. 1.0, 2016-02-08

TLS820D0

Block Description and Electrical Characteristics

Reset Reaction Time

In case the output voltage of the regulator drops below the output undervoltage lower reset threshold V_RT,low, the

reset output “RO” is set to low, after the delay of the internal reset reaction time t_rr,int. The reset blanking time t_rr,blank

is part of the reset reaction time t_rr,int

.

Reset Output “RO”

The reset output “RO” is an open collector output with an integrated pull-up resistor. In case a lower-ohmic “RO”

signal is desired, an external pull-up resistor can be connected to the output “Q”. Since the maximum “RO” sink

current is limited, the minimum value of the optional external resistor “R_RO,ext” is given in Table “Reset Output

RO” on Page 23.

Reset Output “RO” Low for VQ ≥ 1 V

In case of an undervoltage reset condition reset output “RO” is held “low” for V_Q≥ 1 V, even if the input “I” is not

supplied and the voltage V_Idrops below 1 V. This is achieved by supplying the reset circuit from the output

capacitor.

Reset Adjust Function

The undervoltage reset switching threshold can be adjusted according to the application’s needs by connecting

an external voltage divider (R_ADJ1, R_ADJ2) at pin “RADJ”. For selecting the default threshold connect pin “RADJ” to

GND. The reset adjustment range for the TLS820D0ELV50 is given in Reset Threshold Adjustment Range. The

reset adjustment range for the TLS820D0ELV33 is given in Reset Threshold Adjustment Range.

When dimensioning the voltage divider, take into consideration that there will be an additional current constantly

flowing through the resistors.

With a voltage divider connected, the reset switching threshold V_RT,newis calculated as follows

(neglecting the Reset Adjust Pin Current I_RADJ):

V_RT,lo,new= V_RADJ,th× (R_ADJ,1+ R_ADJ,2) / R_ADJ,2

(1)

with

•

V

_RT,lo,new: Desired undervoltage reset switching threshold.

R

V

_ADJ,1, R_ADJ,2: Resistors of the external voltage divider, see Figure 6.

_RADJ,th: Reset adjust switching threshold given in Reset Adjustment Switching Threshold.

Data Sheet

21

Rev. 1.0, 2016-02-08

TLS820D0

Block Description and Electrical Characteristics

V_I

t

t < t_rr,blank

V_Q

V_RH

V_RT,high

V_RT,low

1 V

t

t_rd

t_rr,int

t_rd

t_rr,int

t_rd

t_rr,int

V_RO

t_rd

1V

V_RO,low

t

Thermal

Shutdown

Input

Voltage Dip

Under-

voltage

Spike at Over-

output load

Figure 7

Typical Timing Diagram Reset

Data Sheet

22

Rev. 1.0, 2016-02-08

TLS820D0

Block Description and Electrical Characteristics

Table 9

Electrical Characteristics Reset

T_j= -40 °C to +150 °C, V_I= 13.5 V, all voltages with respect to ground (unless otherwise specified)

Typical values are given at T_j= 25 °C

Parameter

Symbol

Values

Unit Note / Test Condition

Number

Min. Typ. Max.

Output Undervoltage Reset 5V Version only

Output Undervoltage Reset Upper V_RT,high

Switching Threshold

4.6

4.5

60

4.7

4.6

100

4.8

4.7

–

V

V_Qincreasing

P_5.7.1

P_5.7.2

Output Undervoltage Reset Lower V_RT,low

Switching Threshold - Default

V_Qdecreasing

RADJ = GND

Output Undervoltage Reset

Switching Hysteresis

V_RT,hy

V_RH

mV RADJ connected to GND P_5.7.3

Output Undervoltage Reset

200 400

–

mV RADJ = GND

P_5.7.4

Headroom V_Q- V_RT

Output Undervoltage Reset 3V3 Version only

Output Undervoltage Reset Upper V_RT,high

Switching Threshold

3.08 3.15 3.22

V

V_Qincreasing

P_5.7.5

P_5.7.6

Output Undervoltage Reset Lower V_RT,low

Switching Threshold - Default

3.0

60

3.05 3.13

V_Qdecreasing

RADJ = GND

Output Undervoltage Reset

Switching Hysteresis

V_RT,hy

V_RH

100

–

mV RADJ connected to GND P_5.7.7

Output Undervoltage Reset

100 250

mV RADJ = GND

P_5.7.8

P_5.7.9

Headroom V_Q- V_RT

Reset Threshold Adjustment

Reset Adjustment Switching

Threshold

V_RADJ,th

1.15 1.20 1.25

V

–

Reset Threshold Adjustment Range V_RT,range

Reset Output RO

2.5

–

4.4

2.9

V

for V_Q,nom= 5 V

P_5.7.10

P_5.7.11

for V_Q,nom= 3.3 V

Reset Output Low Voltage

V_RO,low

R_RO,int

R_RO,ext

–

0.2

20

–

0.4

36

–

V

1 V ≤ V_Q≤ V_RT;

P_5.7.12

R

_RO≥ 5.1 kΩ

Reset Output

Internal Pull-Up Resistor

13

5.1

kΩ

internally connected to Q P_5.7.13

Reset Output External

Pull-up Resistor to V_Q

1 V ≤ V_Q≤ V_RT

_RO≤ 0.4 V

;

P_5.7.14

V

Reset Delay Timing

Reset Delay Time

t_rd,slow

t_rd,fast

t_rr,blank

t_rr,int

13.2 16.5 19.8 ms

DT connected to GND

DT connected to Q

¹⁾for V_Q,nom= 3.3 V

²⁾for V_Q,nom= 5 V

for V_Q,nom= 3.3 V

for V_Q,nom= 5 V

P_5.7.20

P_5.7.21

P_5.7.22

P_5.7.46

P_5.7.23

P_5.7.36

Reset Delay Time

6.8

–

8.5

6

10.2 ms

Reset blanking time

–

µs

Reset blanking time

–

7

–

Internal Reset Reaction Time

Reset Delay Input DT

–

7

20

33

t_rr,int

–

10

Delay Input DT

V_DT,H

2.0

–

V

–

P_5.7.29

High Signal Valid

Data Sheet

23

Rev. 1.0, 2016-02-08

TLS820D0

Block Description and Electrical Characteristics

Table 9

Electrical Characteristics Reset (cont’d)

T_j= -40 °C to +150 °C, V_I= 13.5 V, all voltages with respect to ground (unless otherwise specified)

Typical values are given at T_j= 25 °C

Parameter

Symbol

Values

Unit Note / Test Condition

Number

Min. Typ. Max.

Delay Input DT

Low Signal Valid

V_DT,L

–

0.80

V

P_5.7.30

P_5.7.35

Delay Input DT

dV_DT/dt

1

–

V/µs V_DT,L< V_DT< V_DT,H

Signal Slew Rate

High Level Input Current

I_DT,H

R_DT

–

3.5

2.6

µA

V

_DT= 3.3 V

P_5.7.32

P_5.7.33

Delay Input DT

0.9

1.5

MΩ

internal pull-down resistor

1) Not subject to production test, specified by design.

2) Not subject to production test, specified by design.

Data Sheet

24

Rev. 1.0, 2016-02-08

TLS820D0

Block Description and Electrical Characteristics

5.8

Typical Performance Characteristics Reset

Typical Performance Characteristics

Undervoltage Reset Threshold V_RTversus

Junction Temperature T_j(3.3 V version)

Undervoltage Reset Threshold V_RTversus

Junction Temperature T_j(5 V version)

3.5

3.4

3.3

3.2

3.1

3

5

4.9

4.8

4.7

4.6

4.5

4.4

2.9

2.8

4.3

I_Q= 1 mA

V_Q= 5 V

RADJ set to GND

V_Q= 3.3 V

2.7

2.6

2.5

4.2

4.1

4

RADJ set to GND

V_{RT, high}

V_{RT, low}

0

50

100

150

0

50

100

150

T_j[°C]

Power On Reset Delay Time t_rdversus

Junction Temperature T_j

Internal Reset Reaction Time t_rr,intversus

Junction Temperature T_j

25

20

V_Q= 3.3 V

fast

slow

I_Q= 1 mA

18

V_Q= 5 V

16

14

12

10

8

20

15

10

5

6

4

2

0

50

100

150

0

50

100

150

T_j[°C]

Data Sheet

25

Rev. 1.0, 2016-02-08

TLS820D0

Application Information

6

Application Information

6.1

Application Diagram

Note:The following information is given as a hint for the implementation of the device only and shall not be

regarded as a description or warranty of a certain functionality, condition or quality of the device.

Supply

Regulated Output Voltage

I

Q

Load

e. g.

Micro

Controller

XC22xx

D_I1

Current

Limitation

RO

Reset

EN

D_I2

C_I2

C_I1

C_Q

R₁

1µF

100nF

<45V

47µF

RADJ

DT

Enable

Bandgap

Reference

Temperature

Shutdown

R₂

GND

e.g. Ignition

Figure 8

Application Diagram

Note:This is a very simplified example of an application circuit. The function must be verified in the real application.

6.2

Selection of External Components

6.2.1

Input Pin

The typical input circuitry for a linear voltage regulator is shown in the application diagram above.

A ceramic capacitor at the input, in the range of 100 nF to 470 nF, is recommended to filter out the high frequency

disturbances imposed by the line e.g. ISO pulses 3a/b. This capacitor must be placed very close to the input pin

of the linear voltage regulator on the PCB.

An aluminum electrolytic capacitor in the range of 10 µF to 470 µF is recommended as an input buffer to smooth

out high energy pulses, such as ISO pulse 2a. This capacitor should be placed close to the input pin of the linear

voltage regulator on the PCB.

An overvoltage suppressor diode can be used to further suppress any high voltage beyond the maximum rating

of the linear voltage regulator and protect the device against any damage due to over-voltage.

The external components at the input are not mandatory for the operation of the voltage regulator, but they are

recommended in case of possible external disturbances.

6.2.2

Output Pin

An output capacitor is mandatory for the stability of linear voltage regulators.

The requirement to the output capacitor is given in “Functional Range” on Page 8. The graph “Output

Capacitor Series Resistor ESR(CQ) versus Output Current IQ” on Page 15 shows the stable operation range

of the device.

Data Sheet

26

Rev. 1.0, 2016-02-08

TLS820D0

Application Information

TLS820D0 is designed to be also stable with low ESR capacitors. According to the automotive requirements,

ceramic capacitors with X5R or X7R dielectrics are recommended.

The output capacitor should be placed as close as possible to the regulator’s output and GND pins and on the

same side of the PCB as the regulator itself.

In case of rapid transients of input voltage or load current, the capacitance should be dimensioned in accordance

and verified in the real application that the output stability requirements are fulfilled.

6.3

Thermal Considerations

Knowing the input voltage, the output voltage and the load profile of the application, the total power dissipation

can be calculated:

P_D= (V_I- V_Q) × I_Q+ V_I× I_q

(2)

with

•

P_D: continuous power dissipation

V_I: input voltage

V_Q: output voltage

I_Q: output current

I_q: quiescent current

The maximum acceptable thermal resistance R_thJAcan then be calculated:

R_thJA,max= ( T_j,max- T_a) / P_D

(3)

with

•

T

_j,max: maximum allowed junction temperature

T_a: ambient temperature

Based on the above calculation the proper PCB type and the necessary heat sink area can be determined with

reference to the specification in “Thermal Resistance” on Page 9.

Example

Application conditions:

V_I= 13.5 V

V_Q= 5 V

I_Q= 150 mA

T_a= 85 °C

Calculation of R_thJA,max

:

P_D= (V_I– V_Q) × I_Q+ V_I× I_q

= (13.5 V – 5 V) × 150 mA

= 1.275 W

(V_I× I_qcan be neglected because of very low I_q)

R_thJA,max= (T_j,max– T_a) / P_D

= (150 °C – 85 °C) / 1.275 W = 50.98 K/W

Data Sheet

27

Rev. 1.0, 2016-02-08

TLS820D0

Application Information

As a result, the PCB design must ensure a thermal resistance R_thJAlower than 50.98 K/W. According to “Thermal

Resistance” on Page 9, at least 600 mm²heatsink area is needed on the FR4 1s0p PCB, or the FR4 2s2p board

can be used to ensure a proper cooling for the TLS820D0 in PG-SSOP-14 package.

6.4

Reverse Polarity Protection

TLS820D0 is not self protected against reverse polarity faults and must be protected by external components

against negative supply voltage. An external reverse polarity diode is needed. The absolute maximum ratings of

the device as specified in “Absolute Maximum Ratings” on Page 7 must be kept.

6.5

Further Application Information

•

For further information you may contact http://www.infineon.com/

Data Sheet

28

Rev. 1.0, 2016-02-08

TLS820D0

Package Outlines

7

Package Outlines

0.35 x 45°

1)

0.1 H D 2x

±0.1

3.9

+0.06

H

0.19

0.08

SEATING

PLANE

C

0.64_±0.25

0.2 C 14x

0.65

6 x 0.65 = 3.9

D

±0.2

6

2)

±0.05

0.25

M

0.15

C A-B D 14x

Bottom View

±0.2

3

A

8

1

7

14

1

7

14

8

Exposed

Diepad

B

0.1 H A-B 2x

Index

Marking 4.9

1)

±0.1

1) Does not include plastic or metal protrusion of 0.15 max. per side

2) Lead width can be 0.61 max. in dambar area

PG-SSOP-14

Figure 9

PG-SSOP-14

Green Product (RoHS compliant)

To meet the world-wide customer requirements for environmentally friendly products and to be compliant with

government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e

Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).

For further information on alternative packages, please visit our website:

http://www.infineon.com/packages.

Dimensions in mm

Data Sheet

29

Rev. 1.0, 2016-02-08

TLS820D0

Revision History

8

Revision History

Revision

Date

Changes

Data Sheet - Initial version

1.0

2016-02-08

Data Sheet

30

Rev. 1.0, 2016-02-08

Trademarks of Infineon Technologies AG

AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, CoolMOS™, CoolSET™, CORECONTROL™, CROSSAVE™, DAVE™, DI-POL™, EasyPIM™, EconoBRIDGE™,

EconoDUAL™, EconoPIM™, EconoPACK™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™, ISOFACE™, IsoPACK™, LITIX™, MIPAQ™,

ModSTACK™, my-d™, NovalithIC™, OptiMOS™, ORIGA™, POWERCODE™, PRIMARION™, PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™,

ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SmartLEWIS™, SPOC™, SOLID FLASH™, TEMPFET™, thinQ!™, TRENCHSTOP™, TriCore™.

Other Trademarks

Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™, PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited,

UK. AUTOSAR™ is licensed by AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™, FirstGPS™ of

Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG. FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay

Consortium. HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data Association

Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc.

MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA

MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of OmniVision Technologies, Inc. Openwave™ Openwave

Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of

Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc.

TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas

Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited.

Last Trademarks Update 2011-11-11

www.infineon.com

Edition 2016-02-08

Published by

Infineon Technologies AG

81726 Munich, Germany

Legal Disclaimer

The information given in this document shall in

no event be regarded as

Warnings

Due to technical requirements, components

may contain dangerous substances. For

information on the types in question, please

contact the nearest Infineon Technologies

Office. Infineon Technologies components may

be used in life-support devices or systems only

with the express written approval of Infineon

Technologies, if a failure of such components

can reasonably be expected to cause the failure

of that life-support device or system or to affect

the safety or effectiveness of that device or

system. Life support devices or systems are

intended to be implanted in the human body or

to support and/or maintain and sustain and/or

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型号：	TLS820D0EL V50
厂家：	Infineon
描述：	TLS820D0EL V50 是一款高性能的极低压差线性稳压器系列，采用 SSOP14-EP 封装，适用于 5V 电源。这些稳压器的输入电压范围为 3 V 至 40 V，静态电流极低（仅 40μA），非常适合汽车或永久连接电池的任何其他电源系统。最大输出电流为 200mA，且过温输出电压精度为2％。新的回路概念结合了快速调节和非常好的稳定性，输出端只需要一个 1μF 的小型陶瓷电容即可。在低于 100 mA 的电流下，该设备的典型压差非常低，仅 70 mV。工作范围从仅 3 V 的输入电压开始（扩展工作范围）。因此，新型 LDO 也适用于需要在启动条件下运行的汽车系统。电池稳压器
文件：	总31页 (文件大小：1263K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TLS820D0EL V50 [INFINEON]

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