TLS820F3ELV50_技术文档

OPTIREG™ linear TLS820F3ELV50

Low dropout linear voltage regulator with watchdog and reset

Features

•

Output voltage 5 V ±2%

Current capability 200 mA

Input voltage range from 3 V to 42 V

Stable with 1 µF ceramic output capacitor

Ultra low current consumption: typically 26 µA

Very low drop out voltage: typically 100 mV at 100 mA

Watchdog circuit for monitoring a microprocessor

Watchdog inhibit

Output voltage supervision by reset circuit:

–

Programmable undervoltage reset threshold: minimum 2.5 V

Programmable delay time

•

Separate outputs for reset and watchdog

Enable

Output current limitation

Overtemperature shutdown

Green Product (RoHS compliant)

Potential applications

•

Automotive general ECUs

Telematics systems

ADAS cameras and radar systems

Navigation systems

Body control modules

Product validation

Qualified for automotive applications. Product validation according to AEC-Q100.

Datasheet

Rev. 1.0

2021-05-27

www.infineon.com/OPTIREG-linear

1

OPTIREG™ linear TLS820F3ELV50

Low dropout linear voltage regulator with watchdog and reset

Description

The OPTIREG™ linear TLS820F3ELV50 is a high performance low drop out fixed output voltage regulator in a

PG-SSOP-14 package. With an input voltage range of 3 V to 42 V and very low quiescent current of only 26 µA,

these regulators are perfectly suitable for automotive systems or other supply systems connected to the

battery permanently. The TLS820F3ELV50 provides an output voltage accuracy of ±2% and a maximum output

current of 200 mA.

The loop concept combines fast regulation and very good stability while requiring only one small ceramic

capacitor of 1 µF at the output. The operating range starts already at an input voltage of only 3 V (extended

operating range). This makes the TLS820F3ELV50 also suitable to supply automotive systems that need to

operate during cranking condition.

The device can be switched on and off via Enable.

The Reset supervises the output voltage, including undervoltage reset, delay reset at power-on and an

adjustable lower reset threshold.

An integrated Watchdog circuit with adjustable timing monitors the microcontroller’s operation. A shared

external delay capacitor sets both reset timing and watchdog timing.

Internal protection features such as output current limitation and overtemperature shutdown are

implemented to protect the device against immediate damage due to failures like output short circuit to GND,

overcurrent and overtemperature.

Type

Package

Marking

TLS820F3ELV50

PG-SSOP-14

820F3V50

Datasheet

2

Rev.1.0

2021-05-27

OPTIREG™ linear TLS820F3ELV50

Low dropout linear voltage regulator with watchdog and reset

Table of contents

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Potential applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Product validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2

2.1

2.2

Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin assignment PG-SSOP-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3

General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.1

3.2

3.3

4

4.1

Block description and electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Electrical characteristics voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Typical performance characteristics voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Typical performance characteristics current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Typical performance characteristics Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Electrical characteristics reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Typical performance characteristics reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Description watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Electrical characteristics watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Typical performance characteristics standard watchdog function . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.1.1

4.1.2

4.2

4.2.1

4.3

4.3.1

4.4

4.4.1

4.4.2

4.5

4.5.1

4.5.2

4.5.3

5

Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Selection of external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Input pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Output pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Reverse polarity protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Further application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.1

5.2

5.2.1

5.2.2

5.3

5.4

5.5

6

7

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Datasheet

3

Rev. 1.0

2021-05-27

OPTIREG™ linear TLS820F3ELV50

Low dropout linear voltage regulator with watchdog and reset

Block diagram

1

Block diagram

I

Q

Current

Limitation

RO

WO

EN

Enable

RADJ

D

Reset &

Watchdog

Generator

Primary

Reference

Temperature

Shutdown

WINH

WI

GND

Figure 1

Block diagram

Datasheet

4

Rev. 1.0

2021-05-27

OPTIREG™ linear TLS820F3ELV50

Low dropout linear voltage regulator with watchdog and reset

Pin configuration

2

Pin configuration

2.1

Pin assignment PG-SSOP-14

SSOP-14

Q

I

n.c.

EN

1

2

3

4

5

6

7

14

13

12

11

10

9

n.c.

WO

RO

n.c.

RADJ

D

n.c.

WINH

WI

8

GND

Figure 2

Pin assignment

2.2

Pin definitions and functions

Symbol Function

1

I

Input

It is recommended to connect a small ceramic capacitor from this pin to GND, close to

the pins, in order to compensate line influences.

2

3

n.c.

EN

Not connected

Leave this pin open or connect it to GND.

Enable input

"High" signal enables the IC.

"Low" signal disables the IC.

This pin has an integrated pull-down resistor.

4

5

n.c.

Not connected

Leave this pin open or connect it to GND.

WINH

Watchdog inhibit input

"Low" activates the watchdog function.

"High" deactivates the watchdog function.

This pin has an integrated pull-down resistor.

6

WI

Watchdog input

Serve watchdog with trigger input signal (usable for microcontroller monitoring).

This pin has an integrated pull-down resistor.

7

8

GND

D

Ground

Delay input

Connect an external capacitor from this pin to GND to set reset timing and watchdog

timing. If no capacitor is placed, then disable the watchdog.

Datasheet

5

Rev. 1.0

2021-05-27

OPTIREG™ linear TLS820F3ELV50

Low dropout linear voltage regulator with watchdog and reset

Pin configuration

Symbol Function

9

RADJ

Reset threshold adjustment

Connect this pin to GND to use the default reset threshold.

Connect this pin to an external voltage divider to set a reset threshold other than the

default value.

If the reset function is not needed, then connect this pin to Q.

10

11

n. c.

RO

Not connected

Leave this pin open or connect it to GND.

Reset output

This pin has an integrated pull-up resistor to Q.

If the reset function is not needed, then leave this pin open.

12

WO

Watchdog output

This pin has an integrated pull-up resistor to Q.

If the watchdog function is not needed, then leave this pin open.

13

14

n.c.

Q

Not connected

Leave this pin open or connect it to GND.

Regulator output

Connect the output capacitor C_Qfrom this pin to GND close to the pin, respecting the

values specified for its capacitance and ESR in Functional range.

Pad

–

Exposed pad

Connect the exposed pad to a heatsink area.

Connect the exposed pad to GND.

Datasheet

6

Rev. 1.0

2021-05-27

OPTIREG™ linear TLS820F3ELV50

Low dropout linear voltage regulator with watchdog and reset

General product characteristics

3

General product characteristics

3.1

Absolute maximum ratings

Table 1

Absolute maximum ratings¹⁾

T_j= -40°C to 150°C; all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition Number

Min. Typ. Max.

Voltage rating

Input voltage I

V_I

-0.3

–

45

7

V

–

P_3.1.1

P_3.1.2

P_3.1.3

P_3.1.4

P_3.1.5

P_3.1.6

P_3.1.7

P_3.1.8

P_3.1.9

Enable voltage EN

Output voltage Q

V_EN

V_Q

Reset output RO

V_RO

V_D

7

Delay voltage D

7

Reset threshold RADJ

Watchdog input WI

Watchdog output WO

Watchdog inhibit WINH

Temperature

V_RADJ

V_WI

V_WO

V_WINH

7

Junction temperature

Storage temperature

ESD susceptibility

ESD susceptibility to GND

T_j

-40

-55

–

150

°C

–

P_3.1.10

P_3.1.11

T_stg

V_ESD,HBM-2

–

2

kV

V

²⁾HBM all pins

³⁾CDM all pins except 1, 7, P_3.1.13

8, 14

P_3.1.12

V_{ESD, CDM}-500

500

ESD susceptibility pins 1, 7, 8, V_ESD,CDM-750

–

750

V

³⁾CDM

P_3.1.14

14 to GND

1) Not subject to production test, specified by design.

2) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS001 (1.5k Ω, 100 pF).

3) ESD susceptibility, Charged Device Model (CDM) according JEDEC JESD22-C101.

Notes

1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the

data sheet. Fault conditions are considered as "outside" normal operating range. Protection functions are

not designed for continuous repetitive operation.

Datasheet

7

Rev. 1.0

2021-05-27

OPTIREG™ linear TLS820F3ELV50

Low dropout linear voltage regulator with watchdog and reset

General product characteristics

3.2

Functional range

Table 2

Functional range

T_j= -40°C to 150°C; all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

1)

Input voltage range

V_I

V_Q,nom+ –

42

V

P_3.2.1

P_3.2.2

V_dr

2)

Extended input voltage

range

V_I(ext)

3

–

42

V

Enable voltage range

Junction temperature

V_EN

T_j

0

–

42

150

–

V

–

P_3.2.3

P_3.2.4

P_3.2.5

-40

1

°C

µF

–

3)4)

Output capacitance for

stable operation

C_Q

4)5)

ESR of output capacitor

ESR_CQ

–

20

Ω

P_3.2.6

1) See the values of output voltage V_Qand drop out voltage V_dr, in Voltage regulator.

2) The output voltage V_Qfollows the input voltage, but is outside the specified range, see Voltage regulator.

3) The minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30%.

4) Not subject to production test, specified by design.

5) Relevant ESR value at f = 10 kHz.

Note:

Within the functional range the IC operates as described in the circuit description. The electrical

characteristics are specified within the conditions given in the related electrical characteristics

table.

Datasheet

8

Rev. 1.0

2021-05-27

OPTIREG™ linear TLS820F3ELV50

Low dropout linear voltage regulator with watchdog and reset

General product characteristics

3.3

Thermal resistance

Note:

This thermal data was generated in accordance with JEDEC JESD51 standards. For more

information, go to www.jedec.org.

Table 3

Thermal resistance

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min. Typ. Max.

1)

Junction to case

R_thJC

R_thJA

–

14

–

K/W

P_3.3.1

P_3.3.2

P_3.3.3

Junction to ambient

132

67

²⁾Footprint only

²⁾300 mm²heatsink

area on PCB

Junction to ambient

R_thJA

–

57

48

–

K/W

²⁾600 mm²heatsink

area on PCB

²⁾2s2p PCB

P_3.3.4

P_3.3.5

1) Not subject to production test, specified by design.

2) Specified R_thJAvalue is according to JEDEC JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product (chip

and package) was simulated on a 76.2 × 114.3 × 1.5 mm3board with 2 inner copper layers (2 × 70 µm Cu, 2 × 35 µm Cu).

Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.

Datasheet

9

Rev. 1.0

2021-05-27

OPTIREG™ linear TLS820F3ELV50

Low dropout linear voltage regulator with watchdog and reset

Block description and electrical characteristics

4

Block description and electrical characteristics

4.1

Voltage regulator

A resistor network divides the output voltage V_Q. The device compares this fractional voltage to an internal

voltage reference and drives the pass transistor accordingly.

The control loop stability depends on the following factors:

•

output capacitor

load current I_Q

chip temperature T_j

internal circuit design

Output capacitor

To ensure stable operation, the capacitance of the output capacitor C_Qand its equivalent series resistor ESR_CQ

requirements must be maintained, see Functional range. The output capacitor must be sized according to

the requirements of the application, for example to buffer steps in the load current I_Q.

Input capacitors, reverse polarity protection diode

An input capacitor C_Iis recommended to compensate line influences. In order to block influences, such as

pulses and high frequency distortion at the input, use a reverse polarity protection diode and a combination

of several capacitors. Connect the capacitors close to the component’s terminals.

Smooth ramp-up

In order to prevent overshoot during startup, a smooth ramp-up function is implemented. This ensures a

reduced output voltage overshoot during startup, mostly independent from load and output capacitor.

Output current limitation

Due to a short circuit or overload condition the load current can exceed the specified limit. In this case the

device limits the output current and the output voltage decreases.

Overtemperature shutdown

The overtemperature shutdown circuit prevents the device from immediate destruction in case of a fault

condition, for example due to a permanent short circuit at the output. In such a condition the

overtemperature shutdown circuit switches off the device. After the device cools down, the regulator restarts.

This leads to an oscillatory behavior of the output voltage V_Q. However, any junction temperature above 150°C

is outside the maximum ratings and therefore significantly reduces the lifetime of the device.

Datasheet

10

Rev. 1.0

2021-05-27

OPTIREG™ linear TLS820F3ELV50

Low dropout linear voltage regulator with watchdog and reset

Block description and electrical characteristics

Regulated

Output Voltage

Supply

I_I

I_Q

Q

I

EN

Current

Limitation

V_I

C_I

C_Q

V_Q

Enable

ESR_CQ

LOAD

Primary

Reference

Temperature

Shutdown

GND

Figure 3

Functional block diagram voltage regulator circuit

V

V_I

V_dr

V_Q,nom

V_Q

dV_QI_load

V_I(ext),min

≈

dV_Q

dt

I

_Q,max- I_load

≈

C_Q

dt

C_Q

Diagram_Output-InputVoltage.svg

t

Figure 4

Output voltage versus input voltage

4.1.1

Electrical characteristics voltage regulator

Table 4

Electrical characteristics voltage regulator

V_I= 13.5 V; T_j= -40°C to 150°C; all voltages with respect to ground, direction of currents as shown in Figure 3

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

5.0

Unit Note or

Test Condition

Number

Min.

Max.

Output voltage accuracy

V_Q

4.9

5.1

V

50 µA ≤ I_Q≤ 100 mA;

_Q,nom+ V_dr≤ V_I≤ 42 V

50 µA ≤ I_Q≤ 200 mA;

_Q,nom+ V_dr≤ V_I≤ 28 V

I_Q≤ 50 µA;

_Q,nom+ V_dr≤ V_I≤ 45 V

P_4.1.1

P_4.1.2

P_4.1.5

P_4.1.10

V

4.9

7

5.0

–

5.1

5.2

70

V

Output voltage startup slew dV_Q/dt

rate

V/ms dV_I/dt = 50 V/ms;

C_Q= 1 µF;

0.5 V ≤ V_Q≤ 4.5 V

Load regulation steady state dV_Q,load–15

Line regulation steady state dV_Q,line–5

-5

1

5

mV

dB

I_Q= 0.05 mA to 200 mA; P_4.1.12

V_I= 6.5 V

10

–

V_I= 8 V to 32 V;

P_4.1.14

I_Q= 5 mA

1)

Power supply ripple rejection PSRR

–

60

f

= 100 Hz;

ripple

P_4.1.15

V

_ripple= 0.5 V_pp;

I_Q=10 mA

Datasheet

11

Rev. 1.0

2021-05-27

OPTIREG™ linear TLS820F3ELV50

Low dropout linear voltage regulator with watchdog and reset

Block description and electrical characteristics

Table 4

Electrical characteristics voltage regulator (cont’d)

V_I= 13.5 V; T_j= -40°C to 150°C; all voltages with respect to ground, direction of currents as shown in Figure 3

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

100

Unit Note or

Test Condition

Number

Min.

–

Max.

240

480

550

200

Dropout voltage V_dr= V_I- V_Q

Output current limitation

V_dr

mV

mA

°C

²⁾I_Q= 100 mA

²⁾I_Q= 200 mA

P_4.1.17

P_4.1.18

V_dr

–

200

I_Q,max

201

151

350

0 V ≤ V_Q≤ V_Q,nom- 0.1 V P_4.1.25

³⁾T_jincreasing

Overtemperature shutdown T_j,sd

175

P_4.1.27

threshold

Overtemperature shutdown T_j,sdh

–

15

–

K

³⁾T_jdecreasing

P_4.1.28

threshold hysteresis

1) Not subject to production test, specified by design.

2) Measured when the output voltage V_Qhas dropped 100 mV from its nominal value obtained at V_I= 13.5 V.

3) Not subject to production test, specified by design.

Datasheet

12

Rev. 1.0

2021-05-27

OPTIREG™ linear TLS820F3ELV50

Low dropout linear voltage regulator with watchdog and reset

Block description and electrical characteristics

4.1.2

Typical performance characteristics voltage regulator

Output voltage V_Qversus

junction temperature T_j

Output current limitation I_Qmaxversus

input voltage V_I

Dropout voltage V_drversus

junction temperature T_j

Dropout voltage V_drversus

output current I_Q

Datasheet

13

Rev. 1.0

2021-05-27

OPTIREG™ linear TLS820F3ELV50

Low dropout linear voltage regulator with watchdog and reset

Block description and electrical characteristics

Output voltage V_Qversus

output current I_Q

Output voltage V_Qversus

input voltage V_I

Line transient response

Load transient response

Datasheet

14

Rev. 1.0

2021-05-27

OPTIREG™ linear TLS820F3ELV50

Low dropout linear voltage regulator with watchdog and reset

Block description and electrical characteristics

Power supply ripple rejection PSRR versus

frequency f

Datasheet

15

Rev. 1.0

2021-05-27

OPTIREG™ linear TLS820F3ELV50

Low dropout linear voltage regulator with watchdog and reset

Block description and electrical characteristics

4.2

Current consumption

Table 5

Electrical characteristics current consumption

V_I= 13.5 V, T_j= -40°C to 150°C; all voltages with respect to ground; direction of currents see Figure 5 (unless

otherwise specified).

Parameter

Symbol

Values

Typ.

–

Unit Note or Test Condition Number

Min.

Max.

Current consumption I_q= I_I

I_q,off

–

1

µA

V_EN= 0 V;

T_j≤ 105°C

P_4.2.1

P_4.2.2

P_4.2.3

P_4.2.4

–

2

V_EN= 0 V;

T_j≤ 125°C

–

2

V_EN= 0.4 V;

T_j≤ 125°C

Current consumption I_q= I_I- I_QI_q

23

35

I_Q= 50 µA;

T_j= 25°C;

watchdog disabled

–

26

29

26

30

33

43

51

39

47

55

µA

I_Q= 50 µA;

T_j≤ 125°C;

watchdog disabled

P_4.2.5

P_4.2.6

P_4.2.7

P_4.2.8

P_4.2.9

P_4.2.10

I_Q= 50 µA;

T_j≤ 150°C;

watchdog disabled

I_Q= 50 µA;

T_j= 25°C;

watchdog enabled

¹⁾I_Q= 50 µA;

T_j≤ 125°C;

watchdog enabled

¹⁾I_Q= 50 µA;

T_j≤ 150°C;

watchdog enabled

²⁾I_Q= 200 mA ;

T_j≤ 125°C;

watchdog enabled

1) Not subject to production test, specified by design.

2) Not subject to production test, specified by design.

Datasheet

16

Rev. 1.0

2021-05-27

OPTIREG™ linear TLS820F3ELV50

Low dropout linear voltage regulator with watchdog and reset

Block description and electrical characteristics

Regulated

Output Voltage

Supply

I_Q

I_I

I

Q

Voltage Regulator

+

LOAD

C_Q

V_Q

C_I

V_I

GND

I_q

Figure 5

Parameter definition

Datasheet

17

Rev. 1.0

2021-05-27

OPTIREG™ linear TLS820F3ELV50

Low dropout linear voltage regulator with watchdog and reset

Block description and electrical characteristics

4.2.1

Typical performance characteristics current consumption

Current consumption I_qversus

junction temperature T_j

Current consumption I_qversus

output current I_Q

Current consumption I_q,offversus

junction temperature T_j

Current consumption I_qversus

input voltage V_I

Datasheet

18

Rev. 1.0

2021-05-27

OPTIREG™ linear TLS820F3ELV50

Low dropout linear voltage regulator with watchdog and reset

Block description and electrical characteristics

Current consumption I_q,offversus

input voltage V_I

Datasheet

19

Rev. 1.0

2021-05-27

OPTIREG™ linear TLS820F3ELV50

Low dropout linear voltage regulator with watchdog and reset

Block description and electrical characteristics

4.3

Enable

The device can be switched on and off via the EN input:

•

"High", for example battery voltage, enables the device

"Low", for example GND, disables the device

The enable function has a built in hysteresis to avoid toggling between on-state and off-state when signals

with slow slopes are applied to the EN input.

Table 6

Electrical Characteristics enable

V_I= 13.5 V, T_j= -40°C to 150°C, all voltages with respect to ground (unless otherwise specified)

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min.

2

Typ. Max.

Enable “high” input voltage

Enable "low" input voltage

V_EN,H

V_EN,L

–

V

V_Qsettled

P_4.3.1

P_4.3.2

P_4.3.3

P_4.3.4

P_4.3.5

P_4.3.6

–

0.8

–

V

V_Q≤ 0.1 V

Enable threshold hysteresis V_EN,Hy

90

–

mV

µA

MΩ

–

Enable “high" input current

Enable "high" input current

I_EN,H

R_EN

–

1

V_EN= 3.3 V

V_EN≤ 18 V

–

6

Enable internal pull-down

resistor

2.8

10

20

Datasheet

20

Rev. 1.0

2021-05-27

OPTIREG™ linear TLS820F3ELV50

Low dropout linear voltage regulator with watchdog and reset

Block description and electrical characteristics

4.3.1

Typical performance characteristics Enable

Current consumption I_ENversus

input voltage V_EN

Output Voltage V_Qversus time t

Datasheet

21

Rev. 1.0

2021-05-27

OPTIREG™ linear TLS820F3ELV50

Low dropout linear voltage regulator with watchdog and reset

Block description and electrical characteristics

4.4

Reset

The reset function monitors the output voltage V_Q. It allows a connected system or microcontroller to react to

an imminent loss of power. To meet the requirements of the application, some reset related parameters can

be adjusted by measures described below.

Output undervoltage reset event

If V_Qdrops below the output undervoltage reset lower switching threshold V_RT,low, then the device detects an

output undervoltage event and sets the reset output pin RO to “low”. This signal can be used to reset a

microcontroller, which is supplied by V_Q.

Reset reaction time

If the output voltage of the regulator drops below the output undervoltage reset lower switching threshold

V_RT,low, then the delay capacitor C_Ddischarges with the discharge current I_DR,dsch. As soon as the delay

capacitor’s voltage V_Dreaches the lower delay switching threshold V_DR,lo, then the device sets the reset output

RO to "low". The time from V_Qdropping below V_RT,lowand the transition of the reset output RO to “low” is the

total reset reaction time t_rr,total

.

The total reset reaction time t_rr,totalis related to the delay capacitor discharge time t_rr,dand the internal

reaction time t_rr,int

t_rr,total= t_rr,int+ t_rr,d

with

:

(4.1)

•

t

_rr,total: Total reset reaction time

_rr,int: Internal reset reaction time, see Internal reset reaction time

_rr,d: Delay capacitor discharge time. For C_D=10nF see value specified in Delay capacitor discharge time.

If the output voltage drop lasts shorter than the reset blanking time t_rr,blank, then the delay capacitor does not

discharge and the device does not set the reset output RO to "low". The reset blanking time prevents

unintentional microcontroller reset due to very short distortion of the output voltage, see Timing diagram

reset.

Datasheet

22

Rev. 1.0

2021-05-27

OPTIREG™ linear TLS820F3ELV50

Low dropout linear voltage regulator with watchdog and reset

Block description and electrical characteristics

Power-on reset delay time

Before startup of the regulator or after an undervoltage reset event, the delay capacitor C_Ddischarges. If the

output voltage of the regulator exceeds the output undervoltage reset upper switching threshold V_RT,hi, then

this triggers the charging cycle of C_D. C_Dis charged with the delay capacitor charge current I_D,ch. If V_Dreaches

the higher delay switching threshold V_DR,hi, then the device sets the reset output RO to “high”. The time from

V_Qexceeding V_RT,hiuntil the device sets the reset output RO to “high” is the power-on reset delay time t_d,PWR-ON

.

The power-on reset delay time allows a microcontroller to start up properly before the reset output RO is

released to “high”. The power-on reset delay time t_d,PWR-ONcan be configured with the capacitance of the delay

capacitor C_Dconnected to pin D.

If a power-on reset delay time t_d,PWR-ONdifferent from the value for C_D= 10 nF is required, then the necessary

delay capacitor’s value can be derived from the specified value given in Reset delay timing by:

C_D= 10 nF × t_d,PWR-ON/ t_{d,PWR-ON,10nF}

(4.2)

with

•

t

_d,PWR-ON: Desired power-on reset delay time

_{d,PWR-ON,10nF}: Power-on reset delay time, see Power-on reset delay time

C_D: Delay capacitor required

The formula is valid for C_D≥ 1 nF. For precise timing calculations also consider the delay capacitor’s tolerance.

Reset output RO

The reset output RO is an open collector output with an integrated pull-up resistor. If a lower-ohmic RO signal

is desired, then connect an external pull-up resistor to the output Q. Since the maximum RO sink current is

limited, the minimum optional external resistor R_RO,extis specified in Reset output, external pull-up resistor

to Q.

Reset output RO "low" for V_Q≥ 1 V

If an undervoltage reset condition occurs, then the device keeps the reset output RO "low" for V_Q≥ 1 V, even if

the input voltage V_Iis 0 V. This is achieved by supplying the reset circuit from the output capacitor.

Primary and secondary voltage reference

There are two voltage references implemented in the reset circuit to provide the V_RADJ,thsignal. The input of

the device supplies the primary voltage reference, while the output of the device supplies the secondary

voltage reference. If EN is "low", then the device disables the primary bandgap along with the power stage. As

a consequence, the primary bandgap voltage drops below the secondary bandgap voltage reference, whereas

the secondary bandgap then defines V_RADJ,th. This ensures that the device performs a controlled reset of the

output on being disabled. Due to internal filtering and buffering, switching from the primary voltage reference

to the secondary voltage reference occurs with some delay. The EN slope and the speed of the output voltage

ramp down determine this delay.

Datasheet

23

Rev. 1.0

2021-05-27

OPTIREG™ linear TLS820F3ELV50

Low dropout linear voltage regulator with watchdog and reset

Block description and electrical characteristics

V_I

t

< t_rr,blank

V_Q

V_RT,high

V_RT,low

1 V

t_d,power-on

t_rr,total

V_D

V_DW,hold

V_DW,high

t_rr,total

t_d,power-on

V_DR,high

V_DR,low

t_d,power-on

t_rr,total

t_d,power-on

t_rr,total

V_RO

t_d,power-on

1V

V_RO,low

t

Thermal

Shutdown

Input

Voltage Dip

Under-

voltage

Spike at Over-

output load

Figure 6

Timing diagram reset

Datasheet

24

Rev. 1.0

2021-05-27

OPTIREG™ linear TLS820F3ELV50

Low dropout linear voltage regulator with watchdog and reset

Block description and electrical characteristics

Reset adjust function

An external voltage divider (R_ADJ1, R_ADJ2) connected to RADJ can adjust the undervoltage reset switching

threshold to the application’s needs. To select the default threshold, connect the RADJ pin to GND. For reset

adjustment range, see Reset adjustment range.

For dimensioning the voltage divider, consider the additional current flowing through the resistors.

With a voltage divider connected to RADJ, the output undervoltage reset lower switching threshold V_RT,low,new

is calculated as follows (neglecting the reset adjust pin current I_RADJ):

V_RT,low,new= V_RADJ,th× (R_ADJ,1+ R_ADJ,2)/R_ADJ,2

(4.3)

with

•

V

_RT,low,new: Desired reset switching threshold

_ADJ,1, R_ADJ,2: Resistors of the external voltage divider, see Figure 7

R

V

_RADJ,th: Reset adjust switching threshold, see Reset adjust switching threshold

I

VDD

Supply

Q

C_Q

R_RO

Control

Secondary

Reference

I_RO

RO

Reset

Int.

Supply

I_D,charge

R

S

Q

V_{RA DJ,th}

Microcontroller

V_{DS T,high}

≥

Primary

Reference

R_ADJ,1

I_RD,discharge

EN

V_{DS T,low}

RADJ

I_{RA DJ}

OR

R_ADJ,2

GND

D

C_D

Figure 7

Functional block diagram reset

4.4.1

Electrical characteristics reset

Table 7

Electrical characteristics reset

V_I= 13.5 V, T_j= -40°C to 150°C; all voltages with respect to ground; direction of currents see Figure 7 (unless

otherwise specified).

Parameter

Symbol

Values

Unit Note or Test Condition Number

Min. Typ. Max.

Output undervoltage reset comparator default values (Pin RADJ = GND)

Output undervoltage reset

lower switching threshold

V_RT,low

4.5

4.6

4.7

V

V_EN≥ 2.0 V;

P_4.4.1

V_Qdecreasing;

RADJ connected to

GND;

V

_RT,low≤ V_I≤ 42 V

Datasheet

25

Rev. 1.0

2021-05-27

OPTIREG™ linear TLS820F3ELV50

Low dropout linear voltage regulator with watchdog and reset

Block description and electrical characteristics

Table 7

Electrical characteristics reset (cont’d)

V_I= 13.5 V, T_j= -40°C to 150°C; all voltages with respect to ground; direction of currents see Figure 7 (unless

otherwise specified).

Parameter

Symbol

Values

Unit Note or Test Condition Number

Min. Typ. Max.

Output undervoltage reset

upper switching threshold

V_RT,high

4.6

4.7

4.8

V

V_EN≥ 2.0 V;

P_4.4.2

P_4.4.9

V_Qincreasing;

RADJ connected to

GND;

V

_RT,high≤ V_I≤ 42 V

Output undervoltage reset

switching hysteresis

V_RT,hy

30

100

200

mV

V_Iwithin operating

range;

RADJ connected to

GND;

V

_EN≥ 2.0 V

Reset threshold adjustment

Reset adjust switching

threshold

V_RADJ,th

0.82 0.9

0.94

4.4

V

–

P_4.4.13

P_4.4.14

1)

Reset adjustment range

Reset output RO

V_RT,range

2.5

–

Reset output low voltage

V_RO,low

–

0.2

–

0.4

–

V

1 V ≤ V_Q≤ V_RT;

P_4.4.16

P_4.4.17

R

_RO,ext≥ 6.2 kΩ

1 V ≤ V_Q≤ V_RT;

V_RO≤ 0.4 V

Reset output, external pull-up R_RO,ext

resistor to Q

6.2

10

kΩ

Reset output, internal pull-up R_RO,int

resistor

20

35

internally connected to P_4.4.18

Q

Reset delay timing

Upper delay switching

threshold

V_DR,high

V_DR,low

I_D,ch

–

3

0.9

0.6

1.6

180

6

–

9

V

–

P_4.4.19

P_4.4.20

P_4.4.21

P_4.4.22

P_4.4.23

Lower delay switching

threshold

V

–

Delay capacitor charge

current

µA

mA

ms

V_D= 1.2 V

Delay capacitor reset

discharge current

I_DR,dsch

Power-on reset delay time

t_d,PWR-

²⁾Calculated value;

C_D= 10 nF;

ON,10nF

C_Ddischarged to 0 V

Internal reset reaction time

t_rr,int

3

–

8

40

µs

C_D= 0 nF, V_Q= 4 V;

P_4.4.24

P_4.4.26

V

_WINH,high≤ V_WINH

Delay capacitor discharge

time

t_rr,d,10nF

0.2

0.3

²⁾C_D= 10 nF

Datasheet

26

Rev. 1.0

2021-05-27

OPTIREG™ linear TLS820F3ELV50

Low dropout linear voltage regulator with watchdog and reset

Block description and electrical characteristics

Table 7

Electrical characteristics reset (cont’d)

V_I= 13.5 V, T_j= -40°C to 150°C; all voltages with respect to ground; direction of currents see Figure 7 (unless

otherwise specified).

Parameter

Symbol

Values

Unit Note or Test Condition Number

Min. Typ. Max.

Total reset reaction time

t_{rr,total,10nF}

–

10

41

µs

Calculated value:

_rr,d,10nF+ t_rr,int

C_D= 10 nF

3)

P_4.4.27

P_4.4.28

t

;

Reset blanking time

t_rr,blank

–

3

–

µs

1) If the reset switching threshold is modified, then the related parameters V_RT,hi, V_RT,hyare changed directly

proportional.

2) For programming a different delay and reset reaction time, see Reset.

3) Not subject to production test, specified by design.

Datasheet

27

Rev. 1.0

2021-05-27

OPTIREG™ linear TLS820F3ELV50

Low dropout linear voltage regulator with watchdog and reset

Block description and electrical characteristics

4.4.2

Typical performance characteristics reset

Undervoltage reset lower switching threshold

_RT,loversus junction temperature T_j

Power-on reset delay time t_d,PWR-ONversus

delay capacitor C_D

V

Power-on reset delay time t_d,PWR-ON

versus junction temperature T_j

Internal reset reaction time t_rr,int

versus junction temperature T_j

Datasheet

28

Rev. 1.0

2021-05-27

OPTIREG™ linear TLS820F3ELV50

Low dropout linear voltage regulator with watchdog and reset

Block description and electrical characteristics

Total reset reaction time t_rr,total

versus junction temperature T_j

Datasheet

29

Rev. 1.0

2021-05-27

OPTIREG™ linear TLS820F3ELV50

Low dropout linear voltage regulator with watchdog and reset

Block description and electrical characteristics

4.5

Watchdog

4.5.1

Description watchdog

The device offers a watchdog with inhibit feature and programmable watchdog timing. The watchdog

function monitors a microcontroller to detect time based failures. If the device detects a missing rising edge

at the WI pin, then it sets the watchdog output to "low" after a defined time. An external delay capacitor C_Dis

used to configure the timing. For details on how the WI signal can comply with watchdog timing, see Timing

diagram watchdog.

The watchdog output WO is separated from the reset output RO. Therefore, the watchdog output can be used

as an interrupt signal for the microcontroller independently from the reset signal. It is possible to interconnect

WO pin and RO pin in order to establish a wired OR function with a dominant "low" signal.

Supply

I

Q

VDD

C_Q

R_WO

Control

I_WO

WO

Reset

Int.

Supply

I_D,charge

Q

R

S

V_DW,high

Microcontroller

WINH

Q

V_DW,low

OR

AND

Rising

Edge

WI

I/O

R_WINH

detect

I_WD,discharge

R_WI

Q

S

R

GND

D

GND

C_D

Figure 8

Functional block diagram watchdog

Watchdog inhibit input WINH

The watchdog inhibit input WINH enables or disables the watchdog function. A "high" signal at WINH disables

the watchdog. When disabled, the capacitor at the D pin is charged to the watchdog deactivation hold voltage

V_DW,hold. The signal applied to WINH must comply with the values in Watchdog inhibit WINH.

Watchdog output WO

The watchdog output WO is an open collector output with an integrated pull-up resistor. If a lower-ohmic WO

signal is desired, then connect an external pull-up resistor to the output Q. Since the maximum WO sink

current is limited, the minimum external resistor value R_WO,extis specified in Watchdog output external pull-

up resistor.

Datasheet

30

Rev. 1.0

2021-05-27

OPTIREG™ linear TLS820F3ELV50

Low dropout linear voltage regulator with watchdog and reset

Block description and electrical characteristics

Watchdog input WI

A positive edge at the watchdog input WI triggers the watchdog. Because of the integrated high pass filter, the

amplitude and slope of the signal at WI pin must comply with the values in Watchdog input WI. For details on

the test pulse applied, see Figure 9.

V_WI

t_WI,ph

V_WI,high

t_WI,pl

V_WI,low

dV_WI/ dt

t

Figure 9

Test pulses watchdog input WI

Watchdog timing

If the watchdog is enabled and the device does not detect a rising edge at the WI pin, then the delay

capacitor C_Dis continously charged and discharged between V_DW,lowand V_DW,high, see Functional block

diagram watchdog. The WO pin goes “low” for t_WD,lowwhen the delay capacitor voltage V_Ddischarges

to V_DW,low. Due to the cyclic nature of this behavior, this pattern repeats with the watchdog period t_WD,p

.

If the device detects a rising edge at the WI pin during the C_Ddischarge cycle, then a new charge cycle starts.

To prevent the device from setting WO to “low”, a rising edge on the WI pin must occur within the watchdog

trigger time t_WI,tr. For timing details see Timing diagram watchdog.

If a watchdog trigger time t_WI,trdifferent from the one for C_D= 10 nF is required, then the delay capacitor’s value

can be derived from the value in Watchdog timing by:

C_D= 10 nF × t_WI,tr/ t_WI,tr,10nF

(4.4)

The watchdog output "low" time t_WD,lowand the watchdog period t_WD,pequate to:

t_WD,lo= t_WD,low,10nF× C_D/ 10 nF

(4.5)

(4.6)

t_WD,p= t_WI,tr+ t_WD,low

The formula applies for C_D≥ 1nF. For precise timing calculations consider the delay capacitor’s tolerance.

Datasheet

31

Rev. 1.0

2021-05-27

OPTIREG™ linear TLS820F3ELV50

Low dropout linear voltage regulator with watchdog and reset

Block description and electrical characteristics

V_WI

V_WI,high

V_WI,low

dV

_WI/ d

t

t_WI,p

1/f_WI

t_WD,p

outside spec

Nopositive

_WIedge

V

V_D

t_WI,tr

V_DW,hold

V_DW,high

V_DW,low

t

t_WD,low

V_WO

V_WO,low

t

t_WINH,ph

V_WINH,high

V_WINH,low

t

Figure 10 Timing diagram watchdog

Datasheet

32

Rev. 1.0

2021-05-27

OPTIREG™ linear TLS820F3ELV50

Low dropout linear voltage regulator with watchdog and reset

Block description and electrical characteristics

4.5.2

Electrical characteristics watchdog

Table 8

Electrical characteristics watchdog

V_I= 13.5 V, T_j= -40°C to 150°C; all voltages with respect to ground, direction of currents see Figure 8 (unless

otherwise specified).

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min.

Typ. Max.

Watchdog inhibit WINH

Watchdog inhibit "low" signal V_WINH,low

valid

–

0.8

–

V

P_4.5.1

P_4.5.2

P_4.5.3

P_4.5.5

P_4.5.6

Watchdog inhibit "high" signal V_WINH,high

valid

2

–

V

Watchdog inhibit "high" level I_WINH,high

input current

–

3.5

–

µA

ms

MΩ

V_WINH= 3.3 V

C_D= 10 nF;

Watchdog inhibit high signal

pulse length

t_WINH,ph

–

2.5

1.5

V

_WINH≥ V_WINH.high

Watchdog inhibit internal pull- R_WINH

0.9

2.6

–

down resistor

Watchdog input WI

1)

Watchdog input "low" signal

valid

V_WI,low

–

0.8

–

V

P_4.5.7

P_4.5.8

P_4.5.9

P_4.5.10

P_4.5.11

Watchdog input "high" signal V_WI,high

valid

2

–

V

Watchdog input "low" signal

pulse length

t_WI,pl

1

–

µs

µA

V/µs

MΩ

V ≤ V_WI,low

WI

Watchdog input "high" signal t_WI,ph

pulse length

1

–

V ≥ V_WI,high

WI

Watchdog input "high" level

input current

I_WI,H

–

3.5

–

V_WI= 3.3 V

1)

Watchdog input signal slew

rate

dV_WI/dt

1

–

V

≤ V_WI≤ V_WI,highP_4.5.12

WI,low

Watchdog input internal pull- R_WI

0.9

1.5

2.6

–

P_4.5.13

down resistor

Watchdog output WO

Watchdog output low voltage V_WO,low

–

0.2

–

0.4

–

V

V_Q≥ 2.5 V;

_WO≥ 6.2 kΩ

V_Q≥ 2.5 V;

P_4.5.14

P_4.5.15

P_4.5.16

R

Watchdog output external pull- R_WO,ext

up resistor

6.2

10

kΩ

V

_WO≤ 0.4 V

Watchdog output internal pull- R_WO,int

20

35

–

up resistor

Watchdog timing

Delay capacitor charge current I_D

–

1.6

–

µA

V_D= 1.2 V

P_4.5.17

Datasheet

33

Rev. 1.0

2021-05-27

OPTIREG™ linear TLS820F3ELV50

Low dropout linear voltage regulator with watchdog and reset

Block description and electrical characteristics

Table 8

Electrical characteristics watchdog (cont’d)

V_I= 13.5 V, T_j= -40°C to 150°C; all voltages with respect to ground, direction of currents see Figure 8 (unless

otherwise specified).

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min.

Typ. Max.

Delay capacitor deactivation

charge current

I_DW,ch,deact

I_DW,disch

V_DW,high

V_DW,low

–

1.6

0.5

1.45

0.9

1.5

13

–

µA

V

V_D= 1.2 V

P_4.5.18

P_4.5.19

P_4.5.20

P_4.5.21

P_4.5.22

P_4.5.23

P_4.5.24

P_4.5.25

Delay capacitor watchdog

discharge current

–

V_D= 1.2 V

Upper watchdog timing

threshold

–

Lower watchdog timing

threshold

–

V

–

Upper delay watchdog

deactivated hold voltage

V_DW,deact

–

V

V_WINH≥ V_WINH.high

Watchdog trigger time

Watchdog output low time

Watchdog period

t_WI,tr,10nF3.5

t_WD,lo,10nF1.5

t_WD,p,10nF

21

6

ms

²⁾Calculated value;

C_D= 10 nF

²⁾Calculated value;

C_D= 10 nF

4

5

17

27

²⁾Calculated value;

t

_WI,tr,10nF+ t_WD,lo,10nF

;

C_D= 10 nF

1) For details on the test pulse applied, see Figure 9.

2) For programming the watchdog timing, see Description watchdog.

Datasheet

34

Rev. 1.0

2021-05-27

OPTIREG™ linear TLS820F3ELV50

Low dropout linear voltage regulator with watchdog and reset

Block description and electrical characteristics

4.5.3

Typical performance characteristics standard watchdog function

Watchdog trigger time t_WI,trversus

delay capacitor C_D

Watchdog trigger time t_WI,trversus

junction temperature T_J

Watchdog inhibit high signal pulse length t_WINH,phWatchdog output low time t_WD,loversus

versus junction temperature T_J

junction temperature T_J

Datasheet

35

Rev. 1.0

2021-05-27

OPTIREG™ linear TLS820F3ELV50

Low dropout linear voltage regulator with watchdog and reset

Block description and electrical characteristics

Watchdog output low time t_WD,loversus

delay capacitor C_D

Datasheet

36

Rev. 1.0

2021-05-27

OPTIREG™ linear TLS820F3ELV50

Low dropout linear voltage regulator with watchdog and reset

Application information

5

Application information

Note:

The following information is given as a hint for the implementation of the device only and shall not

be regarded as a description or warranty of a certain functionality, condition or quality of the device.

5.1

Application diagram

D_I1

Regulated output voltage

Supply

I

Q

Current

Limitation

RO

C_I2

10µF

C_I1

100nF

WO

EN

D_I2

<42V

R₁

C_Q=1µF

Enable

RADJ

D

Microcontroller

Reset &

Watchdog

Generator

Primary

Reference

Temperature

Shutdown

R₂

C_D

WINH

WI

GND

Figure 11 Application diagram

5.2

Selection of external components

5.2.1

Input pin

Figure 11 shows the typical input circuitry for a linear voltage regulator. A ceramic capacitor at the input, in

the range of 100 nF to 470 nF, is recommended to filter out high frequency disturbances imposed by the line,

such as ISO pulses 3a/b. The capacitor must be placed very close to the input pin of the linear voltage regulator

on the PCB.

An aluminum electrolytic capacitor in the range of 10 µF to 470 µF is recommended as an input buffer to

smooth out high energy pulses, such as ISO pulse 2a. This capacitor should be placed close to the input pin of

the linear voltage regulator on the PCB.

An overvoltage suppressor diode can be used to further suppress any voltage exceeding the maximum rating

of the linear voltage regulator and protect the device against damage due to overvoltage.

The external components at the input are not mandatory for the operation of the voltage regulator, but they

are recommended in case of possible external disturbances.

5.2.2

Output pin

An output capacitor is mandatory for the stability of a linear voltage regulator. The requirement to the output

capacitor is given in Functional range.

The device is designed to be stable with extremely low ESR capacitors. According to automotive requirements,

ceramic capacitors with X5R or X7R dielectrics are recommended.

The output capacitor should be placed as close as possible to the regulator’s output and to GND pins and on

the same side of the PCB as the regulator itself.

Datasheet

37

Rev. 1.0

2021-05-27

OPTIREG™ linear TLS820F3ELV50

Low dropout linear voltage regulator with watchdog and reset

Application information

In case of rapid transients of input voltage or load current, the capacitance should be dimensioned in

accordance and verified in the real application to fulfill the output stability requirements.

5.3

Thermal considerations

Knowing the input voltage, the output voltage and the load profile of the application, the total power

dissipation can be calculated:

P_D= (V_I- V_Q) × I_Q+ V_I× I_q

(5.1)

with

•

P_D: continuous power dissipation

V_I: input voltage

V_Q: output voltage

I_Q: output current

I_q: quiescent current

The maximum acceptable thermal resistance R_thJAcan then be calculated:

R_thJA,max= (T_j,max- T_a) / P_D

(5.2)

with

•

T

_j,max: maximum allowed junction temperature

T_a: ambient temperature

Based on the above calculation the proper PCB type and the necessary heat sink area can be determined with

reference to the specification in Thermal resistance.

Example

Application conditions:

V_I= 13.5 V

V_Q= 5 V

I_Q= 50 mA

T_a= 85°C

Calculation of R_thJA,max

:

P_D= (V_I– V_Q) × I_Q+ V_I× I_q

= (13.5 V – 5 V) × 50 mA + 13.5 V × 33 µA

= 0.425 W + 0.000446 W

= 0.425446 W

R_thJA,max= (T_j,max– T_a) / P_D

= (150°C – 85°C) / 0.425446W = 152.781 K/W

As a result, the PCB design must ensure a thermal resistance R_thJAlower than 152.781 K/W. According to

Thermal resistance, at least 300 mm²heatsink area is needed on the FR4 1s0p PCB, or the FR4 2s2p board can

be used.

5.4

Reverse polarity protection

The device must be protected from reverse polarity by external components. An external reverse polarity

diode is required. The Absolute maximum ratings of the device must be maintained.

Datasheet

38

Rev. 1.0

2021-05-27

OPTIREG™ linear TLS820F3ELV50

Low dropout linear voltage regulator with watchdog and reset

Application information

5.5

Further application information

•

Please contact Infineon for information on pin behavior assessment

Existing application note

For further information you may contact https://www.infineon.com

Datasheet

39

Rev. 1.0

2021-05-27

OPTIREG™ linear TLS820F3ELV50

Low dropout linear voltage regulator with watchdog and reset

Package information

6

Package information

1)

3.9 0.1

1)

4.9 0.1

0.35 x 0.45°

6 0.2

3 0.2

2)

0.25 0.05

1

7

14

8

7

1

8

14

Index Marking

0.65

Bottom View

6 x 0.65 = 3.9

1) Does not include plastic or metal protrusion of 0.15 max. per side

2) Lead width can be 0.61 max. in dambar area

All dimensions are in units mm

The drawing is in compliance with ISO 128-30, Projection Method 1 [

]

Figure 12 PG-SSOP-14

Green Product (RoHS compliant)

To meet the world-wide customer requirements for environmentally friendly products and to be compliant

with government regulations the device is available as a green product. Green products are RoHS-Compliant

(i.e. Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).

Further information on packages

https://www.infineon.com/packages

Datasheet

40

Rev. 1.0

2021-05-27

OPTIREG™ linear TLS820F3ELV50

Low dropout linear voltage regulator with watchdog and reset

Revision history

7

Revision history

Revision

Date

Changes

1.0

2021-05-17

Datasheet created

Datasheet

41

Rev. 1.0

2021-05-27

Trademarks

All referenced product or service names and trademarks are the property of their respective owners.

IMPORTANT NOTICE

The information given in this document shall in no For further information on technology, delivery terms

Edition 2021-05-27

Published by

Infineon Technologies AG

81726 Munich, Germany

event be regarded as a guarantee of conditions or and conditions and prices, please contact the nearest

characteristics ("Beschaffenheitsgarantie").

Infineon Technologies Office (www.infineon.com).

With respect to any examples, hints or any typical

values stated herein and/or any information regarding

the application of the product, Infineon Technologies

hereby disclaims any and all warranties and liabilities

of any kind, including without limitation warranties of

non-infringement of intellectual property rights of any

third party.

In addition, any information given in this document is

subject to customer's compliance with its obligations

stated in this document and any applicable legal

requirements, norms and standards concerning

customer's products and any use of the product of

Infineon Technologies in customer's applications.

The data contained in this document is exclusively

intended for technically trained staff. It is the

responsibility of customer's technical departments to

evaluate the suitability of the product for the intended

application and the completeness of the product

information given in this document with respect to

such application.

WARNINGS

Due to technical requirements products may contain

dangerous substances. For information on the types

in question please contact your nearest Infineon

Technologies office.

Do you have a question about any

aspect of this document?

Email: erratum@infineon.com

Except as otherwise explicitly approved by Infineon

Technologies in a written document signed by

authorized representatives of Infineon Technologies,

Infineon Technologies’ products may not be used in

any applications where a failure of the product or any

consequences of the use thereof can reasonably be

expected to result in personal injury.

Document reference

Z8F66842413


型号：	TLS820F3ELV50
厂家：	Infineon
描述：	The OPTIREG™ linear TLS820F3ELV50 is a high performance, low drop out, fixed output voltage regulator in a PG-SSOP-14 package. With an input voltage range of 3 V to 42 V and very low quiescent current of only 26 µA, this regulator is perfectly suitable for automotive systems or other supply systems connected to the battery permanently.
文件：	总42页 (文件大小：2084K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TLS820F3ELV50 [INFINEON]

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