TLE84106ELXUMA1 [INFINEON]
Half Bridge Based Peripheral Driver, 1.5A, BICMOS, PDSO24, GREEN, PLASTIC, SSOP-24;
| 型号： | TLE84106ELXUMA1 |
| 厂家： | 
Infineon |
| 描述： | Half Bridge Based Peripheral Driver, 1.5A, BICMOS, PDSO24, GREEN, PLASTIC, SSOP-24 驱动 信息通信管理 光电二极管 接口集成电路 |
| 文件： | 总31页 (文件大小：382K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet, Rev. 1.0, April 2010
TLE84106EL
Hex-Half-Bridge Driver IC
Automotive Power
TLE84106EL
Hex Half Bridge IC
Table of Contents
Table of Contents
1
2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
3.1
3.2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1
4.2
4.3
4.4
5
Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power Supply Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
VS Undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
VS Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Temperature Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Protection and Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Short Circuit of Output to Supply or Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Open Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Cross-Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.2.4.1
5.2.4.2
5.2.5
5.3
5.4
5.4.1
5.4.2
5.4.3
6
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Status Register Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SPI Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Control - Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Diagnosis - Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.1
6.2
6.3
6.3.1
6.3.2
7
7.1
7.2
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Thermal application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8
9
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Data Sheet
2
Rev. 1.0, 2010-04-27
Hex-Half-Bridge Driver IC
TLE84106EL
1
Overview
Features
•
•
•
•
6 Half Bridge Power Outputs
3.3V / 5V compatible inputs with hysteresis
Independently Diagnosable Outputs
16-bit Standard SPI interface with daisy chain capability for control and
diagnosis
•
•
•
•
•
•
•
•
Open load diagnostics in ON-state for all outputs
All outputs with overload and short circuit protection and diagnosis
Overtemperature prewarning and protection
Over- and Undervoltage lockout
PG-SSOP-24-4
Cross-current protection
Thermally enhanced exposed pad package
Green Product (RoHS compliant)
AEC Qualified
Description
The TLE84106EL is a protected Hex-Half-Bridge-Driver designed especially for automotive motion control applications
such as Heating, Ventilation and Air Conditioning (HVAC) flap DC motor control. It is part of the MonolythIC family in
Infineon’s Smart Power Technology SPT® which combines bipolar and CMOS control circuitry with DMOS power
devices.
The 6 half bridge drivers are designed to drive DC motor loads in sequential or parallel operation. Operation modes
forward (cw), reverse (ccw), brake and high impedance are controlled from a 16-bit SPI interface. The diagnosis features
such as short circuit, open load, power supply failure and overtemperature in combination with its low quiescent current
makes this device attractive for automotive applications. The extremely small fine pitch exposed pad PG-SSOP-24-4
package in a SO -14 body provides good thermal performance and reduces PCB-board space and costs.
Table 1
Product Summary
Operating Voltage
Logic Supply Voltage
Maximum Supply Voltage for Load Dump
Protection
VS
VDD
VS(LD)
7 ... 18 V
3.0 ... 5.5 V
40 V
Minimum Overcurrent Threshold
ISD1-6_MOTOR
0.8 A
Maximum On-State Path Resistance at Tj = 150°C RDSON(total)_HSx+LSy
2 + 2 Ω
1 μA
5 MHz
Typical Quiescent Current at Tj = 85°C
IS (off))
fSCLK
Maximum SPI Access Frequency
Type
TLE84106EL
Package
PG-SSOP-24-4
Marking
TLE84106EL
Data Sheet
3
Rev. 1.0, 2010-04-27
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TLE84106EL
Hex Half Bridge IC
Block Diagram
2
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Block Diagram
Data Sheet
4
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
Block Diagram
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Terms
Data Sheet
5
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
Pin Configuration
3
Pin Configuration
3.1
Pin Assignment
GND
OUT 1
OUT 5
NC
1
24
23
22
21
20
19
18
17
16
15
14
13
GND
OUT 2
NC
2
3
4
VS2
SDI
5
6
7
8
SCLK
CSN
TEST
TEST
VS1
NC
OUT 3
GND
Exposed
Die
VDD
SDO
INH
Pad
NC
9
OUT 6
OUT 4
GND
10
11
12
Figure 3
Pin Configuration
Data Sheet
6
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
Pin Configuration
3.2
Pin Definitions and Functions
Pin
1
2
3
4
Symbol
Function
Ground
GND
OUT 1
OUT 5
NC
Power Half-Bridge 1
Power Half-Bridge 5
Not Connected. This pin can either be left open or connected to ground.
5
SDI
Serial-Data-Input
6
7
8
VDD
SDO
INH
Logic Supply Voltage
Serial-Data-Output
Inhibit input with internal pull-down; Place device in standby mode by pulling the INH
line LOW
9
NC
Not Connected. This pin can either be left open or connected to ground.
10
11
12
13
14
15
16
17
OUT 6
OUT 4
GND
GND
OUT 3
NC
Power Half-Bridge 6
Power Half-Bridge 4
Ground
Ground
Power Half-Bridge 3
Not Connected. This pin can either be left open or connected to ground.
Power Supply Voltage for Group 1 supplying current to OUT 3, OUT 4 and OUT 6.
Test input with internal pull down. Used for production test only. This pin should be left
open or connected to ground on board.
VS1
TEST
18
TEST
Test input with internal pull down. Used for production test only. This pin should be left
open or connected to ground on board.
19
20
21
22
23
24
EDP
CSN
SCLK
VS2
NC
OUT 2
GND
-
Chip-Select-Not-Input
Serial Clock Input
Power Supply Voltage for Group 2 supplying current to OUT 1, OUT 2 and OUT 5.
Not Connected. This pin can either be left open or connected to ground.
Power Half-Bridge 2
Ground
Exposed Die Pad; For cooling purposes only; Do not use as electrical ground.1)
1) The exposed die pad at the bottom of the package allows better heat dissipation from the device via the PCB. The exposed
die pad is not connected to any active part of the IC. When connecting onto PCB, it can either be left floating or connected
to GND for the best EMC and thermal performance.
Note:All GND pins must be externally connected together to a common GND potential. All VS pins must be
externally connected together to a common Vs potential. See Figure 17 for more Application Information.
Data Sheet
7
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
General Product Characteristics
4
General Product Characteristics
4.1
Absolute Maximum Ratings
Absolute Maximum Ratings 1)
Tj = -40 °C to +150 °C
Pos.
Parameter
Symbol
Limit Values Unit Conditions
Min.
Max.
Voltages
4.1.1
4.1.2
Supply voltage
Logic supply voltage
Logic input voltages
(SDI, SCLK, CSN; INH)
VS
VDD
VSDI,VSCLK
VCSN, VINH
-0.3
-0.3
-0.3
40
5.5
5.5
V
V
V
VS = VS1 = VS2
0 V < VS < 40 V
,
4.1.3
0 V < VS < 40 V
0 V < VDD < 5.5V
4.1.4
Logic output voltage
(SDO)
VSDO
-0.3
5.5
V
0 V < VS < 40 V
0 V < VDD < 5.5V
Currents
4.1.5
4.1.6
Continuous Supply Current for VS1 IS1
Continuous Supply Current for VS2 IS2
0
0
1.80
1.80
A
A
–
–
Temperatures
4.1.7
4.1.8
Junction temperature
Storage temperature
Tj
Tstg
-40
-50
150
150
°C
°C
–
–
ESD Susceptibility
2)
2)
4.1.9
ESD capability of OUTx and VS pin VESD
ESD capability of other pins VESD
-4
-2
4
2
kV
kV
4.1.10
1) Not subject to production test, specified by design.
2) Human Body Model according to ANSI EOS\ESD S5.1 standard (eqv. to MIL STD 883D and JEDEC JESD22-A114)
Note:Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note:Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
Data Sheet
8
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
General Product Characteristics
4.2
Functional Range
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Max.
4.2.1
4.2.2
Supply voltage range for
normal operation
VS(nor)
7
18
V
V
–
Extended Supply Voltage Range VS(ext)
VUV OFF
VOV OFF
Limit Values
for Operation
Deviations Possible;
After VS rising above
VUV ON
4.2.3
4.2.4
4.2.5
4.2.6
Supply Voltage Slew Rate
|dV
S
/dt|
–
10
V/μs
V
VS increasing and
decreasing 1)
Logic supply voltage range for
normal operation
Logic input voltages
(DI, CLK, CSN; INH)
VDD
3.0
-0.3
-40
5.5
5.5
150
–
–
–
VDI, VCLK
VCSN, VINH
Tj
,
V
Junction temperature
°C
1) Not subject to production test, specified by design.
Note:Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
Data Sheet
9
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
General Product Characteristics
4.3
Thermal Resistance
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
4
5
Max.
1)
4.3.1
4.3.2
4.3.3
Junction to Case, Ta = -40°C
Junction to Case, Ta = 85°C
Junction to Ambient, Ta = -40°C
(1s0p, minimal footprint)
RthjC_cold
RthjC_hot
RthjA_cold_min
–
–
–
–
–
–
K/W
K/W
K/W
1)
1) 2)
124
1) 2)
1) 3)
1) 3)
1) 4)
1) 4)
1) 5)
1) 5)
4.3.4
4.3.5
4.3.6
4.3.7
4.3.8
4.3.9
Junction to Ambient, Ta = 85°C
RthjA_hot_min
RthjA_cold_300
RthjA_hot_300
RthjA_cold_600
RthjA_hot_600
RthjA_cold_2s2p
RthjA_hot_2s2p
–
–
–
–
–
–
–
103
75
60
67
54
38
31
–
–
–
–
–
–
–
K/W
K/W
K/W
K/W
K/W
K/W
K/W
(1s0p, minimal footprint)
Junction to Ambient, Ta = -40°C
(1s0p, 300mm2 Cu)
Junction to Ambient, Ta = 85°C
(1s0p, 300mm2 Cu)
Junction to Ambient, Ta = -40°C
(1s0p, 600mm2 Cu)
Junction to Ambient, Ta = 85°C
(1s0p, 600mm2 Cu)
Junction to Ambient, Ta = -40°C
(2s2p)
4.3.10 Junction to Ambient, Ta = 85°C
(2s2p)
1) Not subject to production test, specified by design.
2) Specified RthJA value is according to JEDEC JESD51-2,-3 at natural convection on FR4 1s0p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with minimal footprint copper area and 35 μm thickness.
Ta = -40°C, Ch 1 to Ch 6 are dissipating a total of 1.5W (0.25W each). Ta = 85°C, Ch 1 to Ch 6 are dissipating a total of
1.08W (0.18W each).
3) Specified RthJA value is according to JEDEC JESD51-2,-3 at natural convection on FR4 1s0p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with additional cooling of 300 mm2 copper area and 35
μm thickness. Ta = -40°C, Ch 1 to Ch 6 are dissipating a total of 1.5W (0.25W each). Ta = 85°C, Ch 1 to Ch 6 are dissipating
a total of 1.08W (0.18W each).
4) Specified RthJA value is according to JEDEC JESD51-2,-3 at natural convection on FR4 1s0p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with additional cooling of 600 mm2 copper area and 35
μm thickness. Ta = -40°C, Ch 1 to Ch 6 are dissipating a total of 1.5W (0.25W each). Ta = 85°C, Ch 1 to Ch 6 are dissipating
a total of 1.08W (0.18W each).
5) Specified RthJA value is according to JEDEC JESD51-2,-3 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (4 x 35μm Cu). Ta = -40°C,
Ch 1 to Ch 6 are dissipating a total of 1.5W (0.25W each). Ta = 85°C, Ch 1 to Ch 6 are dissipating a total of 1.08W (0.18W
each).
Data Sheet
10
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
General Product Characteristics
4.4
Electrical Characteristics
Electrical Characteristics
VS= 7 V to 18 V, VDD= 3.0 V to 5.5 V, Tj = -40 °C to +150 °C, INH = HIGH; IOUT1-6 = 0 A; all voltages with respect
to ground, positive current flowing into pin (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
Current Consumption, INH = GND
4.4.1
Supply Quiescent current
ISQ
–
1
2.5
μA
VS = 13.5 V;
V
DD= 0 V
Tj = 85°C
Tj = 85°C
Tj = 85°C
4.4.2
4.4.3
Logic supply quiescent current
Total quiescent current
IDD_Q
–
–
0.5
2
1
4
μA
μA
I
SQ + IDD_Q
Current Consumption, INH = HIGH
4.4.4
Supply current
IS
–
4.5
10
mA
Power drivers and
power stages are off
4.4.5
4.4.6
Logic supply current
Logic supply current
IDD
IDD_RUN
–
–
1.5
5
3
–
mA
mA
SPI not active
VDD = 3.0V;
SPI 5MHz
–
IS + IDD_RUN
4.4.7
Total supply current
–
9.5
–
mA
Over- and Undervoltage Lockout
4.4.8
4.4.9
UV Switch ON voltage
UV Switch OFF voltage
VUV ON
VUV OFF
VUV HY
VOV OFF
VOV ON
VOV HY
–
4
–
21
20
–
2.60
2.50
–
–
0.25
–
–
1
2.80
2.70
5.2
5.0
–
25
24
–
3.00
2.90
V
V
V
V
V
V
V
V
VS increasing
VS decreasing
VUV ON - VUV OFF
VS increasing;
VS decreasing;
4.4.10 UV ON/OFF hysteresis
4.4.11 OV Switch OFF voltage
4.4.12 OV Switch ON voltage
4.4.13 OV ON/OFF hysteresis
4.4.14
4.4.15
V
V
V
OV OFF - VOV ON
DD increasing
DD decreasing
;
V
V
DD Power-On-Reset
DD Power-Off-Reset
VDD POR
VDD POffR
Static Drain-source ON-Resistance
4.4.16
RDSON(1-6)
–
–
0.8
1.4
–
2
Ω
Ω
I
OUT (1-6)= ±0.5 A;
High- and Low-side switch
Tj = 25 °C
I
OUT (1-6)= ±0.5 A;
Tj = 150 °C
Output Protection and Diagnosis
High-Side Switches
4.4.17 HS Overcurrent Shutdown
ISD_HS
-1.6
-1.15 -0.8
A
HS Switch;
VS=13.5V; See
Figure 7
1)
Threshold
4.4.18 HS Short Circuit Current Limit
4.4.19 HS_Shutdown Delay Time
ISC_HS
tdSD
-2.0
10
-1.5
25
-1.0
50
A
μs
HS Switch;
VS=13.5V; See
Figure 7
Data Sheet
11
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
General Product Characteristics
Electrical Characteristics (cont’d)
VS= 7 V to 18 V, VDD= 3.0 V to 5.5 V, Tj = -40 °C to +150 °C, INH = HIGH; IOUT1-6 = 0 A; all voltages with respect
to ground, positive current flowing into pin (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
Low-Side Switches
4.4.20 LS Overcurrent Shutdown
ISD_LS
0.8
1.15
1.6
A
LS Switch;
VS=13.5V; See
Figure 7
1)
Threshold
4.4.21 LS Short Circuit Current Limit
4.4.22 LS_Shutdown Delay Time
ISC_LS
tdSD
1.0
10
1.5
25
2.0
50
A
μs
LS Switch;
VS=13.5V; See
Figure 7
4.4.23 Open Load Detection Current
4.4.24 Open Load Delay Time
IOLD
tdOLD
3
200
8
350
15
600
mA
μs
LS Switch;
VS=13.5V; See
Figure 8
Output Switching Times
4.4.25 High-Side ON delay-time
4.4.26 High-Side OFF delay-time
4.4.27 Low-Side ON delay-time
4.4.28 Low-Side OFF delay-time
4.4.29 Dead Time H to L
tdONH
tdOFFH
tdONL
tdOFFL
tDHL
tDLH
tONH
tOFFH
tOFFL
tONL
–
–
–
–
1.5
2.5
–
–
–
7.5
3
6.5
2
–
–
4
2
1
1
12
6
12
5
–
–
–
–
–
–
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
VS=13.5V, resistive
Load = 100Ω, See
Figure 9 and
Figure 10
4.4.30 Dead Time L to H
4.4.31 High-Side RiseTime
4.4.32 High-Side Fall Time
4.4.33 Low-Side RiseTime
4.4.34 Low-Side Fall Time
Input Interface, Logic Inputs INH
4.4.35 High-input voltage
4.4.36 Low-input voltage
4.4.37 Hysteresis of input voltage
4.4.38 Pull down resistor
SPI INTERFACE
–
VINHH
VINHL
VINHHY
RPD_INH
70
–
50
–
–
–
200
120
–
% VDD
% VDD
mV
–
–
–
–
30
500
–
kΩ
Delay Time from Sleep mode to first Data in
1)
1)
4.4.39 Setup time
tset
–
100
–
–
100
–
μs
μs
4.4.40 Time between two consecutive SRR tSRR
commands
Input Interface, Logic Inputs SDI, SCLK, CSN
4.4.41 High-input voltage
4.4.42 Low-input voltage
4.4.43 Hysteresis of input voltage
4.4.44 Pull up resistor at pin CSN
4.4.45 Pull down resistor at pin SDI, SCLK RPD_SDI,
VIH
VIL
VIHY
RPU_CSN
70
–
50
–
–
–
200
140
120
–
% VDD
% VDD
mV
kΩ
kΩ
–
–
–
–
–
30
500
–
–
–
RPD_SCLK
Data Sheet
12
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
General Product Characteristics
Electrical Characteristics (cont’d)
VS= 7 V to 18 V, VDD= 3.0 V to 5.5 V, Tj = -40 °C to +150 °C, INH = HIGH; IOUT1-6 = 0 A; all voltages with respect
to ground, positive current flowing into pin (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
–
Typ.
10
Max.
15
4.4.46 Input capacitance at pin CSN, SDI CI
pF
0V < VDD < 5.25V 1)
or SCLK
Input Interface, Logic Outputs SDO
4.4.47 High-output voltage
VSDOH
VDD
-
VDD
-
–
V
I
I
SDOH = -1 mA
SDOL = 1.6 mA
1.0
0.7
4.4.48 Low-output voltage
4.4.49 Tri-state Leakage Current
VSDOL
ISDOLK
–
-10
0.2
–
0.4
10
V
μA
VCSN = VDD
0V < VSDO < VDD
Data Input Timing. See Figure 12 and Figure 15
1)
4.4.50 SCLK Frequency
fCLK
–
–
5
MHz
4.4.51 SCLK Period
tpCLK
500
200
–
–
–
–
–
–
–
–
–
–
–
ns
ns
V
DD = 5.25V
DD = 3.0V 1)
V
1)
4.4.52 SCLK High Time
4.4.53 SCLK Low Time
4.4.54 SCLK Setup Time
4.4.55 SDI Setup Time
4.4.56 SDI Hold Time
4.4.57 CSN Setup Time
4.4.58 CSN High Time
tSCLKH
tSCLKL
tlag
tSDI_setup
tSDI_hold
tlead
85
85
85
50
50
100
500
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
1)
1)
1)
1)
1)
1) 2)
1)
tCSNH
4.4.59 Input Signal Rise Time at pin SDI, trIN
50
SCLK, CSN
1)
4.4.60 Input Signal Fall Time at pin SDI,
SCLK, CSN
tfIN
–
–
50
ns
Data Output Timing. See Figure 14 and Figure 15
4.4.61 SDO Rise Time
4.4.62 SDO Fall Time
4.4.63 SDO Valid Time
trSDO
tfSDO
tVASDO
–
–
–
10
10
20
25
25
50
ns
ns
ns
Cload = 40pF 1)
Cload = 40pF 1)
V
SDO < 0.2VDD
V
SDO > 0.7VDD
Cload = 40pF 1)
4.4.64 SDO Enable Time after CSN falling tENSDO
–
–
–
–
50
50
60
ns
ns
%
Low Impedance 1)
edge
4.4.65 SDO Disable Time after CSN rising tDISSDO
–
High Impedance 1)
edge
1)
4.4.66 Duty cycle of incoming clock at
SCLK
dutySCLK
40
Data Sheet
13
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
General Product Characteristics
Electrical Characteristics (cont’d)
VS= 7 V to 18 V, VDD= 3.0 V to 5.5 V, Tj = -40 °C to +150 °C, INH = HIGH; IOUT1-6 = 0 A; all voltages with respect
to ground, positive current flowing into pin (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
Thermal Prewarning & Shutdown
4.4.67 Thermal warning junction
TjW_enter
TjW_exit
120
90
140
–
170
140
°C
°C
See Figure 6 1)
temperature
4.4.68 Thermal warning junction
temperature - switch off
4.4.69 Temperature warning hysteresis
ΔTjW
–
30
–
K
4.4.70 Thermal shutdown junction
temperature
TjSD
150
175
200
°C
4.4.71 Thermal switch-on junction
temperature
TjSO
130
–
180
°C
4.4.72 Temperature shutdown hysteresis ΔTjSD
4.4.73 Ratio of SD to W temperature
1) Not subject to production test, specified by design
2) CSN High Time : This is the minimum time the user must wait between SPI commands
–
20
1.20
–
–
K
–
TjSD / TjW 1.05
Data Sheet
14
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
Block Description
5
Block Description
General
5.1
5.2
5.2.1
Power Supply
General
The TLE84106EL has two power supply inputs: The half bridge outputs are connected to VS supply, which is
connected to the 12V automotive supply rail. The internal logic part is supplied by a separate voltage VDD = 5 V.
VS and VDD supplies are separated so that information stored in the logic block remains intact in the event of
voltage drop outs or disturbances on VS. The system can therefore continue to operate once VS has recovered,
without having to resend commands to the device.
A rising edge on VDD triggers an internal Power-On Reset (POR) to initialize the IC at power-on. All data stored
internally is deleted, and the outputs are switched to high-impedance status (tristate). A 10μF electrolytic and
100nF ceramic capacitor are recommended to be placed as close as possible to the VS supply pin of the device
for improved EMC performance in the high and low frequency band.
5.2.2
Sleep Mode
The TLE84106EL enters low power mode (or sleep mode) by setting the INH input to low. The INH input has an
internal pull-down resistor. In sleep-mode, all output transistors are turned off and the SPI register banks are reset.
5.2.3
Reverse Polarity Protection
The TLE84106EL requires an external reverse polarity protection. During reverse polarity, the freewheeling diodes
across the half bridge output will begin to conduct, causing an undesired current flow (IRB) from ground potential
to battery and excessive power dissipation across the diodes. As such, a reverse polarity protection diode is
recommended (see Figure 4).
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Reverse Polarity Protection
5.2.4
Power Supply Monitoring
The power supply rails VS and VDD are monitored for over- and undervoltage. See Figure 5.
Data Sheet
15
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
Block Description
5.2.4.1
VS Undervoltage
If the supply voltage VS drops below the switch off voltage VUVOFF, all output transistors are switched off but logic
information remains intact and uncorrupted. The “undervoltage” (Power Supply Fail, PSF) error bit is flagged and
can be read out via SPI. Once VS rises again and reaches the threshold switch on voltage VUVON, the power stages
are restarted and the PSF error bit is reset.
5.2.4.2
VS Overvoltage
If the supply voltage VS rises above the switch off voltage VOVOFF, all output transistors are switched off and the
“overvoltage” (PSF) error bit is set. The error is not latched, i.e. if VS falls again and reaches the switch on voltage
V
OVON, the power stages are restarted and the Error Flags are reset.
VS
VOVHY
VOVOFF
VOVON
VUVHY
VUVON
VUVOFF
t
VOUTx
ON
High Z
t
Under -voltage output &
error flag behaviour
Over-voltage output &
error flag behaviour
PSF error bit
High
Low
t
Figure 5
Output behavior during Over- and Undervoltage VS condition
5.2.5
Reset Behavior
The following reset triggers have been implemented in the TLE84106EL:-
V
DD Undervoltage Reset:
The SPI Interface shall not function if VDD is below the undervoltage threshold, VDD POffR. The digital Block will be
initialized. The output stages are switched off to High-Z. The undervoltage reset and SRR is released once VDD
voltage levels are above the undervoltage threshold, VDD POR
.
Reset on INH pin:
If the INH pin level is low, the device shall enter reset and the current consumption is reduced to ISQ + IDD_Q
.
Data Sheet
16
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
Block Description
5.3
Temperature Monitoring
Temperature sensors are integrated in the power stages. The temperature monitoring circuit compares the
measured temperature to the warning and shutdown thresholds. If one or more temperature sensors reach the
warning temperature, the temperature warning bit, TW is set to HIGH. This bit is not latched (i.e. if the temperature
falls below the warning threshold (with hysteresis), the TW bit is reset to LOW again).
If one or more temperature sensors reach the shut-down temperature threshold, all outputs are shut down and
latched (i.e. the output stages remain off until an SRR command is sent or a power-on reset is performed). See
Figure 6.
T
j
ΔΤSD
T
jSD
TjW_enter
T
jSO
TjW _exit
ΔΤJW
t
VOUTx
Output is switched off if
ON
TjSD is reached and can
only be reset via SRR
High Z
t
no error
TW error bit
High
Error flag is reset
automatically
Low
t
no error
Figure 6
Overtemperature Behavior
Data Sheet
17
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
Block Description
5.4
Protection and Diagnosis
This device features embedded protective functions which are designed to prevent IC destruction under fault
conditions described in the following sections. Fault conditions are treated as “outside” normal operating range.
Protection functions are not designed for continuous repetitive operation.
5.4.1
Short Circuit of Output to Supply or Ground
The high-side switches are protected against short to ground where as the low-side switches are protected against
short to supply.
If a switch is turned on and the current rises above the overcurrent shutdown threshold, ISD for longer than the
shutdown delay time tdSD, the output transistor is turned off and the corresponding diagnosis bit, OC, is set. During
this delay time, the current is limited to ISC as shown in Figure 7. The output stage remains off and the error bit
remains set until a status register reset is sent to the SPI or a power-on reset is performed.
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,
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High-Side and Low-Side Switch - Short Circuit and Overcurrent Protection
5.4.2
Open Load
Open-load detection in ON-state is implemented in the Low-Side switches of the bridge outputs: If the current
through the low side transistor is lower than the reference current IOLD in ON-state for longer than the open-load
detection delay time tdOLD, the corresponding open-load, OL diagnosis bit is set. The output transistor, however,
remains ON. The open load error bit is latched and can be reset by the SPI status register reset or by a power-on
reset.
As an example, if a motor is connected between outputs OUT 1 and OUT 2 with a broken wire as shown in
Figure 8, the resulting diagnostic information is shown in Table 2.
Open Load Detection Shutdown (OL SD EN) Bit via the Control Register can be activated or deactivated as
required. If the OL SD EN bit is set and an open load on the Low-Side Switch is detected, the respective output is
disabled. The error remains latched and output is off until an SRR or power on reset is performed. This has the
added advantage of independently diagnosing and isolating error flags to the corresponding failed output.
Data Sheet
18
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
Block Description
OUT 1
OUT 2
Open
Load
M
Figure 8
Table 2
Open Load Example
Open Load Diagnosis Example
Control
Diagnostic Information
Motor
Connected
Motor
Open Load Detection
Disconnected (OPLD) Error Flag
LS1
ON
HS1
LS2
ON
HS2
ON
Motor Rotation
LS1
LS2
LS1
LS2
ON
0
OpL
OpL
OpL
OpL
0
1
0
0
1
0
0
1
0
1
0
1
0
1
0
motor off
clock-wise
counter clock-wise 0
brake high
brake low
0
0
0
0
0
0
1
0
1
0
0
1
0
0
1
0
1
de-activated
activated
activated
de-activated
activated
0
1
1
0
0
1
5.4.3
Cross-Current
In bridge configurations the high-side and low-side power transistors are ensured never to be simultaneously “ON”
to avoid cross currents. This is realized by integrating delays in the driver stage of the power outputs, intended to
create a dead-time between switching off one Power Transistor and switching on of the other Power Transistor of
the same half-bridge. To ensure that there is no overlap of the switching slopes that would lead to a cross current,
the dead-times, tDHL and tDLH are specified.
In the event a cross-current has occurred, the device shall turn off both switches and the Overcurrent bit is set
High.
Data Sheet
19
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
Block Description
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Data Sheet
20
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
SPI
6
SPI
6.1
General
The SPI is used for bidirectional communication with a control unit. The TLE84106EL acts as SPI-slave and the
control unit acts as SPI-master. The 16-bit control word is read via the SDI serial data input. The status word
appears synchronously at the SDO serial data output. The communication is synchronized by the serial clock input
SCLK.
Standard data transfer timing is shown in Figure 11. The clock polarity is data valid on falling edge. SCLK must
be low during CSN transition. The transfer is MSB first.
The transmission cycle begins when the chip is selected with the chip-select-not (CSN) input (H to L). Then the
data is clocked through the shift register. The transmission ends when the CSN input changes from L to H and the
word which has been read into the shift register becomes the control word. The SDO output switches then to
tristate status, thereby releasing the SDO bus circuit for other uses. The SPI allows to parallel multiple SPI devices
by using multiple CSN lines. The SPI can also be used with other SPI-devices in a daisy-chain configuration.
The control word transmitted from the master to the TLE84106EL is executed at the end of the SPI transmission
( CSN L -> H ) and remains valid until a different control word is transmitted or a power on reset occurs. At the
beginning of the SPI transmission ( CSN H -> L ), the diagnostic data currently valid are latched into the SPI and
transferred to the master.
Data integrity is maintained by polling multiples of 8 data bits to ensure that a valid command has been received.
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Data Sheet
21
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
SPI
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Figure 14 SPI SDO and CSN
Data Sheet
22
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
SPI
6',
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Figure 15 SPI SDI, SDO and SCLK
6.2
Status Register Reset
The SPI is using a standard shift-register concept with daisy-chain capability. Any data transmitted to the SPI will
be available to the internal logic part at the end of the SPI transmission (CSN L -> H). To read a specific register,
the address of the register is sent by the master to the SPI in a first SPI frame. The data that corresponds to this
address is transmitted by the SDO during the following (second) SPI frame to the master. The default address for
Status Register transmission after Power-ON Reset is 0.
The Status-Register-Reset command-bit is executed after the next SPI transmission. The two bits, Address
Register and SRR act as command to read and reset (or not reset) the addressed Status-Register. The request
and response behaviour of the SPI is further illustrated in Figure 16 below.
CSN
SCLK
SDI
SRR 1
SRR2
SRR 3
Request 1
Request 2
Request 3
SDO
Response 0
Response 1
Response 2
Figure 16 Status Register Reset
Data Sheet
23
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
SPI
6.3
SPI Bit Definitions
Control - Word
6.3.1
Control Register Overview
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OL_SD ACT_ ACT_ ACT_ ACT_ ACT_ ACT_ CONF_ CONF_ CONF_ CONF_ CONF_ CONF_
SRR
0
0
_EN HB6 HB5 HB4 HB3 HB2 HB1 HB6 HB5 HB4 HB3 HB2 HB1
Bit
Control Register Control Register - DESCRIPTION
- LOCATE
Diagnosis Control
15
SRR
(ALL CHANNELS)
Status Register Reset (SRR).
If set to high, the errors bits of the coresponding status register are reset on the
rising edge of CSN if sent to the uC. Low indicates no reset.
14
13
0
Set to 0 to select HB 1 to 6
Open Load Detection Shutdown Enable (OL SD EN) allows the affected output
OL SD EN
(ALL CHANNELS) stage to be switched off if a true open load or underload condition has been
detected. This feature can be activated or deactivated by bit 13.
Activate Half-Bridge X
12
11
10
9
8
7
ACT_HB 6
ACT_HB 5
ACT_HB 4
ACT_HB 3
ACT_HB 2
ACT_HB 1
H => Half Bridge 6 is active
H => Half Bridge 5 is active
H => Half Bridge 4 is active
H => Half Bridge 3 is active
H => Half Bridge 2 is active
H => Half Bridge 1 is active
L => Half Bridge 6 is in Hi-Z
L => Half Bridge 5 is in Hi-Z
L => Half Bridge 4 is in Hi-Z
L => Half Bridge 3 is in Hi-Z
L => Half Bridge 2 is in Hi-Z
L => Half Bridge 1 is in Hi-Z
Configure Half-Bridge X
6
5
4
3
2
1
CONF_HB 6
CONF_HB 5
CONF_HB 4
CONF_HB 3
CONF_HB 2
CONF_HB 1
0
H => HSD6 = ON & LSD6 = OFF
H => HSD5 = ON & LSD5 = OFF
H => HSD4 = ON & LSD4 = OFF
H => HSD3 = ON & LSD3 = OFF
H => HSD2 = ON & LSD2 = OFF
H => HSD1 = ON & LSD1 = OFF
L => HSD6 = OFF & LSD6 = ON
L => HSD5 = OFF & LSD5 = ON
L => HSD4 = OFF & LSD4 =ON
L => HSD3 = OFF & LSD3 = ON
L => HSD2 = OFF & LSD2 = ON
L => HSD1 = OFF & LSD1 = ON
0
Least Significant Bit (LSB) is set to Low
Data Sheet
24
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
SPI
6.3.2
Diagnosis - Word
Diagnosis Register Overview
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SACT_ SACT_ SACT_ SACT_ SACT_ SACT_ SCONF SCONF SCONF SCONF SCONF SCONF
OC
PSF
OL
TW
HB6 HB5 HB4 HB3 HB2 HB1 _HB6 _HB5 _HB4 _HB3 _HB2 _HB1
Table 4
Bit
Output (Status) Data Register
Status Register Status Register - DESCRIPTION
- LOCATE
15
14
13
OC
Overcurrent Error is set if any one of the Half-Bridges has an overload, short circuit
or cross current; The error is latched and the corresponding output is switched off;
Bit 15 error can only be reset via SRR or power-on reset.
(ALL
CHANNELS)
PSF
(ALL
CHANNELS)
OL
(ALL
CHANNELS)
Power Supply Failure;
Bit 14 is set if
V
S has an overvoltage or undervoltage condition; All outputs are switched
OFF. Bit 14 is automatically reset if VS returns to its normal operating range.
Open Load Error is set if any one of the Half-Bridges has a true open load or
underload error condition; The error is latched. The corresponding output is
switched off if Bit 13, OL SD EN of the Control Register is activated or high. Bit 13
error can only be reset via SRR or power-on reset.
Activated Driver Status of Half-Bridge X
12
11
10
9
8
7
SACT_HB 6
SACT_HB 5
SACT_HB 4
SACT_HB 3
SACT_HB 2
SACT_HB 1
H => Half Bridge 6 is active
H => Half Bridge 5 is active
H => Half Bridge 4 is active
H => Half Bridge 3 is active
H => Half Bridge 2 is active
H => Half Bridge 1 is active
L => Half Bridge 6 is in Hi-Z
L => Half Bridge 5 is in Hi-Z
L => Half Bridge 4 is in Hi-Z
L => Half Bridge 3 is in Hi-Z
L => Half Bridge 2 is in Hi-Z
L => Half Bridge 1 is in Hi-Z
Configured Driver Status of Half-Bridge X
6
5
4
3
2
1
SCONF_HB 6
SCONF_HB 5
SCONF_HB 4
SCONF_HB 3
SCONF_HB 2
SCONF_HB 1
TW
H => HSD6 = ON & LSD6 = OFF
H => HSD5 = ON & LSD5 = OFF
H => HSD4 = ON & LSD4 = OFF
H => HSD3 = ON & LSD3 = OFF
H => HSD2 = ON & LSD2 = OFF
H => HSD1 = ON & LSD1 = OFF
Thermal Warning Bit; Global Error Flag;
L => HSD6 = OFF & LSD6 = ON
L => HSD5 = OFF & LSD5 = ON
L => HSD4 = OFF & LSD4 = ON
L => HSD3 = OFF & LSD3 = ON
L => HSD2 = OFF & LSD2 = ON
L => HSD1 = OFF & LSD1 = ON
0
This bit is treated as an early warning and will be set to High if the junction
temperature reaches TJW. The output remains on until one or more sensors
reaches TSD causing all outputs to be switched off simultaneously.
Bit 0 is automatically reset if the junction temperature cools down to TJSO
Note:Status HBx represents status of Half-Bridge Driver and NOT status of Control Register.
Note:The PSF and TW bits in the first Diagnosis word will reflect the current clock cycle status, all other remaining
bits are 0.
Data Sheet
25
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
Application Information
7
Application Information
Note:The following simplified application examples are given as a hint for the implementation of the device only
and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the
device. The function of the described circuits must be verified in the real application.
7.1
Application Diagram
96
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Figure 17 Application Example for DC-motor Loads
For optimum EMC performance, a ferrite is recommended to be placed in series and as close as possible to the
Vdd line of the TLE841xy device. This is shown in the above application diagram example. The ferrite should have
an impedance of 1000ohm at an effective frequency of 100MHz frequency. A recommended ferrite is the
MMZ1608 type series available in a geometry size of 0603 with a DC resistance of 0.6ohm and allowable DC
current of 190mA.
Data Sheet
26
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
Application Information
7.2
Thermal application information
Ta = -40°C, Ch 1 to Ch 6 are dissipating a total of 1.5W (0.25W each).
Ta = 85°C, Ch 1 to Ch 6 are dissipating a total of 1.08W (0.18W each).
Zth-ja Curves for TLE 84106EL (6 channels on)
135
120
-40°C; 1s0p + 600 mm²
-40°C; 1s0p + 300 mm²
-40°C; 1s0p +footprint
-40°C; 2s2p
+85°C; 1s0p + 600 mm²
+85°C; 1s0p + 300 mm²
+85°C; 1s0p + footprint
+85°C; 2s2p
105
90
75
60
45
30
15
0
0,00001 0,0001 0,001
0,01
0,1
1
10
100
1000
10000
Pulse [sec]
Figure 18 ZthJA Curve for different PCB setups
Zth-jc Curves for TLE 84106EL (6 channels on)
5
4
3
2
1
Ta = -40°C
Ta = +85°C
0
0,00001
0,0001
0,001
0,01
0,1
1
10
100
1000
Pulse [sec]
Figure 19 ZthJC Curve
Data Sheet
27
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
Application Information
1s0p + 600mm² cooling
area
2s2p / 1s0p + footprint
Figure 20 Board Setup
Board Setup based on JESD 51-3, -7 FR4 PCB with 35μm Cu.
Data Sheet
28
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
Package Outlines
8
Package Outlines
0.35 x 45˚
2x
1)
0.1
3.9
0.1 C D
0.08
Seating Plane
C
C
0.65
2)
0.05
0.2
0.25
6
M
M
0.2
D
0.2
C A-B D 24x
D
Bottom View
A
24
1
12
13
1
12
24
13
B
0.25
6.4
0.1 C A-B 2x
0.1
8.65
Index Marking
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Does not include dambar protrusion of 0.13 max.
PG-SSOP-24-4-PO V01
Figure 21 PG-SSOP-24-4 (Plastic/Plastic Green - Dual Small Outline Package)
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e
Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
Dimensions in mm
Data Sheet
29
Rev. 1.0, 2010-04-27
TLE84106EL
Hex Half Bridge IC
Revision History
9
Revision History
0.30.40.3
TLE84106EL
Revision History: Rev. 1.0, 2010-04-27
Version
Subjects (major changes since last revision)
Final Data Sheet Release
1.0
Data Sheet
30
Rev. 1.0, 2010-04-27
Edition 2010-04-27
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2010 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
相关型号：
TLE84110ELXUMA1
Half Bridge Based Peripheral Driver, 1.5A, BICMOS, PDSO24, GREEN, PLASTIC, SSOP-24
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