TLD6098-2ES_技术文档

LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

Features

•

Dual channel device

Wide input voltage (up to 58 V) and output voltage range

(up to 70 V)

•

Switching frequency range from 100 kHz to 500 kHz and

synchronization at 2.2 MHz with an external clock source

•

EMC optimized device

Analog adjust input

Overvoltage, Short to ground, overcurrent, open feedback

and overtemperature diagnostic output

PMOS gate driver for dimming and protection with

enhanced dimming features

LED current accuracy ±3.5%

Product type Package

Marking

TLD6098-2ES PG-TSDSO-24 TLD6098-2

•

Potential applications

•

LED driver for: front light module, rear light module, interior light

Voltage regulator

V_S

L_1,2

D_1,2

R_FB1,2

M_P1,2

C_BO

LED_1-1,2

LED_2-1,2

IVCC

IN

M_1,2

SWO1,2

IVCC

C_IVCC

LED_3-1,2

LED_4-1,2

LED_5-1,2

LED_6-1,2

LED_7-1,2

LED_8-1,2

SWCS1,2

FPWM/FAULT1,2

R_SWCS1,2

R_FAULT1,2

FBH1,2

FBL1,2

FREQ/SYNC/SPREAD

R_FREQ

IVCC

R_SETH1,2

R_VFBH1,2

SET1,2

VFB1,2

IVCC

R_SETL1,2

R_VFBL1,2

R_DCH1,2

DC/PWMI1,2

COMP1,2

PWMO1,2

GND

R_DCL1,2

C_COMP1-1,2

R_COMP1,2

C_COMP2-1,2

TLD6098-2ES

B2G-2ch.vsdx

Figure 1

Application diagram

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

Rev.1.10

2021-09-30

LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

Description of TLD6098-2ES

TLD6098-2ES is a dual channel multi-topology DC-DC controller designed for LED applications with built-in

protection features to implement a compact LED driver.

The output current generated by the two channels are independent and they are regulated by means of a peak

current control loop. An internal slope compensation is used to avoid sub-harmonic oscillation at high duty

cycle (e.g. higher than 50%).

The current accuracy is better than 3.5% (with no analog adjustment applied) over the operating temperature

range. A rail to rail current sense amplifiers provide flexibility on the topology choice needed to supply LED

string with more than 20 white LED (up to 70 V at output).

The switching frequency can be adjusted from 100 kHz to 500 kHz using an external resistor. A synchronization

with an external clock is also possible. The device incorporates even a spread spectrum modulator to achieve

easy fulfilment of electromagnetic emission standards.

Each channel of TLD6098-2ES can drive an external PMOS for dimming and protection.

For this purpose each channel of TLD6098-2ES incorporates even a PWM generator controlled by an analog

voltage on DC/PWM1,2 pin. The generated PWM signal has the duty cycle adjustable from 0 to 100% with 10 bits

of resolution and the frequency range programmable from 150 Hz to 750 Hz. On the same DC/PWMI1,2 pin the

digital PWM signal can also be used.

Product validation

Qualified for automotive applications.

Product validation according to AEC-Q100.

Datasheet

2

Rev.1.10

2021-09-30

LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

Table of contents

Table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1

2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3

General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.1

3.2

3.3

4

4.1

4.2

Switching regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Soꢀ start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5

5.1

5.2

Linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Undervoltage protection for the external switching MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6

6.1

Switching frequency setup and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Switching frequency setup with external resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Synchronization with external clock (low frequency mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Synchronization with external clock (high frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.1.1

6.1.2

6.1.2.1

6.2

6.2.1

6.3

7

Analog output adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

7.1

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

8

8.1

8.2

8.2.1

8.3

Dimming functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Digital PWM dimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Embedded PWM engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

8.3.1

9

9.1

9.2

9.2.1

9.3

9.3.1

9.4

9.4.1

Protections and fault management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Short to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Output overvoltage and voltage regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Overvoltage on FBH pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Datasheet

3

Rev.1.10

2021-09-30

LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

Table of contents

9.5

Output overcurrent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

9.5.1

9.6

9.6.1

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Overtemperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

10

11

12

Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Datasheet

4

Rev.1.10

2021-09-30

LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

1 Block diagram

1

Block diagram

Internal

supply

V_IVCC

LDO

IN

IVCC

Power on

reset

DC/PWMI1

DC/PWMI2

On/Off logic +

digital PWM

dimming

SWO1

SWO2

Power switch

gate driver

VM1_INT

VM2_INT

PWM dimming

generator + fault

report logic +

control loop

selector

Slope comp.

FPWM/FAULT1

FPWM/FAULT2

Switch current

error amplifier

SWCS1

SWCS2

DC/DC

switching regulators

and logic

Leading edge

blanking

Clock

generator

FREQ/SYNC/SPREAD

Slope comp.

Thermal

protection

Switch current

error amplifier

V

_FBH1– V_FBL1

_FBH2– V_FBL2

Leading edge

blanking

Soft start

Open load and

short to GND

V_FBH1

V_FBH2

Over

voltage

protection

VM1_INT

g_m1

VFB1

V_{VFB_REF}

COMP1

SET1

FBL1

FBH1

g_m2

x1

Reference current

V

_FBH1– V_FBL1

generation

Open load and

short to GND

VM2_INT

g_m1

VFB2

V_{VFB_REF}

COMP2

SET2

FBL2

FBH2

g_m2

x1

Reference current

generation

V

_FBH2– V_FBL2

GND

Block diagram TLD6098-2.vsdx

Figure 2

Block diagram

Datasheet

5

Rev.1.10

2021-09-30

LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

2 Pin configuration

2

Pin configuration

1

2

24

23

22

21

20

19

18

PWMO1

SET1

FBH1

FBL1

VFB1

SWO1

3

IVCC

Exposed

Pad

COMP1

4

FPWM/FAULT1

IN

5

SWCS1

GND

6

DC/PWMI1

7

FREQ/SYNC/SPREAD

SWCS2

PIN_POS_24.VSDX

8

17

DC/PWMI2

FPWM/FAULT2

COMP2

SWO2

9

16

15

14

13

10

11

12

VFB2

FBL2

SET2

FBH2

PWMO2

Figure 3

Table 1

Pin configuration - PG-TSDSO-24

Pin configuration of PG-TSDSO-24

Name

Pos.

Description

Direction

PWMO1

1

PMOS driver for dimming and protection

Channel 1

Output

Connect to gate of external MOSFET

Pin must be leꢀ open if external MOSFET is not used

SET1

2

Analog adjust input

Input

Channel 1

Load current adjustment pin

Pin must not be leꢀ open

If analog adjustment is not used, connect to IVCC pin

IVCC

3

4

Internal linear voltage regulator

Used for internal biasing and gate drive

Bypass with external capacitor

Pin must not be leꢀ open

Output

Input

COMP1

Compensation

Channel 1

Connect R and C network for stability

(table continues...)

Datasheet

6

Rev.1.10

2021-09-30

LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

2 Pin configuration

Table 1

(continued) Pin configuration of PG-TSDSO-24

Name

Pos.

Description

Direction

FPWM/FAULT1

5

PWM frequency selector/Fault

Channel 1

Input/Output

Connect external R to set PWM frequency

Faults are reported by raising the voltage on this pin

IN

6

7

Supply

Supply for internal biasing

Input

DC/PWMI1

PWM adjustment

Channel 1

Set Duty cycle of PWM engine or digital input for PWM

dimming

DC/PWMI2

8

9

PWM adjustment

Channel 2

Set Duty cycle of PWM engine or digital input for PWM

dimming

Input

FPWM/FAULT2

PWM frequency selector / Fault

Channel 2

Input/Output

Connect external R to set PWM frequency

Faults are reported by raising the voltage on this pin

COMP2

SET2

10

11

Compensation

Channel 2

Connect R and C network for stability

Input

Analog adjust input

Channel 2

Load current adjustment pin

Pin must not be leꢀ open

If analog adjustment is not used, connect to IVCC pin

PWMO2

12

PMOS driver for dimming and protection

Channel 2

Output

Connect to gate of external MOSFET

Pin must be leꢀ open if external MOSFET is not used

FBH2

FBL2

VFB2

13

14

15

Voltage feedback positive

Channel 2

Non inverting input (+)

Input

Voltage feedback negative

Channel 2

Inverting input (-)

Overvoltage/Voltage loop reference

Channel 2

(table continues...)

Datasheet

7

Rev.1.10

2021-09-30

LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

2 Pin configuration

Table 1

Name

(continued) Pin configuration of PG-TSDSO-24

Pos.

Description

Direction

Connect to resistive voltage divider to set the maximum

voltage at output and the short to ground threshold

SWO2

16

Switch gate driver

Output

Channel 2

Connect to gate of external switching power n-channel

MOSFET

SWCS2

17

18

Current sense/Power ground

Channel 2

Detects peak current through power switch

Power ground for gate driver of SWO2

Input

FREQ/SYNC/SPREAD

Frequency select or synchronization

Connect external resistor to GND to set switching frequency

Apply square waveform for synchronization

GND

19

20

Ground

–

SWCS1

Current sense/Power ground

Channel 1

Input

Detects peak current through power switch

Power ground for gate driver of SWO1

SWO1

VFB1

21

22

Switch gate driver

Channel 1

Connect to gate of external switching power n-channel

MOSFET

Output

Input

Overvoltage/Voltage loop reference

Channel 1

Connect to resistive voltage divider to set the maximum

voltage at output and the short to ground threshold

FBL1

23

24

EP

Voltage feedback negative

Channel 1

Inverting input (-)

Input

–

FBH1

Voltage feedback positive

Channel 1

Non inverting input (+)

Exposed pad

Used only for heat dissipation

Connect to pin 19 (GND)

Datasheet

8

Rev.1.10

2021-09-30

LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

3 General product characteristics

3

General product characteristics

3.1

Absolute maximum ratings

Table 2

Absolute maximum ratings

T_J= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise

specified)

Not subject to production test, specified by design

Parameter

Symbol

Values

Typ.

Unit Note or condition

P-

Number

Min.

-0.3

Max.

60

Power supply input

voltage

V_IN

–

V

–

PRQ-31

Voltage at pin SET1,

SET2

V_SET1,2

-0.3

-1

–

5.5

60

75

PRQ-182

PRQ-286

PRQ-171

PRQ-172

PRQ-173

Voltage at pin DC/

PWMI1, DC/PWMI2

V_DC/PWMI1,2

V_FBH1,2

V_FBL1,2

Voltage at pin FBH1,

FBH2

Voltage at pin FBL1,

FBL2

-1

Diﬀerential input

V_REF1,2(MAX)

-75

V_REF1,2(MAX)= V_FBH1,2-

voltage

V_FBL1,2

Diﬀerential signal (not

referred to ground)

Current at pin FBH1,

FBH2, FBL1, FBL2

I_FBH1,2

I_FBL1,2

-7.5

–

7.5

mA

V_REF1,2=150 mV

PRQ-288

Voltage at pin VFB1,

VFB2

V_FB1,2

-0.3

–

5.5

0.3

5.5

V

–

PRQ-174

PRQ-175

PRQ-176

PRQ-179

PRQ-177

PRQ-180

PRQ-42

Voltage at pin SWCS1, V_SWCS1,2

SWCS2

Voltage at pin SWO1,

SWO2

V_SWO1,2

Voltage at pin FPWM/

FAULT1

V_FPWM/FAULT1

V_FPWM/FAULT2

Voltage at pin FPWM/

FAULT2

Voltage at pin COMP1, V_COMP1,2

COMP2

Voltage at pin FREQ/

SYNC/SPREAD

V_FREQ/SYNC

(table continues...)

Datasheet

9

Rev.1.10

2021-09-30

LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

3 General product characteristics

Table 2

(continued) Absolute maximum ratings

T_J= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise

specified)

Not subject to production test, specified by design

Parameter

Symbol

Values

Typ.

Unit Note or condition

P-

Number

Min.

-0.3

Max.

75

Voltage at pin PWMO1, V_PWMO1,2

PWMO2

–

V

–

PRQ-181

PRQ-580

PMOS output voltage

V_PMOS1,2

-1

–

10

V_PMOS1,2= V_FBH1,2-

V_PWMO1,2

Diﬀerential signal (Not

referred to ground)

Voltage at pin IVCC

V_IVCC

-0.3

5.5

V

–

PRQ-45

Temperature

Junction temperature T_J

-40

–

150

°C

–

PRQ-46

PRQ-47

Storage temperature

ESD susceptibility

T_stg

V_{ESD_HBM}

-2

–

2

kV

HBM: ESD

PRQ-48

PRQ-49

PRQ-50

susceptibility, Human

Body Model "HBM"

according to AEC

Q100-002

ESD susceptibility

inner pins

V_{ESD_CDM}

-0.5

-0.75

0.5

0.75

CDM: ESD

susceptibility, Charged

Device Model "CDM"

according to AEC

Q100-011

ESD susceptibility

corner pins

V_{ESD_CDM_CR}

CDM: ESD

susceptibility, Charged

Device Model "CDM"

according to AEC

Q100-011

Attention:

1.

Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute

maximum rating conditions for extended periods may aﬀect device reliability

2.

Integrated protection functions are designed to prevent IC destruction under fault conditions

described in the datasheet. Fault conditions are considered as "outside" normal operating range.

Protection functions are not designed for repetitive operation.

Datasheet

10

Rev.1.10

2021-09-30

LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

3 General product characteristics

3.2

Functional range

Table 3

Functional range

T_J= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise

specified)

Parameter

Symbol

Values

Typ.

Unit Note or condition

P-

Number

Min.

4.5

Max.

58

1)

Extended power supply V_{IN_EXT}

input voltage range

–

V

PRQ-51

PRQ-52

Parameter deviations

possible

Power supply input

voltage operating

range

V_{IN_OP}

8

–

36

V

–

Operating voltage at

pin FBH1, FBH2

V_{FBH1,2_OP}

V_{FBL1,2_OP}

f_SWO

0

-

70

V

–

PRQ-303

PRQ-582

PRQ-85

PRQ-90

Operating voltage at

pin FBL1, FBL2

-0.3

100

–

70

V

Switching frequency

adjustment range

500

kHz

Synchronization low

frequency capture

range

f_FREQ/SYNC/

SPREAD(LF)

Synchronization high

frequency capture

range

f_FREQ/SYNC/

SPREAD(HF)

2

–

2.4

MHz

Hz

–

PRQ-132

PRQ-213

PWM1, PWMO2

frequency range

f_PWMO1,2

150

750

1) Not subject to production test, specified by design

Attention: Within the functional range the IC operates as described in the circuit description. The electrical

characteristics are specified within the conditions given in the related electrical characteristics

table.

3.3

Thermal resistance

Table 4

Thermal resistance

Not subject to production test, specified by design

Parameter

Symbol

Values

Typ.

22.3

Unit Note or condition

P-

Number

Min.

Max.

1)

Junction to case

R_thJC

R_thJA

–

K/W

PRQ-362

PRQ-363

PRQ-364

Junction to ambient

52.7

K/W

²⁾2s2p

²⁾1s0p + 600 mm²

Junction to ambient

(table continues...)

Datasheet

71.2

11

Rev.1.10

2021-09-30

LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

3 General product characteristics

Table 4

(continued) Thermal resistance

Not subject to production test, specified by design

Parameter

Symbol

Values

Typ.

Unit Note or condition

²⁾1s0p + 300 mm²

P-

Number

Min.

Max.

Junction to ambient

R_thJA

–

80.4

–

K/W

PRQ-365

1) Specified R_thJCvalue is simulated at natural convection on a cold plate setup (all pins and exposed pads

are fixed to ambient temperature) T_A= 25°C dissipates 1 W

2) Specified R_thJAvalue is according JEDEC 2s2p (JESD 51-7) + (JESD 51-5) and JEDEC 1s0p (JESD 51-3) +

heatsink area at natural convection on FR4 board. The device was simulated on 76.2 x 114.3 x 1.5 mm

board. The 2s2p board has 2 outer copper layers (2 x 70 μm Cu) and 2 inner copper layer (2 x 35 μm

Cu). A thermal via (diameter = 0.3 mm and 25 μm plating) array was applied under the exposed pad and

connected the top layer and the inner layers to bottom layers of JEDEC PCB. T_A= 25°C; IC dissipates 1 W

Note:

This thermal data was generated in accordance with JEDEC JESD51 standards. For further

information visit https://www.jedec.org

Datasheet

12

Rev.1.10

2021-09-30

LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

4 Switching regulator

4

Switching regulator

The TLD6098-2ES implements a dual channel regulator suitable for Boost-to-ground, Boost-to-battery, Buck-to-

battery, SEPIC, Flyback and Cuk configurations. The two channels work independently.

Each channel has two distinct control loops:

•

A current control loop (always enabled)

A voltage control loop (optional)

If the voltage loop is enabled the device regulates the output current as long as the feedback voltage on VFB1,2

pin is below the VFB1,2 voltage mode ON threshold (V_{VFB1,2_VM(ON)}). The voltage control loop takes over and

regulates the output voltage once the VFB1,2 reference voltage (V_{VFB1,2_REF}) is reached.

The controller generates two independent PWM signals by sensing the inductor peak currents and the output

of the internal error amplifiers. The control signals are applied to the internal gate drivers connected to SWO1,2

pin to drive the external n-channel MOSFETs.

4.1

Soꢀ start

The soꢀ start routine has 2 functionalities:

•

Limiting the input current and output overshoot

Guaranteeing that the system output reaches the target value in a reasonable time even when being

operated in PWM dimming with low duty cycles

Each channel performs its own soꢀ start routine independently.

The first rising edge on DC/PWMI1,2 pin or the first cycle of the embedded PWM engine enables the soꢀ start

routine.

It is then performed in the following cases:

•

At start-up

Aꢀer an overvoltage on FBH1,2 pin

Aꢀer an overvoltage on VFB1,2 pin

Aꢀer an overtemperature fault

Aꢀer an undervoltage on IVCC pin

The soꢀ start is applied aꢀer a short to ground fault and retriggered every t_FAULTin case of continuous presence

of the fault.

The operation of the soꢀ start is conditioned by the analog output adjustment.

During the soꢀ start the switching regulator adjusts the PWM signal to make the voltage between FBH1,2 and

FBL1,2 evolve from 0 to V_REF(100%)in t_SStime. The evolution is performed in 15 steps if the analog adjustment is

not applied, otherwise the intended steady-state is reached before the soꢀ start ends.

An ON time extension of the PWM dimming pulses is applied to ensure a reasonable power-up time when a low

duty cycle dimming is applied.

Datasheet

13

Rev.1.10

2021-09-30

LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

4 Switching regulator

V_IN

V_IN(ON)

t

V_DC/PWMI1,2

V

_FBH1,2– V_FBL1,2

V_REF

V_{PWM_EXT}

t

ON time extension

SWO1,2

Gate driver

enabled

Gate driver enabled

t

PWMO1,2

PMOS

OFF

PMOS

OFF

PMOS

OFF

PMOS ON

soft start timing diagram_TLD6098-2ES.vsdx

Figure 4

Soꢀ start timing diagram (the linear waveform of V_VFBH-V_VFBLis an example of possible

scenario)

The ON time extension is triggered if :

•

The applied PWM dimming signal (or the signal generated by the PWM engine) has an ON time shorter than

t_SSduring the soꢀ start

and

•

The voltage across FBH1,2 and FBL1,2 is lower than the reference voltage during PWM extension V_{PWM_EXT}at

the end of the ON time of the PWM signal

The ON time extension persists as long as the voltage across FBH1,2 and FBL1,2 reaches V_{PWM_EXT.}

The V_{PWM_EXT}is limited by the analog output adjustment down to a minimum reference voltage during ON time

extension V_{PWM_MIN}

For the first 3 steps of the V_REFsignal, the V_{PWM_EXT}is higher than V_REF

.

If the reference voltage across FBH1,2 and FBL1,2 adjusted by analog adjustment feature is lower than the

V_{PWM_MIN}the ON time extension ends aꢀer t_SS

.

Datasheet

14

Rev.1.10

2021-09-30

LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

4 Switching regulator

V_REF

V_{PWM_EXT}

V_REF(100%)

V_REF

V_{PWM_EXT}

V_{PWM_MIN}

t

t_SS

VREF evolution during soft-start.vsdx

Figure 5

V_REFand V_{PWM_EXT}waveforms during the soꢀ start routine without analog output

adjustment

V_REF

V_{PWM_EXT}

Soft start steady state

Adjusted V_REF

V_REF

V_{PWM_EXT}

V_{PWM_MIN}

t

t_SS

VREF evolution during soft-start.vsdx

Figure 6

V_REFand V_{PWM_EXT}waveforms during the soꢀ start routine with analog output

adjustment

If the ON time extension ends before t_SSelapsed, the ON time extension is retriggered in the following PWM

cycle, in case the voltage between FBH1,2 and FBL1,2 is once again lower than V_{PWM_EXT}

When the ON time extension ends, the remaining part of the soꢀ start is allowed to evolve during the following

ON time of the PWM dimming signal. In this case the actual duration of soꢀ start could be longer than t_SS

.

Datasheet

15

Rev.1.10

2021-09-30

LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

4 Switching regulator

4.2

Electrical characteristics

Table 5

Electrical characteristics

V_IN= 8 V to 36 V; T_J= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin;

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or condition

P-

Number

Min.

Max.

Regulator

VFB1,2 reference

voltages (voltage loop)

V_{VFB1,2_REF}

1.568 1.6

144.75 150

1.632

V

–

PRQ-183

Current loop reference V_REF1,2(100%)

155.25 mV

Diﬀerential signal (not PRQ-184

voltages

referred to ground)

V_REF1,2= V_FBH1,2

V_FBL1,2

-

;

V_SET1,2= 5V

1)

Current loop reference V_REF1,2(40%)

voltages

54.6

–

60

–

65.4

10

mV

PRQ-185

Diﬀerential signal (not

referred to ground)

V_SET1,2= 940 mV

Current loop reference V_REF1,2(0%)

Diﬀerential signal (not PRQ-186

voltages

referred to ground)

V_SET1,2= 100 mV

1)

Transconductance

error amplifier voltage

loop

g_m1

–

0.95

1.6

–

mS

PRQ-600

1)

Transconductance

error amplifier current

loop

g_m2

PRQ-463

Switch current limit

thresholds

V_{SWCS1,2_TH}

80

91

88

100

–

120

–

mV

%

–

PRQ-187

PRQ-70

PRQ-71

Maximum duty cycle in D_MAX

adjust. freq. mode

R_FREQ/SYNC/

_SPREAD= 27 kΩ

Maximum duty cycle

in low frequency sync

mode

D_MAX(LF)

–

%

f_SW= 500 kHz

Maximum duty cycle

in high frequency sync

mode

D_MAX(HF)

80

–

%

f_SW= 2.2 MHz

PRQ-289

1)

Soꢀ start time

t_SS

1.8

–

2

2.2

–

ms

V

PRQ-72

1)

Reference voltage

V_{PWM_EXT}

0.8*V_RE

PRQ-588

during PWM extension

F1,2

V_{PWM_EXT}> V_{PWM_MIN}

(table continues...)

Datasheet

16

Rev.1.10

2021-09-30

LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

4 Switching regulator

Table 5

(continued) Electrical characteristics

V_IN= 8 V to 36 V; T_J= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin;

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or condition

P-

Number

Min.

Max.

1)

Minimum reference

voltage during PWM

extension

V_{PWM_MIN}

–

31.5

–

mV

PRQ-589

PRQ-188

Input current at pin

FBH1, FBH2

I_FBH1,2

550

800

μA

V_FBH1,2-

V_FBL1,2= 0.15 V

V_FBH1,2= 60 V

Input current at pin

FBL1, FBL2

I_FBL1,2

I_FBH1,2

–

50

70

μA

V_FBH1,2- V_FBL1,2= 0.15V PRQ-189

V_FBH1,2= 60 V

Input current at pin

FBH1, FBH2

V_FBH1,2- V_FBL1,2= 0.15 V PRQ-190

V_FBL1,2= 0 V

Current flows out of

Input current at FBL1, I_FBL1,2

FBL2

–

50

70

μA

V_FBH1,2- V_FBL1,2= 0.15 V PRQ-191

V_FBL1,2= 0 V

Current flows out of

1)

Threshold voltage high V_{FBH1,2_HSS}

side sensing

2.55

2.3

–

2.8

–

V

PRQ-265

V_FBH1,2increasing

1)

Threshold voltage low V_{FBH1,2_LSS}

side sensing

2.1

2.5

PRQ-266

V_FBH1,2decreasing

Power supply

undervoltage

shutdown

V_IN(OFF)

4.5

V_INdecreasing

PRQ-77

PRQ-78

PRQ-430

Power supply

minimum startup

voltage

V_IN(ON)

–

8

5.5

12

V

V_INincreasing

Power supply current I_IN

mA

V_DC/PWMI1,2= 0 V

consumption

V_SET1,2= V_IVCC

R_{FREQ/SYNC/SPREAD}

=

33 kΩ

R_{FPWM/FAULT1,2}= 57 kΩ

no faults detected

Gate driver for external switch

(table continues...)

Datasheet

17

Rev.1.10

2021-09-30

LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

4 Switching regulator

Table 5

(continued) Electrical characteristics

V_IN= 8 V to 36 V; T_J= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin;

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or condition

P-

Number

Min.

Max.

1)

Gate drivers peak

output current

I_SWO1,2

1

–

A

PRQ-192

V_SWO1,2increasing 1 V

to 4 V

Current flows out of

1)

Gate drivers peak

output current

I_SWO1,2

1

–

A

PRQ-193

PRQ-194

V_SWO1,2decreasing 4 V

to 1 V

1)

Gate drivers output rise t_{R_SWO1,2}

time

20

ns

C_{L_SWO1,2}= 3.3 nF

V_SWO1,2increasing 1 V

to 4 V

1)

Gate drivers output fall t_{F_SWO1,2}

–

ns

PRQ-195

time

C_{L_SWO1,2}= 3.3 nF

V_SWO1,2decreasing 4 V

to 1 V

1)

Gate driver high side

resistance

R_{SWO_HS}

R_{SWO_LS}

–

1

3

Ω

PRQ-83

I_SWO= -10 mA

1)

Gate driver low side

resistance

Ω

PRQ-196

I_SWO= 10 mA

1) Not subject to production test, specified by design

Datasheet

18

Rev.1.10

2021-09-30

LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

5 Linear regulator

5

Linear regulator

The device incorporates a linear regulator to generate a 5 V output used to supply the internal gate drivers

and, through IVCC pin, other auxiliary devices on the PCB (for example a microcontroller and resistor dividers).

The maximum output current of the linear regulator is limited to the IVCC output current limit I_IVCC

.

If the load on IVCC (gate drivers plus connected devices on PCB) draws more than I_IVCCthe linear regulator

output voltage decreases.

The linear regulator starts to deliver current to IVCC pin when the input voltage V_INgoes above the power supply

minimum start up voltage V_{IN (ON)}for a time longer than IVCC start time t_ST

A low ESR capacitor has to be connected from IVCC to ground (C_IVCCin the figure) to stabilize the output voltage

of the linear regulator.

The ESR of the capacitor C_IVCChas to be lower than IVCC buﬀer capacitor ESR R_IVCC(ESR)

.

V_S

IVCC

IN

Voltage regulator

Clock generator

C_IVCC

FREQ/SYNC

SWO1

SWO2

DC/PWMI1

DC/PWMI2

Switching

regulators 1 & 2

TLD6098-2ES

Linear regulator on TLD6098-2ES.vsdx

Figure 7

Block diagram of the linear regulator

5.1

Undervoltage protection for the external switching MOSFET

During the ON time of the switching PWM signal, the gate drivers have to bias the switching NMOS in deep

ohmic region to avoid the overheating of the MOSFET themselves. This is ensured by choosing a logic level

MOSFET with a maximum threshold voltage lower than IVCC undervoltage switch-oﬀ threshold V_{IVCC_TH_D.}

TLD6098-2ES has an integrated undervoltage reset threshold circuit to disable the gate driver if the V_IVCCdrops

below the V_{IVCC_TH_D}. The gate driver are then enabled again when the V_IVCCgoes above the IVCC undervoltage

switch-on threshold V_{IVCC_TH_I}

.

Datasheet

19

Rev.1.10

2021-09-30

LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

5 Linear regulator

V_IN

V_IN(ON)

V_IN(OFF)

t

V_IVCC

V_{IVCC_TH_I}

V_{IVCC_TH_D}

t

V_DC/PWMI1,2

t_ST

V_{DC/PWMI1,2(ON)}

V_SWO1,2

t_SS

Gate drivers

disabled

Gate driver

disabled

Gate drivers disabled

Gate drivers enabled

t

V_FPWM1,2

Soft start routine

V_{FPWM/FAULT1,2}

Timing diagram of linear regulator on TLD6098-2ES.vsdx

Figure 8

Thresholds and timing diagram related to the linear regulator

5.2

Electrical characteristics

Table 6

Electrical characteristics

V_IN= 8 V to 36 V; T_J= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin;

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or condition

P-

Number

Min.

4.85

Max.

5.15

IVCC output voltage

V_IVCC

I_IVCC

5

V

8 V ≤ V_IN≤ 36 V; 0.1 mA PRQ-58

≤ I_IVCC≤ 40 mA

IVCC output current

limit

51

–

100

mA

8 V < V_IN< 13.5 V; V_IVCCPRQ-59

< 4.5 V; Current flows

out of pin

IVCC dropout voltage

IVCC start time

V_{IVCC_DV}

t_ST

–

0.5

V

V_IN= 5 V; I_IVCC< 20 mA PRQ-60

1)

300

μs

PRQ-285

V_INslew rate higher

than 1 V/10 μs

1)

IVCC buﬀer capacitor

C_IVCC

1

4.7

10

μF

PRQ-61

If embedded PWM

engine is used, 4.7 μF

has to be chosen as a

minimum

(table continues...)

Datasheet

20

Rev.1.10

2021-09-30

LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

5 Linear regulator

Table 6

(continued) Electrical characteristics

V_IN= 8 V to 36 V; T_J= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin;

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or condition

P-

Number

Min.

Max.

0.2

1)

IVCC buﬀer capacitor

R_IVCC(ESR)

–

Ω

PRQ-62

ESR

Maximum value given

for regulator stability

IVCC undervoltage

switch-oﬀ threshold

V_{IVCC_TH_D}

V_{IVCC_TH_I}

3.6

–

4.0

4.5

V

V_IVCCdecreasing

PRQ-64

PRQ-65

IVCC undervoltage

switch-on threshold

V_IVCCincreasing

1) Not subject to production test, specified by design

Attention: Select external switching MOSFET with worst case threshold voltage V_GS(th)lower than minimum

V_{IVCC_TH_D}

Datasheet

21

Rev.1.10

2021-09-30

LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

6 Switching frequency setup and synchronization

6

Switching frequency setup and synchronization

The DC-DC switching frequency is adjusted by a resistor placed from FREQ/SYNC/SPREAD pin to ground or by

providing to this pin a digital clock. The device incorporates also a spread spectrum modulator to reduce the

design eﬀort to fulfill the EMI compliance.

By using a resistor, the switching frequency of the regulator is adjusted in the switching frequency adjustment

range f_SWO

.

If an external clock is provided, the device accepts a digital clock in these two working windows:

•

Synchronization low frequency capture range f_{FREQ/SYNC/SPREAD(LF)}(low frequency synchronization mode)

Synchronization high frequency capture range f_{FREQ/SYNC/SPREAD(HF)}(high frequency synchronization mode)

Outside these ranges, the device does not recognize a valid clock and then the behavior of the regulator can be

out of specification.

TLD6098-2ES

Spread spectrum

modulator

Clock generator

FREQ/SYNC/SPREAD

SWO1

SWO2

DC/DC

switching

regulator

Gate

driver

Multiplexer

Clock frequency

detector

Oscillator and synchronization block inside TLD6098-2.vsdx

Figure 9

Diagram of switching frequency adjustment and synchronization blocks

To limit the input current spikes and then to relax the input filter requirements, SWO2 is in phase opposition

to SWO1.

This means SWO2 is activated with a 1/(2*f_SWO) delay respect to SWO1.

6.1

Switching frequency setup with external resistor

The resistor placed on FREQ/SYNC/SPREAD pin adjusts the frequency of the DC-DC and enables or disables the

spread spectrum modulator.

The relationship between the biasing resistor and switching frequency with spread spectrum activated is

1

f_SW

=

(1)

1 . 11 · 10⁻⁹· R_{FREQ/SYNC/SPREAD}

The relationship between the biasing resistor and the switching frequency with the spread spectrum not active

is

1

f_SW

=

(2)

1 . 11 · 10⁻¹⁰· R_{FREQ/SYNC/SPREAD}

Datasheet

22

Rev.1.10

2021-09-30

LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

6 Switching frequency setup and synchronization

Figure 10

Switching frequency versus R_{FREQ/SYNC/SPREAD}

6.1.1

Electrical characteristics

Table 7

Electrical characteristics

V_IN= 8 V to 36 V; T_J= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin;

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or condition

P-

Number

Min.

288

Max.

378

Switching frequency

f_{SWO_SSM(OFF)}

333

kHz

mA

R_{FREQ/SYNC/SPREAD}

27 kΩ

=

PRQ-277

FREQ/SYNC/SPREAD

output current

I_FREQ/SYNC/

SPREAD

–

3

V_{FREQ/SYNC/SPREAD}= 0 V PRQ-86

Current flowing out of

FREQ/SYNC/SPREAD

output voltage

V_FREQ/SYNC/

SPREAD_SSM(OFF)

0.72

0.8

0.88

V

R_{FREQ/SYNC/SPREAD}

27 kΩ

=

PRQ-87

6.1.2

Spread Spectrum

The spread spectrum modulation technique significantly reduces the electromagnetic harmonics

emission at the lower frequency range of the spectrum (f < 30 MHz).

This technique is enabled by changing the switching frequency over the time. The final result is the movement

over a broad band of the energy associated with the peaks of the electromagnetic harmonics emission.

The switching frequency is modulated with a triangular shape digitalized in 7 steps equally distributed over the

entire frequency span (2 times the frequency deviation f_DEV).

Datasheet

23

Rev.1.10

2021-09-30

LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

6 Switching frequency setup and synchronization

f_SWO

f_DEV

f_{SW_SSM(ON)}

f_DEV

t

1/f_FM

Spread spectrum modulator characteristic.vsdx

Figure 11

Spread spectrum modulator characteristic

6.1.2.1

Electrical characteristics

Table 8

Electrical characteristics

V_IN= 8 V to 36 V; T_J= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin;

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or condition

P-

Number

Min.

288

Max.

378

1)

Average switching

frequency

f_{SWO_SSM(ON)}

333

kHz

PRQ-84

PRQ-88

PRQ-89

PRQ-385

R_{FREQ/SYNC/SPREAD}

=

2.7 kΩ

1)

Modulation frequency f_FM

13.5

15

16.5

–

kHz

V

1.8 kΩ ≤ R_FREQ/SYNC/

_SPREAD≤ 9 kΩ

1)

Frequency deviation

f_DEV

0.09*f_S0.15*f_S

WO

1.8 kΩ ≤ R_FREQ/SYNC/

_SPREAD≤ 9 kΩ

FREQ/SYNC/SPREAD

output voltage

V_FREQ/SYNC/

SPREAD_SSM(ON)

0.72

0.8

0.88

R_{FREQ/SYNC/SPREAD}=

2.7 kΩ

1) Not subject to production test, specified by design

Datasheet

24

Rev.1.10

2021-09-30

LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

6 Switching frequency setup and synchronization

6.2

Synchronization with external clock (low frequency mode)

The switching frequency is synchronized with an external clock source applied on FREQ/SYNC/SPREAD pin if the

frequency is in the synchronization low frequency capture range f_{FREQ/SYNC/SPREAD(LF)}and the duty cycle is in the

synchronization input duty cycle range DC_{FREQ/SYNC/SPREAD}

.

The device detects the external clock source if the voltage on FREQ/SYNC/SPREAD exceeds the two thresholds:

•

The synchronization input high voltage V_{FREQ/SYNC/SPREAD(H)}during the positive pulse,

The synchronization input low voltage V_{FREQ/SYNC/SPREAD(L)}during the negative pulse.

V_{FREQ/SYNC/SPREAD}

t

_{FREQ/SYNC/SPREAD}= 1 / f_{FREQ/SYNC/SPREAD}

t_{FREQ/SYNC/SPREAD(H)}

t_{FREQ/SYNC/SPREAD(ON)}

t_{FREQ/SYNC/SPREAD}

DC_SWO

=

V_{FREQ/SYNC/SPREAD(H)}

V_{FREQ/SYNC/SPREAD(L)}

t

Timing diagram in synchronization mode.vsdx

Figure 12

Timing diagram when synchronization mode is enabled

6.2.1

Electrical characteristics

Table 9

Electrical characteristics

V_IN= 8 V to 36 V; T_J= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin;

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or condition

P-

Number

Min.

3.0

Max.

Synchronization input V_FREQ/SYNC/

high voltage

–

V

–

PRQ-91

PRQ-92

PRQ-94

SPREAD(H)

Synchronization input V_FREQ/SYNC/

low voltage

–

0.8

60

V

–

SPREAD(L)

1)

Synchronization input DC_FREQ/SYNC/

40

%

duty cycle range

SPREAD

1) Not subject to production test, specified by design

6.3

Synchronization with external clock (high frequency range)

High switching frequency enables a system cost down due to reduced value for the reactive components.

The high frequency synchronization is enabled if the input clock is in the synchronization high frequency

capture range f_{FREQ/SYNC/SPREAD(HF).}

Voltage threshold levels on FREQ/SYNC/SPREAD pin are the same as in the low frequency synchronization

mode.

Datasheet

25

Rev.1.10

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LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

7 Analog output adjustment

7

Analog output adjustment

Each channel can adjusts the reference voltage V_REF1,2across FBH1,2 and FBL1,2 pins (thus adjusting the output

currents) by monitoring the analog voltage on the respective SET1,2 pin (V_SET1,2).

The analog output adjustment acts independently channel by channel without any relations between the

channels.

The SWO1,2 NMOS gate driver is disabled If the voltage applied on the SET1,2 pin is lower than SET input

voltage no switching activity V_{SET1,2(NOSW).}

The SET1,2 pin has to be connected to a voltage higher than V_SET1,2(100%)(e.g. connecting SET1,2 pin to IVCC pin)

to exclude the output current adjustment feature.

The voltage on SET1,2 pins influences the voltage reference of the corresponding channel following the

behavior of showed in the picture below.

V

_FBH1,2-V_FBL1,2

V_REF1,2(100%)

V_REF1,2(40%)

V_{REF1,2(OFFSET)}

V_SET1,2(NOSW)V_SET1,2(0%)

V_SET1,2(40%)

_1,2− 0.1 V

V_SET1,2(100%)

V_SET1,2

Gate

driver

V

SET

0%

100%

dimming

V_REF

=

1,2

dimming

disabled

14

Analog dimming with TLD6098-2ES.vsdx

Figure 13

Relationship between V_SET1,2and the respective voltage V_REF1,2

The SET pin can also be wired to an external thermistor (usually mounted on the LED module) to perform a

thermal protection.

7.1

Electrical characteristics

Table 10

Electrical characteristics

V_IN= 8 V to 36 V; T_J= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin;

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

2.2

Unit Note or condition

P-

Number

Min.

Max.

1)

SET1 SET2 input

voltage 100%

V_SET1,2(100%)

V_SET1,2(40%)

V_SET1,2(0%)

–

V

PRQ-596

PRQ-599

PRQ-598

1)

SET1 SET2 input

voltage 40%

940

100

mV

1)

SET1 SET2 input

voltage 0%

mV

(table continues...)

Datasheet

26

Rev.1.10

2021-09-30

LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

7 Analog output adjustment

Table 10

(continued) Electrical characteristics

V_IN= 8 V to 36 V; T_J= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin;

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or condition

P-

Number

Min.

Max.

50

SET1 SET2 input

voltage no switching

activity

V_SET1,2(NOSW)

–

mV

–

PRQ-597

1) Not subject to production test, specified by design

Datasheet

27

Rev.1.10

2021-09-30

LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

8 Dimming functions

8

Dimming functions

The TLD6098-2ES oﬀers two dimming inputs (one for each channel) for pulse width modulating (PWM) the

output current.

This modulation is beneficial to reduce the average current at output (and then the brightness of the LEDs),

without showing color shiꢀ on the light produced by the LEDs.

The output current modulation is operated by the channel as function of the signal on DC/PWMI1,2 pins:

•

A digital clock signal imposes the duty cycle and the frequency

An analog voltage is translated to a duty cycle and the frequency is adjusted with a resistor on FPWM/

FAULT1,2 pin.

These features are present on both channels and they act independently channel by channel without any

relations between channels.

For each channel, diﬀerent voltage levels on DC/PWMI1,2 pins activates diﬀerent functions on the respective

channel, as described below:

•

If the voltage is higher than DC/PWMI1,2 input voltage high threshold V_DC/PWMI(ON)the dimming duty cycle is

set to 100%

If the voltage is in between the two digital thresholds (V_{DC/PWMI(100%)}and V_DC/PWMI(0%)), the embedded PWM

dimming function is activated

If the voltage is lower than DC/PWMI1,2 input voltage low threshold V_DC/PWMI(OFF)the dimming duty cycle is

0%

When a dimming function is activated, the PWM signal controls the switching regulator gate driver and the

PMOS gate driver of the respective channel where the dimming function is applied.

To allow fast transitions of the dimming PMOS even at low output voltage, the positive power supply of the

PWMO1,2 gate driver is connected to FBH1,2 pin if its voltage V_FBH1,2is higher than V_IVCC, otherwise the gate

driver is supplied by the IVCC pin.

During the ON state of the PWM dimming of each channel, the respective PMOS is biased with a PWMO output

voltage ON state V_PWMO1,2,ON(minimum V_PWMO1,2,ONcannot go below 0 V).

8.1

Electrical characteristics

Table 11

Electrical characteristics

V_IN= 8 V to 36 V; T_J= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin;

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or condition

P-

Number

Min.

Max.

1)

PWMO1, PWMO2 peak I_PWMO1,2

2

5

–

mA

PRQ-199

output current

V_FBH1,2= 14 V

V_PWMO1,2increasing

V_PWMO1,2(ON)+ 0.5 V to

V_PWMO1,2(ON)+ 3.5 V

C_L,PWMO1,2= 3.3 nF

Current flows out of

(table continues...)

Datasheet

28

Rev.1.10

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LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

8 Dimming functions

Table 11

(continued) Electrical characteristics

V_IN= 8 V to 36 V; T_J= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin;

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or condition

P-

Number

Min.

Max.

1)

PWMO1 PWMO2 peak I_PWMO1,2

2

5

–

mA

PRQ-200

output current

V_FBH1,2= 14 V

V_PWMO1,2

decreasing V_PWMO1,2(OF

_F)- 0.5 V to

V_PWMO1,2(OFF)- 3.5 V

C_L,PWMO1,2= 3.3 nF

1)

PWMO1 PWMO2 gate

drivers output rise time

t_{R_PWMO1,2}

–

2

6

μs

PRQ-201

PRQ-202

V_FBH1,2= 14 V

V_PWMO1,2increasing

V_PWMO1,2(ON)+ 0.5 V to

V_PWMO1,2(ON)+ 3.5 V

C_L,PWMO1,2= 3.3 nF

1)

PWMO1 PWMO2 gate

drivers output fall time

t_{F_PWMO1,2}

μs

V_FBH1,2= 14 V

V_PWMO1,2decreasing

V_PWMO1,2(OFF)- 0.5 V to

V_PWMO1,2(OFF)- 3.5 V

C_PWMO1,2= 3.3 nF

1)

PWMO1 PWMO2 output V_PWMO1,2(ON)

voltage ON state

–

V_FBH1,2V_FBH- 5 V

- 6.5

PRQ-203

PRQ-204

V_FBH1,2> 7.5

1)

PWMO1 PWMO2 output V_PWMO1,2(OFF)

V_FBH1,2

–

V

voltage OFF state

V_FBH1,2= 14 V

1) Not subject to production test, specified by design

8.2

Digital PWM dimming

Each channel of the TLD6098-2ES has a dedicated input pin to modulate the average current in a LED string

with a digital pattern.

Each channel recognizes a digital PWM dimming signal on DC/PWMI1,2 pin if:

•

The minimum voltage on DC/PWMI1,2 pin is lower than V_{DC/PWMI1,2(OFF)}

The maximum voltage on DC/PWMI1,2 pin is higher than V_{DC/PWMI1,2(ON)}

The maximum frequency on DC/PWMI1,2 is less than 1 kHz

No faults are detected

If a valid pattern is recognized and the V_DC/PWMIis higher than V_DC/PWMI(ON)the NMOS gate driver is enabled and

the voltage of PWMO pin is V_PWMO(ON); else the NMOS gate driver is disabled and the voltage of PWMO pin is

V_PWMO(OFF)

Datasheet

29

Rev.1.10

2021-09-30

LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

8 Dimming functions

8.2.1

Electrical characteristics

Table 12

Electrical Characteristics

V_IN= 8 V to 36 V; T_J= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin;

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or condition

P-

Number

Min.

Max.

DC/PWMI1, DC/PWMI2 V_{DC/PWMI1,2(ON)}4.0

input voltage high

threshold

–

V

–

PRQ-205

PRQ-206

DC/PWMI1, DC/PWMI2 V_{DC/PWMI1,2(OFF)}

input voltage low

–

0.8

threshold

DC/PWMI1 DC/PWMI2 I_DC/PWMI1,2

input current

–

6

–

200

1

μA

μs

V_DC/PWMI1,2= V_IN

V_DC/PWMI1,2= 0.8 V

–

PRQ-207

PRQ-208

PRQ-209

DC/PWMI1 DC/PWMI2 I_DC/PWMI1,2

input current

DC/PWMI1 DC/PWMI2 t_{DC/PWMI1,2(ON)}

–

minimum ON time

8.3

Embedded PWM engine

The embedded PWM engine helps to reduce the color shiꢀ when a LED string is dimmed down without using

timer or microcontroller. It generates a pulse width modulation (PWM) adjustable in frequency and duty cycle. A

possible application is the daytime running light dimmed down to position light without using microcontroller

or timer.

For each channel the embedded PWM dimming function is enabled if the voltage on DC/PWMI pin is in between

DC/PWMI input voltage 0% dimming V_{DC/PWM1,2(0%)}and DC/PWMI input voltage 100% dimming V_{DC/PWMI1,2(100%).}

This voltage is translated in the duty cycle of the PWM signal with DC/PWMI duty cycle resolution n_DC/PWMI

.

DC_PWMO1,2

100%

0%

V_{DC/PWMI1,2(OFF)}

V_{DC,PWMI1,2(0%)}

V_{DC/PWMI1,2(100%)}

V_DC/PWMI(ON)

V_DC/PWMI1,2

Digital dimming

_PWMO1,2= V_PWMO1,2(OFF)

Digital dimming

_PWMO1,2= V_PWMO1,2(ON)

Embedded PWM engine working window

V

Duty cycle vs PWMIn voltage.vsdx

Figure 14

Relationship between V_DC/PWMI1,2and dimming duty cycle

Datasheet

30

Rev.1.10

2021-09-30

LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

8 Dimming functions

If the embedded PWM dimming function is enabled the behavior of PWMO1,2 pin is the following:

•

The PWMO1,2 voltage switches between PWMO1,2 output voltage ON state V_PWMO1,2(ON)and PWMO1,2

output voltage OFF state V_PWMO1,2(OFF)

•

The PWMO1,2 switching frequency depends on the resistor value placed on FPWM/FAULT1,2 pin

The PWM duty cycle is linearly adjusted with the voltage on DC/PWMI1,2 pin

Any fault disables the embedded PWM engine and forces the voltage on PWMO1,2 pin to V_PWMO1,2(OFF)

.

The resistor connected on FPWM/FAULT1,2 is used to:

•

Adjust the frequency of the embedded PWM engine

Enables two diﬀerent reactions on FPWM/FAULT1,2 pin during the fault report

Enable or disable the voltage control loop on the respective channel

If the resistor on FPWM/FAULT1,2 pin is in FPWM/FAULT high resistor range R_{FPWM/FAULT(H)}the channel has the

following behavior:

•

The frequency of PWM engine is adjusted in f_PWMOrange

In case a fault is detected, it is reported on FPWM/FAULT1,2 pin with proper duty cycle

The voltage loop is disabled and the overvoltage is detected with a comparator (detailed information are

described in Protection and fault management section)

while, if resistor on FPWM/FAULT1,2 pin is in FPWM/FAULT low resistor range R_{FPWM/FAULT(L)}

:

•

The frequency of PWM engine is adjusted in f_PWMOrange

The faults are reported on FPWM/FAULT1,2 pin without a specific indication

Voltage regulation loop is enabled and concurrent to current regulation loop

The frequency of embedded PWM generator can be calculated by:

1

f_{PWMO_HR}

=

(3)

(4)

7 . 4 · 10⁻⁸· R_FPWM/FAULT

for resistor R_{FPWM/FAULT(H)}range

1

f_{PWMO_LR}

7 . 4 · 10⁻⁷· R_FPWM/FAULT

for resistor R_{FPWM/FAULT(L)}range.

Datasheet

31

Rev.1.10

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LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

8 Dimming functions

Figure 15

Relationship between R_FPWM/FAULTand the frequency of PWMO

The table below summarizes the diﬀerences between two resistor sets on FPWM/FAULT pin

Table 13

Resistor diﬀerences on fault pin

R_{FPWM/FAULT(H)}

R_{FPWM/FAULT(L)}

Fault report

Each fault reported with a dedicated duty The faults are reported by raising the

cycle on the respective FPWM/FAULT1,2

Disabled

voltage on the respective FPWM/FAULT1,2

pin until the faulty status is removed

Voltage loop

Enabled

Datasheet

32

Rev.1.10

2021-09-30

LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

8 Dimming functions

8.3.1

Electrical characteristics

Table 14

Electrical characteristics

V_IN= 8 V to 36 V; T_J= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin;

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or condition

P-

Number

Min.

V_{DC/PWMI1,2(0%)}0.965

Max.

DCPWMI1 DC/PWMI2

input voltage 0%

dimming

1

1.035

V

V_IVCC= 5 V

PRQ-211

PRQ-212

PRQ-434

DC/PWMI1 DC/PWMI2 V_DC/

input voltage 100%

dimming

3.53

1.5

3.6

2.5

3.67

3.5

V

PWMI1,2(100%)

DC/PWMI1 DC/PWMI2 R_DC/PWMI1,2

equivalent pull down

resistor

MΩ

V_DC/PWMI1,2= 4 V

1)

PWMO duty cycle

DC_PWMO

8

10

12

%

V

V_PWMI= 1.26 V

V_IVCC= 5 V

PRQ-112

PRQ-214

FPWM/FAULT1, FPWM/ V_FPWM/

0.72

0.80

0.88

–

FAULT2 reference

FAULT1,2(REF)

voltage

FPWM/FAULT1, FPWM/ I_{FPWM/FAULT1,2}

–

3

mA

V_FPWM1,2= 0 V

PRQ-215

FAULT2 output current

PWMO1, PWMO2

dimming frequency

f_PWMO1,2

n_DC/PWMI

315

–

345

10

–

375

–

Hz

bit

kΩ

R_FPWM1,2= 3.92 kΩ

PRQ-216

PRQ-374

PRQ-313

PRQ-590

PRQ-591

PWMO1, PWMO2

dimming frequency

R_{FPWM/FAULT1,2}=

39.2 kΩ

1)

DC/PWMI duty cycle

resolution

FPWM/FAULT high

range resistor

R_{FPWM/FAULT(H)}18

90

9

FPWM/FAULT low range R_{FPWM/FAULT(L)}1.8

–

resistor

1) Not subject to production test, specified by design

Datasheet

33

Rev.1.10

2021-09-30

LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

9 Protections and fault management

9

Protections and fault management

The fault conditions are identified by checking the status of PWMO1,2, IVCC and FPWM/FAULT1,2 pins. The

faults on the two channels are independently managed and reported.

Each channel of the device disables the gate drivers and reports fault on its FPWM/FAULT1,2 pin if it detects:

•

Short to ground

Overvoltage on VFB1,2 pin

Overtemperature

Overvoltage on FBH1,2 pin

Overcurrent

The faults are reported by raising the voltage on the respective FPWM/FAULT1,2 pin to V_{FPWM/FAULT1,2(FAULT)}

.

The output waveform of the fault reporting depends on the resistor connected to FPWM/FAULT1,2 pin.

The status of FPWM/FAULT1,2 pin can be monitored by a microcontroller. In this case a series resistor (10 kΩ

minimum) has to be used between FPWM/FAULT1,2 and the input pin of the microcontroller.

The PWMO1,2 gate driver biases the respective PMOS in OFF state to disconnect the load from the DC-DC output

during:

•

Overvoltage on VFB1,2 pin,

Overvoltage on FBH1,2 pin

Overtemperature

Overcurrent

During a short to ground, the PMOS is biased in OFF state during the t_S2Gand it is biased in ON state every

t_FAULTfor a (t_SS) to detect if the fault has been removed.

9.1

Electrical characteristics

Table 15

Electrical characteristics

V_IN= 8 V to 36 V; T_J= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin;

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or condition

P-

Number

Min.

Max.

1)

FPWM/FAULT1,2 output V_FPWM/

4

9

–

V

PRQ-609

PRQ-133

voltage with fault

FAULT1,2(FAULT)

1)

Fault period

t_FAULT

10

11

ms

1) Not subject to production test, specify by design

9.2

Short to ground

The short to ground detection feature protects each channel from an excess of current during a short circuit.

Each channel detects this fault if the voltage of VFB1,2 pin is lower than short to ground voltage

threshold V_{FB1,2_S2G}for a time longer than short to ground reaction time t_{S2G_RT}. Aꢀer a fault time with short

to ground t_S2Ga soꢀ start routine is triggered. The fault is released if the voltage on VFB1,2 pin is higher than

(V_{FB1,2_S2G}+V_{FB1,2_S2G_HYST}) at the end of the soꢀ start

During soꢀ-start routine, the short to ground detection is disabled and the voltage of FPWM/FAULT1,2 pin is

kept at V_{FPWM/FAULT1,2(REF)}

The reaction to short to ground is:

1. The voltage on FPWM/FAULT1,2 pin is raised to V_{FPWM/FAULT1,2(FAULT)}for t_S2Gtime

.

Datasheet

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LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

9 Protections and fault management

2.

3.

Aꢀer a t_S2Gtime the soꢀ-start routine is performed

At the end of soꢀ-start routine, the check on the voltage V_VFB1,2is redone

If the fault is still present, the procedure is repeated, otherwise the channel restarts.

This routine is valid whatever resistor used on FPWM/FAULT pin.

V_VFB1,2

V_{VFB1,2_S2G_HYS}

V_{VFB1,2_S2G}

t

t_fault

t_S2G

t_fault

t_SS

t_fault

t_SS

V_PWM/FAULT1,2

t_SS

V_{FPWM/FAULT1,2(HIGH)}

V_{FPWM/FAULT1,2(REF)}

t

V_SWO1,2

Gate driver

disabled

Gate driver

disabled

Gate driver

disabled

Gate driver enabled

S2G - TLD6098-2ES.vsdx

Figure 16

Timing diagram during short to ground detection

A short to ground event simultaneous with an overcurrent event is detected once even the voltage on DC/

PWMI1,2 pin is lower than V_{DC/PWMI1,2(OFF)}

.

In all the other cases, the short to ground is not detected when the voltage on DC/PWMI1,2 pin is lower than

V_{DC/PWMI1,2(OFF)}

.

9.2.1

Electrical characteristics

Table 16

Electrical characteristics

V_IN= 8 V to 36 V; T_J= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin;

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or condition

P-

Number

Min.

7.2

Max.

8.8

1)

Fault time with short to t_S2G

ground

8

ms

PRQ-134

PRQ-121

PRQ-218

PRQ-219

Short to ground

reaction time

t_{S2G_RT}

4

–

20

μs

–

Short to ground

voltage threshold

V_{FB1,2_S2G}

93

–

100

5

107

10

mV

Voltage decreasing

1)

Short to ground

V_{FB1,2_S2G_HYST}

voltage hysteresis

1) Not subject to production test, specified by design

Datasheet

35

Rev.1.10

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LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

9 Protections and fault management

9.3

Output overvoltage and voltage regulation

Based on the resistor used on FPWM/FAULT1,2 pin the channel implements an overvoltage detection with a

comparator or enabling a voltage regulation by using the internal voltage loop.

If the resistor connected to FPWM/FAULT1,2 pin is in the R_{FPWM/FAULT(H)}range, the overvoltage comparator is

enabled with VFB1 VFB2 overvoltage threshold V_{VFB1,2_OV.}The fault is detected when the VFB voltage is above

this threshold.

The channel reacts by:

•

raising the respective V_{FPWM/FAULT1,2}to V_{FPWM/FAULT1,2(FAULT)}for a fault time with overvoltage t_OVFB

disabling the respective NMOS gate driver for t_FAULT

aꢀer t_FAULTthe voltage on VFB1,2 is rechecked and if it is still higher than (V_{VFB1,2_OV}-V_{VFB1,2_OV,HYS}) the routine is

repeated, else the device restarts with a soꢀ-start routine.

V_VFB1,2

V_{VFB1,2_OV}

V_{VFB1,2_OV_HIS}

t

V_{FPWM/FAULT1,2}

V_{FPWM/FAULT1,2(FAULT)}

V_{FPWM/FAULT1,2(REF)}

t

t_OVFB

V_SWO1,2

t_fault

Gate driver disabled

t_fault

Gate driver enabled

Gate driver disabled

Gate driver enabled

t

OVFB-HR TLD6098-2ES.vsdx

Figure 17

Timing diagram during overvoltage detection

The channel works as a voltage regulator with the voltage loop enabled if the resistor connected to FPWM/

FAULT1,2 pin is in the R_{FPWM/FAULT(L)}range.

The voltage loop is taking over the regulation when the voltage on VFB1,2 pin goes higher than V_{FB1,2_VM(ON)}. At

this time the voltage on FPWM/FAULT1,2 pin is raised to V_{FPWM/FAULT1,2(FAULT)}

.

The channel also reports when the voltage on VFB1,2 pin goes below V_{FB1,2_VM(OFF)}to highlight the voltage loop

is ineﬀective. In this condition the voltage on FPWM/FAULT pin is V_{FPWM/FAULT1,2(REF)}

The fault is detected even the voltage on DC/PWMI1,2 pin is lower than V_{DC/PWMI1,2(OFF)}

.

Datasheet

36

Rev.1.10

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LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

9 Protections and fault management

V_VFB1,2

V_{VFB1,2_REF}

V_{VFB1,2_VM(ON)}

V_{VFB1,2_VM(OFF)}

t

V_{FPWM/FAULT1,2}

V_{FPWM/FAULT1,2(FAULT)}

V_{FPWM/FAULT1,2(REF)}

V_SWO1,2

Gate driver enabled

t

OVFB-LR-TLD6098-2ES.vsdx

Figure 18

Timing diagram in voltage regulation

9.3.1

Electrical characteristics

Table 17

Electrical characteristics

V_IN= 8 V to 36 V; T_J= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin;

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or condition

P-

Number

Min.

Max.

VFB1, VFB2 overvoltage V_{VFB1,2_OV}

threshold

1.568 1.6

1.632

V

Voltage increasing

PRQ-217

PRQ-323

PRQ-221

1)

VFB overvoltage

hysteresis

V_{VFB_OV_HYS}

I_VFB1,2

180

-1

200

-0.1

220

1

mV

μA

VFB1, VFB2 input

current

V_FB1,2= 1.6 V

VFB1, VFB2 voltage

mode ON thresholds

V_{VFB1,2_VM(ON)}1.45

V_{VFB1,2_VM(OFF)}1.3

t_OVFB3.6

1.5

1.55

1.4

V

Voltage increasing

Voltage decreasing

1)

PRQ-408

PRQ-409

VFB1, VFB2 voltage

mode OFF threshold

1.35

Fault time with

overvoltage

4

4.4

ms

PRQ-135

1) Not subject to production test, specified by design

9.4

Overvoltage on FBH pin

The channels have a protection feature to prevent an excess voltage on FBH1,2 pin. The report of this fault

depends on the resistor connected to FPWM/FAULT1,2 pin.

Datasheet

37

Rev.1.10

2021-09-30

LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

9 Protections and fault management

An overvoltage on FBH1,2 pin fault is detected if the voltage V_FBH1,2is higher than FBH1,2 overvoltage high

threshold V_FBH1,2(H)and the fault is released when the voltage V_FB1,2is below the FBH overvoltage low threshold

V_FBH1,2(L)

.

With a resistor on FPWM/FAULT1,2 pin in R_{FPWM/FAULT(H)}range the channel reacts by:

•

Disabling the respective NMOS gate driver

Raising the voltage of FPWM/FAULT1,2 pin to V_{FPWM/FAULT1,2(FAULT)}for t_FBHtime

Aꢀer t_FAULTperiod, the device checks if V_FBH1,2is still higher than V_FBH1,2(L)

V_VFBH1,2

V_VFBH1,2(H)

V_VFBH1,2(L)

t

t_fault

t_FBH

t_fault

V_{FPWM/FAULT1,2}

V_{FPWM/FAULT1,2(FAULT)}

V_{FPWM/FAULT1,2(REF)}

t

V_SWOn

Gate driver enabled

Gate driver disabled

Gate driver enabled

OV_FBH_HRES_TLD6098-2ES.vsdx

Figure 19

Timing diagram during overvoltage on FBH1,2 detection with R_{FPWM/FAULT(H)}used on

FPWM/FAULT1,2 pin

With a resistor on FPWM/FAULT1,2 pin in R_{FPWM/FAULT(L)}range the channel reacts to the fault by:

•

Disabling the respective NMOS gate driver

Raising the voltage of respective FPWM/FAULTn pin to V_{FPWM/FAULT1,2(FAULT)}

Aꢀer t_FAULTperiod, the device checks if the voltage on FBH pin is still higher than V_FBH1,2(L)

Datasheet

38

Rev.1.10

2021-09-30

LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

9 Protections and fault management

V_VFBH1,2

V_VFBH1,2(H)

V_VFBH1,2(L)

t

t_FAULT

V_{FPWM/FAULT1,2n}

V_{FPWM/FAULT1,2(FAULT)}

V_{FPWM/FAULT1,2(REF)}

t

V_SWO1,2

Gate driver enabled

Gate driver disabled

Gate driver enabled

OV_FBH_LRES_TLD6098-2ES.vsdx

Figure 20

Timing diagram during overvoltage on FBH detection with R_{FPWM/FAULT(L)}used on

FPWM/FAULT1,2 pin

When the fault disappears, the channel restarts with soꢀ-start routine and lowers the voltage of FPWM/FAULT1,2

pin to V_{FPWM/FAULT1,2(REF)}

.

If the fault appears during the soꢀ-start routine, it interrupts the soꢀ-start for a t_FAULTtime and then the routine

restarts.

The fault is detected even when the voltage on DC/PWMI1,2 pin is lower than V_{DC/PWMI1,2(OFF)}

.

9.4.1

Electrical characteristics

Table 18

Electrical characteristics

V_IN= 8 V to 36 V; T_J= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin;

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or condition

P-

Number

Min.

70

Max.

75

FBH1 FBH2 overvoltage V_FBH1,2(H)

upper threshold

–

V

V_FBH1,2increasing

PRQ-414

PRQ-415

PRQ-329

FBH1 FBH2 overvoltage V_FBH1,2(L)

lower threshold

65

–

6

–

V

V_FBH1,2decreasing

1)

Fault time FBH

t_FBH

5.4

6.6

ms

1) Not subject to production test, specified by design

Datasheet

39

Rev.1.10

2021-09-30

LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

9 Protections and fault management

9.5

Output overcurrent

An output overcurrent event could damage the load if the current exceed the load specification. The output

overcurrent detection increases the system reliability by reducing the load average current.

The output overcurrent detection acts independently for each channel.

The output overcurrent is detected when voltage across FBH1,2 and FBL1,2 is higher than overcurrent detection

threshold V_{OC_200%}

.

The channel reacts in overcurrent detection time t_{OC_200%}by increasing the voltage of PWMO1,2 pin

to V_PWMO1,2(OFF)and disabling the respective NMOS gate driver.

The protection is released when the voltage across FBH1,2 and FBL1,2 drops below (V_{OC_200%}- V_{OC_HYS}). At

this time the NMOS gate driver is enabled again and the voltage of PWMO1,2 pin evolves as demanded by the

dimming features.

A continuously re-triggering of the protection could cause an overheating of the PMOS. Then a timer records

the period in which the channel is in over current state. The fault reporting depends on the resistor used on

FPWM/FAULT pin.

With a resistor on FPWM/FAULT1,2 pin in R_{FPWM/FAULT(H)}range, the channel reacts to an overcurrent by:

•

Entering into overcurrent state

Disables the NMOS gate driver and raises the voltage on PWMO1,2 pin to V_PWMO1,2(OFF)

As soon as (V_FBH1,2- V_FBL1,2) < (V_{OC_200%}- V_{OC_HYS}) the NMOS gate driver is enabled again

PWMO1,2 pin is again controlled by the dimming features

Exiting from the overcurrent state

When the cumulative time in which the channel is in overcurrent state reaches the overcurrent detection t_OCin

a time window of 8*t_FAULTthe channel:

•

Raises the voltage of FPWM/FAULT1,2 pin at V_{FPWM/FAULT1,2(FAULT)}for the overcurrent fault time t_FBH-FBLand

then releases it to V_{FPWM/FAULT1,2(REF)}for (t_FAULT- t_FBH-FBL

)

•

Repeats this sequence 8 times

V

_FBH1,2-V_FBL1,2

8*t_FAULTtime window

V_{OC_HYS}

V_{OC_200%}

V_REF

t

8*t_FAULT

+

t_FAULT

V_{FPWM/FAULT1,2}

t_FBH-FBL

Cumulative time > t_OC

V_{FPWM/FAULT1,2(FAULT)}

V_{FPWM/FAULT1,2(REF)}

t

V_PWMO1,2

V_PWMO1,2(OFF)

V_PWMO1,2(ON)

V_SWO1,2

Gate driver enebled

Gate driver disabled

Gate driver enabled

Overcurrent HRES with PMOS-TLD6098-2ES.vsdx

Figure 21

System behavior with R_{FPWM/FAULT(H)}during overcurrent detection with PMOS as

dimming/protection element

Datasheet

40

Rev.1.10

2021-09-30

LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

9 Protections and fault management

V

_FBH1,2-V_FBL1,2

V_{OC_200%}

V_REF

t

V_OUT1,2

V_IN

8*t_FAULT

t_FAULT

t_OCt_FBH-FBL

V_{FPWM/FAULT1,2}

V_{FPWM/FAULT1,2(FAULT)}

V_{FPWM/FAULT1,2(REF)}

t

V_SWO1,2

Gate driver enabled

Gate driver disabled

Gate driver enabled

Overcurrent HRES without PMOS-TLD6098-2ES.vsdx

Figure 22

System behavior with R_{FPWM/FAULT(H)}during overcurrent detection without PMOS as

dimming/protection element

With a resistor on FPWM/FAULT pin in R_{FPWM/FAULT(L)}range, the channel reacts to an overcurrent by:

•

Entering into the overcurrent state

Disabling the NMOS gate driver and raises the voltage on PWMO1,2 pin to V_PWMO1,2(OFF)

As soon as (V_FBH1,2- V_FBL1,2) < (V_{OC_200%}- V_{OC_HYS}) the NMOS gate driver is enabled again

PWMO1,2 pin is again controlled by the dimming feature

Exiting from the overcurrent state

When the cumulative time in which the device is in overcurrent state reaches t_OCin a time window of 8*t_FAULT

•

Raises the voltage of FPWM/FAULT1,2 pin at V_{FPWM/FAULT1,2(FAULT)}for a time 8*t_FAULTand then releases it

to V_{FPWM/FAULT1,2(REF)}

Datasheet

41

Rev.1.10

2021-09-30

LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

9 Protections and fault management

V

_FBH1-V_FBL2

8*t_FAULTtime window

V_{OC_HYS}

V_{OC_200%}

V_REF

t

8*t_FAULT

+

V_{FPWM/FAULT1,2}

Cumulative time > t_OC

V_{FPWM/FAULT1,2(FAULT)}

V_{FPWM/FAULT1,2(REF)}

t

V_PWMO1,2

V_PWMO1,2(OFF)

V_PWMO1,2(ON)

V_SWO1,2

Gate driver enebled

Gate driver disabled

Gate driver enabled

Overcurrent LRES with PMOS-TLD6098-2ES.vsdx

Figure 23

System behavior with R_{FPWM/FAULT(L)}during overcurrent detection with PMOS as

dimming/protection element

V

_FBH1,2-V_FBL1,2

V_{OC_200%}

V_REF

t

V_OUT1,2

V_IN

8*t_FAULT

V_{FPWM/FAULT1,2}

V_{FPWM/FAULT1,2(FAULT)}

V_{FPWM/FAULT1,2(REF)}

t_OC

t

V_SWO1,2

Gate driver enabled

Gate driver disabled

Gate driver enabled

Overcurrent LRES without PMOS-TLD6098-2ES.vsdx

Figure 24

System behavior with R_{FPWM/FAULT(L)}during overcurrent detection without PMOS as

dimming/protection element

During the overcurrent detection, the t_{S2G_RT}filter time is bypassed. In case of simultaneous short to ground

detection and overcurrent detection, the channel reacts to short to ground failure, cumulating the time in which

Datasheet

42

Rev.1.10

2021-09-30

LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

9 Protections and fault management

the channel is in overcurrent state. When the cumulated time reaches the t_OC, in a time window of 8*t_FAULT, the

overcurrent is detected.

The fault is detected even the voltage on DC/PWMI1,2 pin is lower than V_{DC/PWMI1,2(OFF)}

.

9.5.1

Electrical characteristics

Table 19

Electrical characteristics

V_IN= 8 V to 36 V; T_J= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin;

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or condition

P-

Number

Min.

280

Max.

Overcurrent detection V_{OC_200%}

threshold

300

–

mV

ms

V_FBH1,2-V_FBL1,2

increasing

PRQ-604

PRQ-532

PRQ-533

1)

Overcurrent detection V_{OC_HYS}

hysteresis

15

–

4

35

1)

Overcurrent detection t_OC

3.6

4.4

time

1)

Overcurrent fault time t_FBH-FBL

1.8

–

2

–

2.2

2

ms

μs

PRQ-555

PRQ-538

Reaction time during

overcurrent detection

t_{OC_200%}

1) Not subject to production test, specified by design

9.6

Overtemperature

Thermal shutdown is an internal feature designed to prevent the device destruction and it is not intended for

continuous use in normal operation.

If the junction temperature reaches the overtemperature shutdown T_J(SD), the integrated thermal shutdown

function turns oﬀ the gate drivers and internal linear voltage regulator.

The junction temperature is checked each t_FAULTperiod, and when it is cooled down to (T_J(SD)-T_{J(SD_HYS)}) the

device will automatically restart with a soꢀ-start.

The thermal shutdown operates on both the channels

Datasheet

43

Rev.1.10

2021-09-30

LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

9 Protections and fault management

T_J

T_J(SD)

T_{J(SD_HYS)}

t

V_{FPWM/FAULT1,2}

t_fault

V_{FPWM/FAULT1,2(FAULT)}

V_{FPWM/FAULT1,2(REF)}

t

V_IVCC

V_{IVCC_TH_I}

t

V_SWO1,2

Gate driver

enabled

Gate driver enabled

Gate driver disabled

Gate driver enabled

Gate driver disabled

t

Overtemperatue-TLD6098-2ES.vsdx

Figure 25

Timing diagram during overtemperature protection

9.6.1

Electrical characteristics

Table 20

Electrical characteristics

V_IN= 8 V to 36 V; T_J= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin;

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or condition

P-

Number

Min.

160

Max.

190

1)

Overtemperature

shutdown

T_J(SD)

175

°C

PRQ-336

PRQ-337

1)

Overtemperature

T_{J(SD_HYS)}

–

10

–

°C

shutdown hysteresis

1) Not subject to production test, specified by design

Datasheet

44

Rev.1.10

2021-09-30

LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

10 Application information

10

Application information

Note:

The following information is given as a hint for the implementation of the device only and shall not be

regarded as a description or warranty of a certain functionality, condition or quality of the device

V_S

L_1,2

D_1,2

R_FB1,2

M_P1,2

C_BO

LED_1-1,2

LED_2-1,2

IVCC

IN

M_1,2

SWO1,2

IVCC

C_IVCC

LED_3-1,2

LED_4-1,2

LED_5-1,2

LED_6-1,2

LED_7-1,2

LED_8-1,2

SWCS1,2

FPWM/FAULT1,2

R_SWCS1,2

R_FAULT1,2

FBH1,2

FBL1,2

FREQ/SYNC/SPREAD

R_FREQ

IVCC

R_SETH1,2

R_VFBH1,2

SET1,2

VFB1,2

IVCC

R_SETL1,2

R_VFBL1,2

R_DCH1,2

DC/PWMI1,2

COMP1,2

PWMO1,2

GND

R_DCL1,2

C_COMP1-1,2

R_COMP1,2

C_COMP2-1,2

TLD6098-2ES

B2G-2ch.vsdx

Figure 26

Boost to battery application schematic

Note:

The figure applies whether looking at a single channel or both channels. The channels are identical

and independent.

Datasheet

45

Rev.1.10

2021-09-30

LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

10 Application information

LED_4-1,2LED_3-1,2LED_2-1,2LED_1-1,2

C_BO2-1,2

V_S

L_1,2

D_1,2

R_FB1,2

C_BO1-1,2

M_P1,2

IVCC

IN

M_1,2

SWO1,2

IVCC

C_IVCC

SWCS1,2

FPWM/FAULT1,2

R_FAULT1,2

R_SWCS1,2

FREQ/SYNC/SPREAD

R_FREQ

IVCC

FBH1,2

FBL1,2

R_SETH1,2

R_VFBH1,2

SET1,2

IVCC

R_SETL1,2

VFB1,2

R_VFBL1,2

R_DCH1,2

DC/PWMI1,2

COMP1,2

R_DCL1,2

PWMO1,2

GND

C_COMP1-1,2

C_COMP2-1,2

R_COMP1,2

TLD6098-2ES

B2B-2ch.vsdx

Figure 27

Boost to battery application schematic

Note:

The figure applies whether looking at a single channel or both channels. The channels are identical

and independent.

Datasheet

46

Rev.1.10

2021-09-30

LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

10 Application information

V_S

C_SEPIC1,2

L_1-1,2

D_1,2

R_FB1,2

M_P1,2

C_BO

LED_1-1,2

LED_2-1,2

IVCC

IN

L_2-1,2

M_N1,2

SWO1,2

IVCC

C_IVCC

LED_3-1,2

LED_4-1,2

LED_5-1,2

LED_6-1,2

LED_7-1,2

LED_8-1,2

SWCS1,2

FPWM/FAULT1,2

R_FAULT1,2

R_SWCS1,2

FBH1,2

FREQ/SYNC/SPREAD

R_FREQ

IVCC

FBL1,2

R_SETH1,2

R_VFBH1,2

SET1,2

VFB1,2

IVCC

R_SETL1,2

R_VFBL1,2

R_DCH1,2

DC/PWMI1,2

COMP1,2

PWMO1,2

GND

R_DCL1,2

C_COMP1-1,2

R_COMP1,2

C_COMP2-1,2

TLD6098-2ES

SEPIC-2ch.vsdx

Figure 28

SEPIC application schematic

Note:

The figure applies whether looking at a single channel or both channels. The channels are identical

and independent.

V_S

C_1,2

L_1-1,2

L_2-1,2

C_BO

R_OVH1,2

LED_1-1,2

LED_2-1,2

IVCC

C_IVCC

D_1,2

IN

M_N1,2

SWO1,2

IVCC

Q_3-1,2

LED_3-1,2

LED_4-1,2

LED_5-1,2

LED_6-1,2

LED_7-1,2

LED_8-1,2

SWCS1,2

IVCC

R_CML1,2

R_CMR1,2

FPWM/FAULT1,2

R_SWCS1,2

R_FAULT1,2

Q_1-1,2

R_OVL1,2

Q_2-1,2

M_P1,2

VFB1,2

FREQ/SYNC/SPREAD

R_PWMO1-1,2

R_PWMO2-1,2

R_FREQ

IVCC

R_SETH1,2

PWMO1,2

FBL1,2

M_PWM1,2

SET1,2

IVCC

R_SETL1,2

R_FB1,2

R_DCH1,2

FBH1,2

GND

DC/PWMI1,2

COMP1,2

R_DCL1,2

C_COMP1-1,2

R_COMP1,2

C_COMP2-1,2

TLD6098-2ES

Cuk-2ch.vsdx

Figure 29

Cuk application schematic

Datasheet

47

Rev.1.10

2021-09-30

LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

10 Application information

Note:

The figure applies whether looking at a single channel or both channels. The channels are identical

and independent.

V_S

L_1,2

D_1,2

C_BO

IVCC

C_IVCC

IN

M_1,2

SWO1,2

IVCC

R_LOAD1,2

SWCS1,2

FPWM/FAULT1,2

R_SWCS1,2

R_FAULT1,2

R_VFBH1,2

FREQ/SYNC/SPREAD

R_FREQ

VFB1,2

IVCC

R_VFBL1,2

R_SET1,2

PWMO1,2

SET1,2

IVCC

FBH1,2

FBL1,2

R_ENABLE1,2

DC/PWMI1,2

COMP1,2

GND

C_COMP1-1,2

R_COMP1,2

C_COMP2-1,2

TLD6098-2ES

B2G_CV-2ch.vsdx

Figure 30

Constant output voltage boost to ground DC-DC application schematic

Note:

The figure applies whether looking at a single channel or both channels. The channels are identical

and independent.

Datasheet

48

Rev.1.10

2021-09-30

LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

11 Package

11

Package

Figure 31

Package dimensions PG-TSDSO-24

Note:

Green product (RoHS compliant) To meet the world-wide customer requirements for

environmentally friendly products and to be compliant with government regulations the device is

available as a green product. Green products are RoHS-Compliant (i.e. Pb-free finish on leads and

suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).

Further information on packages https://www.infineon.com/packages

Datasheet

49

Rev.1.10

2021-09-30

LITIX^™Power TLD6098-2ES

Multitopology dual-channel DC-DC controller

12 Revision history

12

Revision history

Document Date of

Description of changes

version

release

Rev.1.10

2021-09-30

•

Editorial changes

New application schematics

Rev.1.00

2021-04-16 Initial Datasheet

Datasheet

50

Rev.1.10

2021-09-30

Trademarks

All referenced product or service names and trademarks are the property of their respective owners.

Edition 2021-09-30

Published by

IMPORTANT NOTICE

WARNINGS

The information given in this document shall in no

event be regarded as a guarantee of conditions or

characteristics (“Beschaﬀenheitsgarantie”).

With respect to any examples, hints or any typical

values stated herein and/or any information regarding

the application of the product, Infineon Technologies

hereby disclaims any and all warranties and liabilities

of any kind, including without limitation warranties of

non-infringement of intellectual property rights of any

third party.

In addition, any information given in this document is

subject to customer’s compliance with its obligations

stated in this document and any applicable legal

requirements, norms and standards concerning

customer’s products and any use of the product of

Infineon Technologies in customer’s applications.

Due to technical requirements products may contain

dangerous substances. For information on the types

in question please contact your nearest Infineon

Technologies oﬀice.

Except as otherwise explicitly approved by Infineon

Technologies in

authorized representatives of Infineon Technologies,

Infineon Technologies’ products may not be used in

any applications where a failure of the product or

any consequences of the use thereof can reasonably

be expected to result in personal injury.

Infineon Technologies AG

81726 Munich, Germany

a written document signed by

©

2021 Infineon Technologies AG

Do you have a question about any

aspect of this document?

Email: erratum@infineon.com

Document reference

IFX-xem1632149255298

The data contained in this document is exclusively

intended for technically trained staﬀ. It is the

responsibility of customer’s technical departments to

evaluate the suitability of the product for the intended

application and the completeness of the product

information given in this document with respect to such

application.


型号：	TLD6098-2ES
厂家：	Infineon
描述：	LITIX™ Power TLD6098-2ES is a dual-channel DC-DC boost controller with spread spectrum frequency modulation and with built-in diagnosis and protection features specially designed for LED drivers.
文件：	总51页 (文件大小：1123K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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