Q67040-S4630 [INFINEON]
CoolMOS Power Transistor; 的CoolMOS功率晶体管
| 型号： | Q67040-S4630 |
| 厂家： | 
Infineon |
| 描述： | CoolMOS Power Transistor |
| 文件： | 总11页 (文件大小：411K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SPD06N60C3
CoolMOSTM Power Transistor
Features
Product Summary
DS @ T j,max
R DS(on),max
I D
V
650
0.75
6.2
V
Ω
A
• New revolutionary high voltage technology
• Ultra low gate charge
• Periodic avalanche rated
• High peak current capability
• Ultra low effective capacitances
• Extreme dv /dt rated
PG-TO252
• Improved transconductance
Type
Package
Ordering Code Marking
SPD06N60C3
PG-TO252
Q67040-S4630
06N60C3
Maximum ratings, at T j=25 °C, unless otherwise specified
Value
Parameter
Symbol Conditions
Unit
I D
T C=25 °C
T C=100 °C
T C=25 °C
6.2
3.9
Continuous drain current
A
Pulsed drain current1)
I D,pulse
E AS
E AR
I AR
18.6
200
0.5
I D=3.1 A, V DD=50 V
I D=6.2 A, V DD=50 V
Avalanche energy, single pulse
mJ
1),2)
1)
Avalanche energy, repetitive t AR
6.2
A
Avalanche current, repetitive t AR
Drain source voltage slope
Gate source voltage
I D=6.2 A, V DS=480 V,
T j=125 °C
50
dv /dt
V/ns
V
V GS
±20
±30
static
V GS
AC (f >1 Hz)
T C=25 °C
P tot
74
Power dissipation
W
T j, T stg
dv/dt
-55 ... 150
15
Operating and storage temperature
°C
7)
Reverse diode dv/dt
V/ns
Rev. 1.4
Page 1
2005-10-05
SPD06N60C3
Values
typ.
Parameter
Symbol Conditions
Unit
min.
max.
Thermal characteristics
R thJC
Thermal resistance, junction - case
-
-
-
-
1.7
75
K/W
SMD version, device
R thJA
on PCB, minimal
footprint
Thermal resistance, junction -
ambient
SMD version, device
on PCB, 6 cm2 cooling
area3)
-
-
50
-
-
1.6 mm (0.063 in.)
from case for 10 s
T sold
Soldering temperature *)
260 °C
Electrical characteristics, at T j=25 °C, unless otherwise specified
Static characteristics
V (BR)DSS
V (BR)DS
V
V
GS=0 V, I D=250 µA
GS=0 V, I D=6.2 A
Drain-source breakdown voltage
Avalanche breakdown voltage
600
-
-
-
-
V
700
V GS(th)
V
DS=V GS, I D=0.26 mA
Gate threshold voltage
2.1
-
3
3.9
1
V
DS=600 V, V GS=0 V,
I DSS
Zero gate voltage drain current
0.1
µA
T j=25 °C
V
DS=600 V, V GS=0 V,
-
-
-
-
-
100
T j=150 °C
I GSS
V
V
GS=20 V, V DS=0 V
GS=10 V, I D=3.9 A,
Gate-source leakage current
100 nA
R DS(on)
Drain-source on-state resistance
0.68
0.75
Ω
T j=25 °C
V
GS=10 V, I D=3.9 A,
-
-
-
1.82
1
-
-
-
T j=150 °C
R G
g fs
Gate resistance
f =1 MHz, open drain
|V DS|>2|I D|R DS(on)max
I D=3.9 A
,
Transconductance
5.6
S
*) reflow soldering, MSL3
Rev. 1.4
Page 2
2005-10-05
SPDT06N60C3
Values
typ.
Parameter
Symbol Conditions
Unit
min.
max.
Dynamic characteristics
Input capacitance
C iss
-
-
-
620
200
17
-
-
-
pF
V
GS=0 V, V DS=25 V,
C oss
C rss
Output capacitance
f =1 MHz
Reverse transfer capacitance
Effective output capacitance, energy
related4)
C o(er)
-
-
28
47
-
-
V
GS=0 V, V DS=0 V
to 480 V
Effective output capacitance, time
related5)
C o(tr)
t d(on)
t r
t d(off)
t f
Turn-on delay time
Rise time
-
-
-
-
7
-
-
-
-
ns
V
V
DD=480 V,
12
52
10
GS=10 V, I D=6.2 A,
Turn-off delay time
Fall time
R G=12 Ω
Gate Charge Characteristics
Gate to source charge
Gate to drain charge
Gate charge total
Q gs
-
-
-
-
3.3
12
-
-
nC
V
Q gd
V
V
DD=480 V, I D=6.2 A,
GS=0 to 10 V
Q g
24
31
-
V plateau
Gate plateau voltage
5.5
1) Pulse width limited by maximum temperature T j,max only
2) Repetitive avalanche causes additional power losses that can be calculated as P AV=E AR*f.
3) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain
connection. PCB is vertical in still air.
4) C o(er) is a fixed capacitance that gives the same stored energy as C oss while V DS is rising from 0 to 80% V DSS.
5) C o(tr) is a fixed capacitance that gives the same charging time as C oss while V DS is rising from 0 to 80% V DSS.
7)
I
<=I , di/dt<=400A/us, V
=400V, V
<V
, T <T
.
j,max
SD DClink
D
peak BR, DSS
j
Identical low-side and high-side switch.
Rev. 1.4
Page 3
2005-10-05
SPD06N60C3
Values
typ.
Parameter
Symbol Conditions
Unit
min.
max.
Reverse Diode
I S
Diode continuous forward current
Diode pulse current
-
-
-
-
6.2
A
V
T C=25 °C
I S,pulse
18.6
V
GS=0 V, I F=6.2 A,
V SD
Diode forward voltage
-
0.97
1.2
T j=25 °C
t rr
Reverse recovery time
-
-
-
400
3.5
25
-
-
-
ns
µC
A
V R=480 V, I F=I S,
di F/dt =100 A/µs
Q rr
I rrm
Reverse recovery charge
Peak reverse recovery current
Typical Transient Thermal Characteristics
Symbol
Value
Unit
Symbol
Value
Unit
typ.
typ.
R th1
R th2
R th3
R th4
R th5
0.0325
0.0448
0.251
0.31
K/W
C th1
C th2
C th3
C th4
C th5
C th6
0.0000502
0.000303
0.000428
0.00243
0.00344
Ws/K
0.231
0.1986)
6) C th6 models the additional heat capacitance of the package in case of non-ideal cooling. It is not needed if
thCA=0 K/W.
R
Rev. 1.4
Page 4
2005-10-05
SPD06N60C3
1 Power dissipation
2 Safe operating area
I D=f(V DS); T C=25 °C; D =0
parameter: t p
P tot=f(T C)
102
80
60
40
20
0
limited by on-state
resistance
1 µs
101
100
10 µs
100 µs
DC
1 ms
10 ms
10-1
10-2
100
101
102
103
0
40
80
120
160
T
C [°C]
V
DS [V]
3 Max. transient thermal impedance
I D=f(V DS); T j=25 °C
4 Typ. output characteristics
I D=f(V DS); T j=25 °C
parameter: D=t p/T
parameter: V GS
101
20
16
12
8
20 V
7 V
6.5 V
0.5
100
6 V
0.2
0.1
5.5 V
5 V
0.05
10-1
0.02
0.01
single pulse
4
4.5 V
4 V
10-2
0
10-6
10-5
10-4
10-3
10-2
10-1
100
0
5
10
15
20
V
DS [V]
t p [s]
Rev. 1.4
Page 5
2005-10-05
SPD06N60C3
5 Typ. output characteristics
I D=f(V DS); T j=150 °C
parameter: V GS
6 Typ. drain-source on-state resistance
DS(on)=f(I D); T j=150 °C
R
parameter: V GS
8
4
6 V
20 V
5.5 V
4 V
4.5 V
5 V
5.5 V
7 V
6.5 V
6
4
2
0
3
2
1
6 V
5 V
20 V
4.5 V
4 V
0
0
0
5
10
15
20
2
4
6
8
10
V
DS [V]
I
D [A]
7 Drain-source on-state resistance
8 Typ. transfer characteristics
I D=f(V GS); |V DS|>2|I D|R DS(on)max
parameter: T j
R
DS(on)=f(T j); I D=3.9 A; V GS=10 V
2
25
20
15
10
5
25 °C
1.6
1.2
98 %
0.8
typ
150 °C
0.4
0
0
-60
-20
20
60
100
140
180
0
2
4
6
8
10
T j [°C]
V GS [V]
Rev. 1.4
Page 6
2005-10-05
SPD06N60C3
9 Typ. gate charge
GS=f(Q gate); I D=6.2 A pulsed
10 Forward characteristics of reverse diode
I F=f(V SD
V
)
parameter: V DD
parameter: T j
102
12
10
8
25 °C
25 °C, 98%
120 V
480 V
150 °C, 98%
101
150 °C
6
4
100
2
10-1
0
0
0
0.5
1
1.5
SD [V]
2
2.5
10
20
30
Q
gate [nC]
V
11 Avalanche SOA
12 Avalanche energy
I
AR=f(t AR
)
E
AS=f(T j); I D=3.1 A; V DD=50 V
parameter: T j(start)
8
250
200
150
100
50
6
4
2
0
125 °C
25 °C
0
10-3
10-2
10-1
100
101
102
103
20
60
100
T j [°C]
140
180
t
AR [µs]
Rev. 1.4
Page 7
2005-10-05
SPD06N60C3
13 Drain-source breakdown voltage
14 Typ. capacitances
V
BR(DSS)=f(T j); I D=0.25 mA
C =f(V DS); V GS=0 V; f =1 MHz
104
700
103
660
620
580
540
Ciss
102
Coss
101
Crss
100
0
100
200
300
DS [V]
400
500
-60
-20
20
60
T j [°C]
100
140
180
V
15 Typ. C oss stored energy
E
oss= f(V DS)
5
4
3
2
1
0
0
100
200
300
400
500
600
V
DS [V]
Rev. 1.4
Page 8
2005-10-05
SPD06N60C3
Definition of diode switching characteristics
Rev. 1.4
Page 9
2005-10-05
SPD06N60C3
PG-TO252-3-1: Outline , PG-TO-252-3-11 (D-PAK), PG-TO-252-3-21 (D-PAK)
Rev. 1.4
Page 10
2005-10-05
SPD06N60C3
Published by
Infineon Technologies AG
81726 München
Germany
© Infineon Technologies AG 2006
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as
warranted characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement,
regarding circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices, please contact your
nearest Infineon Technologies office in Germany or our Infineon Technologies representatives worldwide
(see address list).
Warnings
Due to technical requirements, components may contain dangerous substances.
For information on the types in question, please contact your nearest Infineon Technologies office.
Infineon Technologies' components may only be used in life-support devices or systems with the
expressed written approval of Infineon Technologies if a failure of such components can reasonably
be expected to cause the failure of that life-support device or system, or to affect the safety or
effectiveness of that device or system. Life support devices or systems are intended to be implanted
in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail,
it is reasonable to assume that the health of the user or other persons may be endangered.
Rev. 1.4
Page 11
2005-10-05
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