PEB20256ME [INFINEON]
Multi Protocol Controller, CMOS, PBGA388;
| 型号： | PEB20256ME |
| 厂家： | 
Infineon |
| 描述： | Multi Protocol Controller, CMOS, PBGA388 外围集成电路 |
| 文件： | 总419页 (文件大小：4416K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICs for Communications
Multichannel Network Interface Controller for HDLC/PPP
with 256 Channels, 28 T1 or 21 E1 Framers, M13 Multiplexer and
T3 Framer
MUNICH256FM
PEB 20256M E Version 1.1
PEF 20256M E Version 1.1
Preliminary Data Sheet 11.99
•
PEB 20256M E
PEF 20256M E
Revision History:
Current Version: 11.99
Previous Version:
Page
(in previous (in current
Version) Version)
Page
Subjects (major changes since last revision)
For questions on technology, delivery and prices please contact the Infineon Technologies Offices
in Germany or the Infineon Technologies Companies and Representatives worldwide:
see our webpage at http://www.infineon.com
•
ABM®, AOP®, ARCOFI®, ARCOFI®-BA, ARCOFI®-SP, DigiTape®, EPIC®-1, EPIC®-S, ELIC®, FALC®54, FALC®56,
FALC®-E1, FALC®-LH, IDEC®, IOM®, IOM®-1, IOM®-2, IPAT®-2, ISAC®-P, ISAC®-S, ISAC®-S TE, ISAC®-P TE,
ITAC®, IWE®, MUSAC®-A, OCTAT®-P, QUAT®-S, SICAT®, SICOFI®, SICOFI®-2, SICOFI®-4, SICOFI®-4µC,
SLICOFI® are registered trademarks of Infineon Technologies AG.
ACE™, ASM™, ASP™, POTSWIRE™, QuadFALC™, SCOUT™ are trademarks of Infineon Technologies AG.
Edition 11.99
Published by Infineon Technologies AG,
SC,
Balanstraße 73,
81541 München
© Infineon Technologies AG 1999.
All Rights Reserved.
Attention please!
As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for
applications, processes and circuits implemented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies AG is an approved CECC manufacturer.
Packing
Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales
office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport.
For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice
you for any costs incurred.
Components used in life-support devices or systems must be expressly authorized for such purpose!
Critical components1 of the Infineon Technologies AG, may only be used in life-support devices or systems2 with
the express written approval of the Infineon Technologies AG.
1 A critical component is a component used in a life-support device or system whose failure can reasonably be
expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that
device or system.
2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or
maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be en-
dangered.
PEB 20256M E
PEF 20256M E
Preface
The Multichannel Network Interface Controller for HDLC is a Multichannel Protocol
Controller for a wide area of telecommunication and and data communication
applications.
Organization of this Document
This Preliminary Data Sheet is divided into ten chapters. It is organized as follows:
• Chapter 1, MUNICH256FM Overview
Gives a general description of the product, lists the key features, and presents some
typical applications.
• Chapter 2, Pin Description
Lists pin locations with associated signals, categorizes signals according to function,
and describes signals.
• Chapter 3, General Overview
This chapter provides short descriptions of all MUNICH256FM internal function
blocks.
• Chapter 4, Functional Description
Gives a detailed description about all functions supported by the MUNICH256FM.
• Chapter 5, Interface Description
This chapter provides functional diagrams of all interfaces.
• Chapter 6, Channel Programming / Reprogramming Concept
This chapter provides a detailed description of the channel programming concept.
• Chapter 7, Reset and Initialization procedure
Gives examples for MUNICH256FM initialization procedure and operation.
• Chapter 8, Register Description
Gives a detailed description about all MUNICH256FM on-chip registers.
• Chapter 9, Electrical Characteristics
Gives a detailed description of all electrical DC and AC characteristics and provides
timing diagrams and values for all interfaces.
• Chapter 10, Package Outline
Preliminary Data Sheet
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11.99
PEB 20256M E
PEF 20256M E
Preliminary Data Sheet
4
11.99
PEB 20256M E
PEF 20256M E
1
1.1
MUNICH256FM Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
General Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
M12 Multiplexer and DS2 Framer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
M23 Multiplexer and DS3 Framer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Frame Alignment T1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Signaling Controller T1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Frame Alignment E1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Signaling Controller E1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Bit Error Rate Tester . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
General System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.1.1
1.1.2
1.1.3
1.1.4
1.1.5
1.1.6
1.1.7
1.2
1.3
2
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
PCI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Local Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Test Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Power Supply, Reserved Pins and No-connect Pins . . . . . . . . . . . . . . . . . .39
2.1
2.2
2.3
2.4
2.5
2.6
3
General Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Internal Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
3.1
3.2
3.3
3.4
4
4.1
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Port Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Local Port Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Remote Line Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Test Breakout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Time slot Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Channelized Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Unchannelized Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Data Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Descriptor Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Receive Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Data Management Unit Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Transmit Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Data Management Unit Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Byte Swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Transmission Bit/Byte Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Buffer Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Internal Receive Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
4.1.1
4.1.2
4.1.3
4.2
4.2.1
4.2.2
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
4.4
4.4.1
Preliminary Data Sheet
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PEF 20256M E
4.4.2
4.5
4.5.1
4.5.2
4.5.3
4.5.4
4.6
4.6.1
Internal Transmit Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Protocol Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
HDLC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Bit Synchronous PPP with HDLC Framing Structure . . . . . . . . . . . . . . .72
Octet Synchronous PPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Transparent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
T1 Framer and FDL Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
4-Frame Multiframe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
ESF Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Multiframe Synchronization Procedure of the Receiver . . . . . . . . . . .76
CRC-6 Generation / Check according to ITU-T G.706 . . . . . . . . . . . .76
Remote Alarm (Yellow Alarm) Generation / Detection . . . . . . . . . . . .77
Facility Data Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
SF Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Synchronization Procedure of the Receiver . . . . . . . . . . . . . . . . . . . .80
Remote Alarm (Yellow Alarm) Generation / Detection . . . . . . . . . . . .81
Common Features for SF and ESF . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
AIS (Blue Alarm) Generation/Detection . . . . . . . . . . . . . . . . . . . . . . . .82
Loss of Signal (Red Alarm) Detection . . . . . . . . . . . . . . . . . . . . . . . . .82
In-Band Loop Generation and Detection . . . . . . . . . . . . . . . . . . . . . . .83
Pulse Density Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Error Performance Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Pseudo-random Bit Sequence Generator and Monitor . . . . . . . . . . . .84
E1 Framing and Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Doubleframe Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Synchronization Procedure of the Receiver . . . . . . . . . . . . . . . . . . . .86
A-bit Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Sa-bit Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
CRC-4 Multiframe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Synchronization Procedure of the Receiver . . . . . . . . . . . . . . . . . . . .89
CRC-4 Performance Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
A-Bit Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Sa-bit Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
E-Bit Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Common Features for E1 Doubleframe and CRC-4 Multiframe . . . . . . .94
Error Performance Monitoring and Alarm Handling . . . . . . . . . . . . . . .94
Loss of Signal Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
In-Band Loop Generation and Detection . . . . . . . . . . . . . . . . . . . . . . .96
Pseudo-random Bit Sequence Generator and Monitor . . . . . . . . . . . .96
Signaling Controller Protocol Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
HDLC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Transparent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
BOM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
4.6.2
4.6.2.1
4.6.2.2
4.6.2.3
4.6.2.4
4.6.3
4.6.3.1
4.6.3.2
4.6.4
4.6.4.1
4.6.4.2
4.6.4.3
4.6.4.4
4.6.4.5
4.6.4.6
4.7
4.7.1
4.7.1.1
4.7.1.2
4.7.1.3
4.7.2
4.7.2.1
4.7.2.2
4.7.2.3
4.7.2.4
4.7.2.5
4.7.3
4.7.3.1
4.7.3.2
4.7.3.3
4.7.3.4
4.8
4.8.1
4.8.2
4.8.3
Preliminary Data Sheet
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PEF 20256M E
4.8.4
4.8.5
4.9
4.9.1
Sa-bit Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Signalling Controller FIFO Operations . . . . . . . . . . . . . . . . . . . . . . . . . .101
M12 Multiplexer/Demultiplexer and DS2 framer . . . . . . . . . . . . . . . . . . . .105
M12 multiplex format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
Synchronization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Loopback Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Alarm Indication Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
ITU-T G.747 format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
Synchronization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
Parity Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Remote Alarm Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Alarm Indication Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
M23 multiplexer and DS3 framer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
M23 multiplex format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Synchronization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
X-bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
Alarm Indication Signal, Idle Signal . . . . . . . . . . . . . . . . . . . . . . . . . .112
Loss of Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
Performance Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
C-bit parity format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Synchronization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
X-bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
Far End Alarm and Control Channel . . . . . . . . . . . . . . . . . . . . . . . . .115
Path Maintenance Data Link Channel . . . . . . . . . . . . . . . . . . . . . . . .115
Loopback Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Alarm Indication Signal, Idle Signal . . . . . . . . . . . . . . . . . . . . . . . . . .115
Loss of Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Performance Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Full Payload Rate Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Test Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
Mailbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
Layer Two interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
General Interrupt Vector Structure . . . . . . . . . . . . . . . . . . . . . . . . . . .124
System Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
Port Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
Channel Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
Command Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
Layer One Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
4.9.1.1
4.9.1.2
4.9.1.3
4.9.1.4
4.9.2
4.9.2.1
4.9.2.2
4.9.2.3
4.9.2.4
4.9.2.5
4.10
4.10.1
4.10.1.1
4.10.1.2
4.10.1.3
4.10.1.4
4.10.1.5
4.10.1.6
4.10.2
4.10.2.1
4.10.2.2
4.10.2.3
4.10.2.4
4.10.2.5
4.10.2.6
4.10.2.7
4.10.2.8
4.10.2.9
4.10.3
4.11
4.12
4.13
4.13.1
4.13.1.1
4.13.1.2
4.13.1.3
4.13.1.4
4.13.1.5
4.13.2
Preliminary Data Sheet
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4.13.2.1
4.13.2.2
4.13.2.3
4.13.2.4
4.13.2.5
General Interrupt Vector Structure . . . . . . . . . . . . . . . . . . . . . . . . . .137
T1/E1 Framer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
Facility Data Link Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
DS3, DS2 and Test Unit Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .142
Mailbox Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
5
5.1
Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
PCI Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
PCI Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
SPI Interface (ROM Load Unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
Accesses to a SPI EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
SPI Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
SPI Write Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
Local Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
Intel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
Motorola Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
Serial Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
5.1.1
5.1.2
5.2
5.2.1
5.2.2
5.2.3
5.3
5.3.1
5.3.1.1
5.3.1.2
5.3.2
5.3.2.1
5.3.2.2
5.4
5.5
6
Channel Programming / Reprogramming Concept . . . . . . . . . . . . . . .162
Channel Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
Transmit Channel Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
Receive Channel Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
6.1
6.2
6.3
7
7.1
7.2
Reset and Initialization procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
Chip Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
Mode Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
8
8.1
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
PCI Configuration Register Set (Direct Access) . . . . . . . . . . . . . . . . . .170
PCI Slave Register Set (Direct Access) . . . . . . . . . . . . . . . . . . . . . . . .172
PCI and Local Bus Register Set (Direct Access) . . . . . . . . . . . . . . . . . .174
Transmit T1/E1 Framer Registers (Indirect Access) . . . . . . . . . . . . . . .179
Receive T1/E1 Framer Registers (Indirect Access) . . . . . . . . . . . . . . .180
Facility Data Link Registers (Indirect Access) . . . . . . . . . . . . . . . . . . . .181
Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
PCI Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
PCI Slave Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
PCI and Local Bus Slave Register Set . . . . . . . . . . . . . . . . . . . . . . . . .246
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
8.1.6
8.2
8.2.1
8.2.2
8.2.3
Preliminary Data Sheet
8
11.99
PEB 20256M E
PEF 20256M E
8.2.3.1
8.2.3.2
8.2.4
8.2.5
8.2.6
M13 Transmit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262
DS2 Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .292
Test Unit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307
Transmit Framer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325
Receive Framer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335
Facility Data Link Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .359
8.2.7
9
9.1
9.2
9.3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .388
Important Electrical Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .388
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .388
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .388
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .390
PCI Bus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .391
SPI Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393
Local Microprocessor Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . .394
Intel Bus Interface Timing (Slave Mode) . . . . . . . . . . . . . . . . . . . . . .394
Intel Bus Interface Timing (Master Mode) . . . . . . . . . . . . . . . . . . . . .396
Motorola Bus Interface Timing (Slave Mode) . . . . . . . . . . . . . . . . . .399
Motorola Bus Interface Timing (Master Mode) . . . . . . . . . . . . . . . . .401
Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .405
DS3 Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .405
Overhead Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .409
Stuff Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .411
T1/E1 Tributary Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .412
Test Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .414
JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .417
Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .418
9.4
9.4.1
9.4.2
9.4.3
9.4.3.1
9.4.3.2
9.4.3.3
9.4.3.4
9.4.4
9.4.4.1
9.4.4.2
9.4.4.3
9.4.4.4
9.4.4.5
9.4.5
9.4.6
10
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .419
Preliminary Data Sheet
9
11.99
PEB 20256M E
PEF 20256M E
Preliminary Data Sheet
10
11.99
PEB 20256M E
PEF 20256M E
Figure 1-1
Figure 1-2
Figure 3-1
Figure 4-1
Figure 4-2
Figure 4-3
Figure 4-4
Figure 4-5
Figure 4-6
Figure 4-7
Figure 4-8
Figure 4-9
MUNICH256FM Logic Symbol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
System Integration of the MUNICH256FM . . . . . . . . . . . . . . . . . . . . . .20
MUNICH256FM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Port configuration in M13 mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Local Port Loops in M13 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Remote Line Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Test Breakout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Time slot Assignment in Channelized Modes . . . . . . . . . . . . . . . . . . . .52
Descriptor Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Receive Buffer Thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Transmit Buffer Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
HDLC Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Figure 4-10 Bit Synchronous PPP with HDLC Framing Structure. . . . . . . . . . . . . . .72
Figure 4-11 CRC-4 Multiframe Alignment Recovery Algorithms . . . . . . . . . . . . . . . .91
Figure 4-12 Interrupt Driven Reception Sequence Example. . . . . . . . . . . . . . . . . .103
Figure 4-13 Interrupt Driven Transmit Sequence Example. . . . . . . . . . . . . . . . . . .104
Figure 4-14 Test Unit Access Points. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
Figure 4-15 Pattern Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
Figure 4-16 Mailbox Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
Figure 4-17 Layer Two Interrupts (Channel, command, port and system interrupts . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
Figure 4-18 Interrupt Queue Structure in System Memory . . . . . . . . . . . . . . . . . . .124
Figure 4-19 Framer, M13 and Facility Data Link and Mailbox Interrupt Notification136
Figure 5-1
Figure 5-2
Figure 5-3
Figure 5-4
Figure 5-5
Figure 5-6
Figure 5-7
Figure 5-8
Figure 5-9
PCI Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
PCI Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
SPI Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
SPI Write Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
Intel Bus Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
Intel Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
Motorola Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
Motorola Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
Receive Overhead Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
Figure 5-10 Transmit Overhead Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
Figure 5-11 Block Diagram of Test Access Port and Boundary Scan Unit . . . . . . .160
Figure 9-1
Figure 9-2
Figure 9-3
Figure 9-4
Figure 9-5
Figure 9-6
Figure 9-7
Figure 9-8
Figure 9-9
Input/Output Waveform for AC Tests. . . . . . . . . . . . . . . . . . . . . . . . . .390
PCI Clock Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .391
PCI Input Timing Measurement Conditions . . . . . . . . . . . . . . . . . . . . .391
PCI Output Timing Measurement Conditions . . . . . . . . . . . . . . . . . . .392
SPI Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393
Intel Read Cycle Timing (Slave Mode) . . . . . . . . . . . . . . . . . . . . . . . .394
Intel Write Cycle Timing (Slave Mode). . . . . . . . . . . . . . . . . . . . . . . . .394
Intel Read Cycle Timing (Master Mode, LRDY controlled) . . . . . . . . .396
Intel Write Cycle Timing (Master Mode, LRDY controlled). . . . . . . . . .396
Preliminary Data Sheet
11
11.99
PEB 20256M E
PEF 20256M E
Figure 9-10 Intel Read Cycle Timing (Master Mode, Wait state controlled) . . . . . .397
Figure 9-11 Intel Write Cycle Timing (Master Mode, Wait state controlled) . . . . . .397
Figure 9-12 Intel Bus Arbitration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .398
Figure 9-13 Motorola Read Cycle Timing (Slave Mode) . . . . . . . . . . . . . . . . . . . . .399
Figure 9-14 Motorola Write Cycle Timing (Slave Mode) . . . . . . . . . . . . . . . . . . . . .399
Figure 9-15 Motorola Read Cycle Timing (Master Mode, LDTACK controlled) . . .401
Figure 9-16 Motorola Write Cycle Timing (Master Mode, LDTACK controlled). . . .401
Figure 9-17 Motorola Read Cycle Timing (Master Mode, Wait state controlled). . .402
Figure 9-18 Motorola Write Cycle Timing (Master Mode, Wait state controlled). . .402
Figure 9-19 Motorola Bus Arbitration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .403
Figure 9-20 Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .405
Figure 9-21 DS3 Transmit Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .406
Figure 9-22 DS3 Transmit Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .406
Figure 9-23 DS3 Receive Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .407
Figure 9-24 DS3 Status Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .408
Figure 9-25 DS3 Transmit Overhead Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .409
Figure 9-26 DS3 Transmit Overhead Synchronization Timing . . . . . . . . . . . . . . . .409
Figure 9-27 DS3 Receive Overhead Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .410
Figure 9-28 DS3 Transmit Stuff Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .411
Figure 9-29 DS3 Receive Stuff Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .411
Figure 9-30 T1/E1 Tributary Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .412
Figure 9-31 T1/E1 Tributary Synchronization Timing . . . . . . . . . . . . . . . . . . . . . . .413
Figure 9-32 T1/E1 Test Transmit Clock Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . .414
Figure 9-33 T1/E1 Test Transmit Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .415
Figure 9-34 T1/E1 Test Receive Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .415
Figure 9-35 T1/E1 Test Receive Data Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . .416
Figure 9-36 JTAG Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .417
Figure 9-37 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .418
Preliminary Data Sheet
12
11.99
PEB 20256M E
PEF 20256M E
Table 4-1
Table 4-2
Table 4-3
Table 4-4
Table 4-5
Table 4-6
Table 4-7
Table 4-8
Table 4-9
Table 4-10
Table 4-11
Table 4-12
Table 4-13
Table 4-14
Table 4-15
Table 5-1
Table 5-2
Table 5-3
Table 5-4
Table 5-5
Receive Descriptor Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Transmit Descriptor Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Example for little/big Endian with BNO = 3 . . . . . . . . . . . . . . . . . . . . . 66
Example for little big Endian with BNO = 7 . . . . . . . . . . . . . . . . . . . . . 66
4-Frame Multiframe Structure.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
ESF Multiframe Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
SF Multiframe Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Allocation of Bits 1 to 8 of Time slot 0 . . . . . . . . . . . . . . . . . . . . . . . . . 86
CRC-4 Multiframe Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Summary of Alarm Detection and Alarm Release . . . . . . . . . . . . . . . . 94
M12 multiplex format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
ITU-T G.747 format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
M23 multiplex format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
C-bit parity format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Interrupt Vector Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Correspondence between PCI memory space and chip select . . . . . 151
C/BE to LA/LBHE mapping in Intel bus mode (8 bit port mode) . . . . 154
C/BE to LA/LBHE mapping in Intel bus mode (16 bit port mode) . . . 154
C/BE to LA/LSIZE0 mapping in Motorola bus mode (8 bit port mode) 157
C/BE to LA/LSIZE0 mapping in Motorola bus mode (16 bit port mode) . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
Channel Specification Registers and Channel Commands . . . . . . . . 162
PCI Configuration Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
PCI Slave Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
PCI and Local Bus Slave Register Set . . . . . . . . . . . . . . . . . . . . . . . 174
Transmit T1/E1 Framer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Receive T1/E1 Framer Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Facility Data Link Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Threshold Codings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Signalling Controller Transmit Commands . . . . . . . . . . . . . . . . . . . . 373
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
DC Characteristics (Non-PCI Interface Pins). . . . . . . . . . . . . . . . . . . 389
DC Characteristics (PCI Interface Pins). . . . . . . . . . . . . . . . . . . . . . . 389
PCI Clock Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
PCI Interface Signal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 392
SPI Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
Intel Bus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
Intel Bus Interface Timing (Master Mode) . . . . . . . . . . . . . . . . . . . . . 398
Motorola Bus Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
Motorola Bus Interface Timing (Master Mode). . . . . . . . . . . . . . . . . . 403
Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
DS3 Transmit Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
Table 6-1
Table 8-1
Table 8-2
Table 8-3
Table 8-4
Table 8-5
Table 8-6
Table 8-7
Table 8-8
Table 9-1
Table 9-2
Table 9-3
Table 9-4
Table 9-5
Table 9-6
Table 9-7
Table 9-8
Table 9-9
Table 9-10
Table 9-11
Table 9-12
Table 9-13
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Table 9-14
Table 9-15
Table 9-16
Table 9-17
Table 9-18
Table 9-19
Table 9-20
Table 9-21
Table 9-22
Table 9-23
Table 9-24
Table 9-25
Table 9-26
Table 9-27
DS3 Receive Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
DS3 Status Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
DS3 Transmit Overhead Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
DS3 Receive Overhead Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
DS3 Transmit Stuff Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
DS3 Receive Stuff Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
T1/E1 Tributary Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 412
T1/E1 Tributary Synchronization Timing . . . . . . . . . . . . . . . . . . . . . . 413
T1/E1 Test Transmit Clock Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 414
T1/E1 Test Transmit Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
T1/E1 Test Receive Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
Test T1/E1 Receive Data Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
JTAG Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
Preliminary Data Sheet
14
11.99
Multichannel Network Interface Controller for HDLC/PPP PEB 20256M E
MUNICH256FM
Version 1.1
CMOS
1
MUNICH256FM Overview
The MUNICH256FM is a highly integrated protocol
controller that implements HDLC, PPP and transparent
(TMA) protocol processing for 256 channels as well as
frame alignment for up to 28 T1 signals or 21 E1
signals. An integrated M13 multiplexer together with a
DS3 framer concentrates the data links for direct
connection to a DS3 line interface unit. Optionally the
device supports unchannelized DS3 applications. An
P-BGA-388
internal bit error rate tester can be attached to different test points and provides flexible
PRBS and fixed pattern tests. An on-chip data management unit is optimized to transfer
data packets via a PCI interface by minimizing the bus load.
Note: The MUNICH256FM does not contain DS3 Line Interface Units.
1.1
General Features
• Protocol processing on a channelized or unchannelized DS3 link for frame relay or
router applications
• Direct connection to DS3 line interface unit or DS3 to STS-1 mapper
• Support of 256 bidirectional channels, which can be assigned arbitrarily to a maximum
of 28 links, for HDLC, PPP or transparent mode (TMA) processing
• Concatenation of any, not necessarily consecutive, time slots to logical channels on
each physical link. Supports DS0, fractional T1/E1 or T1/E1 channels
• Provides 32kB data buffer in transmit direction and 12kB data buffer in receive
direction
• Integrates 28T1/21E1 framers (frame alignment function) and 28T1/21E1 signalling
controllers
• Integrates a DS2/DS3 multiplexer and framer
• Remote loopbacks selectable for either DS3 signal, DS2 signal or T1/E1 signal/
payload
Type
Package
PEB 20256M E
P-BGA-388
Preliminary Data Sheet
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11.99
PEB 20256M E
PEF 20256M E
MUNICH256FM Overview
• System interface is a PCI 32 bit, 66 MHz Rev. 2.1 compliant bus interface, which
supports configuration of subsystem ID / subsystem vendor ID via a serial EEPROM
interface. PCI bus interface can be operated in the range of 33 MHz to 66 MHz
• Integrates a local microprocessor master and slave interface (demultiplexed 16 bit
address and data bus in Intel mode or Motorola mode) which allows access to the
local bus via the PCI bus or which can communicate with a PCI host processor
through an on-chip mailbox
• For debugging purposes optional access to the framer and signalling controller
functions via the PCI interface
• JTAG boundary scan according to IEEE1149.1 (5 pins).
• 0.25 µm, 2.5V core technology
• I/Os are 3.3V tolerant and have 3.3V driving capability
• Package P-BGA 388 (35mm x 35mm; pitch 1.27mm)
• Full scan path and BIST of on-chip RAMs for production test
• Performance: 45Mbit/s (DS3) throughput per direction
• Estimated power consumption: 2W
• Also available as device with extended temperature range -40..+85°C
1.1.1
M12 Multiplexer and DS2 Framer
• Multiplexing/Demultiplexing of four asynchronous DS1 bit streams into/from M13
asynchronous format
• Multiplexing/Demultiplexing of 3 E1 signals into/from ITU G.747 compliant DS2 signal.
• DS2 line loopback detection/generation
• Framing according to ANSI T1.107, T1.107a or ITU-T G.747
• Insertion and extraction of X-bit
• Insertion and Extraction of alarms (remote alarm, AIS)
• Detection of AIS in presence of BER 10-3
• Alarm and performance monitoring (framing bit errors, parity errors)
• Reframe time below 7ms (TR-TSY-000009) for DS2 format and below 1 ms for ITU
G.747 format
• Bit Stuffing/Destuffing in M12 multiplex format or C-bit parity format
1.1.2
M23 Multiplexer and DS3 Framer
• Multiplexing/demultiplexing of seven DS2 into/from M13 asynchronous format
according to ANSI T1.107, ANSI T1.107a
• Multiplexing/demultiplexing of seven DS2 into/from C-bit parity format according to
ANSI T1.107, ITU-T G.704
• DS3 framing according to ANSI T1.107, T1.107a, ITU-T G.704
• Support of unipolar and B3ZS encoded signals
• Provides access to the DS3 overhead bits and the DS3 stuffing bits via a serial clock
and data interface (overhead interface)
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
MUNICH256FM Overview
• Insertion and Extraction of alarms according to ANSI T1.404 (remote alarm, AIS, far
end receive failure)
• Supports HDLC (Path Maintenance Data Link) and bit oriented message mode (Far
End Alarm and Control Channel) in C-bit parity mode. An integrated signalling
controller provides 2x32 byte deep FIFO’s for each direction of both channels
• Detection of AIS and idle signal in presence of BER 10-3
• Detection of excessive zeroes and LOS
• Alarm and performance monitoring with 16-bit counters for line code violations,
excessive zeroes, parity error (P-bit), framing errors (F-bit errors with or without M-bit
errors, far end block error (FEBE-bit) and CP-bit errors.
• Automatic insertion of severely errored frame and AIS defect indication
1.1.3
Frame Alignment T1 Features
• Frame alignment/synthesis for 1544 kbit/s according to ITU-T G.704
• Supports T1 frame alignment for F4, SF (F12) and ESF (F24) mode
• Error checking via CRC-6 procedures according to ITU-T G.706
• Performance monitor: 16 bit counter for CRC, framing errors, loss of frame alignment,
loss of signal AIS
• Insertion and extraction of alarms (AIS, Remote (Yellow) Alarm)
• Detection of LOS (Red Alarm)
• Pseudo-random bit sequence generator and monitor for one logical channel
according to ITU-T O.151
• Programmable in-band loop code detection/generation according to TR 62411
1.1.4
Signaling Controller T1 Features
• FDL-channel protocol for ESF format according to ANSI T1.403 specification or
according to AT&T TR54016
• Supports HDLC mode with address recognition
• Supports BOM mode
• FIFO Buffers (64 bytes deep) for efficient transfer of data packets
1.1.5
Frame Alignment E1 Features
• Frame alignment/synthesis for 2048 kbit/s according to ITU-T G.704
• Programmable formats: Doubleframe, CRC-4 Multiframe
Selectable conditions for recover / loss of frame alignment
• CRC-4 to Non-CRC-4 Interworking of ITU-T G.706 Annex B
• Error checking via CRC-4 procedures according to ITU-T G.706
• Performance monitor: 16 bit counter for CRC-, framing errors, error monitoring via E-
bit and Sa6 bit
• Insertion and extraction of alarms (AIS, Remote (Yellow) Alarm, ...)
• Pseudo-random bit sequence (PRBS) generator and monitor for one logical channel
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
MUNICH256FM Overview
• Programmable in-band loop code detection / generation according to TR 62411
1.1.6
Signaling Controller E1 Features
• HDLC controller with address recognition and programmable preamble
• Time slot 0 Sa8-4 HDLC handling via FIFOs
• HDLC access to any Sa-bit combination
• FIFO Buffers (64 byte deep) for efficient transfer of data packets
1.1.7
Bit Error Rate Tester
• User specified PRBS/Fixed Pattern with programmable length of 1 to 32 bits
• Optional Bit Inversion
• Two error insertion modes: Single or programmable bit rates
• Optional zero suppression
• 32-bit counters for errors and received bits
• Programmable bit intervals for receive measurements
Preliminary Data Sheet
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11.99
PEB 20256M E
PEF 20256M E
MUNICH256FM Overview
1.2
Logic Symbol
•
DS3
Overhead
Bits
Status
Signals
Serial
Interface
RSPO
TRCLK
Test and
AD[31:0]
C/BE[3:0]
Reference
Signals
TRD
TTCLK
TTD
FRAME
TRDY
IRDY
STOP
DEVSEL
IDSEL
PAR
LA(12:0)
LD(15:0)
LBHE/LSIZE0
LRDY/LDTACK
LRD/LDS
PCI
REQ
GNT
MUNICH256FM
PEB 20256M E
PEF 20256M E
LWR/LRDWR
CLK
RST
LHOLD/LBR
Local
LHLDA/LBG
PERR
SERR
INTA
Bus
LBGACK
LCLK
LMODE
LINT
SPCLK
SPCS
SPI
SPITM
LCS0
LCS1
SPO
SPLOAD
LCS2
JTAG
Figure 1-1
MUNICH256FM Logic Symbol
Preliminary Data Sheet
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11.99
PEB 20256M E
PEF 20256M E
MUNICH256FM Overview
1.3
General System Integration
The MUNICH256FM provides the HDLC/PPP protocol handling, T1/E1 framing and
signalling functions, an integrated M13 multiplexer and a DS3 framer. The line interface
of the MUNICH256FM directly connects to a DS3 line interface unit. Protocol data is
transferred to the packet RAM via the PCI bus and handled (e.g. for layer3 protocol
handling) by the line card processor. An external processor provides control of the
integrated T1/E1 framer, M13 multiplexer, DS3 framer and the signalling channels. A
mailbox allows the transfer of information between both CPUs.
•
Linecard
Processor
Local CPU
Packet
RAM
M256FM
DS3 LIU
Backplane
Connection
Router
PCI
Backplane
Bus
T3 Linecard
Figure 1-2
System Integration of the MUNICH256FM
Preliminary Data Sheet
20
11.99
PEB 20256M E
PEF 20256M E
Pin Description
2
Pin Description
Signal Type Definitions:
The following signal type definitions are partly taken from the PCI Specification Rev. 2. 1:
I
Input is a standard input- only signal.
O
Totem Pole Output is a standard active driver.
Tri-State or I/O is a bidirectional, tri-state input/output pin.
t/s, I/O
s/t/s
Sustained Tri-State is an active low tri-state signal owned and driven by
one and only agent at a time. The agent that drives an s/t/s pin low must
drive it high for at least one clock before letting it float. A new agent
cannot start driving a s/t/s signal any sooner than one clock after the
previous owner tri-states it. A pullup is required to sustain the inactive
state until another agent drives it, and must be provided by the central
resource.
o/d
Open Drain allows multiple devices to share a line as a wire-OR. A pull-
up is required to sustain the inactive state until another agent drives it,
and must be provided by the central resource.
Signal Name Conventions:
NCn
No-connect Pin n
Such pins are not bonded with the silicon. Although any potential at
these pins will not impact the device it is recommended to leave them
unconnected. No-connect pins might be used for additional functionality
in later versions of the device. Leaving them unconnected will guarantee
hardware compatibility to later device versions.
Reserved
Reserved pins are for vendor specific use only and should be connected
as recommended to guarantee normal operation.
Note: The signal type definition specifies the functional usage of a pin. This does not
reflect necessarily the implementation of a pin, e.g. a pin defined of signal type
‘Input’ may be implemented with a bidirectional pad.
Preliminary Data Sheet
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11.99
PEB 20256M E
PEF 20256M E
Pin Description
2.1
PCI Bus Interface
•
Pin No.
Symbol
Input (I)
Output (O)
Function
Address/Data Bus
A bus transaction consists of an address
phase followed by one or more data
phases.
When the MUNICH256FM is the bus
master, AD(31:0) are outputs in the
address phase of a transaction. During
the data phases, AD(31:0) remain outputs
for write transactions, and become inputs
for read transactions.
T3, T4, U1, U3, AD(31:0)
V2, W1, W2,
V4, AA2, W4,
AC1, AB2, Y3,
Y4, AD1, AC2,
AC8, AE6,
AD8, AF6,
AC9, AE8,
AF7, AD10,
AC11, AF8,
t/s
AF10, AD11,
AC12, AE11,
AD12, AF11
When the MUNICH256FM is bus slave,
AD(31:0) are inputs in the address phase
of a transaction. During the data phases,
AD(31:0) remain inputs for write
transactions, and become outputs for
read transactions.
AD(31:0) are tri-state when the
MUNICH256FM is not involved in the
current transaction.
AD(31:0) are updated and sampled on
the rising edge of CLK.
Preliminary Data Sheet
22
11.99
PEB 20256M E
PEF 20256M E
Pin Description
Pin No.
Symbol
Input (I)
Function
Output (O)
V3, AA4, AD7, C/BE(3:0)
AE9
t/s
Command/Byte Enable
During the address phase of
a
transaction, C/BE(3:0) define the bus
command. During the data phase, C/
BE(3:0) are used as byte enable lines.
The byte enable lines are valid for the
entire data phase and determine which
byte lanes carry meaningful data. C/BE(0)
applies to byte 0 (LSB) and C/BE(3)
applies to byte 3 (MSB).
When the MUNICH256FM is bus master,
C/BE(3:0) are outputs.
When the MUNICH256FM is bus slave,
C/BE(3:0) are inputs.
C/BE(3:0) are tri-stated when the
MUNICH256FM is not involved in the
current transaction.
C/BE(3:0) are updated and sampled on
the rising edge of CLK.
AF4
PAR
t/s
Parity
PAR is even parity across AD(31:0) and
C/BE(3:0). PAR is stable and valid one
clock after the address phase. PAR has
the same timing as AD(31:0) but delayed
by one clock.
When the MUNICH256FM is Master,
PAR is output during address phase and
write data phases and input during read
data phase. When the MUNICH256FM is
Slave, PAR is output during read data
phase and input during write data phase.
PAR
is
tri-stated
when
the
MUNICH256FM is not involved in the
current transaction.
Parity
errors
detected
by
the
MUNICH256FM are indicated on PERR
output.
PAR is updated and sampled on the rising
edge of CLK.
Preliminary Data Sheet
23
11.99
PEB 20256M E
PEF 20256M E
Pin Description
Pin No.
AB3
Symbol
Input (I)
Output (O)
Function
FRAME
s/t/s
Frame
FRAME indicates the beginning and end
of an access. FRAME is asserted to
indicate a bus transaction is beginning.
While FRAME is asserted, data transfers
continue. When FRAME is deasserted,
the transaction is in the final phase.
When the MUNICH256FM is bus master,
FRAME is an output. When the
MUNICH256FM is bus slave, FRAME is
an input. FRAME is tri-stated when the
MUNICH256FM is not involved in the
current transaction.
FRAME is updated and sampled on the
rising edge of CLK.
AC6
IRDY
s/t/s
Initiator Ready
IRDY indicates the bus master’s ability to
complete the current data phase of the
transaction. It is used in conjunction with
TRDY. A data phase is completed on any
clock where both IRDY and TRDY are
sampled asserted. During a write, IRDY
indicates that valid data is present on
AD(31:0). During a read, it indicates the
master is prepared to accept data. Wait
cycles are inserted until both IRDY and
TRDY are asserted together.
When the MUNICH256FM is bus master,
IRDY is an output. When the
MUNICH256FM is bus slave, IRDY is an
input. IRDY is tri-stated, when the
MUNICH256FM is not involved in the
current transaction.
IRDY is updated and sampled on the
rising edge of CLK.
Preliminary Data Sheet
24
11.99
PEB 20256M E
PEF 20256M E
Pin Description
Pin No.
AD5
Symbol
TRDY
Input (I)
Output (O)
Function
s/t/s
Target Ready
TRDY indicates a slave’s ability to
complete the current data phase of the
transaction. During
a
read, TRDY
indicates that valid data is present on
AD(31:0). During a write, it indicates the
target is prepared to accept data.
When the MUNICH256FM is Master,
TRDY is an input. When the
MUNICH256FM is Slave, TRDY is an
output. TRDY is tri-stated, when the
MUNICH256FM is not involved in the
current transaction.
TRDY is updated and sampled on the
rising edge of CLK.
AF3
STOP
s/t/s
Stop
STOP is used by a slave to request the
current master to stop the current bus
transaction.
When the MUNICH256FM is bus master,
STOP is an input. When the
MUNICH256FM is bus slave, STOP is an
output. STOP is tri-stated, when the
MUNICH256FM is not involved in the
current transaction.
STOP is updated and sampled on the
rising edge of CLK.
AA1
IDSEL
I
Initialization Device Select
When the MUNICH256FM is slave in a
transaction, where IDSEL is active in the
address phase and C/BE(3:0) indicates
an configuration read or write, the
MUNICH256FM assumes a read or write
to a configuration register. In response,
the MUNICH256FM asserts DEVSEL
during the subsequent CLK cycle.
IDSEL is sampled on the rising edge of
CLK.
Preliminary Data Sheet
25
11.99
PEB 20256M E
PEF 20256M E
Pin Description
Pin No.
AE4
Symbol
Input (I)
Output (O)
Function
DEVSEL
s/t/s
Device Select
When activated by a slave, it indicates to
the current bus master that the slave has
decoded its address as the target of the
current transaction. If no bus slave
activates DEVSEL within six bus CLK
cycles, the master should abort the
transaction.
When the MUNICH256FM is bus master,
DEVSEL is input. If DEVSEL is not
activated within six clock cycles after an
address is output on AD(31:0), the
MUNICH256FM aborts the transaction.
When the MUNICH256FM is bus slave,
DEVSEL is output. DEVSEL is tri-stated,
when the MUNICH256FM is not involved
in the current transaction.
AC7
PERR
s/t/s
Parity Error
When activated, indicates a parity error
over the AD(31:0) and C/BE(3:0) signals
(compared to the PAR input). It has a
delay of two CLK cycles with respect to
AD and C/BE(3:0) (i.e., it is valid for the
cycle
immediately
following
the
corresponding PAR cycle).
PERR is asserted relative to the rising
edge of CLK.
AE5
T2
SERR
REQ
o/d
t/s
System Error
The MUNICH256FM asserts this signal to
indicate an address parity error and report
a fatal system error.
SERR is an open drain output activated
on the rising edge of CLK.
Request
Used by the MUNICH256FM to request
control of the PCI bus. It is tri-state during
reset.
REQ is activated on the rising edge of
CLK.
Preliminary Data Sheet
26
11.99
PEB 20256M E
PEF 20256M E
Pin Description
Pin No.
Symbol
GNT
Input (I)
Output (O)
Function
T1
I
Grant
This signal is asserted by the arbiter to
grant control of the PCI to the
MUNICH256FM in response to a bus
request via REQ. After GNT is asserted,
the MUNICH256FM will begin a bus
transaction only after the current bus
Master has deasserted the FRAME
signal.
GNT is sampled on the rising edge of
CLK.
R4
R3
CLK
I
Clock
Provides timing for all PCI transactions.
Most PCI signals are sampled or output
relative to the rising edge of CLK. The PCI
clock is used as internal system clock.
The maximum CLK frequency is 66 MHz.
RST
I
Reset
An active RST signal brings all PCI
registers, sequencers and signals into a
consistent state. All PCI output signals
are driven to high impedance.
AC13
INTA
o/d
Interrupt Request
When an interrupt status is active and
unmasked, the MUNICH256FM activates
this open-drain output.
Preliminary Data Sheet
27
11.99
PEB 20256M E
PEF 20256M E
Pin Description
2.2
SPI Interface
•
Pin No.
Symbol
Input (I) Function
Output (O)
P2
SPI
I
SPI Serial Input
SPI is a data input pin, where data coming
from an external EEPROM is shifted in.
SPI is sampled on the rising edge of
SPCLK.
A
pull-up
resistor
is
recommended if the SPI interface is not
used.
P1
N4
SPO
O
O
SPI Serial Output
SPO is a push/pull serial data output pin.
Opcodes, byte addresses and data is
updated on the falling edge of SPCLK. It
is tri-state during reset.
SPCLK
SPI Clock Signal
SPCLK controls the serial bus timing of
the SPI bus. SPCLK is derived from the
PCI bus clock with a frequency of 1/78 of
the PCI bus clock. It is tri-state during
reset.
N3
P4
SPCS
O
I
SPI Chip Select
SPCS is used to select an external
EEPROM. It is tri-state during reset.
SPLOAD
Enable SPI Load Functionality
Connecting SPLOAD to VDD3 enables the
SPI bus after reset. In this case parts of
the PCI configuration space can be
configured via an external EEPROM.
Preliminary Data Sheet
28
11.99
PEB 20256M E
PEF 20256M E
Pin Description
2.3
Local Microprocessor Interface
•
Pin No.
Symbol
Input (I)
Output (O)
Function
Local Bus Mode
W24
LMODE
I
By connecting this pin to either VSS or
VDD3 the bus interface can be adapted to
either Intel or Motorola environment.
LMODE = VSS selects Intel bus mode.
LMODE = VDD3 selects Motorola bus
mode.
Y24
LCLK
O
Local Clock
Reference output clock derived from the
PCI clock.
AE13, AF13,
AF14, AE14,
AF16, AC14,
AD15, AE16,
AF17, AC15,
AD16, AF19,
AE18
LA(12:0)
I/O
Address bus
These input address lines select one of
the internal registers for read or write
access.
Note: Only LA(7:0) are evaluated during
read/write
accesses
to
the
MUNICH256FM.
In local bus master mode the address
lines are output. If local bus master
functionality is disabled these pins are
input only.
AC16, AD17,
AF20, AE19,
AF21, AC18,
AD19, AE21,
AD20, AC19,
AF23, AE24,
AF25, AE26,
AD25, AB23
LD(15:0)
I/O
Data Bus
Bidirectional tri-state data lines.
Y23
LCS0
I
Chip Select
This active low signal selects the
MUNICH256FM as bus slave for read/
write operations.
Preliminary Data Sheet
29
11.99
PEB 20256M E
PEF 20256M E
Pin Description
Pin No.
AC24
Symbol
LRD
Input (I)
Output (O)
Function
I/O
Read (Intel Bus Mode)
This active low signal selects a read
transaction.
or
LDS
I/O
Data strobe (Motorola Bus Mode)
This active low signal indicates that valid
data has to be placed on the data bus
(read cycle) or that valid data has been
placed on the data bus (write cycle).
AB24
AA23
LWR
I/O
I/O
Write Enable (Intel Bus Mode)
This active low signal selects a write
cycle.
Read Write Signal (Motorola Bus
Mode)
or
LRDWR
This input signal distinguishes write from
read operations.
LRDY
I/O
Ready (Intel bus mode)
This signal indicates that the current bus
cycle is complete. The MUNICH256FM
asserts LRDY during a read cycle if valid
output data has been placed on the data
bus. In write direction LRDY will be
asserted when input data has been
latched.
or
In local bus master mode MUNICH256FM
evaluates LRDY to finish a transaction.
Data Transfer Acknowledge (Motorola
bus mode)
DTACK
I/O
This active low input indicates that a data
transfer may be performed. During a read
cycle data becomes valid at the falling
edge of DTACK. The data is latched
internally and the bus cycle is terminated.
During a write cycle the falling edge of
DTACK marks the latching of data and the
bus cycle is terminated.
Preliminary Data Sheet
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Pin Description
Pin No.
AC26
Symbol
LINT
Input (I)
Output (O)
Function
Interrupt Request
I/od
This line indicates general interrupt
requests of the layer one functions or the
mailbox. The interrupt sources can be
masked via registers.
In local bus master mode the
MUNICH256FM can monitor external
interrupts indicated via LINT.
AC25, W23
LCS2,
LCS1
O
O
Chip Select 2, 1
These signals select external peripherals
when MUNICH256FM is the local bus
master. As long as the local bus master
functionality is disabled these outputs are
set to tri-state.
AD13
LBHE
Byte High Enable (Intel Bus Mode)
In local bus master mode this signal
indicates a data transfer on the upper byte
of the data bus LD(15:8).
This signal has no function in slave mode.
When local bus master functionality is
disabled this output is tri-state.
or
LSIZE0
O
Byte Access (Motorola Bus Mode)
In local bus master mode this signal
indicates byte transfers.
This signal has no function when the
MUNICH256FM is local bus slave. When
local bus master functionality is disabled
this output is tri-state.
AA25
LHOLD
O
O
Bus Request (Intel Bus Mode)
This pin indicates a requests to become
local bus master.
When local bus master functionality is
disabled this output is tri-state.
Bus Request (Motorola Bus Mode)
LBR indicates a request to become local
bus master.
or
LBR
When local bus master functionality is
disabled this output is set to tri-state.
Preliminary Data Sheet
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Pin Description
Pin No.
AB25
Symbol
LHLDA
Input (I)
Output (O)
Function
I
Hold (Intel Bus Mode)
LHLDA indicates that the external
processor has released control of the
local bus.
or
LBG
I
Bus Grant (Motorola Bus Mode)
LBG indicates that the MUNICH256FM
may access the local bus.
V23
LBGACK
O
Bus Grant Acknowledge (Motorola
Bus Mode)
LBGACK is driven low when the
MUNICH256FM has become bus master.
When local bus master functionality is
disabled this output is tri-state.
Preliminary Data Sheet
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Pin Description
2.4
Serial Interface
•
Pin No.
Symbol
Input (I)
Function
Output (O)
D12
CTCLK
I
Common Transmit Clock
CTCLK is the external transmit clock for
the T1 or E1 tributaries configured in
external timing mode.
A11
C15
CTFS
RSPO
I
Common
Synchronization
Transmit
Frame
CTFS is used to synchronize the T1/E1
transmit lines, which are clocked with
CTCLK in external timing mode.
If not used CTFS should be connected to
VSS.
O
Regenerated Sync Pulse
RSPO supports debugging of the on-chip
T1/E1 framing function. If the T1/E1
framer achieved synchronization, the
internal synchronization pulse of one
selected T1/E1 framer can be monitored
on RSPO.
or
TRCLK
O
O
Test Receive Clock
In serial test mode the receive clock of
one selected T1/E1 interface is directly
feeded to this output.
M24
TRD
Test Receive Data
In serial test mode the incoming data
stream of one T1/E1 tributary is directly
feeded to this output. Test receive data is
updated on the falling edge of the TRCLK.
N26
C12
TTCLK
TTD
I
I
Test Transmit Clock
In serial test mode this clock provides the
clock reference for the tributary provided
via TTD.
Test Transmit Data
In serial test mode the data stream
provided via TTD replaces the E1/T1 data
stream of the selected tributary. TTD is
sampled on the rising edge of the TTCLK.
Preliminary Data Sheet
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Pin Description
Pin No.
Symbol
Input (I) Function
Output (O)
C14
TC44
I
DS3 Transmit Clock Input
This clock provides a reference clock for
the DS3 interface. The frequency of this
clock is nominally 44.736 MHz.
D14
B16
TC44O
TD44
O
O
DS3 Transmit Clock Output
This output is a buffered version of the
selected transmit clock which can be set
to RC44 or TC44.
DS3 Transmit Data
This unipolar serial data output
represents the DS3 signal. TD44 is
updated on the falling or rising edge of
TC44.
or
TD44P
O
O
DS3 Transmit Positive Pulse
In dual-rail mode this pin represents the
positive pulse of the B3ZS encoded DS3
signal. TD44P is updated on the falling
edge or rising edge of TC44O.
C16
TD44N
DS3 Transmit Negative Pulse
In dual-rail mode this pin represents the
negative pulse of the B3ZS encoded DS3
signal. TD44N is updated on the falling or
rising edge of TC44O.
B14
D13
RC44
RD44
I
I
DS3 Receive Clock Input
The frequency of this clock is nominally
44.736 MHz.
DS3 Receive Data
This unipolar serial data input represents
the DS3 signal. RD44 is sampled on the
falling or rising edge of RC44.
or
DS3 Receive Positive Pulse
RD44P
I
In dual-rail mode this pin represents the
positive pulse of the B3ZS encoded DS3
signal. RD44P is sampled on the falling or
rising edge of RC44.
Preliminary Data Sheet
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Pin Description
Pin No.
Symbol
Input (I)
Function
Output (O)
A14
RD44N
I
DS3 Receive Negative Pulse
In dual-rail mode this pin represents the
negative pulse of the B3ZS encoded DS3
signal. RD44 is sampled on the falling or
rising edge of RC44.
A21
B21
RRED
RLOS
O
O
Received RED
This signal is asserted whenever the DS3
receive framer is in RED alarm state.
Received LOS
This signal is asserted whenever the
received DS3 bit stream contained at
least 175 consecutive ‘0’s.
D19
C19
B8
RLOF
O
O
O
Receive LOF
This signal is asserted whenever the DS3
receive framer is in ’Loss of frame’ state.
RAIS
Received AIS
This signal is asserted whenever the DS3
receive framer is in AIS state.
TOVHCK
Transmit Overhead Bit Clock
This signal provides the bit clock for the
DS3 overhead bits of the outgoing DS3
frame. TOVHCK is nominally a 526 kHz
clock.
C8
TOVHD
I
Transmit Overhead Data
The overhead bits of the outgoing DS3
frame can be provided via TOVHD.
Transmit overhead data is sampled on
the rising edge of TOVHCK and those bits
which are enabled by TOVHEN are
inserted in the overhead bit positions of
the DS3 frame.
D8
TOVHEN
I
Enable Transmit Overhead Data
The asserted TOVHEN signal marks the
bits to be inserted in the DS3 frame.
TOVHEN is sampled together with
TOVHD on the rising edge of TOVHD.
Preliminary Data Sheet
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Pin Description
Pin No.
Symbol
Input (I) Function
Output (O)
A8
TOVHSYN
I/O
Transmit Overhead Synchronization
TOVHSYN provides the means to align
TOVHD to the first M-frame of the DS3
signal. If operated in output mode
TOVHSYN it is asserted when the X-bit of
the 1st subframe of the DS3 overhead bits
has to be inserted via TOVHD. TOVHSYN
is updated on the rising edge of TOVHCK.
If operated in input mode TOVHSYN must
be asserted together with the X-bit of the
1st subframe of the DS3 signal which is
input on TOVHD. TOVHSYN is sampled
on the rising edge of TOVHCK.
D9
A7
TSBCK
TSBD
O
I
Transmit Stuff Bit Clock
This signal provides the bit clock for DS3
stuff bit data. Transmit stuff bit data is
sampled on the rising edge of TSBCK.
Transmit Stuff Bit Data
Data provided via TSBD is optionally
inserted in the stuffed bit positions of the
DS3 signal. TSBD is sampled on the
rising edge of TSBD. This function is
available in M13 asynchronous format
only.
B9
ROVHCK
ROVHD
O
O
O
Receive Overhead Bit Clock
This signal provides the bit clock for the
received DS3 overhead bits. ROVHCK is
nominally a 526 kHz clock.
C9
Receive Overhead Data
ROVHD contains the extracted overhead
bits of the DS3 frame. It is updated on the
rising edge of ROVHCK.
C10
ROVHSYN
Receive Overhead Synchronization
ROVHSYN is asserted while the X-bit of
the 1st subframe of the DS3 overhead bits
is provided via ROVHD. It is sampled on
the rising edge of ROVHCK.
Preliminary Data Sheet
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Pin Description
Pin No.
Symbol
Input (I)
Function
Output (O)
D11
RSBCK
O
Receive Stuff Bit Clock
This signal provides the bit clock for DS3
stuff bit data. Transmit stuff bit data is
sampled on the rising edge of TSBCK.
A10
RSBD
O
Receive Stuff Bit Data
ROVHD provides data which was
inserted in the stuffed bit positions of the
DS3 signal. RSBD is updated on the
rising edge of RSBD. This function is
available in M13 asynchronous format
only.
Preliminary Data Sheet
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Pin Description
2.5
Test Interface
•
Pin No.
Symbol
Input (I) Function
Output (O)
C25
TCK
I
I
I
JTAG Test Clock
This pin is connected with an internal pull-
up resistor.
F23
A24
TMS
TDI
JTAG Test Mode Select
This pin is connected with an internal pull-
up resistor.
JTAG Test Data Input
This pin is connected with an internal pull-
up resistor.
D24
B26
TDO
O
I
JTAG Test Data Output
TRST
JTAG Test Reset
This pin is connected with an internal pull-
down resistor.
E24
SCAN
I
Full Scan Path Test
When
connected
to
VDD3
the
MUNICH256FM works in a vendor
specific test mode. It is recommended to
connect this pin to VSS.
Preliminary Data Sheet
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Pin Description
2.6
Power Supply, Reserved Pins and No-connect Pins
•
Pin No.
Symbol
VSS
Input (I) Function
Output (O)
AF1, AE7, AF9, AE12,
AE15, AF18, AE20,
I
Ground 0V
All pins must have the same level.
AF26, AD3, AD24, AD26,
Y2, Y25, V1, V26, R2,
T12, T11, R12, R11, T14,
T13, R14, R13, T16, T15,
R16, R15, R25, P12, P11,
N12, N11, P14, P13, N14,
N13, P16, P15, N16, N15,
M2, M12, M11, L12, L11,
M14, M13, L14, L13,
M16, M15, L16, L15,
M25, J1, J26, G2, G25,
C3, C24, D25, A1, B7,
A9, B12, B15, A18, B20,
A26, B23, A25
AE2, AF5, AE10, AF12, VDD25
AF15, AE17, AF22,
I
Supply Voltage 2.5V ± 0.25V
All pins must have the same level.
AE25, AB1, AB26, Y1,
Y26, U2, U25, R1, R26,
M1, M26, K2, K25, G1,
G26, E1, E26, B2, A5,
B10, A12, A15, B17, A22,
B25, C22, D21
AC4, AD6, AD9, AC10, VDD3
AD14, AD18, AC17,
I
Supply Voltage 3.3V ± 0.3V
All pins must have the same level.
AD21, AC23, AA3, AA24,
W3, U4, V24, U23, P3,
P23, N24, L24, J3, K23,
J24, H23, F3, F24, D4,
C6, D10, C13, D17, C18,
C21, D23
Preliminary Data Sheet
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PEF 20256M E
Pin Description
Pin No.
Symbol
Input (I) Function
Output (O)
B5, C5, D5, A4, B4, C4, RES1..16,
E3, D2, H3, H2, J4, H1, RES20..93
J2, K4, K3, K1, F4, D1,
E2, G4, F2, G3, F1, H4,
L3, L4, L2, L1, M3, M4,
N1, N2, AA26, W25,
Reserved Pins 1..16, 20..93
A pull-up resistor to VDD3 is
recommended.
W26, T23, U24, T24,
R23, V25, U26, R24, T25,
P24, T26, P25, P26, N25,
N23, L26, K26, M23, L25,
H26, L23, J25, K24, H25,
F26, J23, H24, F25, G24,
D26, G23, E25, C26,
D20, B22, A23, C20, D18,
B19, A20, B18, C17, A19,
A17, D16, D15, A16, B13,
A13, B11, C11, C7, D7,
A6, B6, D6
E4, C1, B1, C2, A3, A2, NC0..7
B3, D3, E23, B24, C23, NC12..31
D22, AC22, AD23, AD22,
AC21, AE22, AC20,
No-connect Pins 0..7, 12..31
It is recommended not to
connect these pins.
AF24, AE23, AF2, AE3,
AC5, AD4, AE1, AD2,
AB4, AC3
Preliminary Data Sheet
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PEF 20256M E
General Overview
3
General Overview
3.1
Functional Overview
The MUNICH256FM is a highly integrated WAN protocol controller that performs HDLC,
PPP and transparent (TMA) protocol processing on 256 full duplex serial channels for a
channelized or unchannelized DS3 link. The device provides the framing functions for 28
T1 links or 21 E1 links. Signalling controller functions for DS3, T1 and E1 mode are
integrated as well.
The following operating modes are provided (assuming a PCI clock frequency of 33 MHz
or more):
• 28 times T1 signals operating at 1.544 MBit/s mapped into M13 asynchronous format
or C-bit parity format
• 21 times E1 signals operating at 2.048 MBit/s mapped into ITU-T G.747 compliant
signal.
• Full payload rate DS3 signal in C-bit parity format
The serial interface operates in unipolar or dual-rail mode and connects directly to
available DS3 LIUs.
Each T1 or E1 tributary can be operated in external timing mode, where the tributary is
clocked with the common transmit clock CTCLK, or in looped timing mode, where data
of the selected tributaries is sent synchronous to the incoming receive clock.
A variety of loop modes is provided to support remote as well as inloop testing of the
device. Remote loops are provided on DS3-, DS2-, DS1- or payload level.
Two bus interfaces, a PCI Rev. 2.1 compliant bus interface and a 16 bit Intel/Motorola
style bus interface, connect the device to system environment. Device configuration and
channel operation is provided through the PCI bus interface, whereas the 16 bit bus
interface provides access to the framing functions and the signalling controller. The
MUNICH256FM supports PCI PnP capability by loading the subsystem ID and the
subsystem vendor ID via a SPITM interface into the PCI configuration space.
Preliminary Data Sheet
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General Overview
3.2
Block Diagram
•
DS3 interface unipolar or
Clock
B3ZS encoded
References
Overhead
Access
DS3 framer
M13 Multiplexer
BERT
1
2
28
CTCLK
T1/E1 Interface/Unchannelized Interface
TestPort
synchronization
Loop buffer
JTAG
interface
Framer
Protocol handler
Internal Buffer
Facility data link
Message FIFO
Interrupt FIFO
Interrupt
controller
Data management unit
Initiator bus
SPITM
Interface
PCI Interface
PCI
Local Bus Interface
local uP interface
Figure 3-1
3.3
MUNICH256FM Block Diagram
Internal Interface
The device consists of several macro functions as shown in Figure 3-1. The internal
modules are connected by busses/signals according to Infineons on-chip bus.
The main busses are:
• The initiator bus, on which the DMA requests of the data management units and the
interrupt controller are arbitrated and funneled into the PCI interface.
Preliminary Data Sheet
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General Overview
• The configuration busses, which serve as the standard programming interface to
access the chip internal registers and functions either via PCI bus or via the local bus
interface.
• The interrupt busses, which collect all interrupt information and forward them to the
corresponding interrupt handler.
The chip’s core functions are all operated with the PCI clock. Transfers between clocking
regions (serial clocks and system clock) are implemented only in the serial interface.
3.4
Block Description
The following section gives a brief overview to the function of each block. For a detailed
description of each function refer to "Functional Description" on page 47.
T1/E1 Interface/Unchannelized Interface
The T1/E1 interface consists of the subfunctions receive and transmit. This block
provides the function of serial/parallel and parallel/serial conversion for up to 28
incoming and up to 28 tributaries of the DS3 signal. Serial data is transferred between
the internal clocking system, which is derived from the PCI clock, and the various line
clocks. This provides a unique clocking scheme on the internal interfaces. The
aggregate bandwidth of all enabled tributaries can be up to 45 Mbit/s in each direction.
Time slot assigner
The time slot assigner exchanges data with the serial interface on a 8 bit parallel bus,
thus funneling all data of up to 28 interfaces. The time slot assigner provides freely
programmable mapping of any time slot or any combination of time slots to 256 logical
channels. A programmable mask can be provided to allow subchanneling of the
available time slots which allows channel data rates starting at 8kbit/s.
At the protocol machine interface the time slot assigner and the protocol machine
exchanges channel oriented data (8 bit) together with the time slots masks.
Protocol handler
Two protocol machines, one for receive direction and one for transmit direction, provide
protocol handling for up to 256 logical channels and a maximum serial aggregate data
rate of up to 45 Mbit/s per direction. The protocol machines implement four modes, which
can be programmed independently for each logical channel: HDLC, bit-synchronous
PPP, octet-synchronous PPP and Transparent Mode A, including frame synchronous
TMA.
Internal buffer
The internal buffers provides channelwise buffering of raw (unformatted/deformatted)
data for 256 logical channels. Channel specific thresholds can be programmed
Preliminary Data Sheet
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General Overview
independently in transmit and receive direction. In order to avoid transmit underrun
conditions each transmit channel has two control parameters for smoothing the filling/
emptying process (transmit forward threshold, transmit refill threshold). In receive
direction each channel has a receive burst threshold. To avoid unnecessary waste of bus
bandwidth, e.g. in case of transmission errors, the receive buffer provides the capability
to discard frames which are smaller than a programmable threshold.
Data management units
The data management units provide direct data transfer between the system memory
and the internal buffers. Each channel has an associated linked list of descriptors, which
is located in system memory and handled by the data management units. This linked list
is the interface between the system processor and the MUNICH256FM for exchange of
data packets. The descriptors and the data packets can be stored arbitrarily in 32 bit
address space of system memory, thus allowing full scatter/gather assembly of packets.
In order to optimize PCI bus utilization, each descriptor is read in one burst and hold on-
chip afterwards.
Interrupt controller
Two interrupt controller manage internal interrupts. Interrupts from the mailbox, the
framing engines and the signalling controller are passed in form of interrupt vectors to
an internal interrupt FIFO which can be read from the local bus. All system, port and
channel related interrupt informations are passed to the main interrupt controller which
is connected to the PCI system. A programmable DMA with nine channels stores these
interrupts in form of interrupt vectors in different interrupt queues in system memory.
PCI interface
The PCI interface unit combines all DMA requests from the internal data management
unit and the interrupt controller and translates them into PCI Rev. 2.1 compliant bus
accesses. The PCI interface optionally includes the function of loading the subsystem
vendor ID and the subsystem ID from an external SPI compliant EEPROM.
Mailbox, internal bridge and global registers
The mailbox is used to exchange data between the PCI attached microprocessor and
the local bus microprocessor and provides a doorbell function between the two
interfaces.
Controlled by an arbiter an internal bridge connects the configuration bus I and the
configuration bus II. It is therefore possible to access the “layer one” registers from the
PCI interface directly. Thus the device could also be operated without a local
microprocessor connected to it, e.g. for debugging purposes. It is NOT possible to
access the configuration bus I and therefore the ’HDLC’ registers or the PCI bridge from
the local bus.
Preliminary Data Sheet
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General Overview
Local bus interface
The local bus interface builds the interface between the local microprocessor and the on-
chip configuration bus II in order to access the registers of the on-chip M13 multiplexer,
DS2/DS3 framer, T1/E1 framer, the registers of the signalling controller and the mailbox.
The local bus interface provides a switchable Intel-style or Motorola-style processor
interface.
M23 multiplexer/demultiplexer and DS3 framer
In channelized operating modes the M23 multiplexer/demultiplexer maps/demaps seven
DS2 signals into/from M13 asynchronous format or C-bit parity format. In unchannelized
mode one logical input stream is mapped into the information bits of the DS3 stream
according to ANSI T1.107. The DS3 framer performs frame and multiframe alignment in
receive direction and inserts the frame and multiframe alignment bits. Performance
monitors provide for counting of framing bit errors, parity errors, CP-bit errors, far end
block errors, excessive zeroes or line code violations. The framer detects loopback
requests and allows insertion of loopback requests under microprocessor control.
M12 multiplexer/demultiplexer and DS2 framer
The M12 multiplexer/demultiplexer operates in two modes. It maps either 28 T1 signals
or 21 E1 signals into/from seven ANSI T1.107 or ITU-T G.747 compliant DS2 signals. It
performs inversion of the second and fourth DS1 signal. The DS2 framer performs frame
and multiframe alignment in receive direction and vice versa inserts the framing bits
according to ANSI T1.107 or ITU-T G.704. It detects loopback requests or enables
insertion of loopback requests under microprocessor control.
T1/E1 framer
Synchronization is achieved with the on-chip framing function. T1/E1 mode is supported
for up to 28 ports. Once the framer achieved synchronization for a line, that is the frame
alignment information in the incoming bit stream has been identified correctly, it informs
the port interface and the facility data link about the frame position. In transmit direction
the framing bits are inserted according to T1 F4 format, T1 SF (F12) format, T1 ESF
(F24) format, E1 doubleframe format or E1 CRC-4 multiframe format. Performance
monitors provide for counting framing errors, CRC errors, block errors, E-bit errors or
PRBS bit errors. The framer detects loopback requests and allows insertion of loopback
requests or pseudo-random bit sequences under microprocessor control.
Facility data link, Signaling controller
The facility data link exchanges the ‘F-bits’ of the T1 links or the Sa-bits of time slot zero
of the E1 links with the framer block and it provides the function of HDLC formatting or
BOM mode in receive and transmit direction.
Preliminary Data Sheet
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General Overview
The signalling controller also provides access to the DS3 signalling bits (Far End Alarm
and Control Channel, Path Maintenance Data Link Channel).
Message FIFO
For intermediate buffering of data link messages two FIFOs are integrated, one for
transmit and one for receive direction. Each FIFO provides two pages of 32 bytes buffer
per line and direction.
JTAG
Boundary Scan logic according to IEEE 1149.1.
Preliminary Data Sheet
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Functional Description
4
Functional Description
4.1
Port Handler
The port handler is the interface between the serial ports and the chip internal protocol
and framing functions. It converts incoming serial data into parallel data for further
internal processing and in the outgoing direction it converts parallel data into a serial bit
stream.
The MUNICH256FM provides one port for operation at DS3 signal speeds. It provides
unipolar data transmission or B3ZS encoded data transmission.
The system interface consists of one receive clock input and either one receive data
input in unipolar mode or two receive data inputs in dual-rail mode, one for the positive
pulse and one for the negative pulse. In transmit direction the system interface is build
of one transmit clock input and one or two transmit data outputs.
•
7
28
1
1
TC44
TC44O
TD44P
TD44N
T1/E1
Transmit
Path
RC44
RD44P
RD44N
T1/E1
Receive
Path
Overhead
Access
Figure 4-1
Port configuration in M13 mode
Preliminary Data Sheet
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Functional Description
4.1.1
Local Port Loop
Local port loops are provided on DS3, DS2 and DS1 level on a per port/tributary basis.
In the local loop the outgoing bit stream of a port/tributary is mirrored to the receive data
path. This allows to prepare data in system memory, which is processed by the
MUNICH256FM in transmit direction, mirrored to the respective receiver and stored in
system memory again. In order to ensure that the local port loop works even without
incoming receive clock, each receiver looped uses the corresponding transmit clock.
•
RC44
DS3
Receive
Framer
DS2
Receive
Framer
T1/E1
Receive
Framer
M23
Demux
DS2
Demux
RD44P
RD44N
Protocol
Data
TC44O
TD44P
TD44N
TC44
DS2
Transmit
Framer
T1/E1
Transmit
Framer
DS3
Transmit
Framer
DS2
Multiplexer
M23
Multiplexer
Protocol
Data
RC44
RD44P
RD44N
DS3
Receive
Framer
DS2
Receive
Framer
T1/E1
Receive
Framer
M23
Demux
DS2
Demux
Protocol
Data
TC44O
TD44P
TD44N
TC44
DS2
Transmit
Framer
T1/E1
Transmit
Framer
DS3
Transmit
Framer
DS2
Multiplexer
M23
Multiplexer
Protocol
Data
Figure 4-2
4.1.2
Local Port Loops in M13 mode
Remote Line Loops
The MUNICH256FM supports remote line loops in different stages of the M13 data path.
In DS3 line loopback mode the incoming DS3 signal is mirrored and placed on the DS3
signal output. While operating in DS3 line loopback mode, the incoming receive clock
RCLK is used to update outgoing transmit data. In DS2 line loopback mode one
arbitrarily selectable DS2 signals is looped in the M12 stage of the MUNICH256FM. The
T1/E1 line loopback mode mirrors one or more incoming lines. Transmit data coming
from the transmit data path is replaced with the mirrored data stream.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Functional Description
•
RC44
RD44P
RD44N
DS3
Receive
Framer
DS2
Receive
Framer
T1/E1
Receive
Framer
M23
Demux
M12
Demux
Protocol
Data
TC44O
TD44P
TD44N
TC44
DS2
Transmit
Framer
T1/E1
Transmit
Framer
DS3
Transmit
Framer
M12
Multiplexer
M23
Multiplexer
Protocol
Data
RC44
DS3
Receive
Framer
DS2
Receive
Framer
T1/E1
Receive
Framer
M23
Demux
DS2
Demux
RD44P
RD44N
Protocol
Data
TC44O
TD44P
TD44N
TC44
DS2
Transmit
Framer
T1/E1
Transmit
Framer
DS3
Transmit
Framer
DS2
Multiplexer
M23
Multiplexer
Protocol
Data
RC44
RD44P
RD44N
DS3
Receive
Framer
DS2
Receive
Framer
T1/E1
Receive
Framer
M23
Demux
DS2
Demux
Protocol
Data
TC44O
TD44P
TD44N
TC44
DS2
Transmit
Framer
T1/E1
Transmit
Framer
DS3
Transmit
Framer
DS2
Multiplexer
M23
Multiplexer
Protocol
Data
Figure 4-3
Remote Line Loops
The T1/E1 line loopback mode mirrors one or more incoming lines. Transmit data
coming from the transmit data path is replaced with the mirrored data stream. While T1/
E1 line loop is closed the transmit framer and the protocol machines are disabled.
Preliminary Data Sheet
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PEF 20256M E
Functional Description
4.1.3
Test Breakout
The test breakout function provides the capability to multiplex one of the incoming 28
receive tributaries to the outgoing test receive port, where an external T1/E1 analyzer
can be easily connected to. A selectable incoming tributary signal can be mapped to the
test receive port where RCLK(x) is mapped to TRCLK and RD(x) to TRD. TRD is
updated on the falling edge of TRCLK. In the opposite direction one of the 28 transmit
tributaries can be replaced with the incoming test transmit data input TTD and the test
transmit clock input TTCLK. TTD is sampled on the rising edge of TTCLK.
•
RCLK(27)
RD(27)
DS2
Receive
Framer
+
M12
Demux
DS3
Receive
Framer
+
M23
Demux
RC44
RD44P
RD44N
RCLK(0)
RD(0)
TCLK(27)
TD(27)
DS3
Transmit
Framer
+
M23
Multiplexer
DS2
Transmit
Framer
+
M12
Multiplexer
TC44
TC44O
TD44P
TD44N
TCLK(0)
TD(0)
Figure 4-4
Test Breakout
Preliminary Data Sheet
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PEF 20256M E
Functional Description
4.2
Time slot Handler
4.2.1
Channelized Modes
The time slot handler assigns any combination of time slots of ports configured in T1 or
E1 mode to logical channels. The assigned time slots are connected internally and the
bit stream of one logical channel is mapped continuously over the selected time slots.
Since the receiver and the transmitter operate independently of each other, the
assignment of time slots to logical channels can be done separately in receive and
transmit direction. Any time slot can be assigned to any channel and any sequence of
time slots can be assigned to one channel.
In normal operation each time slot consists of eight bits and all bits are used for data
transmission. An available mask function provides the capability to mask selected bits,
which in turn are disabled for data transmission. This provides the possibility to operate
time slots with less than 64 kBit/s throughput. So, instead of mapping the bit stream of
one logical channel over all bits of the assigned time slots, the bit stream is mapped
continuously over all unmasked bits of the time slots belonging to that channel.
Figure 4-5 shows a simple assignment process. In this case one port is configured in E1
mode and time slots two and three are assigned to logical channel 5. The bit mask of
time slot two is set to FEH, which disables bit zero of that time slot, and the bit mask of
the third time slot is set to FDH, which disables bit one.
Preliminary Data Sheet
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PEF 20256M E
Functional Description
•
Time
Frame 1
Frame 2
0
7
1
2
3
29 30 31
0
1
2
2
3
29 30 31
Timeslot 2
Timeslot 3
6
0
1
2
3
4
5
6
1
7
1
0
1
1
3
4
5
6
1
7
1
0
1
Timeslot Mask
Timeslot Mask
0
1
1
1
1
1
0
1
1
1
1
Example configuration:
Port three in mode E1.
Timeslot 2 and 3 are assigned to channel 5.
Bit 0 of timeslot 2 and bit 1 of timeslot 3 are masked.
Programming sequence:
1. Port mode configuration
Register
Data
31
0
3H
PMIAR
PMR
Select port 3
E1 mode
8H
2. Timeslot assignment
3H
3H
2H
TSAIA
TSAD
TSAIA
TSAD
Select port 3, timeslot 2
Set channel 5, mask
Select port 3, timeslot 3
Set channel 5, mask
5H
5H
11111110
3H
11111101
Figure 4-5
4.2.2
Time slot Assignment in Channelized Modes
Unchannelized Mode
In unchannelized mode the complete incoming and outgoing serial bit stream belongs to
one logical DS3 channel. To operate the link in unchannelized mode tributary zero (port
zero) has to be programmed for unchannelized operation and all ‘time slots’, that is time
slot 0 to 23 must be assigned to one channel. Additionally the M13 multiplexer must be
switched into unchannelized DS3 mode. The function of bit masks, which is available for
the T1/E1 tributaries, is not available in unchannelized mode.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Functional Description
4.3
Data Management Unit
Each packet or part of a packet is referenced by a descriptor. The descriptors form a link
list, thus connecting all packets together. Packet data as well as descriptors are located
in system memory. Both the MUNICH256FM and the system CPU operate on these data
structures.
Each logical channel has its dedicated linked list of descriptors, one for receive direction
and one for transmit direction. This type of data structure allows channel specific
memory organization which can be specified by the system processor. It provides an
optimized way to transfer data packets between the system processor and the
MUNICH256FM.
The MUNICH256FM has a flexible DMA controller to transfer data either from the
internal receive buffer to the shared memory (receive direction) or from the shared
memory to the internal transmit buffer (transmit direction). Each DMA works on one
linked list. Each linked list located in system memory is associated with one of the 256
transmit channels or one of 256 receive channels.
The address generator of the DMA controller supports full link list handling. Descriptors
are stored independently from the data buffers, thus allowing full scatter/gather
assembly and disassembly of data packets.
4.3.1
Descriptor Concept
A descriptor is used to build a linked list, where each member of the linked list points to
a data section. A descriptor consists of four DWORDS1). The first three DWORDS,
containing link and packet information, are provided by the system CPU and the last
DWORD contains status information, which is written when the MUNICH256FM has
finished operation on a descriptor.
The data section itself can be of any size up to the maximum size of 65535 bytes per
descriptor and is defined in the first DWORD of a descriptor. Each logical data packet
can be split into one or multiple parts, where each part is referenced by one descriptor,
and all parts are referenced by a linked list of descriptors. The descriptor containing the
last part of a data packet is marked with a frame end bit. The descriptor following the
marked descriptor therefore contains the beginning of the next data packet (Figure 4-6).
The last descriptor in a linked list is marked with a hold indication.
For ease of programming the transmit descriptor and the receive descriptor are
structured the same way, thus allowing to link a receive descriptor directly into the linked
list of the transmit queues with minimum descriptor processing.
1)
Preliminary Data Sheet
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PEF 20256M E
Functional Description
•
Linked list in system memory in little endian mode
Data on serial link
7EH
Flag
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
00 0
0
0CH
Next Descriptor Pointer
Data Pointer
01
00000
0CH
03H
07H
0BH
02H
06H
0AH
01H
05H
09H
00H
04H
08H
00 0
1
10H
Payload
Next Descriptor Pointer
Data Pointer
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
CRC
11
00000
09H
0FH
13H
0EH
12H
0DH
11H
0CH
10H
14H
01 0
2
08H
Next Descriptor Pointe
Da
01
CRC
CRC
7EH
Flag
Figure 4-6
Descriptor Structure
Although the data management unit works 32-bit oriented, it is possible to begin a
transmit data section at an uneven address. The two least significant bits of the transmit
data pointer determine the beginning of the data section and the number of bytes in the
first DWORD of the data section, respectively. In receive direction the address of the
data sections must be DWORD aligned.
4.3.2
Receive Descriptor
Each receive descriptor is initialized by the host CPU and stored in system memory as
part of a linked list. The MUNICH256FM reads a descriptor, when requested so from the
host by a receive command or after branching from one receive descriptor to the next
receive descriptor. Each receive descriptor contains four DWORDs, where the first three
DWORDs contain link and packet information and the last DWORD contains status
information. Once the descriptor is processed the status information will be written back
to system memory by the MUNICH256FM (Receive status update). When the
Preliminary Data Sheet
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PEF 20256M E
Functional Description
MUNICH256FM branches to a new descriptor it reads the link and packet information
entirely and stores it in its on-chip channel database.
Table 4-1
Receive Descriptor Structure
DWORD
ADDR.
31
0
30
29
28
27
26
25
0
24
0
23
0
22
0
21
20
19
18
17
16
00H
04H
08H
0CH
HOLD RHI OFFSET(2:0)
DescriptorID(5:0)
NextReceiveDescriptorPointer(31:2)
ReceiveDataPointer(31:2)
FE
15
C
0
0
0
0
0
0
0
0
0
MFL RFOD CRC ILEN RAB
DWORD
ADDR.
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
00H
04H
08H
0CH
NO(15:0)
NextReceiveDescriptorPointer(31:2)
ReceiveDataPointer(31:2)
BNO(15:0)
0
0
0
0
HOLD
Hold indication
HOLD indicates that a descriptor is the last element of a linked list
containing valid information.
0
Next descriptor is available in the shared memory. After checking
the HOLD bit the data management unit branches to the next
receive descriptor.
1
This descriptor is the last one that is available for a channel. This
means that the data section where this descriptor points to is the
last data section which is available for data storage. After
processing of descriptor has finished, the data management unit
repolls the descriptor one time to check if HOLD has already
been cleared. If HOLD is still set the corresponding receive
channel is deactivated as long as the system CPU does not
request a new activation via a ’Receive Hold Reset’ command or
forces the MUNICH256FM to branch to a new linked list via a
’Receive Abort/Branch’ command.
Note: When repolling a descriptor the MUNICH256FM checks the
HOLD bit and the bit field NextReceiveDescriptorPointer. All
other information are NOT updated in the internal channel
database.
Preliminary Data Sheet
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PEF 20256M E
Functional Description
RHI
Receive Host Initiated Interrupt
This bit indicates that the MUNICH256FM shall generate a ’Receive
Host Initiated’ interrupt vector after it has finished processing the
descriptor.
0
Data management unit does not generate an interrupt vector
after it has processed the receive descriptor.
1
Data management unit generates an interrupt vector, as soon as
all data bytes are transferred into the current data section and the
status information is updated.
OFFSET
Offset of unused data section.
This bit field allows to reserve memory space in increments of DWORDs
for an additional header. If the marked descriptor is the first one of a new
packet the data management unit will write data at the address
ReceiveDataPointer+4xOFFSET.
Note: Offset x 4 must be smaller than NO.
Note: This option is not available in transparent mode.
DescriptorID This bit field is read by the data management unit and written back in the
corresponding interrupt status of a channel interrupt vector which is
generated by the data management unit. This value provides a link
between the descriptor and the corresponding interrupt vector.
NO
Byte Number
This bit field defines the size of the receive data section allocated by the
host. The maximum buffer length is 65535 bytes and it has to be a
multiple of 4 bytes. Data bytes are stored in the receive data section
according to the selected mode (little endian or big endian).
Note: Please note that the device handles the status (CRC, flag and
frame status) of frame based protocols (HDLC, PPP) internally in
the same way as payload data. Therefore byte number should
include four bytes more than the maximum length of incoming
frames. Nevertheless, the frame status will be deleted from the
end of the data stream and be attached as a status word to the
receive descriptor. The frame status will not be written to the data
section.
Preliminary Data Sheet
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PEF 20256M E
Functional Description
NextReceiveDescriptorPointer
This pointer contains the start address of the next valid receive
descriptor. After completion of the current receive descriptor the data
management unit branches to the next receive descriptor to continue
data reception.
System CPU can force the MUNICH256FM to branch to the beginning
of a new linked list via the command ’Receive Abort/Branch’. In this case
the receive descriptor address provided via register CSPEC_FRDA is
used as the next receive descriptor pointer to be branched to.
ReceiveDataPointer
This pointer contains the start address of the receive data section. The
start address must be DWORD aligned.
FE
Frame End
It indicates that the current receive data section (addressed by
ReceiveDataPointer) contains the end of a frame. This bit is set by the
data management unit after transferring the last data of a frame from the
internal receive buffer into the receive data section which is located in
the shared memory. Moreover the bit field BNO and the status bits are
updated, the complete (C) bit is set and a ’Frame End’ interrupt vector is
generated.
C
Complete
This bit indicates that
•filling the data section has completed (with or without errors),
•processing of this descriptor was aborted by a ’Receive Abort/Branch’
command,
•or the end of frame (PPP, HDLC) was stored in the receive data section.
The complete bit releases the descriptor.
Byte Number of Received Data
BNO
The data management unit writes the number of data bytes stored in the
current data section into bit field BNO.
Preliminary Data Sheet
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PEF 20256M E
Functional Description
When the MUNICH256FM completes a data section, which included the end of a frame
(C bit and FE bit are set), or when the MUNICH256FM branches to a new linked list due
to a ’Receive Abort/Branch’ command the status information bits RAB, ILEN, CRC,
RFOD and MFL are updated as part of the receive status update. In the abort scenario,
the C bit will always be set. Bit FE will be set only, if the particular channel operates in
HDLC or PPP mode.
RAB
Receive Abort
This bit is set when
•the incoming serial data stream contained an abort sequence, or
•an incoming frame was aborted by the command ’Receive Abort/
Branch’, or
•when a channel is switched off while a frame is being received.
ILEN
CRC
RFOD
MFL
Illegal length
This bit is set, when the length of the incoming data packet was not a
multiple of eight bits.
CRC Error
This bit is set, when the checksum of an incoming data packet was
different to the internally calculated checksum.
Receive Frame Overflow
This bit is set, when a receive buffer overflow occurred during data
reception.
Maximum Frame Length
This bit is set, when the length of the incoming data packet exceeded the
value programmed in CONF1.MFL.
4.3.3
Data Management Unit Receive
The data management unit receive transfers data for each of the 256 logical receive
channels from the internal receive buffer to the data sections of the corresponding
channel. To fulfill the task it has to be initialized for operation, which is described in
"Channel Programming / Reprogramming Concept" on page 162. Relevant part of the
channel information for the data management unit is the address pointer to the first
receive descriptor, the channel interrupt queue and the channel interrupt mask.
The first receive descriptor of a channel is fetched from system memory and stored in
the chip internal channel database the first time the receive buffer requests a data
transfer for the channel. The descriptor contains a pointer to the data section, the size of
the provided data section and a pointer to the next receive descriptor.
The data transfer is requested as soon as a programmed receive buffer threshold is
reached. This threshold is programmed during channel setup on a per channel basis.
Task of the data management unit is to calculate the maximum number of bytes that can
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Functional Description
be stored in the receive data section and to compare this with the length of the requested
data transfer.
In case that the requested transfer length from the receive buffer fits into the provided
data section the data management unit transfers the data block to system memory in one
single burst. If the requested transfer length exceeds the available space of the data
section the transfer is divided into two or more parts. Data packets are written to the data
section until the given data section is filled or the end of a packet is reached.
If the data section in the shared memory is completely filled with data, the data
management unit updates the status word of the receive descriptor by setting the
complete (C) bit and the number of bytes (BNO), which are stored in the data section. In
this case the number of bytes written to the data section equals the size of the data
section.
If the data packet, which is written to system memory, contains the remaining part of a
completely received packet, the data management unit updates the status word of the
receive descriptor by setting the complete bit together with the frame end (FE) bit. The
BNO field is updated on the actual value of bytes written to the data section. If enabled,
the data management unit generates a ‘Frame End’ channel interrupt vector.
With the next receive buffer request the data management unit branches to the next
receive descriptor, which was referenced in the next descriptor field of the current
processed descriptor. To keep track of the linked list the data management unit provides
the possibility to issue a ‘Receive Host Initiated’ interrupt vector, which is generated after
the status word was updated. To enable this interrupt vector the bit RHI must be set in a
descriptor.
Descriptor hold operation
Processing of the descriptor list is controlled by the HOLD bit, which is located in the first
DWORD of each receive descriptor. The HOLD bit indicates that the marked descriptor
is the last descriptor containing a valid data buffer. The data management unit will not
branch to a next descriptor until the hold condition is removed or a ‘Receive Abort’
command forces the MUNICH256FM to branch to the beginning of a new linked list.
Since the HOLD bit marks the last descriptor in a linked list, it may prevent that further
received data packets can be written to system memory.
When a given data section is filled, does not contain the end of a frame (frame based
protocols) and the requested transfer length could not be satisfied, the data
management unit polls the HOLD bit of the current receive descriptor once more. If the
HOLD bit is removed, it branches to the next descriptor. When the HOLD bit is still ’1’,
an internal poll bit is set and the data management unit does not branch to the next
descriptor. Additionally a ’Hold Caused Receive Abort’ interrupt vector is generated. The
status of the descriptor in the shared memory is aborted (RAB bit set) and the complete
bit and the frame end bit are set in the receive descriptor. The rest of the frame will be
discarded. As long as the HOLD bit remains set further data of the same channel is
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Functional Description
discarded and for each discarded frame a ’Silent Discard’ interrupt vector with the bits
HRAB and RAB set is generated.
If the current data section was filled and does contain the end of frame a ’Frame End’
interrupt vector is generated and the descriptor is updated on the FE bit and the C bit.
Therefore the status of this receive descriptor is error free. With the next request of the
receive buffer, the data management unit repolls the HOLD bit of the current receive
descriptor. If the hold bit is removed, it branches to the next descriptor. If the HOLD bit
is still ’1’, an internal poll bit is set. As long as the HOLD bit remains set, further data of
the same channel is discarded and for each discarded frame a ’Silent Discard’ interrupt
vector with bits HRAB and RAB set is generated.
When the receive buffer request matches exactly the remaining size of the data section
and the data block does not contain the end of a packet, it is stored completely in the
data section. The descriptor is updated immediately (C bit set). With the next receive
buffer request, the data management unit repolls the HOLD bit of the current receive
descriptor. If the HOLD bit is removed, it branches to the next descriptor. If the HOLD Bit
is still ’1’, an internal poll bit is set. Additionally a ’Hold Caused Receive Abort’ interrupt
vector is generated and the rest of the frame is discarded. As long as the HOLD bit
remains set further data of the same channel is discarded and for each discarded frame
a ’Silent Discard’ interrupt vector is generated.
The system CPU can remove the hold condition, when the next receive descriptor is
available in shared memory. Therefore the CPU has to execute a ‘Receive Hold Reset’
command, which will reactivate the channel. When the receive buffer requests a new
data transfer, the data management unit will repoll the last receive descriptor. If the
HOLD bit was removed, the data management unit branches to the next receive
descriptor pointed to by bit field NextReceiveDescriptor.
Note: In protocol modes HDLC and PPP data from receive buffer is discarded until the
end of a received frame is reached. As soon as the beginning of a new frame is
received, the data management unit starts to fill the data section.
Note: In transparent mode data transferred from receive buffer is written immediately to
the data section of the next receive descriptor.
If the CPU issues a ’Receive Hold Reset’ command and does not remove the HOLD bit
(erroneous programming), no action will take place.
4.3.4
Transmit Descriptor
The transmit descriptor in shared memory is initialized by the host CPU and is read
afterwards by the MUNICH256FM. The address pointer to the first transmit descriptor is
stored in the on-chip channel database, when requested to do so by the host CPU via
the ’Transmit Init’ command. The first three DWORDs of a transmit descriptor are read
when the transmit buffer requests a data transfer for this channel and then they are
stored in the on-chip memory. Also they are read when branching from one transmit
Preliminary Data Sheet
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PEF 20256M E
Functional Description
descriptor to the next transmit descriptor. Therefore all information in the next descriptor
must be valid when the data management unit branches to a descriptor. The last
DWORD of a transmit descriptor optionally is written by the MUNICH256FM when
processing of a descriptor has finished.
Table 4-2
Transmit Descriptor Structure
DWORD
ADDR.
31
30
29
28
27
0
26
0
25
0
24
0
23
0
22
0
21
20
19
18
17
16
00H
04H
08H
0CH
FE HOLD THI CEN
DescriptorID(5:0)
NextTransmitDescriptorPointer(31:2)
TransmitDataPointer(31:0)
0
C
0
0
0
0
0
0
0
0
0
0
4
0
3
0
2
0
1
0
0
DWORD
ADDR.
15
14
13
12
11
10
9
8
7
6
5
00H
04H
08H
0CH
NO(15:0)
NextTransmitDescriptorPointer(31:2)
TransmitDataPointer(31:0)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FE
Frame end
It indicates that the current transmit data section (addressed by transmit
data pointer) contains the end of a frame. After the last byte is read from
system memory this bit is passed to the transmit buffer and to the
protocol machine. The bit FE informs the transmit buffer to move a
stored frame to the protocol machine even if the programmed transmit
forward threshold is not reached (see "Internal Transmit Buffer" on page
68). The protocol machine is informed to append the checksum (HDLC,
PPP) and then to send the interframe time-fill. Providing a transmit
descriptor with FE = ’0’ and HOLD = ’1’ is an error.
HOLD
Hold indication
It indicates that this descriptor is the last valid element of a linked list.
0
Next descriptor is available in the shared memory. The data
management unit branches to the next descriptor as soon as
processing of the current descriptor has finished.
1
The current descriptor is the last descriptor containing valid data
in the data section. As soon as the data management unit has
transferred the data contained in the data section to the internal
buffer, it tries one more time to read the descriptor. In case that
Preliminary Data Sheet
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Functional Description
the hold indication is still set, it stores further requests of the
receive buffer in its channel database. The channel can be
reactivated by issuing a ’Transmit Hold Reset’ command or by
providing a new linked list via the ’Transmit Abort/Branch’
command, in which case not served requests are processed.
Note: When repolling a descriptor the MUNICH256FM checks the
HOLD bit and the bit field NextTransmitDescriptorPointer. All
other information are NOT updated in the internal channel
database.
NO
Byte Number
The byte number defines the number of bytes stored in the data section
to be transmitted. Thus the maximum length of data buffer is 65535
bytes. In order to provide dummy transmit descriptors NO = 0 is allowed
in conjunction with the FE bit set. In this case (NO = 0) a ’Transmit Host
Initiated’ interrupt vector and/or the C-bit will be generated/set when the
data management unit recognizes this condition. It is an error to set
NO = 0 without FE bit set.
THI
Transmit Host Initiated Interrupt
This bit indicates that the MUNICH256FM shall generate a ’Transmit
Host Initiated’ interrupt vector after it has finished operating on the
descriptor.
0
Data management unit does not generate an interrupt vector
after it has processed the transmit descriptor.
1
Data management unit generates an interrupt vector, as soon as
all data bytes are transferred to the internal transmit buffer and
the status information is updated.
DescriptorID This bit field is read by the data management unit and written back in the
corresponding interrupt status of a channel interrupt vector which is
generated by data management unit. This value provides a link between
the descriptor and the corresponding interrupt vector.
NextTransmitDescriptorPointer
This pointer contains the start address of the next transmit descriptor. It
has to be DWORD aligned. After sending the indicated number of data
bytes, the data management unit branches to the next transmit
descriptor. The transmit descriptor is read entirely at the beginning of
transmission and stored in on-chip memory. Therefore all informations in
the descriptor must be valid.
System CPU can force the MUNICH256FM to branch to the beginning
of a new linked list via the command ’Transmit Abort/Branch’. In this
case the transmit descriptor address provided via register
Preliminary Data Sheet
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Functional Description
CSPEC_FTDA is used as the next transmit descriptor pointer to be
branched to.
TransmitDataPointer
This 32-bit pointer contains the start address of the transmit data section.
Although the data management unit works DWORD oriented, it is
possible to begin transmit data section at byte addresses.
CEN
Complete Enable
This bit is set by the CPU if the complete bit mechanism is desired:
0
The data management unit will NOT update the transmit
descriptor with the C bit. In this mode the use of the THI interrupt
is recommended.
1
The data management unit will set the C bit.
C
Complete
This bit is set by the data management unit, when the bit CEN of a
descriptor is set and when it
•completed reading a data section normally, or
•it was aborted by a ’Transmit Off’ command or by a ’Transmit Abort/
Branch’ command.
The complete bit releases the descriptor.
4.3.5
Data Management Unit Transmit
The data management unit transmit provides the interface between system memory on
one side and the internal transmit buffer on the other side. The data management unit
handles requests of the transmit buffer, controls the address and burst length
calculation, initiates data transfers from system memory to the transmit buffer and
handles the linked lists on a per channel basis.
For initialization the CPU programs the first transmit descriptor address, the interrupt
mask, the interrupt queue and starts the channel with the ’Transmit Init’ command. For
detailed description of channel commands refer to "Channel Commands" on page
163.The data management unit then fetches the given information and stores them in its
on-chip channel database.
The first transmit descriptor is fetched from system memory and stored in the chip
internal channel database the first time the transmit buffer requests data for a channel.
It contains a pointer to the data buffer, the length of the data section as well as a pointer
to the next transmit descriptor. After the first descriptor is stored internally a ’Transmit
Command Complete’ interrupt vector is generated.
Data transfers are requested as long as the number of empty locations is below a
programmable refill threshold. The number of empty locations is reported from the
transmit buffer to the data management unit. Task of the data management unit is to
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Functional Description
calculate the number of bytes that can be loaded from the data section based on the NO
field of the transmit descriptor and to compare this with the number of bytes requested
by the transmit buffer.
Depending on the bit field NO in the transmit descriptor several read accesses must be
performed by the data management unit. It stops serving the request as soon as the
requested amount of data was transferred to the transmit buffer, when a Frame End bit
(FE) in the processed transmit descriptor is set or when the channel was aborted using
a ‘Transmit Abort’ command. Serving the request can also be suspended, when the
programmed transmit burst length (CONF3.TPBL) is reached. All these events may
result in open transmit buffer locations, but the data management unit stores this
information as open requests in the channel database and processes these requests
continuously.
The data management unit alternately serves requests issued by the transmit buffer or
open requests stored in its internal channel database. If there are open requests for a
channel, data transmission will be initiated. The procedure is the same as described
above. It stops, if the requested amount of data is served or when the FE bit field is set.
If a transmit descriptor has its FE bit set and all data of the data section is moved to the
transmit buffer, the data management unit serves requests of further channels or looks
for open requests in its database. Therefore open requests from other channels are
served faster and possible underruns can be avoided. The next transmit descriptor will
be retrieved with the next data transfer of the channel.
When the data management unit completed reading a data section associated with a
transmit descriptor, it updates the complete (C) bit in the status word of the transmit
descriptor if the complete enable (CEN) bit is set. Additionally a ’Transmit Host Initiated’
interrupt vector is generated if the THI bit is set in the transmit descriptor. Afterwards the
data management unit the MUNICH256FM branches to the next transmit descriptor.
Descriptor hold operation
The data transfer is controlled by the HOLD bit, which is located in the first DWORD of
a transmit descriptor. The HOLD bit indicates that the marked descriptor is the last
descriptor in a linked list. The data management unit will not branch to the next descriptor
until the hold condition is removed or a ’Transmit Abort’ command forces the
MUNICH256FM to branch to a new linked list.
If the HOLD bit and the frame end bit are set together in a descriptor, the data
management unit transfers all data of the belonging data section to the transmit buffer
and optionally sets the C-bit in the current transmit descriptor. When a new data transfer
is requested (either from the transmit buffer or an open request) the data management
unit repolls the descriptor. If the HOLD bit is removed, it will branch to the next transmit
descriptor. If the HOLD bit is still set, that channel is suspended for further operation.
Following requests from the transmit buffer will not be served, but the number of
requested data is stored in the open request registers.
Preliminary Data Sheet
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Functional Description
If the HOLD bit is detected in a descriptor and the frame end bit is not set, the data
management unit will transfer all data of the belonging data section to the transmit buffer.
Afterwards it generates a ’Hold Caused Transmit Abort’ interrupt vector in order to inform
the host CPU about the erroneous descriptor structure. In PPP and HDLC mode the
abort status is propagated to the transmit buffer and the protocol machine, so that a abort
sequence is sent on the serial side. In TMA mode the data management unit generates
a ’Hold Caused Transmit Abort’ interrupt vector every time it recognizes the HOLD bit.
Then it reads the transmit descriptor once more. If the HOLD bit is removed it branches
to the next transmit descriptor and proceeds with normal operation. Otherwise, when the
HOLD bit is still set, the channel is suspended for further operation and an internal poll
bit is set. Following requests from the transmit buffer will not be served, but the number
of requested data is stored in the open request register.
The host CPU can remove the hold condition, when the next transmit descriptor is
available in system memory. Therefore the CPU has to execute a ’Transmit Hold Reset’
command, which will reactive the channel. When the transmit buffer requests a new data
transfer or when open request are stored in the on-chip database the data management
unit repolls the transmit descriptor and checks the HOLD bit again. If the HOLD bit is
removed it branches to next transmit descriptor.
If the CPU issues a ’Transmit Hold Reset’ command and does not remove the HOLD bit
(erroneous programming), no action will take place. Nevertheless, the CPU always has
to issue a ’Transmit Hold Reset’ command when it removes the HOLD bit in a descriptor,
no matter the data management unit has already seen the HOLD bit or not.
4.3.6
Byte Swapping
The MUNICH256FM operates per default as a little endian device. To support integration
into big endian environments, the data management unit provides an internal byte
swapping mechanism, which can be enabled via bit CONF1.LBE.
The big endian swapping applies only to the data section pointed to by the receive and
transmit descriptors in the shared memory.
Note: Byte swapping only effects the organization of packet data in system memory. All
internal registers, as well as the descriptors, address pointers or interrupt vectors
are handled with little endian byte ordering.
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Functional Description
Table 4-3
Example for little/big Endian with BNO = 3
Little Endian
BNO
Big Endian
3
-
Byte 2 Byte 1 Byte 0 Byte 0 Byte 1 Byte 2
-
Table 4-4
Example for little big Endian with BNO = 7
Little Endian
BNO
Big Endian
7
Byte3
-
Byte 2 Byte 1 Byte 0 Byte 0 Byte 1 Byte 2
Byte 6 Byte 5 Byte 4 Byte 4 Byte 5 Byte 6
Byte3
-
4.3.7
Transmission Bit/Byte Ordering
Data is transmitted beginning with byte zero in increasing order. Vice versa data
received is stored starting with byte zero. The position of byte zero depends on the
selected endian mode.
Each byte itself consists of eight bits starting with bit zero (LSB) up to bit seven (MSB).
Data on the serial line is transmitted starting with the LSB. The first bit received is stored
in bit zero.
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Functional Description
4.4
Buffer Management
4.4.1
Internal Receive Buffer
The internal receive buffer provides buffering of frame data and status between the
protocol handler and the receive data management units. Internal buffers are essential
to avoid data loss due to the PCI bus latency, especially in the presence of multiple
devices on the same PCI bus, and to enable a minimized bus utilization through burst
accesses.
The incoming data from the protocol handler is stored in a receive central buffer shared
by all the 256 channels. The buffer is written by the protocol handler every time a
complete DWORD is ready or the last byte of a frame has been received. Each channel
has an individual programmable threshold code, which determines after how many
DWORDs a data transfer into the shared memory is generated. The threshold therefore
defines the maximum burst length for a particular channel in receive direction. A data
transfer is also requested as soon as a frame end has been reached. Programming the
burst length to be greater than 1 DWORD avoids too frequent accesses to the PCI bus,
thereby optimizing use of this resource.
For real time channels with lowest possible latency (example: constant bit rate) a value
of one DWORD can be selected for the burst length.
The total size of the internal receive buffer is 12 kByte. If all the 256 channels are active,
the average burst threshold should be programmed with 8 DWORDs, so that 4 DWORDs
are available on the average to compensate for PCI latency and avoid data loss.
However if less than 256 channels are active or if only 64 KBit/s channels are used, the
burst threshold may be programmed to a higher value. In other words, the sum of all
channel thresholds shall not exceed the maximum receive buffer locations.
In order to prevent an overload condition from one particular channel (e.g. receiving only
small or invalid frames), the receive buffer provides the capability to delete frames which
are smaller or equal than a programmable threshold. All frames that have been dropped
will be counted and an interrupt vector will be generated as soon as a programmable
threshold has been reached. The actual value of the counter can be read in the small
frame dropped counter register.
Preliminary Data Sheet
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Functional Description
•
protocol machine
protocol machine
receive buffer
receive buffer
receive burst threshold
receive burst threshold
receive burst threshold
frame
minimum frame length
minimum frame length
frame
data management unit
data management unit
Example A:
Example B:
Normal operation
Drop of small frames
Figure 4-7
Receive Buffer Thresholds
For performance monitoring the receive buffer provides the capability to monitor the
receive buffer utilization and to generate interrupts when certain fill thresholds have been
reached.
4.4.2
Internal Transmit Buffer
The internal transmit buffer with a total size of 32 kByte stores protocol data before it is
processed by the protocol machine. The transmit buffer is essential to ensure that
enough data is available during transmission, since PCI latency and usage of multiple
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Functional Description
channels limit access to system memory for a particular channel. A programmable
transmit buffer size and two programmable threshold are configurable by the host CPU
for each channel.
Note: The sum of both thresholds must be smaller than the transmit buffer size of a
particular channel.
•
protocol machine
request new data as long
as number of empty
l o c a t i on s i s a b o v e
transmit buffer
transmit refill threshold
transmit refill threshold
programmable number of
buffer locations per
channel
transmit forward threshold
wait with data trans-
mission until buffer level
reaches transmit forward
threshold
frame
data management unit
Figure 4-8
Transmit Buffer Thresholds
The threshold values have the following effect:
• Data belonging to one channel stored in the internal transmit buffer will only be
transferred to the protocol machine when the transmit forward threshold is reached or
if a complete frame is stored inside the transmit buffer. This mechanism avoids data
underrun conditions.
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Functional Description
• As long as the amount of data stored in the transmit buffer is below the transmit refill
threshold the data management unit will keep filling the buffer by initiating PCI burst
transfers.
Note: Since there is a delay between the time the transmit buffer requests data from the
data management unit and the time the data management unit serves the request,
the actual number of empty locations may be higher than the transmit refill
threshold. To determine the maximum PCI burst length an additional parameter is
available which limits these requests up to a maximum of 64 DWORDs.
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Functional Description
4.5
Protocol Description
The protocol machines provide protocol handling for up to 256 channels. The protocol
machines implement 4 modes, which can be programmed independently for each
channel: HDLC, bit-synchronous PPP, octet-synchronous PPP and transparent mode A.
The configuration of each logical channel is programmed via the PCI bus and will be
stored inside the protocol machines. Furthermore the current state for the protocol
processing (CRC check, 1 bit count,...) is also stored inside the protocol machines.
Each protocol machine (receive, transmit) handles a maximum of 256 channels and a
maximum aggregate bit rate of up to 45 Mbit/s.
4.5.1
HDLC Mode
•
Address
Control
8 bits
Information
<=0 Bits
CRC
Flag
Flag
8 bits
16/32 bits
0111 1110
0111 1110
Figure 4-9
HDLC Frame Format
The frame begin and frame end synchronization is performed with the flag character
7EH. Shared opening and closing flag is supported in receive direction and can be
programmed in the channel configuration register for transmit direction. Shared ‘0’ bit
between two flags is only supported in receive direction. Interframe time-fill can be
programmed to either flag 7EH or FFH indicating idle.
In receive operation, prior to FCS computation, any ‘0’ bit that directly follows five
contiguous ‘1’ bits is discarded. When closing flag is recognized, a CRC check, octet
boundary check, MFL (maximum frame length) check, a short frame check and an
additional small frame check are performed. Short frames have less than 4 octets if
CRC16 is used or less than 6 octets if CRC32 is used. An aborted frame is recognized
if 7 or more ‘1’s are received.
In transmit operation after the CRC computation a ‘0’ bit is inserted after every sequence
of five contiguous ‘1’ bits. When frame end is indicated in the belonging transmit
descriptor the calculated CRC is transmitted and a flag is generated. If an underrun
occurs in the internal transmit buffer (because of PCI latency e.g.) an abort sequence
with 7 ‘1’s is transmitted and an underrun interrupt is generated. The abort sequence is
also generated if the host CPU resets or aborts a channel during the transmission of a
frame.
An invert option is provided to invert all the data output or data input between serial line
and protocol machines or vice versa.
The following CRC modes are supported:
• 16 bit CRC
1+x5+x12+x16
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Functional Description
• 32 bit CRC
Optionally CRC transfer and check can be disabled.
1+x+x2+x4+x5+x7+x8+x10+x11+x12+x16+x22+x23+x26+x32
4.5.2
Bit Synchronous PPP with HDLC Framing Structure
•
Flag
Address
Control
Protocol
8/16 bits
FCS
Flag
Information
Padding
0111 1110
1111 1111
0000 0011
16/32 bits
0111 1110
Figure 4-10 Bit Synchronous PPP with HDLC Framing Structure
Same as HDLC. The handling of the abort sequence differs from that in HDLC mode. If
7EH is programmed as interframe time fill character, the abort sequence consists of 7
“1”s. If FFH is programmed as interframe time fill character, the abort sequence consists
of 15 “1”s.
The same programmable parameters as in HDLC mode apply to bit synchronous PPP.
4.5.3
Octet Synchronous PPP
This mode uses a frame structure similar to the bit synchronous PPP mode. The frame
begin and end synchronization is performed with the flag character (7EH). Use of a
shared opening and closing flag is supported if programmed in the channel configuration
register. Use of a shared ’0’ bit between two flags is not supported. A 16 or 32 bit CRC
is computed over all service data read from the transmit buffer and appended to the end
of the frame.
The octet synchronous PPP mode uses octet stuffing instead of ‘0’ bit stuffing in order to
replace control characters used by intervening hardware equipment. This allows
transparent transmission and also recognition and removal of spurious characters
inserted by such equipment.
A 32 bit per channel asynchronous control character map (ACCM) specifies characters
in the range 00H-1FH to be stuffed/destuffed in service data and FCS field. In addition,
the DEL control character and any of 4 ACCM extension characters stored in a
programmable 32 bit register can be selected for character stuffing/destuffing. When a
character specified to be mapped is found in service data or the FCS field, it is replaced
by a 2 octet sequence consisting of 7DH (Control Escape) followed by the character
EXORed with 20H (e.g. 13H is mapped to 7DH 33H). In addition to the per channel
specification of characters to be mapped, the control escape sequence 7DH and 7EH in
the service data stream are always mapped. Opening and closing flags are not affected.
The abort sequence consists of the control escape character followed by a flag character
7EH (not stuffed).
Between two frames, the interframe time fill character is always 7EH.
Preliminary Data Sheet
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Functional Description
If in the transmit direction a data underrun occurs during transmission of a frame and the
frame has not finished, an abort sequence is automatically sent (escape character
followed by a flag) and an underrun interrupt vector will generated. If the transmit buffer
indicates an empty condition for a channel between two frames (idle or interframe fill),
the protocol machine will continue to send interframe time fill characters. Also an abort
sequence will be generated if a channel is reset or an abort command is issued during
transmission of a frame.
The following CRC modes are supported:
• 16 bit CRC
• 32 bit CRC
1+x5+x12+x16
1+x+x2+x4+x5+x7+x8+x10+x11+x12+x16+x22+x23+x26+x32
CRC computation/check or removing can be disabled.
4.5.4
Transparent Mode
When programmed in transparent mode, the protocol machine performs fully
transparent data transmission/reception without HDLC framing, i.e. without
• Flag insertion/removing
• CRC generation/CRC check
• Bit stuffing/destuffing (0 bit insertion/removal).
An option ‘Transparent Mode Pack’ is provided to support subchanneling. If
subchanneling is used (logical channels of less than 64 kbit/s), masked bits in the
protocol data are set high and each bit in shared memory maps directly to enabled (not
masked) bits on the serial line. Otherwise they contain protocol data, that is each byte in
shared memory maps directly to a time slot.
A programmable transparent flag can be programmed which will be inserted between
payload data or is removed during reception of a payload data.
An invert option is provided to invert the outgoing or incoming data stream.
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Functional Description
4.6
T1 Framer and FDL Function
The T1 framer includes frame alignment, CRC-6 check/generation, facility data link
(FDL) support and bit error rate test. Three modes can be programmed for each T1 link:
F4, ESF (F24), SF (F12).
4.6.1
4-Frame Multiframe
The allocation of the FT bits (bit 1 of frames 1 and 3) for frame alignment signal is shown
in Table 4-5.
The FS bit may be used for signaling.
Remote alarm (yellow alarm) is indicated by setting bit(2) to ‘0’ in each channel.
Table 4-5
4-Frame Multiframe Structure.
Frame Number
FT
FS
1
2
3
4
1
–
0
–
Service bit
Service bit
Synchronization Procedure
For multiframe synchronization, the terminal framing bits (FT bits) are observed. The
synchronous state is reached if at least one terminal framing candidate is definitely
found, or the synchronizer is forced to lock onto the next available candidate
(RCMDR.FRS).
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Functional Description
4.6.2
ESF Mode
The ESF multiframe consists of 24 consecutive frames. The first bit of each frame (F bit)
is used as frame alignment, data link channel and CRC-6 channel (see Table 4-6).
Table 4-6
ESF Multiframe Structure
F bits
Cyclic
redundancy
check
Framing Pattern
Frame
number
Superframe
bit number
Data link
(DL)
Sequence
(FPS)
(CRC-6)
1
2
0
-
-
m
-
-
c1
-
193
3
386
-
m
-
4
579
0
-
-
5
772
m
-
-
6
965
-
c2
-
7
1158
1351
1544
1737
1930
2123
2316
2509
2702
2895
3088
3281
3474
3667
3860
4053
-
m
-
8
0
-
-
9
m
-
-
10
11
12
13
14
15
16
17
18
19
20
21
22
-
c3
-
-
m
-
1
-
-
m
-
-
-
c4
-
-
m
-
0
-
-
m
-
-
-
c5
-
-
m
-
1
-
-
m
-
-
-
c6
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Functional Description
23
24
4246
4439
-
m
-
-
-
1
Frame 1 is transmitted first. Bit 1 (most significant bit) of each frame is transmitted first.
4.6.2.1 Multiframe Synchronization Procedure of the Receiver
The F-bit of every fourth frame forms the pattern 001011. This multiframe alignment
allows to identify where each particular frame is located within the multiframe in order to
extract the cyclic redundancy check code (CRC-6) and the data link information.
In the synchronous state two errors within 4 or 5 framing bits, two or more erroneous
framing bits within one ESF multiframe or 4 consecutive errored multiframes will lead to
the asynchronous state.
There are two multiframe synchronization modes selectable via RFMR.SSP:
0
In the synchronous state, the setting of RCMDR.FRS resets the synchronizer
and initiates a new frame search. The synchronous state will be reached again,
if there is only one definite framing candidate. In the case of repeated apparent
simulated candidates, the synchronizer remains in the asynchronous state.
In asynchronous state, setting bit RCMDR.FRS induces the synchronizer to
lock onto the next available framing candidate if there is one. At the same time
the internal framing pattern memory will be cleared and other possible framing
candidates are lost.
1
In the synchronous state, the setting of RCMR.FRS resets the synchronizer and
initiates a new frame search. Synchronization is achieved if there is only one
definite framing candidate AND the CRC-6 checksum is received without an
error. If the CRC-6 check failed on the assumed framing pattern the
MUNICH256FM will stay in the asynchronous state, searching for an alternate
framing pattern.
In case no alternate framing pattern can be found, setting bit RCMDR.FRS
starts a totally new multiframe search. At the same time the internal framing
pattern memory will be cleared and other possible framing candidates are lost.
4.6.2.2 CRC-6 Generation / Check according to ITU-T G.706
Generation
In calculating the CRC-6 bits, the F-bits are replaced by binary 1s. All information in the
other bit positions will be identical to the information in the corresponding multiframe bit
positions.
The CRC-6 bit sequence c1, c2, c3, c4, c5, c5 and c6 calculated on multiframe N is
transmitted in multiframe N+1. This CRC polynomial is defined as the remainder after
Preliminary Data Sheet
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Functional Description
multiplication by x6 and then division (modulo 2) by the generator polynomial x6+x+1 of
the polynomial corresponding to multiframe N. The first check bit c1 is the most
significant bit of the remainder; the last check bit c6 is the least significant bit of the
remainder.
Check
At the receiver, the received multiframe, with each F-bit having first been replaced by a
binary 1, is acted upon by the multiplication/division process described above. The
resulting remainder is compared on a bit-by-bit basis, with the CRC-6 check bits
contained in the subsequently received multiframe.
In synchronous state a received CRC-6 error may generate an interrupt status and will
increment a CRC-6 counter.
4.6.2.3 Remote Alarm (Yellow Alarm) Generation / Detection
Generation
If TFMR.AXRA=1, the remote alarm sequence will be automatically sent in the outgoing
data stream when the receiver is in asynchronous state (FRS.LFA bit is set). Remote
Alarm is also sent unconditionally when TCMDR.XRA=’1’. ESF RA is sent by repeating
the pattern ‘1111 1111 0000 0000’ in the Data Link (DL).
Detection
Remote Alarm (yellow alarm) is detected and flagged with bit FRS.RRA when the pattern
’1111 1111 0000 0000’ is received in the DL bits if RFMR.SRAF=0. If RFMR.SRAF=1,
yellow alarm is detected when every bit2 of each time slot is 0. If RFMR.RRAM is set,
Remote Alarm can be detected even in the presence of BER 1/1000. FRS.RRA will be
reset automatically when the alarm condition is no longer detected.
4.6.2.4 Facility Data Link
The Facility Data Link (FDL) contains bit oriented messages (priority or command/
response) or HDLC-based message oriented signals that are processed by a HDLC
machine. Each T1 port has its dedicated FDL controller. In HDLC mode CRC16 is
supported. Additionally one or two byte address comparison is supported.
Note: CAS - BR (Channel Associated Signalling - bit robbing) is not supported. The
protocol machines support access to 56 kBit/s or 64 kBit/s data channels with their
bit masking function. If CCS (Common Channel Signalling) is used, the
corresponding channel (usually time slot 24) is handled as a standard data time
slot by the HDLC/PPP machine and the data is transferred via the PCI bus.
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Functional Description
In transmit and receive direction 64 byte deep FIFOs divided into two pages of 32 bytes
are provided for the intermediate storage of data between the HDLC machine and the
CPU interface.
Receive Signaling Controller
Each of the signaling controllers may be programmed to operate in various signaling
modes. The MUNICH256FM will perform the following signaling and data link methods
on the DL-Channel of the ESF format:
• HDLC/SDLC Access
In case of common channel signaling the signaling procedure HDLC/SDLC will be
supported. The signaling controller of the MUNICH256FM performs the flag detection,
CRC checking, address comparison and zero bit-removing. Depending on the
selected address mode, the MUNICH256FM may perform a 1 or 2 byte address
recognition. If a 2-byte address field is selected, the high address byte is compared
with two individually programmable values in register RAH. Buffering of receive data
is done in the RFIFO. Refer also to Chapter 4.8.1.
• Transparent Access
In signaling controller transparent mode, fully transparent data reception without
HDLC framing is performed, i.e. without flag recognition, CRC checking or bit-stuffing.
This allows the user specific protocol variations.
• Bit Oriented Messages in ESF-DL Channel
The MUNICH256FM supports the DL-channel protocol for ESF format according to
ANSI T1.403 specification or according to AT&T TR54016. The Bit Oriented Message
(BOM) receiver may be switched on/off separately. If the MUNICH256FM is used for
HDLC formats only, the BOM receiver has to be switched off. If BOM-receiver has
been switched on, an automatic switching between HDLC and BOM mode is enabled.
If eight or more consecutive ones are detected, the BOM mode is entered. Upon
detection of a flag in the data stream, the MUNICH256FM switches back to HDLC-
mode. In BOM-mode, the following byte format is assumed (the left most bit is
received first).
111111110xxxxxx0
The MUNICH256FM uses the FFH byte for synchronization, the next byte is stored in
RFIFO (first bit received: LSB) if it starts and ends with a ‘0’. Bytes starting or ending
with a ‘1’ are not stored. If there are no 8 consecutive one’s detected within 32 bits and
the MUNICH256FM is currently in the BOM mode, an interrupt is generated. However,
byte sampling is not stopped.
Transmit Signaling Controller
Similar to the receive signaling controller the same signaling method is provided. The
MUNICH256FM will perform the following signaling and data link methods on the DL-
channel of the ESF format:
Preliminary Data Sheet
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Functional Description
• HDLC access
The transmit signaling controller of the MUNICH256FM performs the FLAG
generation, CRC generation, zero bit-stuffing and programmable IDLE code
generation. Buffering of transmit data is done in the 2x32 byte deep transmit FIFO.
The signaling information will be internally multiplexed with the data applied to the
outgoing ports.
• Transparent/BOM mode
In signaling controller transparent mode, fully transparent data transmission without
HDLC framing is performed. Optionally the MUNICH256FM supports the continuous
transmission of the XFF.XFIFO contents with a maximum of 32 bytes.
Operating in HDLC or BOM mode “flags” or “idle” may be transmitted as interframe time-
fill.
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Functional Description
4.6.3
SF Mode
The SF multiframe consists of 12 consecutive frames. The first bit of each frame (F-bit)
the MUNICH256FMis used as frame alignment (see following table).
Table 4-7
SF Multiframe Structure
F-bits
Frame
number
Superframe bit Terminal Framing (Ft) Signaling Framing (Fs)
number
1
2
0
1
-
-
0
-
193
3
386
0
-
4
579
0
-
5
772
1
-
6
965
1
-
7
1158
1351
1544
1737
1930
2123
0
-
8
1
-
9
1
-
10
11
12
1
-
0
-
0
The Fs-bits are used to get a higher synchronization probability but no CAS - BR
(Channel Associated Signalling - bit robbing) is supported. Only frame alignment is
provided in this mode.
4.6.3.1 Synchronization Procedure of the Receiver
In the synchronous state terminal framing (Ft-bits) and multiframing (Fs-bits) are
observed, independently. Further reaction on framing errors depends on the selected
synchronization/resynchronization procedure (via bit RFMR0.SSP):
0
Terminal frame and multiframe synchronization are combined. Two errors
within 4/5/6 Ft-bits or two errors within 4/5/6 in Fs-bits (via bits RFMR.SSC) will
lead to the asynchronous state for terminal framing and multiframing.
Additionally to the bit FRS.LFA, loss of multiframe alignment is reported via bit
FRS.LMFA. The resynchronization procedure starts with synchronizing upon
the terminal framing. If the pulseframing has been regained, the search for
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Functional Description
multiframe alignment is initiated. Multiframe synchronization has been regained
after two consecutive correct multiframe patterns have been received.
1
Terminal frame and multiframe synchronization are separated. Two errors
within 4/5/6 terminal framing bits will lead to the same reaction as described
above for the ’combined’ mode. Two errors within 4/5/6 multiframing bits will
lead to the asynchronous state only for the multiframing. Loss of multiframe
alignment is reported via bit FRS.LMFA. The state of terminal framing is not
influenced. Now, the resynchronization procedure includes only the search for
multiframe alignment. Multiframe synchronization has been regained after two
consecutive correct multiframe patterns have been received.
4.6.3.2 Remote Alarm (Yellow Alarm) Generation / Detection
There are two possibilities of remote alarm (yellow alarm) indication:
• Bit 2 = ’0’ in each time slot of the frame, selected with bit R/TFMR.SRAF = 0
• The last bit of the multiframe alignment signal (bit 1 of frame 12) changes from ’0’ to
‘1’, selected with bit R/TFMR.SRAF = 1.
Generation
If TFMR.AXRA=1, the remote alarm sequence will be automatically sent in the outgoing
data stream when the receiver is in asynchronous state (FRS.LFA bit is set). Remote
Alarm is also sent unconditionally when TCMDR.XRA = 1.
Detection
Remote alarm (yellow alarm) is detected and flagged with bit FRS.RRA which will be
reset automatically when the alarm condition is no longer detected.
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Functional Description
4.6.4
Common Features for SF and ESF
4.6.4.1 AIS (Blue Alarm) Generation/Detection
Generation
The alarm indication signal is an all one unframed signal and will be transmitted if
enabled via bit TCMDR.XAIS.
Detection
The detection of AIS is done, if 2 or less ’0’s are detected in a multiframe. This condition
is flagged by bit FRS.AIS. AIS detection can also only be enabled in asynchronous state
by bit RFMR0.AIS3. In this case AIS is indicated if three or less zeros within a time
interval of 12 frames (in SF mode), or if five or less zeros within a time interval of 24
frames (ESF mode) are detected in the received bit stream.
4.6.4.2 Loss of Signal (Red Alarm) Detection
The MUNICH256FM can be programmed to satisfy the different definitions for detecting
Loss of Signal (LOS) alarms in ITU-T G.775 and AT&T TR54016. Loss of signal is
indicated by a flag in the receive framer's status register (FRS.LOS). In addition, a ’Loss
of Signal Status’ interrupt vector is generated, if not masked.
LOS detection and recovery conditions are set by a flag RFMR.LOSR and the two
parameters PCD and PCR.
Detection
’Loss of Signal’ alarm will be generated, if the incoming data stream has no pulses (no
’1’) for a certain number N of consecutive bits. ’No pulse’ in the receive interface means
a logical zero octet on receive data inputs. The number N can be set via register PCD
and is calculated as 8*(PCD+1).
Recovery
The recovery procedure starts after detecting a logical ’1’ in the received bit stream. The
value via register PCR defines the number of pulses, which must occur during the time
interval 8*(PCD+1), to clear the LOS alarm.
Additionally, if selected via RFMR.LOSR, any pulse density violation resets the
measurement interval. I.e. in addition to the basic pulse density required for recovery, a
density of at least N ‘1’s in every N+1 octets (0 < N < 24) is required during 8*(PCD+1)
bit intervals.
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Functional Description
4.6.4.3 In-Band Loop Generation and Detection
The MUNICH256FM generates and detects a framed or unframed in-band loop up/
actuate (00001) and down/deactuate (001) pattern according to ANSI T1.403 even in the
presence of bit error rates as high as 1/100. Replacing the transmit data with the in-band
loop codes is done by TCMDR.XLD / XLU for actuate or deactuate loop code.
The CPU must reset this bit to 0 for normal operation (no loop-back code). The
MUNICH256FM also offers the ability to generate and detect a flexible in-band loop up/
actuate and down/deactuate pattern. The loop up and down pattern is individual
programmable in the Loop Code Register from 5 to 8 bits in length.
Status and interrupt-status bits will inform the user whether Loop Actuate- or Deactuate
code was detected, but the CPU must activate the loop-back.
4.6.4.4 Pulse Density Detection
The framer examines the receive data stream of each port on the pulse density
requirement defined by ANSI T1. 403. More than 15 consecutive zeros or less than N
ones in each and every time window of 8(N+1) data bits, where N=23 will be detected.
Violations of these rules are indicated by setting the status bit FRS.PDEN. Moreover the
PDEN bit in the interrupt vector will be set.
4.6.4.5 Error Performance Monitoring
The MUNICH256FM supports the error performance monitoring by detecting following
alarms in the received data.
• Framing errors
• CRC errors
• Loss of frame alignment
• Loss of signal
• Alarm indication signal
Loss of frame alignment, Loss of signal and AIS are indicated with interrupt status bits.
With a programmable interrupt mask (register IMR) all these error events could generate
an Errored Second interrupt (ES) if enabled. Additionally a one Second interrupt could
be generated to indicate that the ES interrupt has to be read. If the ES interrupt is set the
enabled alarm status bits or the error counters have to be examined.
The following counters are implemented in the T1 framer:
• Framing Error Counter: This counter will be incremented when incorrect FT and FS
bits in SF mode or incorrect FPS bits in ESF format are received. Framing errors will
not be counted during asynchronous state.
• CRC Error Counter (Only ESF mode): The counter will be incremented when a
multiframe has been received with a CRC error. CRC errors will not be counted during
asynchronous state.
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Functional Description
• Errored block counter: This counter will be incremented, if a multiframe has been
received with framing errors or CRC errors (ESF only).
Clearing and updating of the counters is done according to bit RFMR1.ECM. If this bit is
reset, the error counter is permanently updated. Reading of actual error counter status
is always possible. The error counters are reset by reading the corresponding status
register. If RFMR1.ECM is set, every second the error counter will be latched and then
automatically reset. The latched error counter state should be read within the next
second.
4.6.4.6 Pseudo-random Bit Sequence Generator and Monitor
A Pseudo-random bit sequence (PRBS) generator and monitor according to ITU O.151
can be activated for one particular logical channel. The PRBS pattern type can be
selected as 215-1 or 220-1 via R/TPRBSC.PRP. Moreover, the number of the time slots
which should be used for PRBS can be defined in R/TPTSL register.
Additionally a fixed pattern can be programmed via registers R/TFPR0 and R/TFPR1
with length up to 32 bit to be defined in R/TPRBSC.FPL.
The PRBS monitor searches synchronization on the inverted and non-inverted PRBS
pattern. The current synchronization status is reported in status and interrupt status
registers. Each PRBS bit error will increment an error counter. An additional counter will
accumulate the total number of received bits. Synchronization will be reached within 400
ms with a probability of 99.9% and a BER of 1/10.
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Functional Description
4.7
E1 Framing and Signaling
The operating mode of the MUNICH256FM is selected by programming the carrier data
rate and characteristics, multiframe structure, and signaling scheme.
The MUNICH256FM implements the standard framing structures for E1 or PCM 30
(CEPT, 2048 Kbit/s) carriers. The internal HDLC controller supports signaling
procedures like signaling frame synchronization/synthesis and signaling alarm detection
in all framing formats.
Summary of E1- Framing Modes:
• Doubleframe format according to ITU-T G. 704.
• Multiframe format according to ITU-T G. 704
CRC-4 processing according to ITU-T G. 706.
• Multiframe format with CRC-4 to non CRC-4 interworking according to ITU-T G. 706.
After reset, the MUNICH256FM is switched into doubleframe format automatically.
Switching between the framing formats is done via bit T/RFMR.FM
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Functional Description
4.7.1
Doubleframe Format
The framing structure is defined by the contents of time-slot 0 (refer to Table 4-8).
Table 4-8
Allocation of Bits 1 to 8 of Time slot 0
Bit
1
2
3
4
5
6
7
8
Alternate
Frames
Number
Frame Containing the
Frame Alignment Signal
Si
Si
0
0
1
1
0
1
1
1)
1)
Frame Alignment Signal
Frame not Containing
the Frame Alignment
Signal
1
A
Sa4
Sa5
Sa6
Sa7
Sa8
2)
3)
4)
1)
Si-bits:
Reserved for international use. They are fixed to ‘1’.
2)
3)
Fixed to ‘1’. Used for synchronization.
Remote alarm indication:
In undisturbed operation ‘0’; in alarm condition ‘1’.
4)
Sa-bits:
Reserved for national use. If not used, they should be fixed at ‘1’. Access to received information
via registers RSAW1-3. Transmission via registers XSAW1-XSAW3. HDLC signalling in bits
Sa4 - Sa8 is selectable.
4.7.1.1 Synchronization Procedure of the Receiver
Synchronization status is reported via bit FRS.LFA. Framing errors are counted by the
Framing Error Counter (FEC). Asynchronous state is reached after detecting 3 or 4
consecutive incorrect FAS words or 3 or 4 consecutive incorrect service words (bit 2 = 0
in time-slot 0 of every other frame not containing the frame alignment word), the
selection is done via bit RFMR.SSC. Additionally, the service word condition can be
disabled. When the framer lost its synchronization an status bit FRS.LFA is generated.
In asynchronous state, counting of framing errors will be stopped.
The resynchronization procedure starts automatically after reaching the asynchronous
state. Additionally, it may be invoked user controlled via bit RCMDR.FRS (Force
Resynchronization: the FAS word detection is interrupted. In connection with the above
conditions this will lead to asynchronous state. After that, resynchronization starts
automatically).
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Functional Description
Synchronous state is established after detecting:
• a correct FAS word in frame n,
• the presence of the correct service word (bit 2 = 1) in frame n + 1,
• a correct FAS word in frame n + 2.
If the service word in frame n + 1 or the FAS word in frame n + 2 or both are not found
searching for the next FAS word will be start in frame n + 2 just after the previous frame
alignment signal.
Reaching the asynchronous state causes the removal of FSR.LFA and additionally an
interrupt vector with LFA bit reset (if not masked). Undisturbed operation starts with the
beginning of the next doubleframe.
4.7.1.2 A-bit Access
If the MUNICH256FM detects a remote alarm indication in the received data stream the
interrupt status bit FRS.RRA will be set.
By setting TFMR.AXRA the MUNICH256FM automatically transmits the remote alarm
bit = 1 in the outgoing data stream if the receiver detects a loss of frame alignment
FRS.LFA = 1. If the receiver is in synchronous state FRS.LFA = 0 the remote alarm bit
will be reset.
4.7.1.3 Sa-bit Access
The MUNICH256FM allows access to the Sa-bits via registers RSAW1-3 and XSAW1-3.
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Functional Description
4.7.2
CRC-4 Multiframe
The multiframe structure shown in Table 4-9 is enabled by setting TFMR.FM for the
transmitter and RFMR.FM for the receiver.
Multiframe
: 2 submultiframes = 2 × 8 frames
Frame alignment: refer to Chapter 4.7.1 Doubleframe Format
Multiframe alignment: bit 1 of frames 1, 3, 5, 7, 9, 11 with the pattern ‘001011’
CRC bits
: bit 1 of frames 0, 2, 4, 6, 8, 10, 12, 14
CRC block size: 2048 bit (length of a submultiframe)
CRC procedure: CRC-4, according to ITU-T G.704, G.706
Table 4-9
CRC-4 Multiframe Structure
Sub-
Frame
Bits 1 to 8 of the Frame
Multiframe Number
1
2
3
4
5
6
7
8
Multiframe
I
0
1
2
3
4
5
6
7
C1
0
C2
0
C3
1
C4
0
0
1
0
1
0
1
0
1
0
A
0
A
0
A
0
A
1
1
0
1
1
Sa4 Sa5 Sa61 Sa7 Sa8
1
Sa4 Sa5 Sa62 Sa7 Sa8
1
Sa4 Sa5 Sa63 Sa7 Sa8
1
Sa4 Sa5 Sa64 Sa7 Sa8
1
0
1
1
1
0
1
1
1
0
1
1
II
8
9
C1
1
C2
1
C3
E
C4
E
0
1
0
1
0
1
0
1
0
A
0
A
0
A
0
A
1
1
0
1
1
Sa4 Sa5 Sa61 Sa7 Sa8
1
Sa4 Sa5 Sa62 Sa7 Sa8
1
Sa4 Sa5 Sa63 Sa7 Sa8
1
Sa4 Sa5 Sa64 Sa7 Sa8
10
11
12
13
14
15
1
0
1
1
1
0
1
1
1
0
1
1
E
Spare bits for international use. E bits are replaced by XSP.XS13 and XSP.XS15 or automatic
transmission for submultiframe error indication.
Sa
Spare bits for national use. Sa-bit access via registers RSAW1-3 and XSAW1-3 is provided.
HDLC-signaling in bits Sa4 - Sa8 is selectable.
C1 … C4
Cyclic redundancy check bits.
A
Remote alarm indication. Automatic transmission of the A-bit is selectable.
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Functional Description
The CRC procedure is automatically invoked when the multiframe structure is enabled.
CRC errors in the received data stream are counted by the 16 bit CRC Error Counter
CEC (one error per submultiframe, maximum).
Additionally a CRC error interrupt vector with CRC set can be generated if enabled.
4.7.2.1 Synchronization Procedure of the Receiver
Multiframe alignment is assumed to have been lost if doubleframe alignment has been
lost (flagged at status bits FRS.LFA and FRS.LMFA). Either edge of these bits will cause
an LFA interrupt.
The multiframe resynchronization procedure starts when Doubleframe alignment has
been regained which is indicated by a FAS interrupt vector. For Doubleframe
synchronization refer to Chapter 4.7.1. It may also be invoked by the user by setting bit
RFMR.FRS for complete doubleframe and multiframe resynchronization.
The CRC checking mechanism will be enabled after the first correct multiframe pattern
has been found. However, CRC errors will not be counted in asynchronous state.
The multiframe synchronous state is established after detecting two correct multiframe
alignment signals at an interval of n × 2 ms (n = 1, 2, 3 …). The loss of multiframe
alignment flag FRS.LMFA will be reset. Additionally a multiframe alignment status
interrupt MFAS is generated on the falling edge of bit FRS.LMFA.
Automatic Force Resynchronization
In addition, a search for Doubleframe alignment is automatically initiated if two
multiframe pattern with a distance of n × 2 ms have not been found within a time interval
of 8 ms after doubleframe alignment has been regained. The new search for frame
alignment will be started just after the previous frame alignment signal.
CRC-4 Interworking Mode
CRC-4 interworking is implemented according to ITU-T G.706 Appendix B. For
operational description refer to Figure 4-11.
4.7.2.2 CRC-4 Performance Monitoring
In the synchronous state checking of multiframe pattern is disabled. However, with bit
RFMR.ALMF an automatic multiframe resynchronization mode can be activated. If 915
out of 1000 errored CRC submultiframes are found then a false frame alignment will be
assumed and a search for double- and multiframe pattern is initiated. The new search
for frame alignment will be started just after the previous basic frame alignment signal.
The internal CRC-4 resynchronization counter will be reset when the multiframe
synchronization has been regained.
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Functional Description
4.7.2.3 A-Bit Access
If the MUNICH256FM detects a remote alarm indication (bit 2 in TS0 not containing the
FAS word) in the received data stream a RAS interrupt will be generated. With the
deactivation of the remote alarm the remote alarm status interrupt with RAS=’0’ is
generated.
By setting TFMR.AXRA the MUNICH256FM automatically transmits the remote alarm
bit = ’1’ in the outgoing data stream if the receiver detects a loss of frame alignment
(FRS.LFA = ’1’). If the receiver is in synchronous state (FRS.LFA = ’0’) the remote alarm
bit will be reset in the outgoing data stream.
Preliminary Data Sheet
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Functional Description
•
Out of primary BFA:
Inhibit incoming CRC-4 performance monitoring
Reset all timers
Set FRS.LFA/LMFA/NMF = 110B.
No
Primary
BFA search ?
Yes
In primary BFA:
Start 400 ms timer
Enable primary BFA (loss checking procedure)
Reset internal frame alignment status
(FRS.LFA = 0)
CRC-4 MFA search
Start 8 ms timer
Yes
Parallel
BFA search
good ?
No
No
Can CRC-4
MFA be found
in 8 ms ?
400 ms
timer
elapsed ?
Yes
No
Yes
Assume CRC-4 to CRC-4 interworking
Confirm primary BFA associated with CRC-4 MFA
Adjust primary BFA if necessary
Assume CRC-4 to non CRC-4 interworking
Confirm primary BFA
Set internal 400 ms timer expiration status bit
(FRS.T400 = 1)
Reset internal multiframe alignment status
(FRS.LMFA = 0)
Start CRC-4 performance monitoring
CRC-4
error count > 914
or LFA
Yes
No
Continue CRC-4 performance monitoring
Figure 4-11 CRC-4 Multiframe Alignment Recovery Algorithms
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Functional Description
4.7.2.4 Sa-bit Access
Due to signaling procedures using the five Sa-bits (Sa4 … Sa8) of every other frame of the
CRC-4 multiframe structure, two possibilities of access via the microprocessor are
implemented.
• The standard procedure, allows reading/writing the Sa-bit registers RSAW1 to RSAW3
and XSAW1 through XSAW3.
Registers RSAW1-3 contains the service word information of the previously received
CRC-4 multiframe or 8 doubleframes (bit slots 4-8 of every service word). These
registers will be updated on every multiframe. Optionally MUNICH256FM provides the
possibility to check the received Sa-data with the Sa-data received earlier. An interrupt
vector is generated on Sa-data change in order to reduce microprocessor bus load.
With the transmit multiframe begin the contents of this registers XSAW1-3 will be
copied into shadow registers. The contents will subsequently sent out in the service
words of the next outgoing CRC-4 multiframe (or doubleframes). The TXSA interrupt
request that these registers should be serviced. If requests for new information will be
ignored, current contents will be repeated.
• The extended access via the receive and transmit FIFOs of the signaling controller. In
this mode it is possible to transmit / receive a HDLC frame or a transparent bit stream
in any combination of the Sa-bits.
Sa-bit Detection according to ETS 300233
Four consecutive received Sa-bits are checked on the by ETS 300233 defined Sa-bit
combinations. The MUNICH256FM can be programmed to detect any bit combination
on one Sa-bit out of Sa4 through Sa8. Enabling of specific bit combination can be done via
register RCR2.SASSM. A valid Sa-bit combination must occur three times in a row. The
corresponding status in register RSAW4 will be set. Register RSAW4 is from type “Clear
on Read”. With any change of state of the selected Sa-bit combinations a ’SSM Data
Valid’ interrupt vector will be generated.
During the basic frame asynchronous state updating of register RSAW4 and interrupt
vector generation is disabled. In CRC-4 multiframe format the detection of the Sa-bit
combinations can be done either synchronous or asynchronous to the submultiframe. In
synchronous detection mode updating of register RSAW4 is done in the multiframe
synch. state. In asynchronous detection mode updating is independent to the multiframe
synchronous state.
Sa-bit Error Indication Counters
The Sa-bit error indication counter CRC1 (16 bits) counts either the received bit
sequence 0001B and 0011B or two user programmable values defined in register VCRC
in every submultiframe on a selectable Sa-bit. In the primary rate access digital section
CRC errors are reported from the TE via Sa6. Incrementing is only possible in the
multiframe synchronous state.
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Functional Description
The Sa-bit error indication counter CRC2 (16 bits) counts either the received bit
sequence 0010B and 0011B or two user programmable values defined in register VCRC
in every submultiframe on a selectable Sa-bit. In the primary rate access digital section
CRC errors detected at T-reference points are reported via Sa6. Incrementing is only
possible in the multiframe synchronous state.
4.7.2.5 E-Bit Access
Due to signalling procedures, the E-bits of frame 13 and frame 15 of the CRC-4
multiframe can be used to indicate received errored submultiframes:
no CRC error : E = ’1’
CRC error
: E = ’0’
Standard Procedure
E-bits of the service word are replaced by values of bit XSP.XS13 and XSP.XS15.
Automatic Procedure
Values programmed in register Status information of received submultiframes is
automatically inserted in E-bit position of the outgoing CRC-4 Multiframe without any
further interventions of the microprocessor.
In the double- and multiframe asynchronous state the E-bits are set to zero. In the
multiframe synchronous state the E-bits are processed according to ITU-T G.704.
Submultiframe Error Indication Counter
The Error Bit Counter counts zeros in E-bit position of frame 13 and 15 of every received
CRC-4 multiframe. This counter option gives information about the outgoing transmit line
if the E-bits are used by the remote end for submultiframe error indication. Incrementing
is only possible in the multiframe synchronous state.
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Functional Description
4.7.3
Common Features for E1 Doubleframe and CRC-4 Multiframe
4.7.3.1 Error Performance Monitoring and Alarm Handling
Alarm detection and generation
Alarm Indication Signal:
Detection and recovery is flagged by bit FRS.AIS and the ’Alarm Indication Signal Status’
interrupt vector. Transmission is enabled via bit TFMR.XAIS.
Loss of Signal:
Detection and recovery is flagged via bit FRS.LOS and a ’Loss of Signal Status’ interrupt
vector.
Remote Alarm Indication:
Detection and release is flagged by bit FRS.RRA and a ’Remote Alarm Status’ interrupt
vector. Transmission is enabled via bit TCMDR.XRA.
Table 4-10 Summary of Alarm Detection and Alarm Release
Alarm
Detection Condition
Clear Condition
Loss of Signal
(LOS)
PCD Register
PCR Register
No transitions (log. zero Programmable amount of ones
octets) in a programmable (1-63) in a progr. time interval of
time interval of 16 - 512 16 - 512 consecutive pulse
consecutive pulse periods. periods. The pulse density is
fulfilled and no more than 15 or 99
contiguous zeros during the
recovery interval are detected.
Alarm Indication
Signal (AIS)
FMR0.ALM = 0:
less than 3 zeros in
FMR0.ALM = 0:
more than 2 zeros in 250 µs and
250 µs and loss of frame frame alignment found
alignment declared
FMR0.ALM = 1:
FMR0.ALM = 1:
more than 2 zeros in each of two
less than 3 zeros in each of consecutive double frame periods
two consecutive double
frame periods
Remote Alarm
(RRA)
bit 3 = 1 in time-slot 0 not set conditions no longer detected.
containing the FAS word
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Functional Description
Automatic remote alarm access
If the receiver has lost its synchronization a remote alarm could be sent if enabled via
TFMR.AXRA to the distant end. The remote alarm bit will be automatically set in the
outgoing data stream if the receiver is in asynchronous state (FRS.LFA bit is set). In
synchronous state the remote alarm bit will be removed.
Error Counter
The MUNICH256FM framer offers four error counters, each of them has a length of 16
bit. They record framing bit errors, CRC-4 bit errors. Updating the buffer is done in two
modes:
- one second boundary
- clear on read
In the one second mode an internal one second timer will update these buffers and reset
the counter to accumulating the error events. The error counter can not overflow. Error
events occurring during reset will not be lost.
Status: Errored Second
MUNICH256FM supports the error performance monitoring by detecting alarms or error
events in the received data.
Loss of frame alignment, including alarm indication signal and loss of signal, as well as
CRC errors could generate an Errored Second interrupt if enabled.
Second Timer
An one-second timer interrupt could be internally generated to indicate that the enabled
alarm status bits or the error counters have to be checked.
4.7.3.2 Loss of Signal Detection
The MUNICH256FM can be programmed to satisfy the different definitions for detecting
Loss of Signal (LOS) alarms in ITU-T G.775 and ETS 300233. Loss of signal is indicated
by a flag in the receive framer's status register (FRS.LOS). In addition, a ’Loss of Signal
Status’ interrupt vector is generated, if not masked.
Detection
’Loss of Signal’ alarm will be generated, if the incoming data stream has no pulses (no
’1’) for a certain number N of consecutive pulse periods. ’No pulse’ in the receive
interface means a logical zero on receive data inputs. The number N can be set via
register PCD and is calculated as 8*(PCD+1).
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Functional Description
Recovery
The recovery procedure starts after detecting a logical ’1’ in the received bit stream. The
value via register PCR defines the number of pulses, which must occur during the time
interval 8*(PCD+1), to clear the LOS alarm.
4.7.3.3 In-Band Loop Generation and Detection
The MUNICH256FM generates and detects a framed or unframed in-band loop up/
actuate (00001) and down/deactuate (001) pattern according to ANSI T1.403 with bit
error rates as high as 1/100. Replacing the transmit data with the in-band loop codes is
done by TCMDR.XLD / XLU for actuate or deactuate loop code.
The CPU must reset this bit to 0 for normal operation (no loop-back code). The
MUNICH256FM also offers the ability to generate and detect a flexible in-band loop up/
actuate and down/deactuate pattern. The loop up and down pattern is individual
programmable in the Loop Code Register from 5 to 8 bits in length.
Status and interrupt-status bits will inform the user whether Loop Up - or Loop Down
code was detected, but the CPU must activate the loop-back.
4.7.3.4 Pseudo-random Bit Sequence Generator and Monitor
A Pseudo-random bit sequence (PRBS) generator and monitor according to ITU O.151
can be activated for one particular logical channel. The PRBS pattern type can be
selected as 215-1 or 220-1 via R/TPRBSC.PRP. Moreover, the number of the time slots
which should be used for PRBS can be defined in R/TPTSL register.
Additionally a fixed pattern can be programmed via registers R/TFPR0 and R/TFPR1
with length up to 32 bit to be defined in R/TPRBSC.FPL.
The PRBS monitor searches synchronization on the inverted and non-inverted PRBS
pattern. The current synchronization status is reported in status and interrupt status
registers. Each PRBS bit error will increment an error counter. An additional counter will
accumulate the total number of received bits. Synchronization will be reached within 400
ms with a probability of 99.9% and a BER of 1/10.
Preliminary Data Sheet
96
11.99
PEB 20256M E
PEF 20256M E
Functional Description
Alarm Simulation
Alarm simulation does not affect the normal operation of the device, i.e. all channels
remain available for transmission. However, possible ‘real’ alarm conditions are not
reported to the processor or to the remote end when the device is in the alarm simulation
mode.
The alarm simulation is initiated by setting different code words in bit field FMR0.SIM.
The following alarms are simulated:
• Loss of Signal
• Alarm Indication Signal (AIS)
• Auxiliary pattern
• Loss of pulse frame
• Remote alarm indication
• Framing error counter
• CRC-4 error counter
• E-Bit error counter
Some of the above indications are only simulated if the MUNICH256FM is configured in
a mode where the alarm is applicable (e.g. no CRC-4 error simulation when doubleframe
format is enabled).
Setting a code word in bit field FMR0.SIM initiates alarm simulation. Error counting and
indication will occurs while this bit is set. After it is reset all simulated error conditions
disappear.
Preliminary Data Sheet
97
11.99
PEB 20256M E
PEF 20256M E
Functional Description
4.8
Signaling Controller Protocol Modes
The signalling controller provides access to the data link and Sa bits of the T1/E1
signaland it provides access to the far end alarm and control channel (FEAC) and the C-
bit parity path maintenance data link channel. It operates in HDLC, BOM or automatic
modes.
4.8.1
HDLC Mode
In HDLC mode the transmit signaling controller of the MUNICH256FM performs the
FLAG generation, CRC generation, zero bit-stuffing and programmable IDLE code
generation. Buffering of transmit data is done in the 2x32 byte deep transmit FIFO. The
signaling information will be internally multiplexed with the data applied to the outgoing
ports and is inserted in or extracted from the DL-Bits in T1 ESF mode or the Sa-bits in E1
modes. Any sequence of Sa-bits can be specified for protocol insertion.
Shared Flags
The closing flag of a previously transmitted frame simultaneously becomes the opening
flag of the following frame if there is one to be transmitted. The Shared Flag feature is
enabled by setting XCR1.SF.
CRC check
As an option in HDLC mode the internal handling of received and transmitted CRC
checksum can be influenced via control bits RCR1.XCRC and XCR1.DISCRC.
• Receive Direction
The received CRC checksum is always assumed to be in the last two bytes of a frame,
immediately preceding a closing flag. If RCR1.XCRC is set, the received CRC
checksum will be written to RFIFO where it precedes the frame status byte. The
received CRC checksum is additionally checked for correctness.
• Transmit Direction
If XCR1.DISCRC is set, the CRC checksum is not generated internally. The checksum
has to be provided via the transmit FIFO (XFF.XFIFO) as the last two bytes. The
transmitted frame will only be closed automatically with a (closing) flag.
The MUNICH256FM does not check whether the length of the frame, i.e. the number of
bytes to be transmitted makes sense or not.
Address comparison
An optional address comparison feature forwards all frames which match a
programmable address to the receive FIFO. Frames not matching the address are
discarded.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Functional Description
If a 2-byte address field is selected, the high address byte is compared with two
individually programmable values defined in register RAH. Similarly, two values can be
programmed in register RAL for the low address byte. A valid address is recognized
when the high byte and the low byte of the address field correspond to one of the
compare values. Thus, the MUNICH256FM can be called (addressed) with 4 different
address combinations.
In case of a 1-byte address, RAL will be used as compare registers. The HDLC control
field, data in the I-field and an additional status byte are temporarily stored in the receive
FIFO.
Preamble Transmission
If enabled, a programmable 8-bit pattern XCR1.PBYTE is transmitted with a selectable
number of repetitions after interframe time-fill transmission is stopped and a new frame
is ready to be sent out.
Zero Bit Insertion is disabled during preamble transmission. To guarantee correct
function the programmed preamble value should be different from Receive Address Byte
values.
4.8.2
Transparent Mode
In transparent mode, fully transparent data transmission/reception without HDLC
framing is performed, i.e. without FLAG generation/recognition, CRC generation/check,
or bit-stuffing. This feature can be profitably used e.g for:
• Specific protocol variations
• Test purposes
Data transmission is always performed out of the transmit FIFO (XFF.XFIFO). In
transparent mode receive data is shifted into the receive FIFO without protocol
processing.
If the transparent mode is selected, the MUNICH256FM supports the continuous
transmission of the contents of the transmit FIFO.
After having written 1 to 32 bytes to transmit FIFO, the command HND via the CMDR
register forces the MUNICH256FM to repeatedly transmit the data stored in transmit
FIFO to the remote end.
The cyclic transmission continues until a reset command (HND. SRES) is issued or with
resetting CMDR.XREP, after which continuous ‘1’-s are transmitted.
4.8.3
BOM Mode
The signalling controller supports the DL channel protocol for ESF format according to
ANSI T1.403 or according to AT&T TR54016. The Bit Oriented Message (BOM) receiver
can be switched on or off separately. If the signalling controller is used for HDLC formats
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Functional Description
only, the BOM receiver has to be switched off (RCR1.BRAC = ’0’). If HDLC and BOM
receiver are switched on, an automatic switching between HDLC and BOM mode is
done, which depends on the received bit sequence ( 01111110B or 11111111B). If eight
or more consecutive ones are detected, the BOM mode is entered automatically. Upon
detection of a flag in the data stream, the FDL-Macro switches back to HDLC-mode.
Once in BOM mode, if eight consecutive ones are not detected in 32 bits, a BOM header
error will be declared.
Transmission of BOM data is done via the transparent mode of the signalling controller.
BOM Regular Mode
The following byte format is assumed (the left most bit is received first):
111111110xxxxxx0B
The signalling controller uses the FFH byte for synchronization, the next byte is stored in
the receive FIFO (first bit received: LSB) if it starts and ends with a ‘0’. Bytes starting or
ending with a ‘1’ are not stored. If there are no 8 consecutive one’s detected within 32
bits and the FDL-Macro is currently in the BOM mode, an ’Incorrect Synchronization
Format’ interrupt vector is generated. However, byte sampling is not stopped.
After detecting an HDLC flag, byte sampling is stopped, the receive status byte marking
a BOM frame is stored in the receive FIFO and a ’Receive Message End’ interrupt vector
is generated.
Byte sampling may be stopped by deactivating the BOM receiver (RCR1.BRAC). In this
case the receive status byte marking a BOM frame is added, a ’Receive Message End’
interrupt vector is generated and HDLC mode is entered.
BOM Filter Mode
In BOM filter mode the received BOM data is validated and then filtered. If same valid
BOM pattern is received for 7 out of 10 patterns, then BOM data is written to the receive
FIFO along with the status byte indicating that filtered BOM data was received.
Filtered BOM mode will be exited if one of the following conditions occurs:
• 4 valid BOM patterns are consecutively received but none of these equals the BOM
data received earlier.
• 4 times idle pattern is received.
• A HDLC flag is received.
4.8.4
Sa-bit Access
The MUNICH256FM supports the Sa-bit signaling of time-slot 0 of the T1/E1 signals in
several ways. The access via registers RSAW and XSAW, capable of storing the
information for a complete multiframe, and the most effective one is the access via the
receive/transmit FIFOS of the integrated signaling controller.
Preliminary Data Sheet
100
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PEB 20256M E
PEF 20256M E
Functional Description
The extended Sa-bit access gives the opportunity to transmit/receive a transparent bit
stream as well as HDLC frames where the signaling controller automatically processes
the HDLC protocol.
Data written to the transmit FIFO will subsequently be transmitted in the selected Sa-bit
positions. Any combination of Sa-bits can be selected. After the data have been
completely sent out an “all ones” or flags will be transmitted. The continuous
transmission of a transparent bit stream, which is stored in the XFF.XFIFO, can be
enabled.
The access to and from the FIFOs is supported by status and interrupts.
Sa-Bit Detection according to ETS 300233
Four consecutive received Sa-bits are checked on the by ETS 300233 defined Sa-bit
combinations. The MUNICH256FM can be programmed to detect any bit combination
on one Sa-bit out of Sa4 through Sa8. Enabling of specific bit combination can be done via
register RCR2.SASSM. A valid Sa-bit combination must occur three times in a row. The
corresponding status in register RSAW4 will be set. Register RSAW4 is from type “Clear
on Read”. With any change of state of the selected Sa-bit combinations a ’SSM Data
Valid’ interrupt vector will be generated.
During the basic frame asynchronous state updating of register RSAW4 and interrupt
vector generation is disabled. In CRC-4 multiframe format the detection of the Sa-bit
combinations can be done either synchronous or asynchronous to the submultiframe. In
synchronous detection mode updating of register RSAW4 is done in the multiframe
synch. state. In asynchronous detection mode updating is independent to the multiframe
synchronous state.
Sa-bit Error Indication Counters
The Sa-bit error indication counter CRC1 (16 bits) counts either the received bit
sequence 0001B or 0011B or user programmable values in every submultiframe on a
selectable Sa-bit. In the primary rate access digital section CRC errors are reported from
the TE via Sa6. Incrementing is only possible in the multiframe synchronous state.
The Sa-bit error indication counter CRC2 (16 bits) counts either the received bit
sequence 0010B or 0011B or user programmable values in every submultiframe on a
selectable Sa-bit. In the primary rate access digital section CRC errors detected at T-
reference points are reported via Sa6. Incrementing is only possible in the multiframe
synchronous state.
4.8.5
Signalling Controller FIFO Operations
Access to the FIFO’s of the signalling controllers is handled via registers RFF and XFF.
FIFO status and commands are exchanged using the port status registers PSR and the
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Functional Description
handshake register HND. Additional facility data link interrupt vectors inform system
software about protocol and FIFO status.
Receive FIFO
In receive direction there are different interrupt indications associated with the reception
of data:
• A ’Receive Pool Full’ (RPF) interrupt vector is indicating that a data block can be read
from the receive FIFO and the received message is not yet complete. It is generated,
when the amount of data bytes has reached the programmed threshold.
• A ’Receive Message End’ (RME) interrupt vector is indicating that the reception of one
message is completed. After this interrupt system software has to read the PSR
register in order to get the number of bytes stored in the receive FIFO. This number
includes the status byte which is written into the receive FIFO as the last byte after the
received frame. The status byte includes information about the CRC result, valid
frame indication, abort sequence or data overflow. The format of the status byte is
shown in the table below:
7
6
5
4
0
SMODE(1:0) BRFO
STAT(4:0)
SMODE
Receiver Status Mode
This bit indicates the type of data received.
10B
01B
HDLC data
BOM data
BRFO
STAT
BOM Receive FIFO Overflow
0
1
No overflow
Receive FIFO overflow
Receive FIFO Status
This bit field reports the status of the data stored in the receive FIFO.
HDLC mode
BOM MODE
00000B
00001B
00010B
00011B
00100B
Valid HDLC Frame
Receive Data Overflow
Receive Abort
Not Octet
BOM Filtered data declared
BOM data available
BOM End
BOM filtered data undeclared
CRC Error
BOM header error (ISF, incorrect
synchronization format)
00101B
Channel Off
Preliminary Data Sheet
102
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PEB 20256M E
PEF 20256M E
Functional Description
After the received data has been read from the FIFO, the receive FIFO can be released
by the CPU by issuing a ’Receive Message Complete’ (HND.RMC) command. The CPU
has to process a ’Receive Pool Full’ interrupt vector and issue the ’Receive Message
Complete’ command before the second page of the FIFO becomes full. Otherwise a
’Receive Data Overflow’ condition will occur. This time is dependent on the threshold
programmed (smaller threshold results in shorter time).
•
Receive frame (79 bytes)
32 bytes
32 bytes
15 bytes
FDL channel
Local Bus
Interface
RD
32 bytes
RD
32 bytes
RD
RBC 15 bytes status
RME
RMC
RD
RD
RPF
RPF
RMC
RMC
Figure 4-12 Interrupt Driven Reception Sequence Example
Transmit FIFO
In the transmit direction after checking the transmit FIFO status by polling the transmit
FIFO write enable bit (PSR.XFW) or after a ’Transmit Pool Ready’ (XPR) interrupt vector,
up to 32 bytes may be written to the transmit FIFO (bit field XFF.XFIFO) by the CPU.
Transmission of a frame can be started by issuing a ’Transmit Transparent Frame’ (XTF)
or ’Transmit HDLC Frame’ (XHF) command via register HND. If the transmit command
does not include a ’Transmit Message End’ indication (HND.XME), the signalling
controller will repeatedly request for the next data block by means of a XPR interrupt
vector as soon as the transmit FIFO becomes free. This process will be repeated until
the local CPU writes the last bytes to the transmit FIFO. The end of message is then
indicated per HND.XME command, after which frame transmission is finished correctly
by appending the CRC and closing flag sequence. Consecutive frames may share a flag
(enabled via bit XCR1.SF) or may be transmitted as back-to-back frames, if service of
transmit FIFO is quick enough. In case that no more data is available in the transmit FIFO
prior to the arrival of HND.XME, the transmission of the frame is terminated with an abort
sequence and the CPU is notified via a ’Transmit Data Underrun’ interrupt vector (XDU).
The frame may also be aborted per software by setting the XAB bit in the handshake
register HND.
Preliminary Data Sheet
103
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PEB 20256M E
PEF 20256M E
Functional Description
•
Transmit frame (79 bytes)
32 bytes
32 bytes
15 bytes
FDL channel
Local Bus
Interface
WR
WR
WR
32 bytes
32 bytes
15 bytes
XTF XPR
XTF
XPR
XTF+XME XPR ALLS
Figure 4-13 Interrupt Driven Transmit Sequence Example
Note: Transmit FIFO is 16 bit wide. In the given example writing 32 bytes requires 16
write accesses. Writing 15 byte requires 8 accesses.
Preliminary Data Sheet
104
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PEB 20256M E
PEF 20256M E
Functional Description
4.9
M12 Multiplexer/Demultiplexer and DS2 framer
The M12 multiplexer and the DS2 framer can be operated in two modes:
• M12 multiplex format according to ANSI T1.107
• ITU-T G.747 format
4.9.1
M12 multiplex format
The framing structure of the M12 signal is shown in Table 4-11. A DS2 multiframe
consists of four subframes. Each subframe combines 6 blocks with 49 bits each. The first
bit of each block contains an overhead (OH) bit and 48 information bits. The 48
information bits are divided into four time slots of 12 bits each. The first time slot is
assigned to the 1st tributary DS1 signal, the second time slot is assigned to the 2nd
tributary DS1 signal and so forth.
Table 4-11 M12 multiplex format
Subframe
Block 1 through 6 of a subframe
1
2
3
4
5
6
1
2
3
4
0M [48] C11 [48] F0 [48] C12 [48] C13 [48] F1 [48]
1M [48] C21 [48] F0 [48] C22 [48] C23 [48] F1 [48]
1M [48] C31 [48] F0 [48] C32 [48] C33 [48] F1 [48]
DS2-
Multiframe
X
[48] C41 [48] F0 [48] C42 [48] C43 [48] F1 [48]
F0, F1
F0 and F1 form the frame alignment pattern. Each DS2 frame consists of eight F-bits, two per
subframe in block 3 and 6. F0 and F1 form the pattern ’01’. This pattern is repeated in every
subframe.
X
This bit is the forth bit of the multiframe alignment signal and can be set to either ’0’ or ’1’. It is
accessible via an internal register.
M0, M1,MX
M0 and M1 and MX form the multiframe alignment signal. Each subframe consists of four M-bits
and they are located in bit 0 of each subframe. The multiframe alignment signal is ’011-’.
C11..C43
The C-bits control the bit stuffing procedure of the multipexed DS1 signals.
[48]
These bits represent a data block, which consists of 48 bits. [48] consists of four time slots of 12
bit and each time slot is assigned to one of four participating DS1 signals.
Preliminary Data Sheet
105
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PEB 20256M E
PEF 20256M E
Functional Description
4.9.1.1 Synchronization Procedure
The integrated DS2 framer searches for the frame alignment pattern ’01’ and the
multiframe alignment pattern in each of the seven DS2 frames which are contained in a
DS3 signal. Frame alignment is declared, when the DS2 framer has found the basic
frame alignment pattern (F-bit) and the multiframe alignment pattern (M-bit).
Loss of frame is declared, when 2 out of 4 or 3 out of 5 incorrect F-bits are found or when
one or more incorrect M-bits are found in 3 out of 4 subframes.
4.9.1.2 Multiplexer/Demultiplexer
Demultiplexer
The demultiplexer extracts four DS1 signals out of each DS2 signal. If two out of three
bits of Ci1, Ci2, Ci3 are set to ’1’ the first information bit in the ith subframe and the 6th block
which is assigned to the ith DS1 signal is discarded.
The demultiplexer performs inversion of the 2nd and 4th tributary DS1 signal.
Multiplexer
The multiplexer combines four DS1 signals to form a DS2 signal. Stuffing bits are
inserted and the Ci1-, Ci2-, Ci3-bits, which are assigned to the ith DS1 signal, are set to ’1’
in case that not enough data is available.
The 2nd and 4th DS1 signal are automatically inverted in transmit direction.
4.9.1.3 Loopback Control
Detection
Loopback requests encoded in the C-bits of the DS2 signal are flagged when they are
repeated for at least five DS2 multiframes. Loops must be initiated by an external
microprocessor.
Generation
A loopback request, which is transmitted in lieu of the C-bits, can be placed in each DS2
signal.
Preliminary Data Sheet
106
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PEB 20256M E
PEF 20256M E
Functional Description
4.9.1.4 Alarm Indication Signal
Detection
AIS is declared, when the AIS condition (the received DS2 data stream contains an all
‘1’ signal with less then 3/9 zeros within 3156 bits while the DS2 framer is out of frame)
is present within a time interval that is determined by register D2RAP.
Generation
The alarm indication signal is an all ’1’ unframed signal and will be transmitted if enabled.
Preliminary Data Sheet
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PEF 20256M E
Functional Description
4.9.2
ITU-T G.747 format
The multiplexing frame structure is shown in Table 4-12.
Table 4-12 ITU-T G.747 format
Set
Content
Frame Alignment Signal 111010000
Bits from tributaries
Bit
1 to 9
10 to 168
1
I
II
Alarm indication to the remote multiplex
equipment
Parity Bit
2
Reserved
3
ITU-T
G.747
Frame
Bits from tributaries
Justification control bits Cj1
Bits from tributaries
Justification control bits Cj2
Bits from tributaries
Justification control bits Cj3
4 to 168
1 to 3
4 to 168
1 to 3
4 to 168
1 to 3
III
IV
V
Bits from tributaries available for justification
Bits from tributaries
4 to 6
7 to 168
4.9.2.1 Synchronization Procedure
The integrated framer searches for the frame alignment pattern ’111010000’ in each of
the seven frames which are contained in a DS3 signal. Frame alignment is declared,
when the framer has found three consecutive correct frame alignment signals. If the
frame alignment signal has been received incorrectly in one of the following frames after
the receiver found the first correct frame alignment signal a new search is started.
Loss of frame is declared, when four consecutive frame alignment signals have been
received incorrectly.
4.9.2.2 Multiplexer/Demultiplexer
Demultiplexer
The demultiplexer extracts three E1 signals from each 6.312 MHz signal. If two out of
three bits of Cj1, Cj2, Cj3 are set to ’1’ the available justification bit of the jth E1 signal is
discarded.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Functional Description
Multiplexer
The multiplexer combines three E1 signals to form a DS2 signal. Stuffing bits are
inserted and the Cj1-, Cj2-, Cj3-bits, which are assigned to the jth E1 signal, are set to ’1’
in case that not enough data is available.
4.9.2.3 Parity Bit
Detection
The receiver optionally calculates the parity of all tributary bits and compares this value
with the received parity bit. Differences are counted in the parity error counter.
Generation
The parity bit is automatically calculated according to ITU-T G.747 or programmable to
a fixed value under microprocessor control.
4.9.2.4 Remote Alarm Indication
Detection
Remote alarm is reported when bit 1 of set II changes and when the change persists for
at least three multiframes.
Generation
Remote alarm is transmitted in bit 2 of “set II” and can be inserted under microprocessor
control.
4.9.2.5 Alarm Indication Signal
Detection
AIS is declared, when the AIS condition (the received DS2 data stream contains an all
‘1’ signal with less then 5/9 zeros within two consecutive multiframes while the DS2
framer is out of frame) is present within a time interval that is determined by register
D2RAP.
Generation
The alarm indication signal is an all ’1’ unframed signal and will be transmitted if enabled.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Functional Description
4.10
M23 multiplexer and DS3 framer
The M23 multiplexer and the DS3 framer can be operated in three modes:
• M23 multiplex format
• C-bit parity format with modified M23 multiplex operation
• C-bit parity format with non-M23 multiplex operation (Full payload rate format)
4.10.1
M23 multiplex format
The framing structure of the M23 multiplex signal is shown in Table 4-13. Each DS3
multiframe consists of 7 subframes and each subframe of eight blocks. One block
consists of 85 bits, where the first bit is the overhead (OH) bit and the remaining 84 bits
are the information bits. The 84 information bits are divided into seven time slots of 12
bits each. The first time slot is assigned to the 1st tributary DS2 signal, the second time
slot is assigned to the 2nd tributary DS2 signal and so forth.
Table 4-13 M23 multiplex format
Sub-
Block 1 through 8 of a subframe
frame
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
X [84] F1 [84] C11 [84] F0 [84] C12 [84] F0 [84] C13 [84] F1 [84]
X [84] F1 [84] C21 [84] F0 [84] C22 [84] F0 [84] C23 [84] F1 [84]
P [84] F1 [84] C31 [84] F0 [84] C32 [84] F0 [84] C33 [84] F1 [84]
P [84] F1 [84] C41 [84] F0 [84] C42 [84] F0 [84] C43 [84] F1 [84]
M0 [84] F1 [84] C51 [84] F0 [84] C52 [84] F0 [84] C53 [84] F1 [84]
M1 [84] F1 [84] C61 [84] F0 [84] C62 [84] F0 [84] C63 [84] F1 [84]
M0 [84] F1 [84] C71 [84] F0 [84] C72 [84] F0 [84] C73 [84] F1 [84]
DS3-
Multi-
frame
F0, F1
F0 and F1 form the frame alignment pattern. Each DS3 frame consists of 28 F-bits, four per
subframe in block 2, 4, 6 and 8. F0 and F1 form the pattern ’1001’. This pattern is repeated in
every subframe.
M0, M
M0 and M1 form the multiframe alignment signal. The M-bit is contained in the OH-bit of the first
block in subframe 5,6 and 7. The multiframe alignment signal is ’010’.
C11..C73
The C-bits control the bit stuffing procedure of the multipexed DS2 signals.
P
The P-bits contain parity information and are calculated as even parity on all information bits of
the previous DS3 frame. Both P-bits are identical.
Preliminary Data Sheet
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PEF 20256M E
Functional Description
X
The X-bits are used for transmission of asynchronous in-service messages. Both X-bits must be
identical and may not change more than once every second.
[84]
These bits represent a data block, which consists of 84 bits.
[84] consists of seven time slots with 12 bits each and they are assigned to one of the seven
participating DS2 signals.
4.10.1.1 Synchronization Procedure
The integrated DS3 framer searches for the frame alignment pattern ’1001’ and when
found for the multiframe alignment pattern in each of the seven DS3 subframes. When
the multiframe alignment pattern is found in three consecutive DS3 frames while frame
alignment is still valid frame alignment is declared. The P-bits and the X-bits are ignored
during synchronization.
Loss of frame is declared, when 3 out of 8 or 3 out of 16 incorrect F-bits are found or
when one or more incorrect M-bits are found in 3 out of 4 subframes.
4.10.1.2 Multiplexer/Demultiplexer
Demultiplexer
The demultiplexer extracts seven DS2 signals from the incoming DS3 signal. If two or
three bits out of Ci1, Ci2, Ci3 are set to ’1’ the first bit following the F1 bit in the ith subframe
which is assigned to the ith DS2 signal is discarded.
Multiplexer
The multiplexer combines seven DS2 signals to form a DS3 signal. If not sufficient data
is available for a DS2 signal, it automatically inserts a stuffing bit and sets the bits Ci1,
Ci2, Ci3 assigned to the ith DS2 signal to ’1’.
4.10.1.3 X-bit
The MUNICH256FM provides access to the X-bit of each tributary via an internal
registers. Data written to the X-bit register is copied to an internal shadow register which
is then locked for one second after each write access.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Functional Description
4.10.1.4 Alarm Indication Signal, Idle Signal
Detection
Alarm indication signal or Idle signal is declared, when the selected signal format was
received with less than 8/15 bit errors (selectable via bit D3RAP.AIS) for at least one
multiframe. The alarm indication signal can be selected as:
• Unframed all ’1’s
• Framed ’1010’ sequence, starting with a binary ’1’ after each OH-bit. C-bits are set to
‘0’. X-bit can be checked as ‘1’ or X-bit check can be disabled.
The idle signal is a
• Framed ’1100’ sequence, starting with a binary ’11’ after each OH-bit. C-bits are set
to ‘0’ in M-subframe 3. X-bit can be checked as ‘1’ or X-bit check can be disabled.
Generation
The alarm indication signal or idle signal will be generated according to the selected
signal format. X-bit needs to be set seperately to ‘1’.
4.10.1.5 Loss of Signal
Detection
Loss of signal is declared, when the incoming data stream contains more than 1022
consecutive ’0’s.
Recovery
Loss of signal is removed, when two or more ones are detected in the incoming data
stream.
4.10.1.6 Performance Monitor
The following conditions are counted:
• Line code violations
• Excessive zeroes
• P-bit errors, CP-bit errors
• Framing bit errors
• Multiframe bit errors
• Far end block errors
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4.10.2
C-bit parity format
The framing structure of the C-bit parity format is shown in Table 4-13. The assignment
of the information bits [84] is identical to the M23 multiplex format, but the function of the
C-bits is redefined for path maintenance and data link channels.
Table 4-14 C-bit parity format
Sub-
Block 1 through 8 of a subframe
frame
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
X [84] F1 [84] AIC [84] F0 [84] Nr [84] F0 [84] FEAC [84] F1 [84]
X [84] F1 [84] DL [84] F0 [84] DL [84] F0 [84] DL [84] F1 [84]
P [84] F1 [84] CP [84] F0 [84] CP [84] F0 [84] CP [84] F1 [84]
P [84] F1 [84] FEBE [84] F0 [84] FEBE [84] F0 [84] FEBE [84] F1 [84]
M0 [84] F1 [84] DLt [84] F0 [84] DLt [84] F0 [84] DLt [84] F1 [84]
M1 [84] F1 [84] DL [84] F0 [84] DL [84] F0 [84] DL [84] F1 [84]
M0 [84] F1 [84] DL [84] F0 [84] DL [84] F0 [84] DL [84] F1 [84]
DS3-
Multi-
frame
F0, F1
F0 and F1 form the frame alignment pattern. Each DS3 frame consists of 28 F-bits, four per
subframe in block 2, 4, 6 and 8. F0 and F1 form the pattern ’1001’. This pattern is repeated in
every subframe.
M0, M
M0 and M1 form the multiframe alignment signal. The M-bit is contained in the OH-bit of the first
block in subframe 5,6 and 7. The multiframe alignment signal is ’010’.
Nr
Reserved. Set to ’1’ in transmit direction.
AIC
Application Identification Channel.
DLt
The terminal-to-terminal path maintenance data link uses the HDLC protocol. Access to the DLt
bits is possible via the DS3 transmit and receive FIFO.
DL
Reserved. Set to ’1’ in transmit direction.
FEAC
The alarm or status information of a far end terminal is sent back over the far end and control
channel. This bit also contains DS3 or DS1 line loopback requests. Messages are sent in bit
oriented mode. Message codes can be accessed via an internal register.
FEBE
The far end block error bits indicate a CP-bit parity error or a framing error. They are used to
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monitor the performance of a DS3 signal. Upon detection of either error in the incoming data
stream the FEBE-bits are set automatically to ’000’ in the outgoing direction. Received far end
block errors are counted.
CP
The CP-bits are used to carry path parity information and are set to the same value as the P-bits.
In receive direction the CP-bits are checked against the calculated parity and differences are
counted.
P
X
The P-bits contain parity information and are automatically calculated as even parity on all
information bits of the previous DS3 frame.
The X-bits are used for transmission of asynchronous in-service messages. Both X-bits must be
identical and may not change more than once every second. Access to the X-bits is possible via
a register.
[84]
These bits represent a data block, which consists of 84 bits. [84] consists of seven time slots with
12 bits each and they are assigned to one of the seven participating DS2 signals.
4.10.2.1 Synchronization Procedure
The integrated DS3 framer searches for the frame alignment pattern ’1001’ and when
found for the multiframe alignment pattern in each of the seven DS3 subframes. Frame
alignment is declared when the multiframe alignment pattern is found in three
consecutive DS3 frames. The P-bits and the X-bits are ignored during synchronization.
Loss of frame is declared, when 3 out of 8 or 3 out of 16 incorrect F-bits are found or
when one or more incorrect M-bits are found in 3 out of 4 subframes.
4.10.2.2 Multiplexer/Demultiplexer
Demultiplexer
The demultiplexer extracts seven DS2 signals from the incoming DS3 signal. Since the
DS3 signal is always stuffed the stuffing bit assigned to each DS2 signal is discarded.
Multiplexer
The multiplexer combines seven DS2 signals to form a DS3 signal and automatically
inserts a stuffing bit for each DS2 signal.
4.10.2.3 X-bit
The MUNICH256FM provides access to the X-bits via internal registers.
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4.10.2.4 Far End Alarm and Control Channel
The far end alarm and control channel is accessible via the signalling controller in BOM
mode.
4.10.2.5 Path Maintenance Data Link Channel
The path maintenance data link channel is accessible via the signalling controller in
HDLC mode.
4.10.2.6 Loopback Control
Detection
Loopback requests are encoded in the messages of the far end alarm and control
channel. The microprocessor has access to the messages as described in
Chapter 4.10.2.4.
Generation
A loopback request can be initiated via the far end alarm and control channel.
4.10.2.7 Alarm Indication Signal, Idle Signal
Detection
Alarm indication signal or Idle signal is declared, when the selected signal format was
received with less than 8/15 bit errors (selectable via bit D3RAP.AIS) for at least one
multiframe. The alarm indication signal can be selected as:
• Unframed all ’1’s
• Framed ’1010’ sequence, starting with a binary ’1’ after each OH-bit. C-bits are set to
‘0’. X-bit can be checked as ‘1’ or X-bit check can be disabled.
The idle signal is a
• Framed ’1100’ sequence, starting with a binary ’11’ after each OH-bit. C-bits are set
to ‘0’ in M-subframe 3. X-bit can be checked as ‘1’ or X-bit check can be disabled.
Generation
The alarm indication signal or idle signal will be generated according to the selected
signal format. X-bit needs to be set seperately to ‘1’.
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4.10.2.8 Loss of Signal
Detection
Loss of signal is declared, when the incoming data stream contains more than 1022
consecutive ’0’s.
Recovery
Loss of signal is removed, when two or more ones are detected in the incoming data
stream.
4.10.2.9 Performance Monitor
The following conditions are counted:
• Line code violations
• Excessive zeroes
• P-bit errors, CP-bit errors
• Framing bit errors
• Multiframe bit errors
• Far end block errors
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4.10.3
Full Payload Rate Format
In full payload rate format the DS3 multiframe structure can be selected according to the
M13 multiplex structure or the C-bit parity structure. In either case the data blocks [84]
carry one continuous data stream which is provided via the tributary interface one.
Multiplexing/Demultiplexing of the data block [84] does NOT apply.
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4.11
Test Unit
The test unit of the MUNICH256FM incorporates a test pattern generator and a test
pattern synchronizer which can be attached to different test points as shown in Figure
4-14. Controlled by a small set of registers it can generate and synchronize to polynomial
pseudorandom test patterns or repetitive fixed length test patterns.
Test patterns can be generated in the following modes:
• Framed DS3
• Unframed DS2
• Framed DS2
• Unframed DS1/E1
•
DS2 Framer
DS2 Framer
M12
M12
M23
(De)multi-
plexer
DS3
Framer
DS2 Framer
0
6
0
6
0
27
Test Port
Select
Test Port
Select
Test Port
Select
Test
Mode
Select
Test Unit
Figure 4-14 Test Unit Access Points
In pseudorandom test mode the receiver tries to achieve synchronization to a test
pattern which satisfies the programmed receiver polynomial. In fixed pattern mode it
synchronizes to a repetitive pattern with a programmable length. An all ’1’ pattern or an
all ’0’ pattern, which satisfies this condition, is flagged. Measurement intervals as well as
receiver synchronization can be controlled by the user. When a test is finished an
interrupt is generated and the bit count and the bit error count are readable.
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•
+
Feedback in
Pseudorandon pattern
mode only
+
0
1
X-1
X
N-2
N-1
Bit error
insertion
N
X
Pattern length
Feedback Tap
Figure 4-15 Pattern Generator
Bit Error Insertion
The test unit provides the optional capability to insert bit errors in the range of 10-7 (1
error in 10.000.000 bits) up to 10-1 bit errors (1 error in 10 bits).
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4.12
Mailbox
The MUNICH256FM contains a mailbox to allow communication between two intelligent
peripherals connected to the PCI bus and the local microprocessor bus. The mailbox is
organized in two pages of eight registers. The first page is used to store information from
the PCI side and to read the information from the local microprocessor side. The second
page is used for the opposite direction, from the local microprocessor side to the PCI
side. Each page consists of one status register and seven data registers.
The mailbox provides a ‘doorbell’ capability. In this case an interrupt vector can be
generated to inform the addressed intelligent peripheral that new information has been
stored in the mailbox. This interrupt vector will be generated on write accesses to the
status register of the selected page.
As an example, consider when the PCI host system wants to transfer data to an
intelligent peripheral. First it loads data into the mailbox data registers MBP2E1 through
MBP2E7, and then writes a status information to the mailbox status register MBP2E0.
This last action causes an interrupt vector to be written to the interrupt FIFO which is
connected to the local bus. The presence of an interrupt vector results in assertion of pin
LINT. The intelligent peripheral recognizes the interrupt pin asserted and reads the
interrupt vector out of the interrupt FIFO (which results in deassertion of pin LINT), and
then reads data from the mailbox data registers.
•
Mailbox registers
PCI --> Local Bus
Interrupt Vector
MBP2E0
read
only
MBP2E1..MBP2E7
Interrupt Controller
Local Bus
Mailbox registers
Local Bus --> PCI
Interrupt Vector
MBE2P0
read
only
MBE2P1..MBE2P7
Interrupt Controller
PCI Side
PCI Interface
Local Bus Interface
Figure 4-16 Mailbox Structure
Alternately, consider when an intelligent peripheral connected to the local bus wants to
transfer data to the PCI host system. First it loads data into the mailbox data registers
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MBE2P1 through MBE2P7 and then it writes status information to the mailbox status
register MBE2P0. This causes a system interrupt vector to be written to the PCI host
system, indicating that valid data is contained in the mailbox data registers.
This interrupt vector will be written to the interrupt queue specified in CONF1.SYSQ and
together with this the pin INTA will be asserted. The processor sees the interrupt pin
asserted, reads the register GISTA in order to determine the interrupt queue, and then
writes a ‘1’ to the interrupt status acknowledge register GIACK to clear the interrupt.
Next, it reads the interrupt vector which contains a copy of the mailbox status register
and then reads the mailbox data registers.
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4.13
Interrupt Controller
Since the MUNICH256FM is divided into the basic functions mailbox, layer one functions
(T1/E1 framer, facility data link, M13 multiplexer and DS2/DS3 framer) and layer two
protocol functions (HDLC, PPP, TMA), the same partitioning is used for the interrupt
handling.
All layer two interrupts (channel, port, system and command interrupts) are handled via
an internal interrupt controller which forwards those interrupts to external interrupt
queues. This interrupt controller is connected to the PCI interrupt pin INTA.
Mailbox interrupts and layer one interrupts are handled via an internal interrupt FIFO
which is connected to the local bus interrupt pin LINT (normal operation). Additionally the
interrupts stored in the internal interrupt FIFO can be notified via the PCI interrupt pin
INTA.
The MUNICH256FM also provides the capability to bridge the local bus interrupt LINT to
the PCI bus.
4.13.1
Layer Two interrupts
All channel interrupts, port interrupts and system interrupts are written in form of interrupt
vectors to interrupt queues.
Each interrupt vector has an interrupt source. An interrupt source is either a channel, the
port handler or certain device functions (system interrupts). After reset no interrupt vector
is generated since port and system interrupts are masked and channels are in their idle
state.
Each interrupt source forwards its interrupt vector to the interrupt controller, together with
the information in which interrupt queue the vector should be forwarded. The interrupt
controller moves the interrupt vector to the selected interrupt queue. Channel interrupts
can optionally be forwarded to a dedicated high priority interrupt queue (interrupt queue
seven). A programmable interrupt queue high priority mask determines channel
interrupts, which shall be forwarded into the high priority interrupt queue instead of
queueing them in the selected interrupt queue. This function is available for each
interrupt queue and allows to queue important interrupt conditions in the high priority
queue.
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•
Int. vector setup:
CSPEC_IVMASK,
CSPEC_BUFFER
Int. vector setup:
CONF1, CONF2
Int. vector setup:
PMR, CONF2
Channel,
Command
interrupts
System
interrupts
Port
interrupts
256
1
IV
1
Interrupt bus
from layer one
interrupt FIFO
Interrupt status:
GISTA, GMASK
Interrupt queue setup:
IQIA, IQBA, IQL, IQMASK
Interrupt
controller
LINT
2
PCI
interface
INTA
4
PCI bus
5
FFFFFFFFH
3
Microprocessor
System memory
Interrupt queue
1. Interrupt source forwards interrupt vector to
interrupt controller.
2. Interrupt controller moves interrupt vector to
interrupt queue.
3. Interrupt controller asserts INTA (if enabled).
4. Microprocessor reads status register GISTA.
5. Microprocessor reads interrupt queue.
IQBA
00000000H
Figure 4-17 Layer Two Interrupts (Channel, command, port and system
interrupts
As soon as the interrupt controller has written an interrupt vector to one of the nine
interrupt queues the PCI interrupt pin INTA is asserted. The global interrupt status
register indicates in which interrupt queue the interrupt vector can be found. Each of the
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nine interrupt queues can be masked. In this case the interrupt pin INTA is not asserted,
but the interrupt vector is still written into the assigned interrupt queue.
An interrupt queues is a reserved memory locations in system memory. The
MUNICH256FM supports up to eight interrupt queues which are organized in form of ring
buffers with a programmable start address and a programmable size per interrupt queue.
Additionally there is one fixed sized command interrupt queue where command
interrupts are stored. The size of this queue is two times 256 DWORDs (Figure 4-18).
•
Interrupt Vector IQL*16
Channel 255: Transmit Command IV
Channel 0: Transmit Command IV
Channel 255: Receive Command IV
Interrupt Vector 3
Interrupt Vector 2
Interrupt Vector 1
IQBA+4H
IQBA
IQBA+4H
IQBA
Channel 1: Receive Command IV
Channel 0: Receive Command IV
Channel, Port and System
Interrupt Queue
Command Interrupt Queue
Note: IV = Interrupt Vector
Figure 4-18 Interrupt Queue Structure in System Memory
4.13.1.1 General Interrupt Vector Structure
Each interrupt vector is 32 bit wide and contains several subfields, which indicate the
interrupt group and depend on the interrupt group the interrupt information. Bit 31 of the
interrupt vector is generally set to ’1’ by the MUNICH256FM and allows the system CPU
to clear the bit in order to mark processed interrupts.
Table 4-15 Interrupt Vector Structure
31
1
30
29
28
27
26
24
23
16
TYPE(1:0) STYPE(1:0)
QUEUE(2:0)
INT(23:0)
15
0
INT(23:0)
124
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TYPE
Interrupt type
The interrupt vectors are divided into four basic groups, where TYPE
determines the interrupt group. A further classification of interrupts is
done with the subtype indication.
00B
01B
10B
11B
Command interrupts
Channel interrupts
Port interrupts
System interrupts
STYPE
QUEUE
Interrupt subtype
A specific interrupt type is divided into several subtypes. In general
STYPE(1) indicates the data path (transmit, receive) generating the
interrupt.
Interrupt queue
The interrupt vectors are written into 9 external interrupt queues located
in the shared memory. Corresponding to these 9 queues are 9 interrupt
queue start addresses and 8 interrupt queue length registers, since the
interrupt queue 8 has a fixed length of 2 x 256).
INT
Interrupt Information
INT itself contains the interrupt information. The meaning of INT is
dependent on TYPE and STYPE indication.
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4.13.1.2 System Interrupts
•
31
1
30
29
28
27
26
24
20
19
18
17
16
11B
00B
QUEUE(2:0)
0
0
0
MB RBF RBEWRAEW PB
15
0
INFO(15:0)
MB
Mailbox
The ’Mailbox’ interrupt vector is generated, in case that the local
microprocessor has written data to the mailbox status register MBE2P0.
The bit field INFO contains a copy of MBE2P0.
RBAF
Receive Buffer Access Failed
The ’Receive Buffer Access Failed’ interrupt vector is generated, when
the protocol machine discarded packets due to permanent
inaccessibility of the receive buffer. This interrupt is issued as soon as
the programmable threshold stored in register RBAFT is reached. The
actual value of discarded packets is stored in register RBAFC.
RBEW
RAEW
Receive Buffer Queue Early Warning
The ’Receive Buffer Queue Early Warning’ interrupt vector is generated,
when the receive buffer data threshold has been exceeded
(RBTH.RBTH). This interrupt can be masked via bit CONF1.RBIM.
Receive Buffer Action Queue Early Warning
The ’Receive Buffer Action Queue Early Warning’ interrupt vector is
generated, when the receive data action queue threshold
(RBTH.RBAQTH) has been exceeded. The receive buffer action queue
stores all requests of the receive buffer to forward data packets to
system memory. This interrupt vector can be masked via bit
CONF1.RBIM.
PB
PCI Access Error
The ’PCI Access Error’ interrupt vector is generated, when system
software tries to read/write internal registers with accesses that do not
enable all byte lanes, e.g. the access is not a full 32 bit access. The bit
field INFO contains the register address which was tried to access.
INFO
Contains additional interrupt information data according to the bit, which
is set: See specific interrupt for details.
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4.13.1.3 Port Interrupts
Port interrupt vectors indicate the synchronous or asynchronous state of a port.
Immediately after enabling both, the port and the port interrupts, port interrupts are
generated indicating the synchronous or asynchronous state of a port. After this initial
interrupt vector generation, further interrupts are written only when the state of a port
changes from synchronous state to asynchronous state or vice versa. Port interrupts are
enabled by resetting the corresponding mask bit in register PMR.
Transmit interrupts
•
31
1
30
29
28
27
26
24
17
16
10B
10B
QUEUE(2:0)
0
0
0
0
0
0
4
0
0
SYN ASYN
15
0
5
0
0
0
0
0
0
0
0
0
PORT(4:0)
PORT
SYN
Port Number
This bit field identifies the port for which the information in the interrupt
vector is valid.
Synchronization achieved
Port has changed from asynchronous state to synchronous state. This
interrupt is available for ports configured in T1 or E1 mode. In
unchannelized mode there is no synchronous state.
A transmit port changes to the synchronous state, if common transmit
frame synchronization is enabled and the number of bits between two
synchronization pulses is equal to the number of frame bits of the
selected mode or is equal to a multiple of that number. The first CTFS
pulse after a port is enabled causes the transmitter to change to the
synchronous state.
In case the common transmit frame synchronization is disabled, i.e. the
looped timing bit or the CTFS disable bit of a port is set in PMR, the initial
asynchronous state will not be left.
ASYN
Asynchronous State
The transmitter generates an ’Asynchronous State’ interrupt vector if a
port has changed from synchronous to asynchronous state. This
interrupt is available for ports configured in T1 or E1 mode. In
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unchannelized mode there is no asynchronous state. In general a port is
in asynchronous state when a port is disabled.
A transmit port changes to the asynchronous mode if the number of bits
between two synchronization pulses is not equal to a multiple of the
number of frame bits of the selected mode
Receive Interrupts
•
31
1
30
29
28
27
26
24
17
16
10B
00B
QUEUE(2:0)
0
0
0
0
0
0
0
4
0
0
SYN ASYN
15
0
0
0
0
0
0
0
0
0
PORT(4:0)
PORT
SYN
Port Number
This bit field identifies the port for which the information in the interrupt
vector is valid.
Synchronization achieved
Port has changed from asynchronous state to synchronous state. This
interrupt is available for ports configured in T1 or E1 mode. In
unchannelized mode there is no synchronous state.
A receive port changes to the synchronous state, if the number of bits
between two synchronization pulses generated by the port related
framer is exactly equal to the number of frame bits of the selected mode.
The first framer pulse after a port is enabled causes the receive port to
change to the synchronous state.
ASYN
Asynchronous state
Port has changed from synchronous to asynchronous state. This
interrupt is available for ports configured in T1 or E1 mode. In
unchannelized mode there is no asynchronous state. In general a port is
in asynchronous state when a port is disabled.
A receive port changes to the asynchronous state if the number of bits
between two framer synchronization pulses is not equal to the number
of frame bits of the selected mode. The synchronization pulses are
generated internally by the T1/E1 framer.
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4.13.1.4 Channel Interrupts
Channel interrupt are divided into two subtypes:
• Receive Interrupt I and Transmit Interrupt I
• Receive Interrupt II and Transmit Interrupt II
Subtype I contains interrupts which indicate the general status of a channel. These
interrupts are not linked to a descriptor.
Subtype II contains interrupts which indicate a channel or packet status that is linked to
a descriptor. Each interrupt vector contains a descriptor ID which can be used for
tracking purposes.
Receive Interrupt I
•
31
1
30
29
28
27
11
26
24
01B
00B
QUEUE(2:0)
0
7
0
0
0
0
0
0
0
0
15
14
13
12
ROFP SF IFFL IFID SFD
0
0
0
CHAN(7:0)
ROFP
Receive Buffer Overflow
The ’Receive Buffer Overflow’ interrupt vector is generated, when one or
more whole frames or short frames or changes of interframe time-fill
(HLDC, PPP) or data in general (TMA) has been discarded due to the
inaccessibility of the internal receive buffer.
SF
Short Frame Detected
The ’Short Frame Detected’ interrupt vector is generated, when the
receiver detected a frame which length matches the condition defined in
CONF1.SFL.
IFFL
IFID
Interframe Time-fill Flag
The ’Interframe Time-fill Flag’ interrupt vector is generated, when the
receiver detected a interframe time-fill change from FFH to 7EH.
Interframe Time-fill Idle
The ’Interframe Time-fill Idle’ interrupt vector is generated, when the
receiver detected a interframe time-fill change from 7EH to FFH.
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SFD
Small Frames Dropped
The ’Small Frames Dropped’ interrupt vector is generated, when the
receiver discarded N small frames. The length of small frames is defined
in CONF3.MINFL and the threshold value N is defined in register SFDT.
CHAN
Channel Number
This bit field identifies the channel for which the information in the
interrupt vector is valid.
Transmit Interrupt I
•
31
1
30
29
28
27
26
24
16
0
01B
10B
QUEUE(2:0)
0
7
0
0
0
0
0
0
15
14
0
UR
FE
0
0
0
0
0
0
CHAN(7:0)
UR
Underrun
The ’Underrun’ interrupt vector is generated, when the transmit buffer
was not able to provide data to the protocol machine transmit. If this
happens during transmission of a HDLC or PPP packet, the transmitter
will end the already started data packet with an abort sequence.
FE
Frame End
The ’Frame End’ interrupt vector is generated, when one complete data
packet has been transmitted via serial side.
CHAN
Channel Number
This bit field identifies the channel for which the information in the
interrupt vector is valid.
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Receive Interrupt II
•
31
1
30
29
28
27
11
26
24
23
0
22
0
21
16
01B
01B
QUEUE(2:0)
DESID(5:0)
15
14
13
12
10
9
8
7
0
RHI RAB FE HRAB MFL RFOD CRC ILEN
CHAN(7:0)
CHAN
Channel Number
This bit field identifies the channel for which the information in the
interrupt vector is valid.
RHI
(Receive) Host Initiated Interrupt
The ’(Receive) Host Initiated’ interrupt vector will be issued, if bit RHI is
set in a receive descriptor and processing of this descriptor has finished.
After receiving this interrupt vector, system software can release the
descriptor, e.g. put the descriptor into a free pool.
RAB
Receive Abort
The ’Receive Abort’ interrupt vector is generated, when an incoming
data packet is aborted (more than 6 ‘1’ in case of HDLC or more than 15
‘1’ in case of PPP) or if the receiver got a receive abort command from
the system CPU.
FE
Frame End
The ’Frame End’ interrupt Vector is generated, when one complete
frame has been received completely and has been stored in system
memory.
HRAB
Hold Caused Receive Abort
The ’Hold Caused Receive Abort’ interrupt vector is generated, when the
receiver discarded the first data packet after it has found a HOLD bit in
a receive descriptor.
RAB, HRAB
Silent Discard
The ’Silent Discard’ interrupt vector (bit RAB and HRAB set together)
occurs, if two or more frames have been discarded by the receiver due
to continuous inaccessibility of receive descriptor. This occurs, if receive
descriptor has HOLD bit set and receiver gets further data packets. The
interrupt vector will be generated for each packet discarded.
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Functional Description
MFL
Maximum Frame Length Exceeded
The ’Maximum Frame Length Exceeded’ interrupt vector is generated,
when the length of a received data packet exceeded the frame length
defined in CONF1.MFL.
RFOD
Receive Frame Overflow DMA
The ’Receive Frame Overflow DMA’ interrupt indicates that protocol
handler was unable to transfer data to the receive buffer. As soon as
receive buffer can store data again, this interrupt is generated.
CRC
ILEN
CRC Error
The ’CRC Error’ interrupt vector is generated, when the internally
calculated CRC and the CRC of a received packet did not match.
Invalid Length
The ’Invalid Length’ interrupt vector is generated, when the bit length of
received frame was not divisible by 8.
Transmit Interrupt II
•
31
1
30
29
28
27
26
24
21
16
01B
11B
QUEUE(2:0)
0
7
0
DESID(5:0)
15
14
12
0
THI TAB
0
HTAB
0
0
0
0
CHAN(7:0)
DESID
Descriptor ID
This bit field is a copy of the descriptor ID of the transmit descriptor which
is currently in use. It can be used for tracking purposes.
THI
(Transmit) Host Initiated Interrupt
The ’(Transmit) Host Initiated’ interrupt vector is generated, if bit THI is
set in a transmit descriptor and processing of this descriptor has finished.
After receiving this interrupt vector, system software can release the
descriptor, e.g. put the descriptor into a free pool.
TAB
Transmit Abort
The ’Transmit Abort’ interrupt vector is generated, either when the
’Transmit Abort/Branch’ command was given and therefore one frame
could not be transmitted completely or when NO and FE were set to 0 in
a transmit descriptor and previous frame was incompletely specified.
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HTAB
Hold Caused Transmit Abort
The ’Hold Caused Transmit Abort’ interrupt vector is generated, when
data management unit retrieved a transmit descriptor where HOLD was
set and FE equals 0. The interrupt will be generated after the data
section was transferred completely. After transmission of frame based
protocols (HDLC, PPP) protocol machine appends abort sequence due
to incomplete packet.
CHAN
Channel Number
This bit field identifies the channel for which the information in the
interrupt vector is valid.
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4.13.1.5 Command Interrupts
Command interrupts are written to the command interrupt queue (interrupt queue eight).
Transmit Interrupts
•
31
1
30
27
17
16
0010B
0
0
0
0
0
0
0
7
0
0
0
0
0
TCF TCC
15
0
0
0
0
0
0
CHAN(7:0)
TCF
Transmit Command Failed
The ’Transmit Command Failed’ interrupt vector is issued, if the
command ’Transmit Init’ given via register CSPEC_CMD.XCMD could
not be finished. This happens, when
•system software tried to allocate more buffer locations for a channel
than were available.
•system software specified thresholds (transmit forward threshold,
transmit refill threshold), which were greater than the specified
transmit buffer size.
Note:The sum of both thresholds must be smaller than the transmit
buffer size of a particular channel. Erroneous programming does
NOT result in the ’Transmit Command Failed’ interrupt vector.
TCC
Transmit Command Complete
The ’Transmit Command Complete’ interrupt vector is issued after
successful completion of commands ’Transmit Init’ and ’Transmit Off’,
which can be issued via register CSPEC_CMD.XCMD.
CHAN
Channel Number
This bit field contains the channel number of the affected channel.
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Receive Interrupts
•
31
1
30
27
16
0000B
0
0
0
0
0
0
0
7
0
0
0
0
0
0
RCC
15
0
0
0
0
0
0
CHAN(7:0)
RCC
Receive Command Complete
The ’Receive Command Complete’ interrupt vector is issued after
successful completion of commands ’Receive Init’ and ’Receive Off’,
which can be issued via register CSPEC_CMD.RCMD.
CHAN
Channel Number
This bit field contains the channel number of the affected channel.
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Functional Description
4.13.2
Layer One Interrupts
All layer one related interrupts, that is interrupts issued by either the T1/E1 framer, the
M13 multiplexer and DS2/DS3 framer, the facility data link or the PCI to Local Bus
mailbox, are stored in an internal interrupt FIFO which is located inside the
MUNICH256FM and can be read from either the local microprocessor or (for test
purposes) via the chip internal bridge from the host processor located on the PCI bus.
The T1/E1 framer, the facility data link, the M13 multiplexer and DS2/DS3 framer, and
the mailbox forward their specific interrupts to the internal interrupt FIFO. The interrupt
FIFO triggers the LINT pin which indicates that there is at least one interrupt vector
available. The interrupt FIFO then can be read from either PCI side or local bus side. The
interrupt vector contains a coding for the interrupt reason and a last indication when
there is no further interrupt vector stored in the internal interrupt FIFO. The interrupts of
the internal layer one interrupt FIFO or the local bus interrupt LINT can also be reported
via pin INTA.
•
Int. vector setup:
Int. vector setup:
Int. vector setup:
Int. vector setup:
MSK
IMR
[]
FCONF.MID
Facility data
link
M13
Test unit
Framer
1
Mailbox
IV
Interrupt bus II
Interrupt Control:
INTCTRL
Interrupt status:
optional interrupt
notification on INTA
Interrupt FIFO
INTFIFO
EBU
MUNICH256FM
LINT
3
Local uP interface
2
1. Interrupt source forwards interrupt
vector to interrupt FIFO.
2. Interrupt controller asserts LINT (if
enabled).
Microprocessor
3. Microprocessor reads interrupt FIFO.
Figure 4-19 Framer, M13 and Facility Data Link and Mailbox Interrupt Notification
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4.13.2.1 General Interrupt Vector Structure
•
15
14
13
7
6
5
4
0
LAST STYPE
STATUS(6:0)
MID(1:0)
INFO(4:0)
LAST
Last indication
LAST indicates that at least one more valid interrupt vector is stored in
the internal interrupt FIFO. This bit is generated at read access time.
0
1
There is at least one more interrupt in the internal interrupt FIFO.
This interrupt is the last interrupt that is stored in the internal
interrupt FIFO.
STYPE
Subtype of interrupt vector
This bit is used to indicate different subtypes of interrupt vectors.
Interrupt status
STATUS
The interrupt status depends on STYPE and MID. Please refer to the
detailed description of the interrupt vectors in the next chapters.
MID
Module ID
The bit field identifies the interrupt source.
00B
01B
10B
11B
T1/E1 Framer Interrupts
Facility Data Link Interrupts
M13 Multiplexer and DS2/DS3 framer Interrupts
Mailbox Interrupt
INFO
Information
The content of this bit field contains further information about the
interrupt, e.g. the affected port.
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Functional Description
4.13.2.2 T1/E1 Framer Interrupts
The framer interrupts are divided into type 0 and type I interrupts. The distinction is made
in bit 14 of the interrupt vector.
Interrupt Type 0
15
14
0
13
12
11
10
9
8
7
6
6
5
5
4
4
0
0
PRBSS
LAST
AISS LOSS RAS ES SEC LLBS
00B
PORT(4:0)
PORT(4:0)
Interrupt Type I
15
14
11
10
9
8
7
PDEN
/AUX
LAST
1
0
0
T400 CRC
FAS MFAS
00B
AISS
Alarm Indication Signal Status
The ‘Alarm Indication Signal Status’ interrupt vector is generated,
whenever the MUNICH256FM detects a change in the alarm indication.
The actual state, i.e. active/not active, is shown in FRS.AIS.
LOSS
RAS
Loss of Signal Status
The ’Loss of Signal Status’ interrupt vector is generated, whenever the
MUNICH256FM detects a change in FRS.LOS.
Remote Alarm Status
The ’Remote Alarm Status’ interrupt vector is generated, whenever the
MUNICH256FM received remote alarm status changes. The actual
state, i.e. active/not active, is shown in FRS.RRA.
ES
Errored Second
The 'Errored Second' interrupt vector is generated for the first errored
second event in a time interval of one second. Errored second events
are:
1. Loss of frame alignment (this includes indirectly AIS or Loss of Signal)
2. CRC error received (CRC-6 or CRC-4).
One Second Tick
SEC
The ’One Second Tick’ interrupt vector is generated, when the internal
one second timer has expired. The timer is derived from the incoming
receive clock of the corresponding port.
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LLBS
PRBS
T400
Line Loopback Status
The ‘Line Loopback Status’ interrupt vector is generated, whenever the
MUNICH256FM detects a change in either the line loopback deactuation
signal or the line loopback actuate signal. The actual state of the signals
is shown in FRS.LLBDD and FRS.LLBAD.
PRBS Status
The ’PRBS Status’ interrupt vector is generated, whenever the
MUNICH256FM synchronization state of the PRBS receiver changes.
The actual state of the receiver, i.e. synchronized/not synchronized, is
shown in FRS.PRBS.
400 Millisecond
This interrupt vector is generated when the framer has found the double
framing (basic framing) and is searching for the multiframing. This
interrupt vector will be generated to indicate that no multiframing could
be found within a time window of 400 ms after basic framing has been
achieved. In multiframe synchronous state this interrupt will not be
generated.
CRC
Receive CRC Error
This interrupt vector is generated, when the CRC-6 checksum of an T1
ESF multiframe or the CRC-4 checksum of an E1 CRC-4 multiframe was
incorrect.
PDEN/AUX
FAS
Pulse Density Violation Detected / Auxiliary Pattern Detected
This interrupt vector is generated, whenever the MUNICH256FM detects
a change in bit FRS.PDEN/AUX. Bit PDEN/AUX is set whenever bit
FRS.PDEN.AUX toggles.
Frame Alignment Status
The ’Frame Alignment Status’ interrupt vector is generated, whenever
the MUNICH256FM detects a change in frame alignment. The actual
state, i.e. aligne/not aligned, is shown in bit FRS.LFA.
MFAS
Multiframe Alignment Status
The ’Multiframe Alignment Status’ interrupt vector is generated,
whenever the MUNICH256FM detects a change in multiframe
alignment. The actual state, i.e. aligned/not aligned, is shown in bit
FRS.LMFA.
PORT
Port Number
0..27 The port number the interrupt vector is associated with.
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4.13.2.3 Facility Data Link Interrupts
Receive Interrupts
•
15
14
0
11
10
9
8
7
6
5
4
0
LAST
0
0
RSA SSM RPF RME ISF
01B
PORT(4:0)
RSA
Receive Sa Data Valid
Sa data in RSAW1 - RSAW3 is valid.
SSM Data Valid
SSM
This bit is set, when a new synchronization status message has been
received. The synchronization status message is stored in register
RSAW4.
RPF
Receive Pool Full
This bit is set, when 32 bytes of a frame have been received and are
stored in the receive FIFO. The frame is not yet completely received.
RME
Receive Message End
This bit is set, when one complete message of length less than 32 bytes
or the last part of a frame at least 32 bytes long is stored in the receive
FIFO. The number of bytes in RFF.RFIFO can be determined reading
the port status register PSR.
ISF
Incorrect Synchronization Format
This bit is set, when no eight consecutive ‘1’s are detected within 32 bits
in BOM mode. Only valid if BOM receiver has been activated.
PORT
Port Number
0..27 The port number the interrupt vector is associated with.
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Transmit Interrupts
•
15
14
1
10
9
8
7
6
5
4
0
LAST
0
0
0
TXSA ALLS XDU XPR
01B
PORT(4:0)
TXSA
Transmit Sa Data Sent
The ’Transmit Sa Data Sent’ is generated, when Sa data stored in
XSAW1 - XSAW3 has been sent N times, where N is defined prior to
transmission in XSAW3.XSAV.
ALLS
XDU
All Sent
The ’All Sent’ interrupt vector is generated, when the last bit of a frame
to be transmitted is completely sent out and XFF.XFIFO is empty.
Transmit Data Underrun
The ’Transmit Data Underrun’ interrupt vector is generated, when the
transmit FIFO runs out of data during transmission of a frame. The
signalling controller terminates the affected frame with an abort
sequence.
XPR
Transmit Pool Ready
The ’Transmit Pool Ready’ interrupt vector is generated, when a new
data block of up to 32 bytes can be written to transmit FIFO. ’Transmit
Pool Ready’ is the fastest way to access the transmit FIFO. It has to be
used for transmission of long frames, back-to-back frames or frames
with shared flag.
PORT
Port Number
0..27 The port number the interrupt vector is associated with.
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4.13.2.4 DS3, DS2 and Test Unit Interrupts
Note: The DS3, DS2 and test unit interrupts are seperated by the INFO field (bits 4
through 0).
DS3 Interrupts Type 0
•
15
14
0
13
12
11
10
9
8
7
6
6
5
5
4
4
0
0
LAST
AIC XBIT IDLES AISS REDS LOSS FAS
10B
00111H
DS3 Interrupts Type 1
•
15
14
1
13
0
12
11
10
9
8
7
LAST
CLKS RSDL TSDL LPCS SEC
N
10B
00111H
r
CLKS
DS3 Clock Status
The ‘DS3 Clock Status’ interrupt vector is generated whenever the
MUNICH256FM detects a change in the transmit clock or the receive
clock, i.e. clock is activated/deactivated. The actual status of the clock is
shown in D3RSTAT.LRXC and D3RSTAT.LTXC.
RSDL
TSDL
LPCS
Receive Spare Data Link Transfer Buffer Full
The ‘Receive Spare Data Link Transfer Buffer Full’ interrupt vector is
generated when the receive spare data link buffer needs to be emptied.
Transmit Spare Data Link Transfer Buffer Empty
The ‘Transmit Spare Data Link Transfer Buffer Empty’ interrupt vector is
generated when the transmit spare data link buffer needs to be filled.
Loopback Code Status
The ‘Loopback Code Status’ interrupt vector is generated whenever the
MUNICH256FM detects a change in the received loopback codes.
Actual loopback codes can be found in register D3RLPCS.
SEC
Nr
1 Second Interrupt
The ‘1 Second Interrupt’ is generated every second.
Received new Nr-Bit
The ‘Received new Nr-Bit’ interrupt vector is generated whenever the
MUNICH256FM detects a change in the NA overhead bits and when its
state is persistent for at least three multiframes.
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Functional Description
AIC
Received new AIC-Bit
The ‘Received new AIC-Bit’ interrupt vector is generated whenever the
MUNICH256FM detects a change in the AIC overhead bits and when its
state is persistent for at least three multiframes.
XBIT
IDLES
AISS
REDS
LOSS
FAS
Received X-Bit
The ‘Received new X-Bit’ interrupt vector is generated whenever the
MUNICH256FM detects a change in the X overhead bits and when its
state is persistent for at least three multiframes.
DS3 Idle Signal Status
The ‘DS3 Idle Signal Status’ interrupt vector is generated whenever the
MUNICH256FM detects a change of the idle signal. D3RSTAT.IDLES
contains the actual state of the idle state, i.e. active/not active.
DS3 Alarm Indication Signal Status
The ‘DS3 Alarm Indication Signal Status’ is generated whenever the
MUNICH256FM detects a change in the AIS alarm state.
D3RSTAT.AISS shows the actual AIS alarm state, i.e. active/not active.
DS3 Red Alarm Status
The ‘DS3 Red Alarm’ interrupt vector is generated whenever the
MUNICH256FM detects a change in the red alarm state.
D3RSTAT.RED shows the actual red alarm state, i.e. active/not active.
DS3 Input Signal Status
The ‘DS3 Input Signal Status’ interrupt vector is generated whenever the
MUNICH256FM detects a change in the DS3 input signal state, i.e. loss/
no loss. D3RSTAT.LOSS shows the actual state of the DS3 input signal.
DS3 Frame Alignment Status
The ‘DS3 Frame Alignment Status’ interrupt vector is generated
whenever the MUNICH256FM detects a change in the DS3 frame
alignment. D3RSTAT.FAS shows the actual state.
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DS2 Framer Interrupts
Note: The effected DS2 tributary is encoded in the INFO field (bits 4..0).
•
15
14
0
12
11
10
9
8
7
6
5
4
0
LAST
0
LPCS AISS REDS RES RAS FAS
10B
00000H - 00110H
LPCS
AISS
REDS
RES
Loop Code Status
The ‘Loopback Code Status’ interrupt vector is generated whenever the
MUNICH256FM detects a change in the received loopback codes.
Actual loopback codes can be found in register D2RLPCD.
DS2 Alarm Indication Signal Status
The ‘DS2 Alarm Indication Signal Status’ is generated whenever the
MUNICH256FM detects a change in the AIS alarm state. D2RSTAT.AIS
shows the actual AIS alarm state, i.e. active/not active.
DS2 Red Alarm Status
The ‘DS2 Red Alarm Status’ interrupt vector is generated whenever the
MUNICH256FM detects a change in the red alarm state.
D3RSTAT.RED shows the actual red alarm state, i.e. active/not active.
Received new Reserved ITU-T G.747 Overhead Bit
The ‘Received new Reserved ITU-T G.747 Overhead Bit’ interrupt
vector is generated whenever the MUNICH256FM detects a change in
the reserved ITU-T G.747 overhead bit and when its state is persistent
for at least three multiframes. D2R[].[] shows the actual state of the
overhead bit.
RAS
FAS
Remote Alarm Status
The ’Remote Alarm Status’ interrupt vector is generated whenever the
MUNICH256FM detects a change in the remote alarm indication and
when its state is persistent for at least three multiframes. D2RSTAT.RA
shows the actual state of the remote alarm indication.
DS2 Frame Alignment Status
The ‘DS2 Frame Alignment Status’ interrupt vector is generated
whenever the MUNICH256FM detects a change in the DS2 frame
alignment. D2RSTAT.LFA shows the actual status of frame alignment.
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Test Unit Interrupts Type 0
•
15
14
0
11
10
9
8
7
6
5
4
0
LAST
0
0
EMI LBE A1
A0 OOS
10B
01000H
OOS
Receiver Out Of Synchronization
The ’Receiver Out of Synchronization’ interrupt vector is generated
whenever the test unit detects a change in synchronization. The actual
state of the receiver is shown in TURSTAT.OOS.
A0
A1
Input all ‘0’s
The ‘Input all ‘0’s’ interrupt vector is generated whenever the
MUNICH256FM detects 32 continuous ‘0’s or when this consition is
resolved. The actual state is shown in TURSTAT.A0.
Input all ‘1’s
The ‘Input all ‘1’s’ interrupt vector is generated whenever the
MUNICH256FM detects 32 continuous ‘1’s or when this consition is
resolved. The actual state is shown in TURSTAT.A1.
LBE
EMI
Latched Bit Error Detected Flag
The ’Latched Bit Error Detected Flag’ interrupt vector is generated with
the first occurance of a bit error.
End of Measurement Interval
The ‘End of Measurement Interval’ interrupt vector is generated when
the end of the programmed measurement interval is reached.
4.13.2.5 Mailbox Interrupts
•
15
14
0
13
7
6
5
4
0
LAST
STATUS(6:0)
11B
00000B
The ’Mailbox’ interrupt vector is generated, in case that the host CPU on PCI side has
written data to the mailbox status register MBP2E0. The bit field STATUS contains a
copy of MBE2P0.MB(6:0).
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5
Interface Description
5.1
PCI Interface
A 32-bit and 66 MHz capable PCI bus controller provides the interface between the
MUNICH256FM and the host system. PCI Interface pins are measured as compliant to
the 3.3V signalling environment according to the PCI specification Rev. 2.1.
The PCI bus controller operates as initiator or target. Commands are supported as
follows:
• Master memory read single DWORD/burst of up to 64 DWORDs with zero wait cycles.
• Master memory write single DWORD/burst of up to 64 DWORDs with zero wait cycles.
• Slave memory read single DWORD.
• Slave memory write single DWORD.
Fast back-to-back transfers are provided for slave accesses only. All read/write
accesses to the MUNICH256FM must be 32-bit wide, that is all bytes must be enabled.
Non 32-bit accesses result in system interrupt.
Refer also to the PCI specification Rev. 2.1 for detailed information about PCI bus
protocol.
5.1.1
PCI Read Transaction
The transaction starts with an address phase which occurs during the first cycle when
FRAME is activated (clock 1 in Figure 5-1). During this phase the bus master (initiator)
outputs a valid address on AD(31:0) and a valid bus command on C/BE (3:0). The first
clock of the first data phase is clock 3. During the data phase C/ BE indicate which byte
lanes on AD(31: 0) are involved in the current data phase.
The first data phase on a read transaction requires a turnaround cycle. In Figure 5-1 the
address is valid on clock 2 and then the master stops driving AD. The target drives the
AD lines following the turnaround when DEVSEL is asserted. (TRDY cannot be driven
until DEVSEL is asserted.) The earliest the target can provide valid data is clock 4. Once
enabled, the AD output buffers of the target stay enabled through the end of the
transaction.
A data phase may consist of a data transfer and wait cycles. A data phase completes
when data is transferred, which occurs when both IRDY and TRDY are asserted. When
either is deasserted a wait cycle is inserted. In the example below, data is successfully
transferred on clocks 4, 6 and 8, and wait cycles are inserted on clocks 3, 5 and 7. The
first data phase completes in the minimum time for a read transaction. The second data
phase is extended on clock 5 because TRDY is deasserted. The last data phase is
extended because IRDY is deasserted on clock 7. The Master knows at clock 7 that the
next data phase is the last. However, the master is not ready to complete the last
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transfer, so IRDY is deasserted on clock 7, and FRAME stays asserted. Only when IRDY
is asserted can FRAME be deasserted, which occurs on clock 8.
•
1
2
3
4
5
6
7
8
CLK
FRAME
AD
Address
Data 1
Data 2
Data 3
Command
BE’s
C/BE
IRDY
TRDY
DEVSEL
Address
phase
Data
phase
Data
phase
Data
phase
Bus transaction
Figure 5-1
PCI Read Transaction
5.1.2
PCI Write Transaction
The transaction starts when FRAME is activated (clock 1 in Figure 5-2). A write
transaction is similar to a read transaction except no turnaround cycle is required
following the address phase. In the example, the first and second data phases complete
with zero wait cycles. The third data phase has three wait cycles inserted by the target.
Both initiator and target insert a wait cycle on clock 5. In the case where the initiator
inserts a wait cycle (clock 5), the data is held on the bus, but the byte enables are
withdrawn. The last data phase is characterized by IRDY being asserted while the
FRAME signal is deasserted. This data phase is completed when TRDY goes active
(clock 8).
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•
1
2
3
4
5
6
7
8
CLK
FRAME
AD
Address
Data 1
BE 1
Data 2
BE 2
Data 3
Command
BE 3
C/BE
IRDY
TRDY
DEVSEL
Address
phase
Data
phase
Data
phase
Data
phase
Bus transaction
Figure 5-2
5.2
PCI Write Transaction
SPI Interface (ROM Load Unit)
Additional pins, which are not covered from the PCI specification, but are closely related,
are the SPI pins. Via the SPI pins the vendor ID and the vendor subsystem ID can be
loaded into the corresponding PCI configuration registers during start-up of the device.
The SPI Interface supports EEPROMs with an eight bit address space.
After a system reset, the MUNICH256FM starts reading the first byte out of the
connected EEPROM at address 00H. If this byte is equal AAH, the device continues
reading out the memory contents. Everytime four bytes are read out of the EEPROM
(starting with byte address 01H), the EEPROM interface writes the read information to
the PCI configuration space. The first four bytes will be written to the PCI configuration
space address 00H, the next four bytes to the PCI configuration space address 04H and
so on. So the contents of the EEPROM, starting with EEPROM byte address 01H, will be
mapped over the PCI configuration space after a system reset. During this configuration
phase, all accesses to the PCI interface will be answered with ‘retry’ by the PCI interface.
If the first byte in the EEPROM is not equal AAH, the EEPROM interface stops loading
the PCI configuration space immediately, and the PCI interface can be accessed. The
PCI configuration space in this case contains the default values.
The configuration mechanism through the serial interface can be disabled by pin
SPLOAD. If this pin is connected to ‘0’, the configuration mechanism is disabled. The
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bridge can be accessed through the PCI Interface directly after a system reset. In this
case the PCI configuration space contains the default values.
5.2.1
Accesses to a SPI EEPROM
The EEPROM contents can also be controlled (read and write) by the software. For this,
a special EEPROM control register is implemented as part of the PCI configuration
space. To start a read/write transaction to an connected EEPROM, you have to set the
command, the byte address (for read-/write data commands), the data to be written and
the start indication by writing to the EEPROM control register SPI in the PCI
configuration space. If the interface detects SPI.START asserted (= ‘1’), it interprets the
command and starts the read-/write transaction to the connected EEPROM. After the
transaction has finished, the EEPROM control module deasserts the start bit. If the
command was a read command (Read Status Register, Read Data from Memory Array),
the byte that was read out of the EEPROM is available in the data register. For
transactions started with the EEPROM Control register, the interface does not check if
an EEPROM is connected to the SPI bus, because the EEPROM is full passive. A full
functional description of the SPI commands and their usage as well as a description of
the EEPROMs status register can be found in the description of the EEPROM that will
be selected by a board vendor.
Byte Address
For read and write transaction to the connected EEPROM, the byte address must be
written in this register before the transaction is started.
Data
For the write status register transaction and the write data to memory array transactions,
the data that has to be written to the EEPROM must be written to this register before the
transaction is started. After a read status register transaction or a read data from memory
array transaction has finished (Bit SPI.START is deasserted), the byte received from the
EEPROM is available in this register.
Start
To start the EEPROM transaction defined via register SPI the bit SPI.START must be
set to ‘1’ by a write transaction through the PCI interface. After the transaction is finished,
the EEPROM start bit is deasserted by the EEPROM interface controller. This signal has
to be polled by system software.
5.2.2
SPI Read Sequence
The MUNICH256FM selects an external EEPROM by pulling SPCS low. The eight bit
read sequence is transmitted followed by the eight bit address. After the read instruction
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and address is sent, the data stored in the memory at the selected address is shifted in
on the SPSI pin. The read operation is terminated by setting SPCS high (see Figure 5-
3).
•
SPCS
0
0
1
0
2
0
3
4
5
6
1
7
1
8
9
14 15 16 17 18 19 20 21 22 23
SPCLK
SPSO
SPSI
instruction
8 bit address
0
0
0
7
6
0
data in
7
6
5
4
3
2
1
0
Figure 5-3
SPI Read Sequence
5.2.3
SPI Write Sequence
Prior to any attempt to write data to an external EEPROM, the write enable latch must
be set by issuing the WREN instruction. This is done by setting SPCS low and then
clocking out the WREN instruction. After all eight bits of the instruction are transmitted,
the SPCS will be brought high to set the write enable latch.
Once the write enable latch is set, the user may proceed by issuing a write instruction,
followed by the eight bit address and then the data to be written. In order that data will
actually be written to the EEPROM, the SPCS is set high after the least significant bit
(D0) of the data byte has been clocked in. Refer to Figure 5-4 for detailed illustrations
on the byte write sequence. While the write is in progress, the register bit SPI.START
may be read to check the status of the transaction. When a write cycle is completed, the
register bit SPI.START is reset.
•
SPCS
0
0
1
0
2
0
3
4
5
6
1
7
0
8
9
14 15 16 17 18 19 20 21 22 23
SPCLK
SPSO
SPSI
instruction
8 bit address
data out
0
0
0
7
6
0
7
6
5
4
3
2
1
0
Figure 5-4
SPI Write Sequence
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5.3
Local Microprocessor Interface
The Local Microprocessor Interface is a demultiplexed switchable Intel or Motorola style
interface with master and slave functionality. In slave mode it is used to operate the M13
multiplexer, DS3/DS2 framer, T1/E1 framer and the facility data link of the
MUNICH256FM. The MUNICH256FM provides a local clock output LCLK, which is a
feed through of the PCI system clock as clock reference for the local microprocessor
interface. The local bus master capability allows to access peripherals located on the
local bus via the PCI interface. Bit FCONF.LME enables the bus master capability.
The base address register two is disabled per default and can be enabled during start-
up of the internal PCI interface. This is done by setting bit MEM.BAR2 in the PCI
configuration space.
The MUNICH256FM supports a maximum of three 8 kByte pages of memory on the local
address bus. The correspondence between the accessed PCI memory space (mapped
via base address register 2) and the asserted chip selects is shown in table 5-1. The
mapping of the PCI byte enables to the local bus address is dependent on the selected
bus mode and is explained in detail in the corresponding section.
Table 5-1
Correspondence between PCI memory space and chip select
Page
AD(14:0)
LCS2
LCS1
0
1
2
3
0000H - 1FFFH
2000H - 3FFFH
4000H - 5FFFH
6000H - 7FFFH
1
0
0
0
1
0
Not valid
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5.3.1
Intel Mode
5.3.1.1 Slave Mode
In Intel slave mode the bus interface supports 16-bit transactions in demultiplexed bus
operation. It uses the local bus port pins LA(12:1) for the 16 bit address and the local bus
port pins LD(15:0) for 16 bit data. A read/write access is initiated by placing an address
on the address bus and asserting LCS0 (Figure 5-5). The external processor then
activates the respective command signal (LRD, LWR). Data is driven onto the data bus
either by the MUNICH256FM (for read cycles) or by the external processor (for write
cycles). After a period of time, which is determined by the access time to the internal
registers valid data is placed on the bus, which is indicated by asserting the active low
signal LRDY.
Note: LCS0 need not be deasserted between two subsequent cycles to the same
device.
Read cycles
Input data can be latched and the command signal can be deactivated now. This causes
the MUNICH256FM to remove its data from the data bus which is then tri-stated again.
LRDY is driven high and will be tri-stated as soon as LCS0 is deasserted.
Write cycles
The command signal can be deactivated now. If a subsequent bus cycle is required, the
external processor can place the respective address on the address bus.
5.3.1.2 Master Mode
A read/write access from the PCI bus to the 16 bit demultiplexed local bus is initiated by
accessing the PCI memory space base which is controlled by the base address
register 2. Each valid read or write access to this base address triggers the local bus
master interface which in turn starts arbitration for the local bus by asserting LHOLD (see
(1) in Figure 5-6). As soon as the MUNICH256FM gets access to the local bus (LHLDA
asserted) it starts the local bus latency timer and begins a read/write transaction as the
bus master. The signal LHOLD remains asserted while a transaction is in progress or as
long as the local bus latency timer is not expired. A read/write transaction begins when
the MUNICH256FM places a valid address on the address bus, sets the LBHE signal
which indicates a 8- or 16-bit bus access and asserts the chip select signals LCS1 and/
or LCS2. Then the MUNICH256FM activates the respective command signals (LRD,
LWR). Data is driven onto the data bus either by the MUNICH256FM (for write cycles)
or by the accessed device (for read cycles).
A transaction is finished on the local bus when the external device asserts LRDY (ready
controlled bus cycles) or when the internal wait state timer expires.
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•
Read Cycle (16 Bit)
Address
Write Cycle (8 bit1)
Address
LA(12:0)
LBHE1
LCS0 (In)
LCS1,2 (Out)
LRD
LWR
LRDY2
LD(15:0)
Data
Data
Note 1: Supported in local bus master mode only.
Note 2: Ready controlled bus cycles only.
Figure 5-5
Intel Bus Mode
•
LHOLD remains asserted as long as a transaction is in
progress or while the latency timer is not expired
1
LHOLD
LHLDA
2
Bus
Cycle
Read/Write Cycle
3
One or more
read/write cycles as bus master
Figure 5-6
Intel Bus Arbitration
Valid C/BE combinations and the correspondence between local address, LBHEand the
mapping of PCI data to the local data bus are shown in table 5-2 and table 5-3. All
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accesses not shown in the table result in generation of a ’PCI Access Error’ interrupt
vector.
Table 5-2
C/BE to LA/LBHE mapping in Intel bus mode (8 bit port mode)
C/BE(3:0)
1110B
LA(1:0)
00B
LBHE
LD(15:8)
LD(7:0)
AD(7:0)
1
1
1
1
-
-
-
-
1101B
01B
AD(15:8)
AD(23:16)
AD(31:24)
1011B
10B
0111B
11B
Table 5-3
C/BE to LA/LBHE mapping in Intel bus mode (16 bit port mode)
C/BE(3:0)
1110B
1101B
1011B
0111B
1100B
0011B
LA(1:0)
00B
LBHE
LD(15:8)
-
LD(7:0)
AD(7:0)
-
1
0
1
0
0
0
01B
AD(15:8)
-
10B
AD(23:16)
-
11B
AD(31:24)
AD(15:8)
AD(31:24)
00B
AD(7:0)
AD(23:16)
10B
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5.3.2
Motorola Mode
5.3.2.1 Slave Mode
The demultiplexed bus modes use the local bus port pins LA(12:1) for the 16- bit address
and the local bus port pins LD(15:0) for 16 bit data. A read/write access is initiated by
placing an address on the address bus and asserting LCS0 together with the command
signal LWRRD (see "Motorola Bus Mode" on page 156). The data cycle begins when the
signal LDS is asserted. Data is driven onto the data bus either by the MUNICH256FM
(for read cycles) or by the external processor (for write cycles). After a period of time,
which is determined by the access time to the internal registers valid data is placed on
the bus, which is indicated by asserting the active low signal LDTACK.
Note: LCS0 need not be deasserted between two subsequent cycles to the same
device.
Read cycles
Input data can be latched and the data strobe signal can be deactivated now. This
causes the MUNICH256FM to remove its data from the data bus which is then tri-stated
again. LDTACK is driven high and will be tri-stated as soon as LCS0 is deasserted.
Write cycles
The data strobe signal can be deactivated now. If a subsequent bus cycle is required,
the external processor can place the respective address on the address bus.
5.3.2.2 Master Mode
As in Intel mode a read/write access from the PCI bus to the 16 bit demultiplexed local
bus is initiated by accessing the PCI memory space base mapped by the base address
register 2. Each valid read or write access to this base address triggers the local bus
master interface which in turn starts arbitration for the local bus using the interface
signals LBR and LBG and LBGACK. As soon as the MUNICH256FM gets access to the
local bus it places a valid address on the address bus, sets the LSIZE0 signal which
indicates a 8- or 16-bit bus access and asserts the corresponding chip select signal. The
signal LWRRD indicates a read or write operation. The data cycle begins when the signal
LDS is asserted. Data is driven onto the data bus either by the MUNICH256FM or by the
external component.
A transaction is finished on the local bus when the external device asserts the active low
signal LDTACK or when the internal wait state timer expires.
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•
Read Cycle (8 bit1)
Address
Write Cycle (16 bit)
Address
LA(12:0)
LSIZE01
LCS0 (In)
LCS1,2 (Out)
LDS
LRDWR
LDTACK2
LD(15:0)
Data
Data
Note 1: Supported in local bus master mode only.
Note 2: LDTACK controlled bus cycles only.
Figure 5-7
Motorola Bus Mode
•
LBGACK remains asserted as long as a
transaction is in progress or while the latency
timer is not expired.
1
LBR
LBG
2
LBGACK
Bus
Cycle
RD/WR Cycle
3
One or more
read/write cycles as bus master
Figure 5-8
Motorola Bus Arbitration
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The address and byte enable signals on the PCI bus are mapped to the local bus
according to table 5-4 and table 5-5. It can be seen that the MUNICH256FM supports
different valid C/BE combinations which result in either a 8- or 16-bit access to the local
bus interface. All accesses not shown in the table result in generation of a ’PCI Access
Error’ interrupt vector. Byte swapping for 16 bit data transfers can be disabled.
Table 5-4
C/BE to LA/LSIZE0 mapping in Motorola bus mode (8 bit port mode)
C/BE(3:0)
1110B
LA(1:0)
00B
LSIZE0
LD(15:8)
AD(7:0)
LD(7:0)
1
1
1
1
-
-
-
-
1101B
01B
AD(15:8)
AD(23:16)
AD(31:24)
1011B
10B
0111B
11B
Table 5-5
C/BE to LA/LSIZE0 mapping in Motorola bus mode (16 bit port mode)
C/BE(3:0)
1110B
1101B
1011B
0111B
1100B
0011B
LA(1:0)
00B
LSIZE0
LD(15:8)
AD(7:0)
-
LD(7:0)
1
1
1
1
0
0
01B
AD(15:8)
-
10B
AD(23:16)
-
11B
AD(31:24)
AD(15:8)
AD(31:24)
00B
AD(7:0)
AD(23:16)
10B
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5.4
Serial Line Interface
The DS3 interface of the MUNICH256FM consists of one receive port and one transmit
port. The receive port provides a clock input (RC44) and one (RD44) or two data inputs
(RD44P, RD44N) for unipolar or dual-rail input signals. Receive data can be sampled on
the rising or falling edge of the receive clock. In transmit direction the port interface
consists of two clock signals, the transmit clock input TC44 and a clock output signal
TC44O. The data signals consists of one (TD44) or two data outputs (TD44P, TD44N)
for unipolar or dual-rail output signals. The transmit port can be clocked by the receive
clock RC44 or by the transmit clock TC44. The selected clock is provided as an output
on TC44O. Transmit data is updated on the rising or falling edge of TC44O.
The MUNICH256FM provides two additional serial interfaces, one for DS3 overhead bit
access and one for DS3 stuff bit access (M13 asynchronous format only).
The overhead access is provided via an overhead clock signal (ROVHCK, TOVHCK), an
overhead data signal (ROVHD, TOVHD) and an synchronization signal (ROVHSYN,
TOVHSYN) which marks the X overhead bit of the first subframe of a DS3 signal. In
transmit direction the overhead enable signal (TOVHEN) marks those bits which shall be
inserted in the overhead bits of the DS3 signal. All overhead signals are updated or
sampled on the rising edge of the corresponding overhead clock, i.e. ROVHCK or
TOVHCK. See Figure 5-9 and Figure 5-10 for details.
•
7th subframe
1st subframe
RC44
RD44
F1
84 data bits
X
4 data bits
F1
84 data bits
C11
ROVHCK
ROVHD
ROVHSYN
F1
X
F1
Figure 5-9
Receive Overhead Access
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•
1. Transmit Overhead Bit Access (TOVHSYN in output mode)
7th subframe
1st subframe
TC44O
TD44
C73
4 data bits
F1
4 data bits
X
84 data bits
F1
TOVHCK
TOVHD
F1
X
F1
TOVHSYN
(Output mode)
TOVHEN
2. Transmit Overhead Bit Access (TOVHSYN in input mode)
7th subframe
1st subframe
TC44O
TD44
C73
4 data bits
F1
4 data bits
X
84 data bits
F1
TOVHSYN
(Input mode)
TOVHCK
TOVHD
F1
X
F1
TOVHEN
Figure 5-10 Transmit Overhead Access
The stuff bit access is provided via a receive and transmit stuff bit clock (RSBCK,
TSBCK) and the two stuff bit signals RSBD and TSBD. Stuff bits are updated and
sampled on the rising edge of the of stuff bit clock.
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5.5
JTAG Interface
A test access port (TAP) is implemented in the MUNICH256FM. The essential part of the
TAP is a finite state machine (16 states) controlling the different operational modes of
the boundary scan. Both, TAP controller and boundary scan, meet the requirements
given by the JTAG standard: IEEE 1149.1. Figure 5-11 gives an overview about the TAP
controller.
•
Test Access Port (TAP)
TCK
Pins
CLOCK
Clock Generation
1
2
CLOCK
.
.
.
TRST
TMS
TDI
Reset
TAP Controller
Test
Control
Control
Bus
- Finite State Machine
- Instruction Register (4 bit)
- Test Signal Generator
.
.
.
Data in
ID Data out
TDO
Enable
SS Data
out
n
Data out
Figure 5-11 Block Diagram of Test Access Port and Boundary Scan Unit
If no boundary scan operation is planned TRST has to be connected with VSS. TMS and
TDI do not need to be connected since pull- up transistors ensure high input levels in this
case. Nevertheless it would be a good practice to put the unused inputs to defined levels.
In this case, if the JTAG is not used:
TMS = TCK = ‘1’ is recommended.
Test handling (boundary scan operation) is performed via the pins TCK (Test Clock),
TMS (Test Mode Select), TDI (Test Data Input) and TDO (Test Data Output) when the
TAP controller is not in its reset state, i. e. TRST is connected to VDD3 or it remains
unconnected due to its internal pull up. Test data at TDI are loaded with a clock signal
connected to TCK. ‘1’ or ‘0’ on TMS causes a transition from one controller state to
another; constant ‘1’ on TMS leads to normal operation of the chip.
An input pin (I) uses one boundary scan cell (data in), an output pin (O) uses two cells
(data out, enable) and an I/O-pin (I/O) uses three cells (data in, data out, enable). Note
that most functional output and input pins of the MUNICH256FM are tested as I/O pins
in boundary scan, hence using three cells. The boundary scan unit of the
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MUNICH256FM contains a total of n = 484 scan cells. The desired test mode is selected
by serially loading a 4-bit instruction code into the instruction register via TDI (LSB first).
EXTEST is used to examine the interconnection of the devices on the board. In this test
mode at first all input pins capture the current level on the corresponding external
interconnection line, whereas all output pins are held at constant values (‘0’ or ‘1’). Then
the contents of the boundary scan is shifted to TDO. At the same time the next scan
vector is loaded from TDI. Subsequently all output pins are updated according to the new
boundary scan contents and all input pins again capture the current external level
afterwards, and so on.
INTEST supports internal testing of the chip, i. e. the output pins capture the current level
on the corresponding internal line whereas all input pins are held on constant values (‘0’
or ‘1’). The resulting boundary scan vector is shifted to TDO. The next test vector is
serially loaded via TDI. Then all input pins are updated for the following test cycle.
SAMPLE/PRELOAD is a test mode which provides a snapshot of pin levels during
normal operation.
IDCODE: A 32-bit identification register is serially read out via TDO. It contains the
version number (4 bits), the device code (16 bits) and the manufacturer code (11 bits).
The LSB is fixed to ‘1’.
The ID code field is set to
Version
: 2H
Part Number : 0076H
Manufacturer : 083H (including LSB, which is fixed to ’1’)
Note: Since in test logic reset state the code ‘0011’ is automatically loaded into the
instruction register, the ID code can easily be read out in shift DR state.
BYPASS: A bit entering TDI is shifted to TDO after one TCK clock cycle.
CLAMP allows the state of signals driven from component pins to be determined from
the boundary-scan register while the bypass register is selected as the serial path
between TDI and TDO. Signals driven from the MUNICH256FM will not change while the
CLAMP instruction is selected.
HIGHZ places all of the system outputs in an inactive drive state.
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6
Channel Programming / Reprogramming Concept
For channel programming the MUNICH256FM provides a on-chip channel specification
data structure. All information necessary to setup a channel has to be provided using this
data structure. As soon as all channel information has been written to the channel
specification registers the information can be released using simple channel commands,
which have to be written to register CSPEC_CMD. The relevant channel information will
then be copied to the chip internal channel database. The channel specification
registers, which need to be programmed before a command can be executed, are shown
in Table 6-1.
Before initializing a channel the time slot assignment process for the affected channel
must be completed. Vice versa after shutting down a channel the time slots associated
with the affected channel should be set to inhibit. Otherwise if a time slot is
reprogrammed afterwards, strange behavior can be expected on the serial side.
For each channel a simple sequence of channel commands must be ensured. After reset
each channel is in its ’off’ state. Therefore, the first command to start a channel is
’Transmit Init’ or ’Receive Init’. This brings the channel into the operational state. In this
state all commands except ’Transmit Init’, ’Receive Init’ or ’Transmit Idle can be given.
To bring a channel back into the idle state a ’Transmit Off’ or ’Receive Off’ command has
to be programmed. For certain channel commands system software has to wait before
new commands can be given for the same channel. This is due to internal buffer
allocation functions which require some processing time. Notification of system software
is done in form of command interrupt vectors, which signal that a command has
successful or even unsuccessful completed.
Table 6-1
Register
Channel Specification Registers and Channel Commands
Transmit Commands
Receive
Commands
CSPEC_MODE_REC
CSPEC_REC_ACCM
CSPEC_MODE_XMIT
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Register
Transmit Commands
Receive
Commands
CSPEC_XMIT_ACCM
CSPEC_BUFFER
CSPEC_FRDA
CSPEC_FTDA
CSPEC_IMASK
6.1
Channel Commands
The following section describes all receive and transmit channel commands and the
programming sequence in details.
6.2
Transmit Channel Commands
Transmit Init
Before a ’Transmit Init’ command is given, the MUNICH256FM will not transmit data for
a channel. After the ’Transmit Init’ command the channel database of the affected
channel is initialized according to the parameters in the channel specification registers.
After initialization the transmit buffer prepares the buffer locations for the selected
channel and the data management unit starts processing the linked list and fills the
prepared buffer locations. In order to prevent a transmit underrun condition, the transmit
buffer is filled up to the transmit forward threshold before data is sent to the serial side.
The protocol machine formats data according to the given channel parameters and the
data is placed in the time slots assigned to the selected channel. When no or not
sufficient data is available, the device sends the idle code according the selected
protocol mode.
If the command was successful, a ’Transmit Command Complete’ interrupt vector is
generated after the first transmit descriptor is read pointed to by register CSPEC_FTDA.
In case that there is insufficient transmit buffer space, the command cannot be
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completed internally and the device responds with a ’Transmit Command Failed’
interrupt vector. Furthermore the MUNICH256FM will not start processing the linked list
for this particular channel.
New commands for the same channel may be given after the user received the ’Transmit
Command Complete’ interrupt vector. Prior to new initialization of the same channel it
must be turned off using the ’Transmit Off’ command.
Transmit Off
After ’Transmit Off’ the transmit channel is disabled immediately and the time slots
assigned to the selected channel are set to ’1’. The transmit buffer releases all buffer
locations assigned to the channel. The data management unit updates the last
processed descriptor with the complete bit if enabled and generates a ’Transmit Host
Initiated’ interrupt vector if the THI bit in the last descriptor was set. All channel related
informations are cleared from the internal channel database.
A ’Transmit Command Complete’ interrupt vector is generated when the channel
command is finished. After that time processing of the linked list is completely stopped.
New commands for the same channel may be given after the user received the ’Transmit
Command Complete’ interrupt vector.
Transmit Abort/Branch
The ’Transmit Abort/Branch’ command is performed on the serial side and in the data
management unit. The data management unit stops immediately processing the current
descriptor and branches to a new descriptor pointed to by CSPEC_FTDA. Data which is
already stored in the transmit buffer is sent on the serial side. The protocol machine will
append an abort sequence if data in transmit buffer was not complete due to ’Transmit
Abort/Branch’ command. System software is informed about the aborted frame by a
’Transmit Abort’ channel interrupt vector. If no data is stored in the transmit buffer this
command does not affect the serial side and no ’Transmit Abort’ interrupt vector is
generated. Data transmission is continued with a new frame when the data management
unit branched to the new descriptor list.
A ’Transmit Command Complete’ interrupt vector is generated after the management
unit released the old descriptor list. New commands for the same channel may be given
after the user received the ’Transmit Command Complete’ interrupt vector.
Transmit Hold Reset
The ’Transmit Hold Reset’ command must be given after system software has set the
HOLD bit of a descriptor from ’1’ to ’0’. In case that the MUNICH256FM is in hold
condition it reads the descriptor which had its HOLD bit set and tests the HOLD bit of the
descriptor. If the HOLD bit is set to ’0’ the data management unit branches to the next
descriptor and continues data transmission. Otherwise the particular channel remains in
hold condition.
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The MUNICH256FM will NOT generate a ’Transmit Command Complete’ interrupt
vector after this command is programmed.
Transmit Update FNUM
The
’Transmit
Update
FNUM’
command
changes
the
parameter
CSPEC_MODE_XMIT.FNUM in the internal channel database, which allows to change
dynamically the number of idle flags that are inserted between two frames.
The MUNICH256FM will NOT generate a ’Transmit Command Complete’ interrupt
vector after this command is programmed.
Transmit Idle
The ’Transmit Idle’ command starts the MUNICH256FM to send the value
CSPEC_MODE_XMIT.TFLAG in the time slots of the selected channel. This command
can only be given if a channel is turned off.
The MUNICH256FM will NOT generate a ’Transmit Command Complete’ interrupt
vector after this command is programmed.
Transmit Debug
The ’Transmit Debug’ command allows to read back the current settings of the internal
channel database. After the ’Transmit Debug’ command has been programmed system
software can read back the current values of the channel specification registers. Register
CSPEC_FTDA contains the value of the next transmit descriptor.
The MUNICH256FM will NOT generate a ’Transmit Command Complete’ interrupt
vector after this command is programmed.
Note: The setting of the internal channel database is not copied into the channel
specification registers and therefore the values read can not be used to program
another channel. After system software has used the ’Transmit Debug’ command
it must reprogram the channel specification registers to setup a new channel.
6.3
Receive Channel Commands
Receive Init
Before a ’Receive Init’ command is given, the MUNICH256FM will not process data for
a channel. After the ’Receive Init’ command the channel database of the affected
channel is initialized according to the parameters programmed in channel specification
registers.
After initialization data received in those time slots assigned to the selected channel is
processed and stored in the internal receive buffer. The data management unit starts
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Channel Programming / Reprogramming Concept
storing this data in the linked list which starts at CSPEC_FRDA. The protocol machine
deformats and checks data according to the given channel parameters.
A ’Receive Command Complete’ interrupt vector is generated after the channel
information is copied into the internal channel database.
New commands for the same channel may be given after the MUNICH256FM issued the
’Receive Command Complete’ interrupt vector. Prior to new initialization of the same
channel it must be turned off using the ’Receive Off’ command.
Receive Off
The ’Receive Off’ command disables the receive channel immediately. Further incoming
data is discarded until the next ’Receive Init’ command is given. Data already stored in
the receive buffer is written to system memory. If a frame is destroyed by the ’Receive
Off’ command a ’Receive Abort’ channel interrupt vector is generated.
A ’Receive Command Complete’ interrupt vector is generated after remaining data in the
receive buffer is written to system memory. After that time processing of the linked list is
stopped and the channel information is cleared from the internal channel database.
New commands for the same channel may be given after the MUNICH256FM issued the
’Receive Command Complete’ interrupt vector.
Receive Abort/Branch
The ’Receive Abort/Branch’ command is performed in the data management unit. The
data management unit stops immediately processing the current descriptor and
branches to a new descriptor pointed to by CSPEC_FRDA. In case that the ’Receive
Abort/Branch’ command is issued while a packet is written to system memory a ’Receive
Abort’ interrupt vector is generated and the rest of the frame already stored in receive
buffer is discarded. Data reception is continued with a new frame when the data
management unit branched to the new descriptor list.
A ’Receive Command Complete’ interrupt vector is generated after the channel
information is copied into the internal channel database. New commands for the same
channel may be given after the MUNICH256FM issued the ’Receive Command
Complete’ interrupt vector.
Receive Hold Reset
The ’Receive Hold Reset’ command must be given after system software has set the
HOLD bit of a receive descriptor from ’1’ to ’0’. In case that the MUNICH256FM is in hold
condition it reads the descriptor which had its HOLD bit set and tests the HOLD bit of the
descriptor. If the HOLD bit is set to ’0’ the data management unit branches to the next
descriptor and continues data reception. Otherwise the particular channel remains in
hold condition.
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Channel Programming / Reprogramming Concept
The MUNICH256FM will NOT generate a ’Receive Command Complete’ interrupt vector
after this command is programmed.
Receive Debug
The ’Receive Debug’ command allows to read back the current settings of the internal
channel database. After the ’Receive Debug’ command has been programmed system
software can read back the current values of the channel specification registers. Register
CSPEC_FRDA contains the value of the next receive descriptor.
The MUNICH256FM will NOT generate a ’Receive Command Complete’ interrupt vector
after this command is programmed.
Note: The setting of the internal channel database is not copied into the channel
specification registers and therefore the values read can not be used to program
another channel. After system software has used the ’Receive Debug’ command
it must reprogram the channel specification registers to setup a new channel.
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Reset and Initialization procedure
7
Reset and Initialization procedure
Since the term “initialization” can have different meanings, the following definition
applies:
Chip Initialization
Generating defined values in all on-chip registers, RAMs (if required), flip-flops etc.
Mode Initialization
Software procedure, that prepares the device to its required operation, i.e. mainly writing
on-chip registers to prepare the device for operation in the respective system
environment.
Operational programming
Software procedures that setup, maintain and shut down operational modes, i.e. initialize
logical channel or maintain framing operations on selected ports.
7.1
Chip Initialization
Hardware reset
The hardware reset RST has to be applied to the device. Chip input TRST must be
activated prior to or while asserting RST and should be held asserted as long as the
boundary scan operation is not required. System clock must start running during reset.
During reset:
• All I/Os and all outputs are tri-state.
• All registers, state machines, flip-flops etc. are set asynchronously to their reset
values and all internal modules are set to their initial state.
• All interrupts are masked.
• The register bit CONF1.STOP is set to ‘1’.
After hardware reset (RST deasserted) system clock CLK is assumed to be running.
Serial clocks must be low/high or running. The PCI and the local bus interface pins go
into their idle state. All serial line outputs are tri-state.
The PCI interface becomes active and depending on input pin SPLOAD starts to read
subsystem ID/subsystem vendor ID and Memory commands out of external EEPROM
via the SPI interface. The serial clock is derived from the PCI clock. As long as this
procedure is active, the PCI interface answers all accesses with retry. After the PCI
interface has finished its self initialization it can be configured with PCI configuration
cycles.
In parallel to PCI self initialization the internal modules start their RAM initialization. As
long as the RAM initialization is running the internal modules indicate this condition with
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Reset and Initialization procedure
their initialization in progress signal. The register bit CONF1.IIP is the result of all signals.
As soon as all internal modules have finished their RAM initialization the register bit
CONF1.IIP is deasserted. Software must poll the register bit CONF1.IIP until this bit has
been deasserted. Read access to registers other than CONF1 is prohibited and may
result in unexpected behavior of the design. Write accesses are not allowed.
Chip initialization is finished when CONF1.IIP is ‘0’.
Software Reset
Alternately the MUNICH256FM provides the capability to issue a software reset via
register bit CONF1.SRST. During software reset all interfaces except PCI interface are
forced into their idle state. After software reset is set the MUNICH256FM starts its self
initialization and IIP will be asserted. Chip initialization is finished when CONF1.IIP is
deasserted. Afterwards the software reset bit must be set to ‘0’ to allow further operation.
7.2
Mode Initialization
After chip initialization is finished the system software has to setup the device for the
required function.
The system software has to poll bit CONF1.IIP (FCONF.IIP). As soon as CONF1.IIP is
deasserted, the system software has to clear bit CONF1.STOP and has to set the
general operating modes in register CONF1.
The M13 multiplexer, DS3/DS2 framer mode, T1/E1 framer mode and the DS1/E1 and
DS3 port interface has to be programmed. It is assumed, that the DS3 port clock and
CTCLK are active. The T1/E1 ports shall be disabled, thus no incoming data is forwarded
to the time slot assigner and to the T1/E1 framer.
Transmit direction
The T1/E1s have to be enabled via register XPI.TEN. After the tributaries are enabled,
the F-Bit (T1 mode) respectively time slot zero (E1 mode) are generated by the on-chip
T1/E1 framer and the signalling controller. To synchronize the first bit of a frame to an
external reference the common transmit frame synchronization pulse CTFS can be used
(in external timing mode only). After a tributary has been enabled, payload data is
provided from the time slot assigner. Since the time slot assignment is in reset state, that
is all time slots are set to inhibit, data bits are sent as ‘1’.
Receive direction
The tributaries have to be enabled via register XPI.REN. After they are enabled, the on-
chip T1/E1 framer tries to achieve frame alignment. As soon as frame alignment has
been achieved, incoming payload data is passed to the time slot assigner. Since time
slot assignment is in reset state, that is all time slots are set to inhibit, data bits are
discarded.
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Register Description
8
Register Description
The register description of the MUNICH256FM is divided into two parts, an overview of
all internal registers and in the second part a detailed description of all internal registers.
8.1
Register Overview
The first part of the register overview describes the PCI configuration space registers.
The second part describes the register set which can be accessed from PCI side only.
These registers are used to setup the main operation modes and to run the channel
engines of the device. The last part describes the register set of the framing engines, the
signalling controller, the mailbox and the local interrupt FIFO. These registers may be
accessed through the local microprocessor interface or via PCI.
Note: Register locations not contained in the following register tables are “reserved”. In
general all write accesses to reserved registers are discarded and read access to
reserved registers result in 00000000H. Nevertheless, to allow future extensions,
system software shall access documented registers only, since writes to reserved
registers may result in unexpected behavior. The read value of reserved registers
shall be handled as don’t care.
Unused and reserved bits are marked with a gray box. The same rules as given
for register accesses apply to reserved bits, except that system software shall
write the documented default value in reserved bit locations.
8.1.1
PCI Configuration Register Set (Direct Access)
Table 8-1
Register
PCI Configuration Register Set
Reset
Access Address
Comment
Page
value
Standard configuration space register
DID/VID
STA/CMD
CC/RID
R
R/W
R
00H
04H
08H
2108110AH Device ID/Vendor ID
02A00000H Status/Command
02800001H Class Code/Revision ID
Built-in Self Test/
182
183
185
BIST/
HEAD/
LATIM/
CLSIZ
Header Type/
Latency Timer/
Cache Line Size
00000000H Base Address 1
00000000H Base Address 2
R/W
0CH
00000000H
186
BAR1
BAR2
BARX
R/W
R/W
R
10H
14H
187
188
14H-24H 00000000H Base Address Not Used
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Register Description
Reset
value
Register
Access Address
Comment
Page
CISP
R
R
28H
00000000H Cardbus CIS Pointer
SSID/
SSVID
Subsystem ID/
00000000H
2CH
189
190
Subsystem Vendor ID
ERBAD
R
R
R
30H
34H
38H
00000000H Expansion ROM Base Adr.
00000000H Reserved
Reserved
Reserved
00000000H Reserved
MAXLAT/
MINGNT/
INTPIN/
INTLIN
Maximum Latency/
Minimum Grant/
Interrupt Pin/
R/W
3CH
06020100H
Interrupt Line
User defined configuration space register
SPI
R/W
R/W
R/W
R
40H
44H
48H
4CH
0000001FH SPI Access Register
00000000H REQ/GNT Config Register
000007E6H PCI Memory Command
00000000H PCI Debug Support
191
193
194
196
REQ
MEM
DEBUG
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Register Description
8.1.2
PCI Slave Register Set (Direct Access)
This section shows all registers which are located on the first configuration bus. These
registers are used to setup the basic operating modes of the device and to setup the port,
time slots and channels. System software has access to these registers via the PCI bus.
Table 8-2
Register
PCI Slave Register Set
Access Address
Reset
value
Comment
Page
General Control
CONF1
R/W
R/W
R/W
040H
044H
048H
Configuration Register 1
214
217
219
CONF2
00000000H Configuration Register 2
00090000H Configuration Register 3
CONF3
Receive Buffer Access Failed
00000000H
RBAFT
SFDT
W
W
04CH
050H
220
221
Interrupt Threshold
Small Frame Dropped
00000000H
Interrupt Threshold Register
Interrupt control PCI bus side
IQIA
R/W
R/W
R/W
R/W
0E0H
0E4H
0E8H
0ECH
00000000H Interrupt Queue Initialization
00000000H Interrupt Queue Base Addr.
00000000H Interrupt Queue Length
00000000H Interrupt Queue Mask
238
240
241
242
IQBA
IQBL
IQMASK
Global Interrupt Status/
00000000H Global Interrupt
Acknowledge
GISTA/GIACK
R/W
R/W
0F0H
243
245
GMASK
0F4H FFFFFFFFH Interrupt Mask
Channel specification registers (* = CSPEC)
*_CMD
W
000H
004H
008H
014H
018H
020H
00000000H Command
197
199
202
203
206
207
*_MODE_REC
*_REC_ACCM
R/W
R/W
00000000H Mode Receive
00000000H Receiver ACCM Map
00000000H Mode Transmit
00000000H Transmit ACCM Map
00200000H Buffer Configuration
*_MODE_XMIT R/W
*_XMIT_ACCM R/W
*_BUFFER
R/W
First Receive Descriptor
*_FRDA
R/W
024H
00000000H
Addr.
210
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Register Description
Reset
value
Register
Access Address
Comment
Page
First Transmit Descriptor
Address
*_FTDA
R/W
R/W
028H
02CH
00000000H
211
212
*_IMASK
00000000H Interrupt Vector Mask
Port and time slot control registers
PMIAR
PMR
REN
R/W
R/W
R/W
R/W
060H
064H
068H
06CH
00000000H Port Mode Indirect Access
0104C000H Port Mode
222
223
225
226
00000000H Receive Enable
00000000H Transmit Enable
TEN
Time slot Assignment
00000000H
TSAIA
R/W
070H
227
229
Indirect Access
TSAD
R/W
074H
02000000H Time slot Assignment Data
PPP character map/ demap registers
Receive Extended ACCM
Map
REC_ACCMX
XMIT_ACCMX
R/W
R/W
080H
090H
00000000H
00000000
231
235
Transmit Extended ACCM
Map
Receive buffer control
RBMON
R
0B0H 02000BFFH Receive Buffer Monitor
Receive Buffer Threshold
236
237
RBTH
R/W
0B4H
02000001H
Report
Maintenance
RBAFC
Receive Buffer Access Failed
Counter
R
R/W
R
084H
088H
08CH
00000000H
00000000H
00000000H
232
233
234
Small Frame Dropped
Indirect Access
SFDIA
SFDC
Small Frame Dropped
Counter
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Register Description
8.1.3
PCI and Local Bus Register Set (Direct Access)
This section describes the registers which are located on the configuration bus II (see
also "MUNICH256FM Block Diagram" on page 42). These registers can be accessed
either from PCI bus via the internal bus bridge or from the local bus side.
Note: Since the local bus is 16-bit wide and the PCI bus is 32-bit wide, the upper 16 bit
of data coming from/to PCI are discarded.
Note: Please note that read accesses to local bus registers via PCI bus and therefore
the internal bus bridge may result in latencies which exceed the 16 clock rule of
PCI specification. Exceeding the 16 clock rule results in target initiated retry on
PCI bus. In this case the read cycle needs to be repeated.
Table 8-3
Register
PCI and Local Bus Slave Register Set
Address
Address
(PCI)
Reset
value
Access
(Local
Bus)
Comment
Page
FCONF
R/W
R/W
100H
100H
00H
8080H Configuration Register 246
Master Local Bus
MTIMER
00H
0001H
248
Timer
Interrupt control for local bus side
INTCTRL
INTFIFO
R/W
R
108H
10CH
04H
06H
0001H Interrupt Control
FFFFH Interrupt FIFO
249
250
DS3 Clock Configuration and Status Register
DS3 Clock Confi-
guration and Status
D3CLKCS
TUCLKC
R/W
R/W
180H
184H
40H
42H
0000H
0000H
262
264
Test Unit Clock
Configuration
DS3 Transmit Control Registers
D3TCFG
D3TCOM
R/W
R/W
188H
18CH
44H
46H
0000H TransmitConfiguration 265
0070H Transmit Command
267
Remote DS2
0000H
D3TLPB
R/W
190H
48H
269
Loopback
Transmit Loopback
0000H
D3TLPC
D3TAIS
D3TFINS
R/W
R/W
R/W
194H
198H
19CH
4AH
4CH
4EH
270
Code Insertion
0000H Transmit AIS Insertion 271
Transmit Fault
0000H
272
Insertion Control
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Register Description
Address
(Local
Bus)
Address
(PCI)
Reset
value
Register
Access
Comment
Page
Transmit Test Unit
Control
D3TTUC
D3TSDL
R/W
R/W
1A0H
1A4H
50H
52H
0000H
01FFH
273
274
Transmit Spare Data
Link
DS3 Receive Control/Status Registers
D3RCFG
D3RCOM
R/W
R/W
1C0H
1C4H
60H
62H
0000H Receive Configuration 275
0000H Receive Command
278
Receive Interrupt
D3RIMSK
D3RESIM
R/W
R/W
1C8H
1CCH
64H
66H
1FFFH
Mask
280
Receive Error
0000H
281
Simulation
Receive Test Unit
Control
D3RTUC
D3RSTAT
D3RLPCS
R/W
R
1D0H
1D4H
1D8H
68H
6AH
6CH
0000H
282
283
286
0841H Receive Status
Receive Loopback
0000H
R
Code Status
Receive Spare Data
D3RSDL
D3RCVE
D3RFEC
D3RPEC
D3RCPEC
D3RFEBEC
D3REXZ
D3RAP
R
1DCH
1E0H
1E4H
1E8H
1ECH
1F0H
1F4H
1F8H
6EH
70H
72H
74H
76H
78H
7AH
7CH
01FFH
Link
287
288
288
289
289
290
290
291
Receive B3ZS Code
0000H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Violation Error Counter
Receive Framing Bit
0000H
Error Counter
Receive Parity Bit
0000H
Error Counter
Receive CP-Bit Error
Counter
0000H
Receive FEBE Error
Counter
0000H
Receive Exzessive
0000H
Zero Counter
Alarm Timer
0000H
Parameter
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Register Description
Address
(Local
Bus)
Address
(PCI)
Reset
value
Register
Access
Comment
Page
DS2 Transmit Control Registers
DS2 Transmit Group
Select
D2TSEL
R/W
200H
80H
0000H
292
D2TCFG
D2TCOM
R/W
R/W
204H
208H
82H
84H
0000H Transmit Configuration 293
0000H Transmit Command
294
Transmit Loopback
0000H
D2TLPC
R/W
20CH
86H
295
Code Insertion
DS2 Receive Control Registers
DS2 Receive Group
D2RSEL
R/W
220H
90H
0000H
Select
296
D2RCFG
D2RCOM
R/W
R/W
224H
228H
92H
94H
0000H Receive Configuration 297
0000H Receive Command
298
300
301
303
Receive Interrupt
D2RIMSK
D2RSTAT
D2RLPCS
R/W
R
22CH
230H
234H
96H
98H
9AH
003FH
Mask
0001H Receive Status
Receive Loopback
0000H
RD
Code Status
Receive Framing Bit
0000H
D2RFEC
D2RPEC
D2RAP
R/W
R/W
R/W
238H
23CH
240H
9CH
9EH
A0H
304
304
305
Error Counter
Receive Parity Bit
0000H
Error Counter
Alarm Timer
0000H
Parameter
Test Unit Transmit Registers
TUTCFG
TUTCOM
R/W
W
280H
284H
C0H
C2H
0000H Transmit Configuration 307
0000H Transmit Command
308
Transmit Error
0000H
TUTEIR
R/W
288H
C4H
310
Insertion Rate
TUTFP0
TUTFP1
R/W
R/W
28CH
290H
C6H
C8H
0000H
Transmit Fixed Pattern 311
0000H
Test Unit Receive Registers
TURCFG R/W 2A0H
D0H
176
0000H Receive Configuration 312
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Preliminary Data Sheet
PEB 20256M E
PEF 20256M E
Register Description
Address
(Local
Bus)
Address
(PCI)
Reset
value
Register
Access
Comment
Page
TURCOM
TURERMI
W
2A4H
2A8H
D2H
0000H Receive Command
314
316
Receive Error Rate
0000H
R/W
D4H
Measurement Interval
Receive Interrupt
TURIMSK
R/W
2ACH
D6H
001FH
Mask
317
318
TURSTAT
TURBC0
TURBC1
TUREC0
TUREC1
TURFP0
TURFP1
R
R
R
R
R
R
R
2B0H
2B4H
2B8H
2BCH
2C0H
2C4H
2C8H
D8H
DAH
DCH
DEH
E0H
E2H
E4H
0021H Receive Status
0000H
Receive Bit Counter
0000H
320
0000H
Receive Error Counter 322
Receive Fixed Pattern 324
0000H
0000H
0000H
T1/E1 Framer transmit registers
Transmit T1/E1
TREGSEL
R/W
110H
08H
0AH
0000H Framer Port &
Register Select
251
252
Transmit T1/E1
0000H
TDATA
R/W
114H
Framer Data
T1/E1 Framer receive registers
Receive T1/E1 Framer
Port & Register Select
RREGSEL
RDATA
R/W
R/W
118H
11CH
0CH
0EH
0000H
0000H
253
254
Receive T1/E1
Framer Data
Facility data link registers
Facility Data Link Port
& Register Select
FREGSEL
R/W
120H
124H
10H
12H
0000H
255
FDATA
R/W
0000H Facility Data Link Data 257
Mailbox registers
Mailbox Local Bus to
PCI Command
MBE2P0
R/W
140H
20H
0000H
258
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Register Description
Address
(Local
Bus)
Address
(PCI)
Reset
value
Register
Access
Comment
Page
MBE2P1
MBE2P2
MBE2P3
MBE2P4
MBE2P5
MBE2P6
MBE2P7
144H
148H
14CH
150H
154H
158H
15CH
22H
24H
26H
28H
2AH
2CH
2EH
Mailbox Local Bus to
0000H PCI Data Registers 1
through 7
R/W
R/W
R/W
259
260
261
Mailbox PCI to Local
0000H
MBP2E0
160H
30H
Bus Command
MBP2E1
MBP2E2
MBP2E3
MBP2E4
MBP2E5
MBP2E6
MBP2E7
164H
168H
16CH
170H
174H
178H
17CH
32H
34H
36H
38H
3AH
3CH
3EH
Mailbox PCI to Local
0000H Bus Data Registers 1
through 7
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Register Description
8.1.4
Transmit T1/E1 Framer Registers (Indirect Access)
Note: The transmit framer registers will be accessed via registers TREGSEL and
TDATA as part of the Local Bus direct access register set. Please refer to page
251 for description of TREGSEL and to page 252 for description of TDATA.
Table 8-4
Register
Transmit T1/E1 Framer Registers
Access Address Reset Comment
value
Page
Control registers
TCMDR
TFMR
R/W
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0000H Command
325
327
329
330
331
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0000H Mode
TLCR0
TLCR1
TPRBSC
TFPR0
TFPR1
TPTSL0
TPTSL1
XSP
0000H Loop Code Register 0
0000H Loop Code Register 0
001FH PRBS Control
0000H
Fixed Pattern Register
0000H
332
FFFFH
PRBS Time slot Register
FFFFH
333
334
0000H Spare bit Register
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Register Description
8.1.5
Receive T1/E1 Framer Registers (Indirect Access)
Note: The receive framer registers will be accessed via the registers RREGSEL and
RDATA. Please refer to page 253 for description of RREGSEL and to page 254
for description of RDATA.
Table 8-5
Register
Receive T1/E1 Framer Registers
Access Address Reset Comment
value
Page
Control Registers
RCMDR
RFMR
RLCR0
RLCR1
RPRBSC
PFPR0
RFPR1
RPTSL0
RPTSL1
IMR
R/W
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0000H Command
335
338
343
344
345
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0000H Mode Register
0000H Loop Code Register 0
0000H Loop Code Register 1
001FH PRBS Control
0000H
Fixed Pattern Register
0000H
346
347
FFFFH
PRBS Time slot Register
FFFFH
0000H Interrupt Mask
348
349
350
351
RFMR1
PCD
0000H Mode Register 1
0015H Pulse Count Detection
0015H Pulse Count Recovery
PCR
Status registers
FRS
R
R
R
R
R
40H
41H
42H
43H
44H
0000H Status
352
355
356
357
358
FEC
0000H Framing Error Counter
0000H CRC Error Counter
0000H Errored Block Counter
0000H Bit Error Counter
CEC
EBC
BEC
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PEF 20256M E
Register Description
8.1.6
Facility Data Link Registers (Indirect Access)
Note: The FDL registers will be accessed via registers FREGSEL and FDATA.
Table 8-6
Register
Facility Data Link Registers
Access Address Reset Comment
value
Page
RCR1
RCR2
RFF
R/W
R/W
R
00H
01H
02H
0000H Receive Configuration Register 1 359
0000H Receive Configuration Register 2 362
0000H Receive FIFO
364
Transmit Configuration
Register 1
XCR1
XCR2
R/W
R/W
03H
04H
0000H
0000H
365
Transmit Configuration
Register 2
367
XFF
W
R
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
0000H Transmit FIFO
368
369
371
374
375
376
377
378
379
380
381
382
383
384
385
386
387
PSR
0000H Port Status
HND
W
0000H Handshake
MSK
R/W
R/W
R/W
R
0000H Interrupt Mask
RAL
0000H Receive Address Low
0000H Receive Address High
0000H Receive Sa Word 1
0000H Receive Sa Word 2
0000H Receive Sa Word 3
0000H Receive Sa Word 4
0000H CRC Status Counter 1
0000H CRC Status Counter 2
0000H Transmit Sa Word 1
0000H Transmit Sa Word 2
0000H Transmit Sa Word 3
0000H Valid SSM Pattern
0000H Valid CRC Count Pattern
RAH
RSAW1
RSAW2
RSAW3
RSAW4
CRCS1
CRCS2
XSAW1
XSAW2
XSAW3
VSSM
VCRC
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
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PEF 20256M E
Register Description
8.2
Detailed Register Description
PCI Configuration Register
8.2.1
DID/VID
Device ID/Vendor ID
Access
: read
Address
: 00H
Reset Value
: 2108110AH
31
15
16
DID(15:0)
VID(15:0)
0
DID
VID
Device ID
The device ID identifies the particular device. It is hardwired to value
2108H.
Vendor ID
The vendor ID identifies the manufacturer of the device. It is hardwired
to value 110AH.
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PEF 20256M E
Register Description
STAT/CMD
Status/Command Register
Access
: read/write
: 04H
Address
Reset Value
: 02A00000H
31
30
29
28
27
0
26
25
24
23
1
22
0
21
1
16
DPE SSE RMA RTA
01B
DPED
0
0
0
0
0
0
0
15
8
6
2
1
0
0
0
0
0
0
0
0
0
SE
0
PER
0
BM
MS
DPE
Detected Parity Error
This bit will be asserted whenever the MUNICH256FM detects a parity
error.
0
1
No parity error detected.
Parity error detected. This bit will be cleared by writing a ‘1’ to this
bit position.
SSE
Signaled System Error
This bit will be asserted whenever the MUNICH256FM asserted SERR.
For system error conditions see bit SE.
0
1
No system error signaled.
System error has been signaled. This bit will be cleared by writing
a ‘1’ to this bit position.
RMA
Received Master Abort
This bit will set whenever a transaction in which the MUNICH256FM
acted as bus master was terminated with master abort.
0
1
No master abort detected.
Transaction terminated with master abort. This bit will be cleared
by writing a ‘1’ to this bit.
Preliminary Data Sheet
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PEF 20256M E
Register Description
RTA
Received Target Abort
This bit will be set whenever a transaction in which the MUNICH256FM
acted as bus master was terminated with target abort.
0
1
No target abort detected.
Transaction terminated with target abort. This bit will be cleared
by writing a ‘1’ to this bit.
DPED
Data Parity Error Detected
0
1
No data parity error detected.
The following three conditions are met:
•The bus agent asserted PERR itself or observed PERR
asserted.
•The bus agent acted as bus master for the operation in which the
error occurred.
•The Parity Error Response Bit is set
SE
SERR Enable
This bit enables assertion of SERR in case of severe system errors.
0
1
Assertion of SERR disabled.
Enables report of
•Address parity errors
•Master abort
•Target abort
PER
Parity Error Response
This bit enables reporting of parity errors via pin PERR.
0
1
Assertion of PERR disabled.
Enables the assertion of PERR. See also Data Parity Error
Detected.
BM
MS
Bus Master
This bit controls a device ability to act as a master on PCI bus.
0
1
Disables the device from generating PCI accesses.
Allows the device to act as bus master.
Memory Space
This bit controls the device response to memory space accesses.
0
1
Response to memory space accesses disabled.
Allows a device to respond to memory space accesses.
Preliminary Data Sheet
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PEF 20256M E
Register Description
CC/RID
Class Code/Revision ID
Access
: read
Address
: 08H
Reset Value
: 02800001H
31
15
24
23
16
BCL(7:0)
ICL(7:0)
SCL(7:0)
8
7
0
RID(7:0)
The class code, consisting of base class, subsystem class and interface class, is used
to identify the generic function of the device and, in some cases, a specific register-level
programming interface.
BCL
Base Class
The base class is hardwired to 02H, which identifies this device as a
network controller.
SCL
Sub Class
The sub class is hardwired to 80H, which together with the base class
identifies this device as ’Other network controller’.
ICL
Interface Class
The interface class is hardwired to 00H.
Revision ID
RID
The revision ID identifies the current version of the device. It is hardwired
to 01H.
Preliminary Data Sheet
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PEF 20256M E
Register Description
BIST/Header Type/Latency Timer/Cache Line Size
Access
: read/write
: 0CH
Address
Reset Value
: 00000000H
31
15
24
23
16
00H
00H
11
10
8
7
0
LT(7:3)
000B
00H
LT
Latency Timer
The value of this register times eight specifies, in units of PCI clocks, the
value of the latency timer for this PCI bus master.
Preliminary Data Sheet
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PEF 20256M E
Register Description
BAR1
Base Address 1
Access
: read/write
Address
: 10H
Reset Value
: 00000000H
31
15
16
BAR(31:12)
12
2
1
0
0
BAR(31:12)
0
0
0
0
0
0
0
0
0
00B
The first base address of the MUNICH256FM is marked as non-prefetchable and can be
relocated anywhere in 32 bit address space of PCI memory. The MUNICH256FM
supports memory accesses only.
BAR
Base Address
The base address will be used for determining the address space of the
MUNICH256FM and to do the mapping of the address space. Since the
device allocates a total of 4 kByte address space BAR(31:12) are
implemented as read/writable.
Preliminary Data Sheet
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PEF 20256M E
Register Description
BAR2
Base Address 2
Access
: read/write
Address
: 14H
Reset Value
: 00000000H
31
16
BAR(31:15)
15
3
0
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
00B
The second base address of the MUNICH256FM is marked as non-prefetchable and can
be relocated anywhere in 32 bit address space of PCI memory. The MUNICH256FM
supports memory accesses only. All accesses to memory regions defined by BAR2 will
be mapped to the local bus.
BAR
Base Address
The base address will be used for determining the address space of the
memory regions located on the local bus of the MUNICH256FM and to
set the mapping of the address space. The MUNICH256FM can access
a total of 24 kByte address space on the local bus as a bus master.
In those applications where the master functionality of MUNICH256FM
is not needed the second base address register BAR2 may be disabled
using bit MEM.BAR2 in the PCI user configuration space.
Preliminary Data Sheet
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PEF 20256M E
Register Description
SID/SVID
Subsystem ID/Subsystem vendor ID
Access
: read
Address
: 2CH
Reset Value
: 00000000H
31
15
16
SID(15:0)
0
SVID(15:0)
SID
Subsystem ID
The subsystem ID uniquely identifies the add-in board or subsystem
where the system resides. The value of SID may be reconfigured after
the reset phase of the system via the SPI interface.
SVID
Subsystem Vendor ID
The subsystem vendor ID identifies the vendor of an add-in board or
subsystem. The value may be reconfigured after the reset phase of the
system via the SPI interface.
Preliminary Data Sheet
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PEF 20256M E
Register Description
ML/MG/IP/IL
Maximum Latency/Minimum Grant/Interrupt Pin/Interrupt Line
Access
: read/write
: 3CH
Address
Reset Value
: 06020100H
31
15
24
23
16
ML(7:0)
MG(7:0)
IL(7:0)
8
7
0
IP(7:0)
ML
Maximum Latency
This value specifies how often the device needs to access the PCI bus
in multiples of 1/4 us. The value is hardwired to 06H.
MG
Minimum Grant
This value specifies how long of a burst period the device needs,
assuming a clock rate of 33 MHz in multiples of 1/4 us. The value is
hardwired to 02H.
IP
IL
Interrupt Pin
The interrupt pin register tells which interrupt pin the device uses. Refer
to section 6.2.4 and to section 2.2.6 of the PCI specification Rev. 2.1.
The value is hardwired to 01H.
Interrupt Line
The interrupt line register is used to communicate interrupt line routing
information.
Preliminary Data Sheet
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PEF 20256M E
Register Description
SPI
SPI Access Register
Access
: read/write
Address
: 40H
Reset Value
: 0000001FH
31
24
23
16
0
0
0
0
0
0
0
SPIS
SCMD(7:0)
15
8
7
0
SBA(7:0)
SWD(7:0)
SPIS
SPI Start
To start the EEPROM transaction, which is defined in the SPI command,
the byte address, and the data field, this bit must be set to ‘1’ by a write
transaction through the PCI interface. After the transaction is finished,
the start bit is deasserted by the SPI interface controller. This signal must
be polled by system software.
SCMD
SPI Command
In this register, the SPI command for the next EEPROM transfer must be
written before the transaction is started. The following SPI commands
are supported:
01H
02H
03H
04H
05H
06H
WRSR
WRITE
READ
WRDI
Write Status Register
Write Data to Memory Array
Read Data from Memory Array
Reset Write Enable Latch
Read Status Register
RDSR
WREN
Set Write Enable Latch
SBA
SPI Byte Address
For read and write transaction to the connected EEPROM, the byte
address must be written in this register before the transaction is started.
Preliminary Data Sheet
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PEF 20256M E
Register Description
SD
SPI Data
For the write status register transactions and the write data to memory
array transactions, the data, that has to be written to the EEPROM, must
be written to this register before the transaction is started. After a read
status register transaction or read data from memory array transaction
has finished (start bit is deasserted), the byte received from the
EEPROM is available in this register.
Preliminary Data Sheet
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PEF 20256M E
Register Description
LR
Long Request Register
Access
: read/write
: 44H
Address
Reset Value
: 00000000H
31
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
0
0
LR
LR
Long Request
0
The PCI interface deasserts the REQ signal in parallel with the
assertion of the FRAME signal.
1
The REQ signal will be deasserted in parallel with the deassertion
of FRAME.
Preliminary Data Sheet
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PEF 20256M E
Register Description
MEM
PCI Memory Command Register
Access
: read/write
: 48H
Address
Reset Value
: 000007E6H
31
0
30
0
17
16
0
0
0
0
0
0
0
0
0
8
0
7
0
0
0
4
0
3
0
BAR2
15
0
11
0
0
MW(3:0)
MRL(3:0)
MR(3:0)
BAR2
Enable Base Address Register 2
Setting this bit enables Base Address Register 2. Per default base
address register two is disabled. If an EEPROM is connected to the SPI
interface the value of this bit can be loaded via the EEPROM.
Additionally this bit can set using standard PCI configuration write
commands.
0
1
Base Address Register 2 is disabled.
Base Address Register 2 is enabled.
MW
Memory Write Command
The value of this register contains the write command to be used during
initiator transfers and is set to memory write after reset. The value of this
register is configurable during setup of the bridge either by loading the
value from EEPROM or by writing from PCI side.
MRL
Memory Read Command (Long transfers)
The value of this register defines command to be used for read transfers
which are equal or more than two DWORDs and is set to memory read
line after reset. The value of this register is configurable during run time
of the bridge either by loading the value from EEPROM or by writing from
PCI side.
MR
Memory Read Command
The value of this register defines command to be used for read transfers
of single DWORDs.The value of this register is configurable during run
Preliminary Data Sheet
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PEF 20256M E
Register Description
time of the bridge either by loading the value from EEPROM or by
reading or writing from PCI side.
Preliminary Data Sheet
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PEF 20256M E
Register Description
DEBUG
PCI Debug Support Register
Access
: read
Address
: 4CH
Reset Value
: 00000000H
31
15
16
DSR(31:0)
DSR(31:0)
0
DSR
Debug Support register
The value of this register contains the address of the next initiator
transfer during normal operation. In case of disconnect, retry, master
abort and target abort the register contains the address of the failed
transaction.
Preliminary Data Sheet
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PEF 20256M E
Register Description
8.2.2
PCI Slave Register
CSPEC_CMD
Channel Specification Command Register
Access
: read/write
: 000H
Address
Reset Value
: 00000000H
31
15
24
23
16
CMDX(7:0)
CMDR(7:0)
7
0
0
0
0
0
0
0
0
0
CHAN(7:0)
The channel specification registers are the access registers to the chip internal channel
database. In order to program or reprogram a channel the channel information must be
setup in the channel specification data registers before a channel command can be
given. As soon as the channel command is issued the channel information is copied to
the chip internal channel database and the device is reconfigured for the intended
operation. Since reconfiguration time is dependent on the given command, certain
commands generate acknowledge/fail command interrupt vectors to report status of
configuration.During this time (command has been given and command interrupt) no
further commands are allowed for the same channel. Please note that any command for
one channel does not affect operation of any other channel.
For configuration of multiple channels the system software needs to program the
channel data registers only once and then can issue channel commands for multiple
channels without reprogramming the channel data registers.
Note: Debugging of channel information using the commands ’Receive Debug’ or
’Transmit Debug’ requires new programming of channel data registers for further
operation.
For detailed description of register concept and command concept refer to chapter
"Channel Programming / Reprogramming Concept" on page 162.
Preliminary Data Sheet
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PEF 20256M E
Register Description
CMDX
Command Transmit
For detailed description of transmit commands and programming
sequences refer to Chapter 6.2.
01H
02H
04H
08H
10H
20H
40H
Transmit Init
Transmit Off
Transmit Abort/Branch
Transmit Hold Reset
Transmit Debug
Transmit Idle
Transmit Update
CMDR
Command Receive
For detailed description of receive commands and programming
sequences refer to Chapter 6.3.
01H
02H
04H
08H
10H
Receive Init
Receive Off
Receive Abort/Branch
Receive Hold Reset
Receive Debug
CHAN
Channel select
0..255 Selects the channel to be programmed or debugged.
Note: Transmit init for a channel must be programmed only after reset or after a transmit
off command, i.e. two transmit init commands for the same channel are not
allowed.
Preliminary Data Sheet
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PEF 20256M E
Register Description
CSPEC_MODE_REC
Channel Specification Mode Receive Register
Access
: read/write
: 004H
Address
Reset Value
: 00000000H
31
28
27
24
23
16
0
0
0
DEL
ACCMX(3:0)
RFLAG(7:0)
15
0
14
13
12
11
10
9
8
1
0
SFDE TFF INV TMP CRCX CRC CRC
0
0
0
0
0
0
PMD(1:0)
32
DIS
DEL
DEL (Delete) Demap
This bit enables demapping of the control character DEL. This bit is valid
in PPP modes only.
0
1
Disable demapping of control character DEL.
Enable demapping of control character DEL.
ACCMX
Extended ACCM
In addition to the Channel Specification Receive ACCM Map the user
can select four global user definable characters for character demapping
in PPP modes. Setting one or more of the bits ACCM(3) through
ACCM(0) enables the corresponding character which can be found in
register REC_ACCMX.
0
Disable the selected character in REC_ACCMX for character
demapping.
1
Enable the corresponding character in register REC_ACCMX for
character demapping.
RFLAG
Receive Flag
Used in transparent mode only. The RFLAG constitutes the flag that is
filtered from the received bit stream if enabled via bit TFF.
Preliminary Data Sheet
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PEF 20256M E
Register Description
SFDE
Short/Small Frame Drop Enable
This bit enables either the drop of short frames or the drop of small
frames. This bit is valid in HLDC and PPP modes only.
0
Short Frame Drop. Frames smaller than four bytes payload data
(CRC32) or smaller than two bytes payload data (CRC16) are
dropped. This function is not available if bit CRCX is enabled.
1
Small Frame Drop. Frames (Payload and CRC) which are
smaller or equal to CONF3.MINFL are dropped.
TFF
INV
TMA Flag
This bit enabled flag extraction in TMA mode and is available if non of
the bits belonging to this channel is masked.
0
1
No flag extraction
Enable flag extraction. The flag specified in RFLAG will be
extracted from the received data stream.
Bit Inversion
When bit inversion is enabled incoming channel data is inverted before
processed by the protocol machine. E.g. incoming octet 81H will be
recognized as idle flag in HDLC mode.
0
1
No Bit Inversion
Bit Inversion
TMP
Transparent Mode Packing
This bit enables the transparent mode packing and is valid in TMA mode
only. This feature is applicable if at least one bit in any time slot is
masked.
0
Incoming masked bits are substituted with ‘1’. The non-used
(masked) data bits are substituted by ‘1’s.
1
If subchanneling is used in transparent mode (i.e. less than 8 bits
of a time slot are used), the non-used (masked) data bits are
discarded.
CRCX
CRC Transfer
This bit enables the capability to store the CRC checksum of incoming
data packets in system memory together with the payload data.
0
The CRC checksum from the incoming data packet will be
removed from the packet and not transferred to the shared
memory.
1
The CRC checksum together with the payload data is transferred
to the shared memory.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
CRC32
CRC32 Select
This bit selects the generator polynomial in the receiver. The checksum
of incoming data packets will be compared against CRC16 or CRC32.
CRC Select is valid in HDLC and PPP modes only.
0
1
Select CRC16 checksum.
Select CRC32 checksum.
CRCDIS
PMD
CRC Check Disable
This bit disables CRC Check in HDLC and PPP protocol modes.
0
1
CRC check is enabled.
CRC check is disabled.
Protocol Machine Mode
These bit fields select the protocol machine mode in receive direction.
00B
01B
10B
11B
Select HDLC operation.
Select Bit synchronous PPP.
Select Byte synchronous PPP.
Select Transparent Mode.
Preliminary Data Sheet
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PEF 20256M E
Register Description
CSPEC_REC_ACCM
Channel Specification Receive ACCM Map Register
Access
: read/write
: 008H
Address
Reset Value
: 00000000H
31
16
1FH 1EH 1DH 1CH 1BH 1AH 19H 18H 17H 16H 15H 14H 13H 12H 11H 10H
15
0
0FH 0EH 0DH 0CH 0BH 0AH 09H 08H 07H 06H 05H 04H 03H 02H 01H 00H
Any of the given characters can be selected for character demapping. If a bit is set the
corresponding character is expected to be mapped by the control ESC character and is
removed if received. These bits are valid in octet synchronous PPP modes only.
Note: If this register needs to be reprogrammed, it must be done before accessing the
register CSPEC_MODE_REC.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
CSPEC_MODE_XMIT
Channel Specification Mode Transmit Register
Access
: read/write
: 014H
Address
Reset Value
: 00000000H
31
24
23
16
FNUM(7:0)
TFLAG(7:0)
15
13
12
11
9
8
7
4
3
1
0
IFTF
0
FA
INV TMP
0
CRC CRC
32 DIS
ACCMX(3:0)
DEL
0
PMD(1:0)
FNUM
Flag number
FNUM denotes the number of flags send between two frames. The flag
number can be updated during transmission with command ’Transmit
Update’.
0
One flag is sent between two frames (shared flag).
1..255 FNUM+1 flags are sent between two frames.
Transparent flag
TFLAG
IFTF
Only valid if transparent mode is selected and if FA is enabled. TFLAG
constitutes the flag that is inserted into the transmit bit stream.
Interframe Time Fill
This bit determines the interframe time fill in HDLC and PPP modes.
0
1
Interframe time fill is 7EH.
Interframe time fill is FFH.
FA
Flag Adjustment
Only valid if transparent mode is selected.
0
The value FFH is sent in sent in all TMA mode exception
conditions.
1
The value specified in TFLAG is sent in all TMA mode exception
conditions (e.g. idle). This bit can be set only when none of the
bits belonging to this channels is masked.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
INV
Bit Inversion
If bit inversion is enabled outgoing channel data is inverted after
processed by the protocol machine. E.g. a outgoing idle flag is
transmitted as octet 81H in HDLC mode.
0
1
Disable bit inversion.
Enable bit inversion.
TMP
Transparent Mode Pack
This bit enables the transparent mode packing and is valid in TMA mode
only. This feature is applicable if at least one bit in any time slot is
masked.
0
If subchanneling is used outgoing masked bits of data octet are
discarded and substituted with ‘1’.
1
If subchanneling is used outgoing masked bits are sent as ‘1’.
The remaining bits of data are sent in the next time slot.
CRC32
CRC 32 Select
This bit selects the generator polynomial in the transmitter. The
checksum of outgoing data packets will be generated according to
CRC16 or CRC32. CRC32 Select is valid in HDLC and PPP modes only.
0
1
Select CRC16 generation.
Select CRC32 generation.
CRCDIS
ACCMX
CRC Disable
This bit enables generation and transmission of a CRC checksum. CRC
disable is valid in HDLC and PPP modes only.
0
1
CRC generation and transmission is disabled.
CRC generation and transmission is enabled.
Enable extended ACCM character
The selected bits in bit field ACCMX denote the enabled characters in
XMIT_ACCMX.
In addition to the Channel Specification Transmit ACCM Map the user
can select four global user definable characters for character mapping in
PPP modes. Setting one or more of the bits ACCM(3) through ACCM(0)
enables the corresponding character which can be found in register
XMIT_ACCMX.
0
Disable the selected character in XMIT_ACCMX for character
mapping.
1
Enable the corresponding character in register XMIT_ACCMX for
character mapping.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
DEL
DEL (Delete) Map Flag
This bit enables mapping of the control character DEL. This bit is valid in
PPP modes only.
0
1
Disable mapping of DEL.
Enable mapping of DEL.
PMD
Protocol Machine Mode
This bit field selects the protocol machine mode in transmit direction.
00B
01B
10B
11B
Select HDLC operation.
Select Bit synchronous PPP.
Select Byte synchronous PPP.
Select Transparent Mode.
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PEF 20256M E
Register Description
CSPEC_XMIT_ACCM
Channel Specification Transmit ACCM Map Register
Access
: read/write
: 018H
Address
Reset Value
: 00000000H
31
16
1FH 1EH 1DH 1CH 1BH 1AH 19H 18H 17H 16H 15H 14H 13H 12H 11H 10H
15
0
0FH 0EH 0DH 0CH 0BH 0AH 09H 08H 07H 06H 05H 04H 03H 02H 01H 00H
Any of the given characters can be selected for character mapping. If a bit is set the
corresponding character will be mapped by the control ESC character. These bits are
valid in octet synchronous PPP modes only.
Preliminary Data Sheet
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PEF 20256M E
Register Description
CSPEC_BUFFER
Channel Specification Buffer Configuration Register
Access
: read/write
: 020H
Address
Reset Value
: 00200000H
31
29
28
16
TQUEUE(2:0)
ITBS(12:0)
6
15
12
11
8
4
3
0
TBRTC(3:0)
TBFTC(3:0)
0
RQUEUE(2:0)
RBTC(3:0)
TQUEUE
ITBS
Transmit Interrupt Vector Queue
This bit field determines the interrupt queue where channel interrupts
transmit will be stored.
Individual transmit buffer size
Note: Please note that the internal architecture is 32 bit wide. Therefore
each buffer location corresponds to four data octets.
The transmit buffer size configures the number of internal transmit buffer
locations for a particular channel. Buffer locations will be
allocated on command transmit init and released after command
transmit off.
Note: The sum of transmit forward threshold and transmit refill
threshold must be smaller than the internal buffer size.
TBRTC
Transmit Buffer Refill Threshold Code
Note: Please note that the internal architecture is 32 bit wide. Therefore
each buffer location corresponds to four data octets.
TBRTC is a coding for the transmit refill threshold. Please refer to Table
8-7 for correspondence between code and threshold.
The internal transmit buffer has a programmable number of buffer
locations per channel. When the number of free locations reach the
transmit buffer refill threshold the internal transmit buffer requests new
data from the data management unit.
Preliminary Data Sheet
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PEF 20256M E
Register Description
TBFTC
Transmit Buffer Forward Threshold Code
Note: Please note that the internal architecture is 32 bit wide. Therefore
each buffer location corresponds to four data octets.
TBFTC is a coding for the transmit buffer forward threshold. Please refer
to Table 8-7 for correspondence between code and threshold.
The transmit buffer forward threshold code determines the number of
buffer locations which must be filled until protocol machine starts
transmission. Nevertheless the transmit buffer forwards data packets to
protocol machine as soon as a whole packet or the end of a packet is
stored in the transmit buffer.
RQUEUE
RBTC
Receive Interrupt Queue.
This bit field determines the interrupt queue number where channel
interrupts receive will be stored.
Receive Buffer Threshold Code
Note: Please note that the internal architecture is 32 bit wide. Therefore
each buffer location corresponds to four data octets.
RBTC is a coding for the receive buffer threshold. Please refer to Table
8-7 for correspondence between code and threshold.
The receive buffer threshold determines the maximum packet size in
DWORDs which will be stored in the internal receive buffer for a specific
channel. When the packet size reaches the receive buffer threshold or a
packet has been completely received, the packet will be forwarded to
system memory.
Table 8-7
Coding
Threshold Codings
Threshold
RBTC
TBFTC
TBRTC
TPBL
in DWORDs
0000B
0001B
0010B
0011B
0100B
0101B
0110B
0111B
1000B
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
4
8
12
16
24
32
40
48
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PEF 20256M E
Register Description
Coding
Threshold
RBTC
TBFTC
TBRTC
TPBL
in DWORDs
1001B
1010B
1011B
1100B
1101B
1110B
1111B
64
x
x
x
x
x
x
x
x
x
x
96
128
192
256
384
512
Not Valid
Not
Valid
Preliminary Data Sheet
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PEF 20256M E
Register Description
CSPEC_FRDA
Channel Specification FRDA Register
Access
: read/write
: 024H
Address
Reset Value
: 00000000H
31
15
16
FRDA(31:2)
2
1
0
0
0
FRDA(31:2)
FRDA
First Receive Descriptor Address
This 30-bit pointer contains the start address of the first receive
descriptor. The receive descriptor is read entirely after the first request
of the receive buffer and stored in the on-chip channel database.
Therefore all information in the descriptor pointed to by FRDA must be
valid when the data management unit branches to this descriptor.
The user can specify a new First Receive Descriptor Address using
receive abort/branch command. In this case the First Receive Descriptor
Address (FRDA) is used as a pointer to a new linked list. See details on
commands in section "Channel Commands" on page 163.
Preliminary Data Sheet
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PEF 20256M E
Register Description
CSPEC_FTDA
Channel Specification FTDA Register
Access
: read/write
: 028H
Address
Reset Value
: 00000000H
31
15
16
FTDA(31:2)
0
FTDA(31:2)
0
0
FTDA
First Transmit Descriptor Address
This 30-bit pointer contains the start address of the first transmit
descriptor. The transmit descriptor is read entirely after the first request
of the transmit buffer and stored in the on-chip channel database.
Therefore all information in the descriptor pointed to by FTDA must be
valid when the data management unit branches to this descriptor.
The user can specify a new First Transmit Descriptor Address using the
’Transmit Abort/Branch’ command. In this case the first transmit
descriptor address (FTDA) is used as a pointer to a new linked list. See
details on commands in Chapter 6.2.
Preliminary Data Sheet
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PEF 20256M E
Register Description
CSPEC_IMASK
Channel Specification Interrupt Vector Mask Register
Access
: read/write
: 02CH
Address
Reset Value
: 00000000H
31
0
30
28
23
22
16
TAB
0
HTAB
0
0
0
9
0
8
UR TFE
0
5
0
0
0
3
0
2
0
0
TCC
15
0
14
13
12
11
10
7
6
0
RAB RFE HRAB MFL ROFD CRC ILEN RFOP SF IFTC
SFD SD
RCC
For each channel or command related interrupt vector an interrupt vector generation
mask is provided. Generation of an interrupt vector itself does not necessarily result in
assertion of the interrupt pin. For description of interrupt concept and interrupt vectors
see Chapter 4.13.1.
The following definition applies:
1
The device will not generate the corresponding interrupt vector, i.e. the
interrupt vector is masked.
0
An interrupt condition results in generation of the corresponding interrupt
vector.
Channel Interrupt Vector Transmit
TAB
HTAB
UR
Mask ’Transmit Abort’
Mask ’Hold Caused Transmit Abort’
Mask ’Transmit Underrun’
Mask ’Transmit Frame End’
TFE
Command Interrupt Vector Transmit
TTC
Mask ’Transmit Command Complete’
Preliminary Data Sheet
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PEF 20256M E
Register Description
Command Interrupt Vector Receive
RAB
RFE
HRAB
MFL
RFOD
CRC
ILEN
RFOP
SF
Mask ’Receive Abort’
Mask ’Receive Frame End’
Mask ’Hold Caused Receive Abort’
Mask ’Maximum Frame Length Exceeded’
Mask ’Receive Frame Overflow DMU’
Mask ’CRC Error’
Mask ’Invalid Length’
Mask ’Receive Frame Overflow’
Mask ’Short Frame Detected’
IFTC
SFD
SD
Mask ’Interframe Time-fill Flag’ and ’Interframe Time-fill Idle’
Mask ’Short Frame Dropped’
Mask ’Silent Discard’
RCC
Mask ’Receive Command Complete’
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
CONF1
Configuration Register 1
Access
: read/write
: 040H
Address
Reset Value
: 820000F0H
31
25
24
23
0
21
20
16
IIP
0
0
0
0
0
STOP SRST
0
6
MFLE
MFL(12:0)
15
8
7
5
4
3
2
1
0
0
MFL(12:0)
MBIM PBIM RBIM RFIM SFL RBM LBE
IIP
Initialization in Progress (Read Only)
After reset (hardware reset or software reset) the internal RAM’s are self
initialized by the MUNICH256FM. During this time (approx. 250 µs) no
other accesses to the device than reading register CONF1 or FCONF
are allowed. This bit must be polled until it has been deasserted by the
MUNICH256FM.
0
Self initialization has finished.
Self initialization in progress.
1
STOP
Stop
After reset the MUNICH256FM can be switched to ’Fast Initialization’
mode. During stop mode internal RAM’s will not be accesses by internal
state machines. This mode is for test purposes only and allows writing or
reading the internal RAM’s.
0
Device is in normal operation. This bit must be set to zero after
chip initialization. See also "Mode Initialization" on page 169.
1
Device is in ‘Fast Initialization Mode’. This function is used for test
purposes only.
SRST
Software Reset
This bit issues a software reset to the MUNICH256FM. During software
reset all interfaces except PCI interface are forced into their idle state.
After software reset is set the MUNICH256FM starts its self initialization
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PEF 20256M E
Register Description
and IIP will be asserted. When IIP is deasserted system software can
reset SRST to ’0’ to start normal operation again.
0
1
Normal operation
Start software reset.
MFLE
MFL
Maximum Frame Length Check Enable
0
1
Disable maximum frame length check.
Enable maximum frame length check.
Maximum Frame Length
MFL defines the maximum length of incoming data packets. Packets
exceeding the specified length are reported in the status field of the
receive descriptor and if selected in an additional channel interrupt.
MBIM
PBIM
RBIM
Mailbox Interrupt Vector Mask
This bit enables or disables mailbox system interrupt vectors generated
by the mailbox.
0
1
Enable interrupt vector.
Disable interrupt vector.
PCI Bridge Interrupt Vector Mask
This bit enables or disables the ’PCI Access Error’ interrupt vector
generated by the PCI bridge.
0
1
Enable interrupt vector.
Disable interrupt vector.
Receive Buffer Interrupt Vector Mask
This bit enables or disables system interrupt vectors ’Receive Buffer
Queue Early Warning’ and ’Receive Buffer Action Queue Early Warning’
which are generated by the receive buffer. RBIM is valid only if bit RBM
is set.
0
1
Enable interrupt vector.
Disable interrupt vector.
RFIM
Receive Buffer Failed Interrupt Vector Mask
This bit enables or disables the ’Receive Buffer Access Failed’ interrupt
vector.
0
1
Enable interrupt vector.
Disable interrupt vector.
Preliminary Data Sheet
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PEF 20256M E
Register Description
SFL
RBM
LBE
Short Frame Length
This bit is a global parameter which defines the length of short frames for
all channels.
0
Short frame is defined as a frame containing less than 4 bytes
(CRC16) or less than 6 bytes (CRC32).
1
Short frame is defined as a frame containing less than 2 bytes
(CRC16) or less than 4 bytes (CRC32).
Receive Buffer Monitor
This bit is provided to switch between two monitoring functions of the
receive buffer. Receive buffer monitor functions are available in register
RBTH and RBMON.
0
1
The minimum free pool count is captured in register RBTH.
An interrupt is generated, if the free pool counter falls below the
value programmed in register RBTH.
Little/Big Endian Byte Swap
This bit enables the little or big endian mode, which affects the data
structures pointed to by data pointer of receive or transmit descriptor in
system memory. Registers, interrupt vectors or descriptors are not
affected by little/big endian byte swap.
0
1
Switch data section to little endian mode.
Switch data section to big endian mode.
Preliminary Data Sheet
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PEF 20256M E
Register Description
CONF2
Configuration Register 2
Access
: read/write
: 044H
Address
Reset Value
: 00000000H
31
0
30
28
12
27
0
26
24
23
22
21
20
16
SYSQ(2:0)
PORTQ(2:0)
TBE RSPEN
SPA(4:0)
15
13
0
8
7
0
RCL
0
LPID(4:0)
LCID(7:0)
SYSQ
System Interrupt Queue
SYSQ sets up the interrupt queue where system interrupt vectors will be
written to. One system interrupt queue can be selected for system
interrupts.
PORTQ(2:0) Port Interrupt Vector Queue
PORTQ sets up the interrupt queue where port interrupt vectors will be
written to. One interrupt queue can be selected for port interrupts.
Test Breakout Enable
TBE
This bit enables the test breakout function. The incoming signals of the
port selected via LPID are switched to the test ports and the incoming
signals on the test port replace the output signals of the selected port.
Setting TBE enables the selected port (tri-state no longer active) and has
priority over functions selected in register PMR and priority over bit
RSPEN. The port may be disabled using register REN and TEN to
disable internal processing while test function is active.
0
1
Disable test function.
Enable test function.
RSPEN
Receive Synchronization Pulse Enable
0
The selected transmit clock of port zero is visible on pin TCLKO.
This function is available when port zero is operated in
unchannelized mode.
Preliminary Data Sheet
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PEF 20256M E
Register Description
1
The internally generated synchronization pulse of input port
CONF2.SPA is switched to pin RSPO for test purposes.
SPA
RCL
Synchronization Pulse Access
This bit field selects one framer 0..27 whose synchronization pulse can
be externally monitored. Only valid if RSPEN is set.
Remote Channel Loop
The remote channel loop switches incoming data of one channel to the
outgoing bit stream of the same channel. The bit rate of the receiver and
the transmitter must be the same. The channel to be looped can be
selected using bit field LCID. One channel at a time can be looped.
0
1
Disable remote channel loop.
Enable remote channel loop.
LPID
LCID
Port Identifier
This bit field selects the port which shall be switched to the test port. See
also bit CONF1.TBE.
Loop Channel Identifier
This bit field selects the channel which shall be looped through the
internal loop buffer.
Preliminary Data Sheet
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PEF 20256M E
Register Description
CONF3
Configuration Register 3
Access
: read/write
: 048H
Address
Reset Value
: 00090000H
31
19
16
0
0
0
0
0
0
0
0
0
8
0
0
0
0
0
0
0
0
TPBL(3:0)
15
0
13
0
0
MINFL(5:0)
0
0
0
TPBL
Transmit Packet Burst Length
This bit field is a coding for the maximum burst length on PCI bus, when
data management unit fetches transmit packets. Please refer to Table
8-7 "Threshold Codings" on page 208 for correspondence between
code and maximum burst length.
MINFL
Minimum Frame Length
Only valid for those channel which have bit CSPEC_MODE_REC.SFDE
set. MINFL sets the minimum frame length in bytes (payload bytes and
CRC bytes) for frames which will be forwarded to system memory. If
enabled the receive buffer will drop frames which are smaller or equal to
the programmed value MINFL to avoid wasting of PCI bandwidth in case
of error conditions. The small frame check is disabled, if MINFL is set to
zero.
Note: Since the receive packets will be dropped inside the receive
buffer, the receive packet threshold CSPEC_BUFFER.RTC has
to be greater than MINFL/4 in order to work properly.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
RBAFT
Receive Buffer Access Failed Interrupt Threshold Register
Access
: read/write
: 04CH
Address
Reset Value
: 00000000H
31
15
16
RBAFT(31:0)
RBAFT(31:0)
0
RBAFT
Receive Buffer Access Failed Interrupt Threshold
This register sets the threshold for the ’Receive Buffer Access Failed’
interrupt vector.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
SFDT
Small Frame Dropped Interrupt Threshold Register
Access
: read/write
: 050H
Address
Reset Value
: 00000000H
31
15
16
SFDIT(31:0)
SFDIT(31:0)
0
SFDIT
Small Frame Dropped Interrupt Vector Threshold
The programmed threshold defines the threshold for the ’Small Frame
Dropped’ interrupt vector. As soon as the internal number of dropped,
small frames reaches the programmed value a channel interrupt vector
with bit SFD set will be generated. The actual value of dropped frames
can be read using register SFDC. The value is applied to all 256
channels.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
PMIAR
Port Mode Indirect Access Register
Access
: read/write
: 060H
Address
Reset Value
: 00000000H
31
23
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIP
0
0
0
0
0
4
0
0
0
0
0
15
0
0
PORT(4:0)
Note: This register is an indirect access register which must be programmed before
accessing the register PMR.
AIP
Auto Increment Port
This bit enables the auto increment function of bit field PORT. Each read/
write access to register PMR increments PORT. This allows to program
multiple, consecutive ports without accessing PMIAR again.
0
1
Disable auto increment function.
Enable auto increment function.
PORT
Port Select
This bit field selects the port number, which can be accessed via register
PMR.
0..27 Port Number
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
PMR
Port Mode Register
Access
: read/write
Address
: 064H
Reset Value
: 0104C000H
31
28
24
22
18
16
PCM(3:0)
0
0
0
000B
0
5
0
0
0
0
000B
15
14
13
0
12
11
0
10
0
9
8
7
6
0
0
CTFSD
RIM TIM
TXR
LT
RLL RPL LPL
0
0
Note: Effected port is selected via register PMIAR. All settings in this register affect the
selected port only.
PCM
Select Port Mode
This bit field selects the port mode.
0000B T1 mode (1.544 MHz)
1000B E1 mode (2.048 MHz)
1111B Unchannelized mode
RIM
TIM
Receive Synchronization Error Interrupt Vector Mask
This bit disables generation of the port interrupt vector receive. See "Port
Interrupts" on page 127 for description of interrupt vectors.
0
1
Enable
Disable
Transmit Synchronization Error Interrupt Vector Mask
This bit disables generation of the port interrupt vector transmit. See
"Port Interrupts" on page 127 for description of interrupt vectors.
0
1
Enable
Disable
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
TXR
Transmit Data Rising
This bit defines the edge the common transmit frame synchronization
pulse CTFS is sampled on with respect to the common transmit clock
CTCLK.
0
1
CTFS is sampled on the rising edge of CTCLK.
CTFS is sampled on the falling edge of CTCLK.
CTFSD
LT
Common transmit frame synchronization disable
0
1
Bit 0 of transmit data is synchronized to CTFS.
Synchronization of data to CTFS is disabled.
Looped Timing
This bit selects the transmit clock in MUNICH256FM. Per default the
transmit clock of the selected tributary is the common transmit clock. If
set to ‘1’ the corresponding tributary is switched into looped timed mode.
0
1
Select normal operation mode.
Select looped timing mode.
RLL
RPL
LPL
Remote Line Loop
This bit enables the remote line loop of the selected port.
0
1
Disable remote line loop.
Enable remote line loop.
Remote Payload Loop
This bit enables the remote payload loop of the selected port.
0
1
Disable remote payload loop.
Enable remote payload loop.
Local Port Loop
This bit enables the local port loop on the selected port. When local loops
are closed, the corresponding transmit clock and the synchronization
pulse is switched to the receive port.
0
1
Disable local port loop.
Enable local port loop.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
REN
Receive Enable Register
Access
: read/write
: 068H
Address
Reset Value
: 00000000H
31
27
16
0
0
0
0
REN(27:0)
15
0
REN(27:0)
REN
Receive Enable
Setting a bit in this bit field enables the receive function of the selected
port. After reset all ports are disabled and thus all incoming receive data
is discarded. While a port is disabled communication between port
handler, time slot assigner and synchronization function is disabled. A
port should be enabled if it is correctly configured using registers PMIAR
and PMR.
0
1
Disable receive port.
Enable receive port.
Preliminary Data Sheet
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PEF 20256M E
Register Description
TEN
Transmit Enable Register
Access
: read/write
: 06CH
Address
Reset Value
: 00000000H
31
27
16
0
0
0
0
TEN(27:0)
15
0
TEN(27:0)
TEN
Transmit Enable
This bit field enables the transmit function of the selected port. After reset
all transmit ports are disabled and thus all TD lines are set to tri-state.
While a port is reset the communication between port handler, time slot
assigner and synchronization function is disabled. After the port mode
has been selected using register PMIAR and PMR a transmit port can
be enabled.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
TSAIA
Time slot Assignment Indirect Access Register
Access
: read/write
: 070H
Address
Reset Value
: 00000000H
31
23
16
DIR
0
0
0
0
0
0
0
8
AIT
0
0
0
0
4
0
0
0
0
15
12
0
PORT(4:0)
TSNUM(4:0)
DIR
Direction
This bit select the direction for which programming is valid.
0
1
Program time slots in receive direction.
Program time slots in transmit direction.
AIT
Auto Increment Time slot
This bit enables the auto increment function of bit field TSNUM. Each
read/write access to register TSAD increments TSNUM. This allows to
program multiple, consecutive time slots without accessing TSAIA
again.
0
1
Disable auto increment function.
Enable auto increment function.
PORT
Port Select
This bit field selects the port number, which can be accessed via register
TSAIA.
0..27 Port number
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
TSNUM
Time Slot Number
This bit field selects the time slots, which can be accessed via register
TSAIA.
Valid time slot numbers are:
0..23 T1, Unchannelized
0..31 E1
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
TSAD
Time slot Assignment Data Register
Access
: read/write
: 074H
Address
Reset Value
: 02000000H
31
25
24
0
0
0
0
0
0
INHI TMA
BIT 1ST
0
7
0
0
0
0
0
0
0
0
15
8
CHAN(7:0)
MASK(7:0)
Note: The time slot assignment data register assigns a channel and a mask to a specific
port/time slot combination. The related port/time slot must be chosen by accessing
TSAIA.
The time slot assignment has to be done before a specific channel is configured for
operation. After operation the port/time slot assignment of a particular channel has to be
set to inhibit.
INHIBIT
Inhibit Time slot
This bit disabled processing of the selected port/time slot.
0
1
The time slot is enabled.
The time slot is disabled. In receive direction incoming octets are
discarded. In transmit direction the octet of this time slot and port
is set to FFH.
TMA1ST
CHAN
TMA First
This bit marks the first time slot belonging to a TMA superchannel for
TMA synchronization. Receiver starts processing data on the marked
time slot. In transmit direction data transmission is started on the marked
time slot. If TMA channel uses only one time slot this bit must be set.
Channel Number
This bit field selects the channel number which will be associated to the
port and time slot which is selected in register TSAIA.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
MASK
Mask Bits
Setting a bit in this bit field selects the corresponding bit in a time slot
which is enabled for operation.
0
In receive direction the corresponding bit is discarded. In transmit
direction the bit is sent as ‘1’.
1
In receive direction the corresponding bit is forwarded to the
protocol machine (via time slot assigner). In transmit direction
data on the serial line is generated by the protocol machine.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
REC_ACCMX
Receive Extended ACCM Map Register
Access
: read/write
: 080H
Address
Reset Value
: 00000000H
31
15
24
23
16
CHAR3(7:0)
CHAR1(7:0)
CHAR2(7:0)
8
7
0
CHAR0(7:0)
This register is only used by channels operated in octet synchronous PPP mode. A
character written to this register is mapped with a control escape sequence, if the
corresponding
enable
flag
is
set
in
the
corresponding
bit
CSPEC_MODE_REC.ACCMX(3:0).
Preliminary Data Sheet
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PEF 20256M E
Register Description
RBAFC
Receive Buffer Access Failed Counter Register
Access
: read
Address
: 084H
Reset Value
: 00000000H
31
15
16
RBAFC(31:0)
RBAFC(31:0)
0
RBAFC
Receive Buffer Access Failed Counter
The read value of this register defines the number of packets which have
been discarded due to inaccessibility of the internal receive buffer. A
read access resets the counter to zero.
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PEF 20256M E
Register Description
SFDIA
Small Frame Dropped Indirect Access Register
Access
: read/write
: 088H
Address
Reset Value
: 00000000H
31
23
22
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIC CLR
0
0
0
0
0
0
15
0
7
0
CHAN(7:0)
AIC
Auto Increment Channel
This bit enables the auto increment function of bit field CHAN. Each
read/write access to register SFD increments CHAN by two. This allows
to read the status of multiple channels without accessing SFDIA again.
0
Disable auto increment function.
Enable auto increment function.
1
CLR
Clear
This bit enables the counter mode on reads to register SFDC.
0
Read of register SFDC does not affect the small frame dropped
counter.
1
After reading register SFDC the value of the small frame dropped
counter will be reset to zero.
CHAN
Channel Number
This bit field selects the channel, whose status can be read in register
SFDC.
0..255 Channel number
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PEF 20256M E
Register Description
SFDC
Small Frame Dropped Counter Register
Access
: read
Address
: 08CH
Reset Value
: 00000000H
31
15
16
SFDC++(15:0)
SFDC(15:0)
0
These both bit fields show the current value of the small frame dropped counter of the
channel N and N+1 selected via SFDIA.CHAN. Dependent on bit field SFDIA.CLR the
counter will be cleared after they are read.
SFDC++
Small Frame Dropped Counter for Channel N+1
The number of dropped, small frames of channel SFDIA.CHAN+1.
Small Frame Dropped Counter
SFDC
The number of dropped, small frames of channel SFDIA.CHAN.
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PEF 20256M E
Register Description
XMIT_ACCMX
Transmit Extended ACCM Map
Access
: read/write
: 090H
Address
Reset Value
: 00000000H
31
15
24
23
16
CHAR3(7:0)
CHAR1(7:0)
CHAR2(7:0)
8
7
0
CHAR0(7:0)
This register is only used by a channel in octet synchronous PPP mode. A character
written to this register will be mapped with a Control Escape sequence, if the
corresponding enable flag is set in the CSPEC_MODE_XMIT register (ACCMX(3:0)).
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PEF 20256M E
Register Description
RBMON
Receive Buffer Monitor Indirect Access Register
Access
: read
Address
: 0B0H
Reset Value
: 02000BFFH
31
25
16
0
0
0
0
0
0
0
0
0
RBAQC(9:0)
15
0
11
0
RBFPC(11:0)
RBAQC
RBFPC
Receive Buffer Action Queue Free Count
The value of this register determines the actual number of free actions
inside the receive buffer.
Receive Buffer Free Pool Count
The value of this register determines the actual number of free buffer
locations inside the receive buffer. After reset a total number of 3072
receive buffer locations, which equals 12kB receive buffer, is available.
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PEF 20256M E
Register Description
RBTH
Receive Buffer Threshold Register
Access
: read/write
: 0B4H
Address
Reset Value
: 02000001H
31
25
16
0
0
0
0
0
0
0
0
0
RBAQTH(9:0)
15
0
11
0
RBTH(11:0)
RBAQTH
Receive Buffer Action Queue Free Pool Threshold
Function of RBAQTH is dependent on bit CONF1.RBM.
CONF1.RBM = ’0’:
The minimum value of RBMON.RBAQC, which occurred since the last
reset or the last read of this register, is captures in here.
CONF1.RBM = ’1’:
A ’Receive Buffer Action Queue Early Warning’ interrupt will be
generated, if the receive buffer action queue free pool drops below the
value programmed in bit field RBAQTH. The value to be programmed
must be in the range of 000H to 1FFH.
RBTH
Receive Buffer Free Pool Threshold
Function of RBTH is dependent on CONF1.RBM.
CONF1.RBM = ’0’:
The minimum value of RBMON.RBFP, which occurred since the last
reset or the last read of this register, is captured in here.
CONF1.RBM = ’1’:
A ’Receive Buffer Queue Early Warning’ interrupt vector will be
generated, if the receive buffer free pool drops below the value
programmed in bit field RBTH.
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PEF 20256M E
Register Description
IQIA
Interrupt Queue Indirect Access Register
Access
: read/write
: 0E0H
Address
Reset Value
: 00000000H
31
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DBG SIQM SIQL SIQBA
15
0
3
0
0
Q(3:0)
DBG
Debug
This bit selects the debug mode of the interrupt controller. When DEBUG
is set, the actual values of interrupt queue base address, interrupt queue
length and high priority interrupt queue mask of queue Q are copied to
register IQBA, IQL and IQMASK. The value can be read with a following
access to these registers.
Note: Setting DEBUG is only allowed, if neither SIQBA, SIQL and SIQM
are set.
0
1
No operation
Enable debug mode.
SIQM
Set High Priority Interrupt Queue Mask
This bit field enables setup of the high priority interrupt queue mask of
queue Q. The value to be programmed has to be configured via register
IQMASK prior to a write access to this bit.
0
1
No operation
Set high priority mask.
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PEF 20256M E
Register Description
SIQL
Set Interrupt Queue Length
This bit field enables setup of the interrupt queue length of queue Q. The
value to be programmed has to be configured via register IQL prior to a
write access to this bit.
0
1
No operation
Set interrupt queue length.
SIQBA
Set Interrupt Queue Base address
This bit field enables setup of the interrupt queue base address of queue
Q. The value to be programmed has to be configured via register IQBA
prior to a write access to this bit.
0
1
No operation
Update interrupt queue base address with value programmed in
register IQBA.
Q
Interrupt Queue Number
This bit field determines the interrupt queue number for which
programming is valid. The first eight (0..7) interrupt queues are used for
channel, port and system interrupt vectors, while the last interrupt queue
(8) is used for command interrupt vectors. Interrupt queue number seven
is per default the high priority interrupt queue.
System software may setup the interrupt queue high priority mask, the
interrupt queue length and the interrupt queue base address
simultaneously by setting SIQL, SIQBA and SIQM.
The command interrupt queue has a fixed length of two times 256
DWORDs, that is one DWORD for each interrupt vector.
It is possible to setup the interrupt queue high priority mask, the interrupt
queue length and the interrupt queue base address concurrently by
setting SIQBA, SIQL and SIQM to ’1’.
Note: Programming of interrupt queue length or interrupt queue high
priority mask is not valid for the command interrupt queue
(interrupt queue 8).
Note: Programming of interrupt queue high priority mask is not valid for
the high priority interrupt queue (interrupt queue 7).
0..8 Interrupt Queue
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PEF 20256M E
Register Description
IQBA
Interrupt Queue Base Address Register
Access
: read/write
: 0E4H
Address
Reset Value
: 00000000H
31
15
16
IQBA(31:2)
2
1
0
0
0
IQBA(31:2)
IQBA
Interrupt Queue Base Address
The interrupt queue base address register assigns a base address to the
eight channel interrupt queues and the command interrupt queue. To set
a new base address for a specific queue, system software must first
program IQBA. Afterwards the value is released by selecting the
associated queue via bit field IQIA.Q and setting of bit IQIA.SIQBA. The
interrupt queue base address has to be DWORD aligned. Whenever the
base address of a particular interrupt queue is modified, the next
interrupt vector written to that queue is stored in the first location of the
queue.
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PEF 20256M E
Register Description
IQL
Interrupt Queue Length Register
Access
: read/write
: 0E8H
Address
Reset Value
: 00000000H
31
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
0
0
0
0
0
0
0
15
0
0
IQL(7:0)
IQL
Interrupt Queue Length
This bit field assigns a interrupt queue length to the eight channel
interrupt queues. To set the interrupt queue length of a specific queue,
system software must first program IQL. Afterwards the value is released
by selecting the associated queue via bit field IQIA.Q and setting of bit
IQIA.SIQL. IQL specifies the interrupt queue length L (number of
DWORDs) in the shared memory with
L=(IQL+1)*16 (maximum of 4092 DWORDs).
Note: IQL = 255 equals a queue length of 1 DWORD.
Whenever the length of a particular interrupt queue is modified, the next
interrupt vector written to that queue is stored in the first location of the
queue.
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PEF 20256M E
Register Description
IQMASK
Interrupt Queue High Priority Mask
Access
: read/write
: 0ECH
Address
Reset Value
: 00000000H
31
30
28
23
22
16
THI TAB
0
HTAB
0
0
0
9
0
8
UR TFE
0
5
0
0
0
3
0
2
0
0
0
15
14
13
12
11
10
7
6
0
0
RHI RAB RFE HRAB MFL ROFD CRC ILEN RFOP SF IFTC
SFD SD
In normal operation each channel interrupt vector is written to the interrupt queue
associated with a specific channel, that is interrupt queue 0 to 7. The interrupt queue
mask provides the functionality to forward selected channel interrupts to the high priority
interrupt queue, which is hardwired as queue 7.Therefore a mask can be set for each of
the interrupt queues, which specifies the channel interrupt vector to be forwarded to the
high priority interrupt queue. To set the IQMASK for interrupt queues 0 to 6, system
software must first program IQMASK. Afterwards the mask is released by selecting the
affected interrupt queue via bit field IQIA.Q and setting of bit SIQM.
Those interrupt vectors which have an interrupt bit set, that is also masked in this high
priority mask are forwarded to the high priority interrupt queue instead of the regular
interrupt queue associated with a specific channel.
If a channel interrupt vector has at least one interrupt bit set, that is also masked in the
high priority mask, the interrupt vector will be forwarded to the high priority interrupt
queue.
In case that a channel interrupt vector has at least one bit set, that is not masked in the
high priority mask, the interrupt vector is queued into the regular interrupt queue
associated with the corresponding channel.
Preliminary Data Sheet
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PEF 20256M E
Register Description
GISTA/GIACK
Interrupt Status/Interrupt Acknowledge Register
Access
: read/write
: 0F0H
Address
Reset Value
: 00000000H
31
17
16
IF
INTOF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LBI
15
0
8
7
6
5
4
3
2
1
0
Q8
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Depending on the corresponding bits in register GMASK, an interrupt indication in this
register will be flagged at pin INTA. If an interrupt bit is masked (set to ’1’) in register
GMASK, system software has to poll this register in order to get status information of the
disabled interrupt bit.
INTOF
Interrupt Overflow
This bit indicates that interrupt information has been lost due to overload
conditions of the internal interrupt controller. This interrupt indicates a
severe system problem. If this bit is set and INTOF is not masked in
register GMASK, the interrupt pin INTA will be asserted. INTOF is
cleared, when an ’1’ is written to this bit.
0
1
No interrupt overflow.
Interrupt overflow. The interrupt will be cleared by writing a ‘1’ to
the corresponding bit.
LBI
Local Bus Interrupt
The MUNICH256FM supports bridging of interrupts from the local bus to
the PCI bus. In this application the pin LINT is used as an input and as
Preliminary Data Sheet
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PEF 20256M E
Register Description
soon as LINT changes from an inactive to an active state the interrupt
pin INTA will be asserted.
Note: This bit does not clear by writing a ’1’. This bit is set as long as
the interrupt pin LINT is asserted.
0
1
LINT not asserted.
LINT asserted.
IF
Interrupt FIFO
This bit indicates that there is an interrupt vector stored in the internal
interrupt FIFO. The IF interrupt is available if the interrupt pin LINT is
switched to input mode (INTCTRL.ID = ’1’) and when the interrupt mask
GMASK.IF is set to ’0’.
Note: This bit does not clear by writing a ’1’. This bit is set as long as an
interrupt vector is stored in the interrupt FIFO.
0
1
No Interrupt vector in interrupt FIFO.
Interrupt vector stored in internal interrupt FIFO.
Q8..Q0
Interrupt Queue 8..0
On reads each bit flags one or more interrupt vectors that have been
written to the corresponding interrupt queue. If one of the bits is set and
the same bit is not masked in register GMASK, the interrupt pin INTA will
be asserted. A bit is cleared, when an ’1’ is written to the specific bit.
0
1
No interrupt vector written.
Read: One or more interrupt vectors have been written to
interrupt queue.
Write: Clear bit
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PEF 20256M E
Register Description
GMASK
Global Interrupt Mask Register
Access
: read/write
: 0F4H
Address
Reset Value
: FFFFFFFFH
31
17
16
INTOF
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
LINT IF
15
1
8
7
6
5
4
3
2
1
0
Q8
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Each bit in this register mask the interrupts, which are flagged in register GISTA/GIACK.
INTOF
Mask Interrupt Overflow
This bit masks the interrupt overflow interrupt.
Local Bus Interrupt
LINT
This bit masks bridging of interrupt from the local bus to the PCI bus.
0
1
Bridging of LINT to INTA enabled.
Bridging of LINT to INTA disabled.
IF
Interrupt FIFO
This bit masks the internal mailbox/layer one interrupt FIFO.
0
1
IF interrupt is enabled.
IF interrupt is disabled.
Q8..Q0
Mask Interrupt Queue 8..0
Each of the bits Q8..Q0 masks an interrupt, which will be asserted, when
an interrupt vector has been written to the corresponding interrupt queue
8..0. Masking an interrupt does not suppress generation of the interrupt
vector itself.
0
Enable interrupt, when interrupt vector has been written to
selected interrupt queue.
1
Mask (Disable) interrupt, when interrupt vector has been written
to selected interrupt queue.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
8.2.3
PCI and Local Bus Slave Register Set
FCONF
Framer and FDL Configuration Register
Access
: read/write
Address
: 100H (PCI), 00H (Local Bus)
: 8080H
Reset Value
15
IIP
14
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
MBID WSE BSD P28 P18 P08 LAE LME
IIP
Initialization in Progress (Read Only)
After reset (hardware reset or software reset) the internal RAM’s are self
initialized by the MUNICH256FM. During this time (approx. 250 µs) no
other accesses to the device than reading register CONF1 or FCONF
are allowed. This bit must be polled until it has been deasserted by the
MUNICH256FM.
0
1
Self initialization has finished.
Self initialization in progress.
MBID
WSE
Mailbox Interrupt Vector Disable
0
Enable generation of mailbox interrupt vectors. As soon as
system software on PCI side writes to register MBP2E0 an
interrupt vector indicating a mailbox interrupt will be forwarded to
the internal interrupt FIFO and can be read by the local CPU.
1
Disable generation of mailbox interrupt vectors.
Wait State Enable
This bit enables the wait state controlled master mode.
0
1
LRDY (Intel), LDTACK (Motorola) controlled bus mode.
Wait state controlled bus mode. Wait states are defined in
register MTIMER.WS.
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PEF 20256M E
Register Description
BSD
Byte Swap Disable
This bit disables byte swapping on 16-bit transfers when the local bus is
operated in Motorola master mode.
0
1
Enable byte swap.
Disable byte swap.
P28..P08
Switch Page 2..0 to 8-bit mode
The MUNICH256FM maps three pages of 8 kByte each to the local bus
in master mode. Each page accessed from the PCI side can be mapped
in 8-bit mode or 16-bit mode. In 8-bit mode the data bits LD(15:8) are
unused.
0
1
Set page mode to 16-bit mode.
Set page mode to 8-bit mode.
LAE
Local Bus Arbiter Enable
This bit enables the local bus arbiter. In case that the local bus arbiter is
enabled the MUNICH256FM will arbitrate for each bus access on the
local bus using the arbitration signals. If local bus arbiter functionality is
disabled it assumes bus ownership and does not arbitrate for the local
bus.
0
1
Disable the local bus arbiter.
Enable the local bus arbiter.
LME
Local Bus Master Enable
This bit enables the local bus master functionality. As long as the local
bus master functionality is disabled the MUNICH256FM can be
accessed from the local bus as slave only.
0
1
Disable Local Bus Master.
Enable Local Bus Master.
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PEB 20256M E
PEF 20256M E
Register Description
MTIMER
Master Local Bus Timer Register
Access
: read/write
Address
: 104H (PCI), 02H (Local Bus)
: 0000H
Reset Value
15
4
3
0
TIMER(15:4)
WS(3:0)
TIMER
Local Bus Latency Timer
TIMER*16 determines the time in clock cycles the MUNICH256FM holds
the local bus as bus master after it was granted the bus. It holds the bus
as long as the first transaction is in progress or the latency timer is
counting. In case that the MUNICH256FM shall release the bus after it
each transaction the latency TIMER value must be set to zero.
WS
Wait State Timer
The value of this register determines the time in clock cycles the
MUNICH256FM asserts LRD, LWR (Intel Mode) respectively LDS
(Motorola Bus Mode). See also FCONF.WSE.
Preliminary Data Sheet
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PEF 20256M E
Register Description
INTCTRL
Interrupt Control Register
Access
: read/write
Address
: 108H (PCI), 04H (Local Bus)
: 0001H
Reset Value
15
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
ID
IP CLIQ IM
ID
IP
Interrupt Direction
This pin determines the direction of the interrupt pin LINT.
0
1
LINT is output.
LINT is input.
Interrupt Polarity
0
1
LINT is active low.
LINT is active high.
CLIQ
Clear Interrupt Queue
Setting this bit will clear the internal interrupt FIFO. This effects all
interrupts of facility data link, framer and mailbox interrupts to the local
bus.
0
1
No action
Clear interrupt FIFO.
IM
Interrupt Mask
This bit masks assertion of the pin LINT when interrupts are stored in the
internal interrupt FIFO. If the interrupt direction bit is set to output mode
interrupt are flagged at interrupt pin LINT. If the interrupt direction is set
to input mode interrupts are flagged at pin INTA.
0
1
Enable assertion of interrupt pin LINT.
Disable assertion of interrupt pin LINT.
Preliminary Data Sheet
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PEF 20256M E
Register Description
INTFIFO
Interrupt FIFO
Access
: read
Address
: 10CH (PCI), 06H (Local Bus)
: FFFFH
Reset Value
15
0
IV(15:0)
IV
Interrupt Vector
After the MUNICH256FM asserted interrupt pin LINT on the local bus
side, this bit field contains an interrupt vector containing interrupt
information. Please refer to section "Layer One Interrupts" on page 136
for a detailed description of interrupt vector contents.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
TREGSEL
Transmit T1/E1 Framer Port & Register Select
Access
: read/write
Address
: 110H (PCI), 08H (Local Bus)
: 0000H
Reset Value
15
0
14
12
8
7
3
0
AIP
0
PORT(4:0)
AIA
0
0
0
ADDR(3:0)
Note: This register is an indirect access register, which must be programmed before
accessing the register TDATA.
AIP
Auto Increment Port
This bit enables the auto increment function of bit field PORT. Each read/
write access to register TDATA increments PORT. This allows to
program multiple, consecutive ports without accessing TREGSEL again.
0
1
Disable auto increment function.
Enable auto increment function.
PORT
AIA
Port Select
This bit field selects the port number, which can be accessed via register
TDATA.
0..27 Port Number.
Auto Increment Address
This bit enables the auto increment function of bit field ADDR. Each
read/write access to register TDATA increments ADDR. This allows to
program multiple, consecutive registers without accessing TREGSEL
again.
0
1
Disable auto increment function.
Enable auto increment function.
ADDR
Register Address
This bit field selects the register address of the transmit framer, which
can be accessed via register TDATA.
0H..FH Register address.
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PEF 20256M E
Register Description
TDATA
Transmit T1/E1 Framer Data Register
Access
: read/write
Address
: 114H (PCI), 0AH (Local Bus)
: 0000H
Reset Value
15
0
DATA(15:0)
Note: Effected port and address is selected via register TREGSEL. All settings in this
register affect the selected port only.
DATA
Data register
The transmit framer data register assigns a value to the transmit framer
of port TREGSEL.PORT and the register selected via bit field
TREGSEL.ADDR. Read/write operation depends on the selected
register.
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PEF 20256M E
Register Description
RREGSEL
Receive T1/E1 Framer Port & Register Select
Access
: read/write
Address
: 118H (PCI), 0CH (Local Bus)
: 0000H
Reset Value
15
0
14
12
8
7
6
0
AIP
0
PORT(4:0)
AIA
ADDR(6:0)
Note: This register is an indirect access register, which must be programmed before
accessing the register RDATA.
AIP
Auto Increment Port
This bit enables the auto increment function of bit field PORT. Each read/
write access to register RDATA increments PORT. This allows to
program multiple, consecutive ports without accessing RREGSEL again.
0
1
Disable auto increment function.
Enable auto increment function.
PORT
AIA
Port Select
This bit field selects the port number, which can be accessed via register
RDATA.
0..27 Port Number.
Auto Increment Address
This bit enables the auto increment function of bit field ADDR. Each
read/write access to register RDATA increments ADDR. This allows to
program multiple, consecutive registers without accessing RREGSEL
again.
0
1
Disable auto increment function.
Enable auto increment function.
ADDR
Register Address
This bit field selects the register address of the transmit framer, which
can be accessed via register RDATA.
0H..7FHRegister address.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
RDATA
Receive T1/E1 Framer Data Register
Access
: read/write
Address
: 11CH (PCI), 0EH (Local Bus)
: 0000H
Reset Value
15
0
DATA(15:0)
Note: Effected port and address is selected via register RREGSEL. All settings in this
register affect the selected port only.
DATA
Data register
The receive framer data register assigns a value to the receive framer of
port RREGSEL.PORT and the register selected via bit field
RREGSEL.ADDR. Read/write operation depends on the selected
register.
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PEF 20256M E
Register Description
FREGSEL
FDL Port & Register Select
Access
: read/write
Address
: 120H (PCI), 10H (Local Bus)
: 0000H
Reset Value
15
12
8
7
4
0
AIP
0
0
PORT(4:0)
AIA
0
0
ADDR(4:0)
Note: This register is an indirect access register which must be programmed before
accessing the register FDATA.
AIP
Auto Increment Port
This bit enables the auto increment function of bit field PORT. Each read/
write access to register FDATA increments PORT. This allows to
program multiple, consecutive ports without accessing FREGSEL again.
0
1
Disable auto increment function.
Enable auto increment function.
PORT
Port Select
This bit field selects the port number, which can be accessed via register
FDATA.
0..27 Port Number for T1/E1.
28
29
Far End Alarm and Control Channel (DS3)
C-bit parity path maintenance data link channel (DS3)
AIA
Auto Increment Address
This bit enables the auto increment function of bit field ADDR. Each
read/write access to register FDATA increments ADDR. This allows to
program multiple, consecutive registers without accessing FREGSEL
again.
0
1
Disable auto increment function.
Enable auto increment function.
Preliminary Data Sheet
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PEF 20256M E
Register Description
ADDR
Register Address
This bit field selects the register address of the facility data link channel,
which can be accessed via register FDATA.
0H..1FHRegister address.
Preliminary Data Sheet
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PEF 20256M E
Register Description
FDATA
FDL Data Register
Access
: read/write
Address
: 124H (PCI), 12H (Local Bus)
: 0000H
Reset Value
15
0
DATA(15:0)
Note: Effected port and address is selected via register FREGSEL. All settings in this
register affect the selected port only.
DATA
Data register
The FDL data register assigns a value to the facility data link controller
of port FREGSEL.PORT and the register selected via bit field
FREGSEL.ADDR. Read/write operation depends on the selected
register.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
MBE2P0
Mailbox Local Bus to PCI Command Register
Access
: read/write
Address
: 140H (PCI), 20H (Local Bus)
: 0000H
Reset Value
15
0
MB(15:0)
MB
Mailbox Data register
This register can be written and read from local bus side. From PCI side
this register should be used as read only in order to allow stable
interprocessor communication. Write access to this register results in
mailbox interrupt vectors on local bus side to the internal interrupt FIFO
when FCONF.MBID is set to ‘0’.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
MBE2P1-7
Mailbox Local Bus to PCI Data Register 1-7
Access
: read/write
Address
: 144H-15CH (PCI), 22H-2EH (Local Bus)
: 0000H
Reset Value
15
0
MB(15:0)
MB
Mailbox Data register
This register can be written and read from local bus side. From PCI side
this register should be used as read only in order to allow stable
interprocessor communication.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
MBP2E0
Mailbox PCI to Local Bus Status Register
Access
: read/write
Address
: 160H (PCI), 30H (Local Bus)
: 0000H
Reset Value
15
0
MB(15:0)
MB
Mailbox Status Register
This register can be written and read from PCI side. From local bus side
this register should be used as read only in order to allow stable
interprocessor communication. Write access to this register results in
mailbox interrupt vectors to PCI side when CONF1.MBIM is set to ‘0’.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
MBP2E1-7
Mailbox PCI to Local Bus Data Register 1-7
Access
: read/write
Address
: 164H-17CH (PCI), 32H-3EH (Local Bus)
: 0000H
Reset Value
15
0
MB(15:0)
MB
Mailbox Data Register
This register can be written and read from PCI side. From local bus side
this register should be used as read only in order to allow stable
interprocessor communication.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
8.2.3.1 M13 Transmit Registers
D3CLKCS
DS3 Clock Configuration and Status Register
Access
: read/write
Address
: 180H (PCI), 40H (Local bus)
: 0000H
Reset Value
15
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RCA TCA RRX RTX T2RL R2TL TXLT
RCA
Receive Clock Activity
This bit monitors the receive clock activity (RC44).
0
No receive DS3 clock since last read of this register. This bit is
set to ‘0’ approx. 125 µs after the last active clock was detected.
1
At least one receive DS3 clock since last read of this register.
TCA
Transmit Clock Activity
This bit monitors the transmit clock activity (TC44).
0
No transmit DS3 clock since last read of this register. This bit is
set to ‘0’ approx. 125 µs after the last active clock was detected.
1
At least one transmit DS3 clock since last read of this register.
RRX
RTX
Reset Receiver Clock Unit
This bit resets the receivers clock unit.
0
1
Normal operation.
Reset DS3 receiver clock unit. This bit is self clearing.
Reset Transmitter Clock Unit
This bit resets the transmitters clock unit.
0
1
Normal operation.
Reset DS3 transmitter clock unit. This bit is self clearing.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
T2RL
R2TL
TXLT
Transmit to Receive Loop (Local DS3 Loopback)
This bit enables the local DS3 loop where the outgoing DS3 bit stream
is mirrored to the DS3 input.
0
1
Disable local loop.
Enable local loop.
Receive to Transmit Loop (Remote DS3 Loopback)
This bit enables the remote DS3 line loop where the complete incoming
DS3 bit stream is mirrored to the transmitter.
0
1
Disable remote loop.
Enable remote loop.
Transmit Loop Timing Mode
This bit enables DS3 looped timing where the transmitter uses the
receivers DS3 input clock.
0
1
Disable looped timing.
Enabled looped timing.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
TUCLKC
Test Unit Clock Configuration Register
Access
: read/write
Address
: 184H (PCI), 42H (Local bus)
: 0000H
Reset Value
15
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RTUR TUL
RTUR
Reset Test Unit Receiver
This bit resets the test unit receiver.
0
1
Normal operation.
Reset Receiver (automatically removed). This bit is self clearing.
TUL
Test Unit Transmit to Receive Loop
This bit switches a local loop from the test unit transmitter to the test unit
receiver. While operating in loop mode the test unit is operated with
TC44.
0
1
Normal operation.
Test unit transmitter output connected to test unit receiver input.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
D3TCFG
DS3 Transmit Configuration Register
Access
: read/write
Address
: 188H (PCI), 44H (Local bus)
: 0000H
Reset Value
15
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
FAM ITCK ITD UTD AISC LPC(1:0)
FPL CBP
FAM
TOVHSYN Mode
This bit switches between input mode and output mode of the signal pin
TOVHSYN. If TOVHSYN is operated in input mode it marks the position
of the X-bit. Therefor the outgoing DS3 frame is aligned to TOVHSYN. If
TOVHSYN is switched to output mode TOVHSYN is asserted when the
X-bit needs to be inserted via the transmit overhead interface.
0
1
TOVHSYN switched to input.
TOVHSYN switched to output.
ITCK
ITD
Invert Transmit Clock
This bit sets the clock edge for data transmission.
0
1
Update transmit data on the rising edge of transmit clock.
Update transmit data on the falling edge of transmit clock.
Invert Transmit Data
This bit enables inversion of transmit data.
0
1
Transmit data is logic high (not inverted).
Transmit data is logic low (inverted).
UTD
Unipolar data mode
This bit sets the port mode to dual-rail mode or unipolar mode.
0
1
B3ZS (dual rail data)
Unipolar mode (single rail data)
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
AISC
AIS Code Type
This bit field sets the AIS code.
0
Set AIS to ’1010... ’ between overhead bits, C-bits all ‘0’s, X-bits
all ‘1’s (standard)
1
Set AIS to unframed all ‘1’s (non-standard).
LPC
Loopback Code.
This bit field selects the C-bit which will be inverted when loopback
requests are transmitted.
00
01
10
Invert 1st C-bit.
Invert 2nd C-bit.
Invert 3rd C-bit.
FPL
Full Payload Mode
This bit enables the M23 multiplex operation or the full payload rate
format.
0
Enable M23 multiplex operation. Payload is formed by
interleaving 7 asynchronous DS2 tributaries
1
Enable full payload rate format. The payload is one single, high
speed data stream without stuffing.
CBP
C-bit parity mode
This bit enables M13 asynchronous mode or C-bit parity mode.
0
1
M13 asynchronous mode
C-bit parity mode
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
D3TCOM
DS3 Transmit Command Register
Access
: read/write
Address
: 18CH (PCI), 46H (Local bus)
: 0070H
Reset Value
15
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
TAIC TNrB TXBITSIDLESAISA SAIS
TAIC
Transmitted AIC-bit
This bit sets the value to be transmitted in the DS3 overhead bit of
block 3, subframe 1. This function is available in C-pit parity format only.
0
AIC-bit = ‘0’
AIC-bit = ‘1’
1
TNrB
Transmitted Nr-bit
This bit sets the value to be transmitted in the DS3 overhead bit of
block 5, subframe 1. This function is available in C-pit parity format only.
0
1
Nr-bit = ‘0’
Nr-bit = ‘1’
TXBIT
Transmitted X-bits
This bit sets the value to be transmitted in the DS3 overhead bit of
block 1, subframes 1 and 2.
TXBIT is synchronized to the M23 multiframe. Both X-bits in a multiframe
are guaranteed identical. Software should limit changes to maximum of
1 per second.
0
1
X-bit = ‘0’
X-bit = ‘1’
SIDLE
Send DS3 Idle Code
This bit enables transmission of the DS3 idle code (’1010’ between
overhead bits, X-bits all ‘1’s, C-bits all ‘0’s).
0
1
Normal operation.
Send DS3 idle code.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
SAISA
Send AIS in DS3 output and on DS3 loop)
This bit enables transmission of AIS on the DS3 output. If the DS3 is
additionally switched to local DS3 loopback mode the DS3 signal
including AIS is mirrored to the receiver. The AIS code transmitted
depends on D3TCFG.AISC.
0
1
Normal operation.
Enable transmission of AIS.
SAIS
Send AIS at DS3 output
This bit enables transmission of AIS on the DS3 output. If the DS3 signal
is switched into local DS3 loopback mode the DS3 signal without AIS
code is mirrored to the DS3 receiver. The AIS code transmitted depends
on D3TCFG.AISC.
0
1
Normal operation.
Enable transmission of AIS.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
D3TLPB
DS3 Transmit Remote DS2 Loopback Register
Access
: read/write
Address
: 190H (PCI), 48H (Local bus)
: 0000H
Reset Value
15
6
0
0
0
0
0
0
0
0
0
0
LPB(6:0)
LPB
Remote DS2 Loopback
Setting LPB(x) enables the remote DS2 loopback of tributary x. In this
mode the demultiplexed DS2 tributary is internally looped and
multiplexed into the outgoing DS3 signal.
0
1
Normal operation.
Enable remote DS2 loopback of tributary x.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
D3TLPC
DS3 Transmit Loopback Code Insertion Register
Access
: read/write
Address
: 194H (PCI), 4AH (Local bus)
: 0000H
Reset Value
15
6
0
0
0
0
0
0
0
0
0
0
LPC(6:0)
LPC
Send Loopback
Setting LPC(x) enables transmission of the loopback code in tributary x
of the DS3 signal. The loopback code inserted depends on
D3TCFG.LPC.
0
1
Normal operation.
Enable transmission of loopback code in tributary x.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
D3TAIS
DS3 Transmit AIS Insertion Register
Access
: read/write
Address
: 198H (PCI), 4CH (Local bus)
: 0000H
Reset Value
15
7
6
0
0
0
0
0
0
0
0
0
AISE
AIS(6:0)
AISE
AIS Error Insertion
Toggling this bit inserts one ‘0’ in all DS3 tributaries which transmit AIS.
Send DS2 Alarm Indication Signal
AIS
Setting AIS(x) enables insertion of the DS2 alarm indication signal in the
outgoing tributary x of the DS3 signal. AIS is an all ’1’ signal.
0
1
Normal operation
Enable transmission of AIS in tributary x.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
D3TFINS
DS3 Transmit Fault Insertion Control Register
Access
: read/write
Address
: 19CH (PCI), 4EH (Local bus)
: 0000H
Reset Value
15
3
0
0
0
0
0
0
0
0
0
0
0
0
0
FINSC(3:0)
FINSC
Fault Insertion Code.
Fault insertion is service affecting and is intended for testing only. Codes
are not self clearing, i.e. errors are continuously generated as indicated
until bit cleared. A single FEBE, P, CP, or code violation is guaranteed
to be inserted if the respective code is written and then immediately
cleared.
0
1
2
3
4
Normal operation (no fault insertion)
Insert FEBE event every multiframe (106 µsec).
Insert P-bit errors every 2nd multiframe (212 µsec).
Insert CP-bit errors every 2nd multiframe (212 µsec).
Insert 4 F-bit errors/multiframe (satisfies 3 out of 15 threshold
trigger).
5
6
Insert 5 F-bit errors/multiframe (satisfies 3 out of 7 threshold
trigger).
Insert 3 M-bit errors/multiframe (caution: receiver can frame on
emulator).
7
Force DS3 output to all ‘0’s.
8
Insert B3ZS violation/multiframe (violation of alternate polarity
rule).
9
Insert 3 zero string/multiframe (B3ZS code word suppressed)
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
D3TTUC
DS3 Transmit Test Unit Control Register
Access
: read/write
Address
: 1A0H (PCI), 50H (Local bus)
: 0000H
Reset Value
15
7
6
4
3
2
1
0
0
0
0
0
0
0
0
0
EN
TUDS2(2:0)
TUDS1(1:0)
TUIM
EN
Enable Test Unit Insertion
Setting this bit enables insertion of the test unit data.
0
1
Normal operation
Enable insertion of test unit data.
TUDS2
TUDS1
TUIM
Test Unit DS2 Group
This bit field selects the DS2 group the test unit is attached to. Only valid
if TUIM is 10B, 01B or 00B.
0..6 Selects DS2 group 0..6.
Test Unit DS1 Tributary
This bit field selects the DS1 tributary the test unit is attached to. Only
valid if TUIM is 00B. The DS2 group is selected via TUDS2.
0..3 DS1/E1 tributary
Bit Error Rate Test Unit (TU) Insertion Mode
This bit field selects the interface the test unit is attached to.
00B
01B
10B
11B
Insert test stream into DS1/E1 tributary (unframed)
Insert test stream into DS2 tributary (unframed, bypass M12)
Insert test stream into DS2 payload (framed)
Insert test stream into DS3 payload (framed)
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
D3TSDL
DS3 Transmit Spare Data Link Register
Access
: read/write
Address
: 1A4H (PCI), 52H (Local bus)
: 01FFH
Reset Value
15
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
DL77 DL75 DL73 DL67 DL65 DL63 DL27 DL25 DL23
Multiframe buffer for spare DL bits transmitted in blocks 3, 5, and 7 of subframes 2, 6,
and 7. If enabled, the M13 will generate an interrupt every multiframe to request a refresh
of this register. The software must write these registers within 106 µsec to avoid an
underrun.
DL(S)(B)
Overhead bit for block B of subframe S
These bits store the DL bits to be transmitted in blocks 3, 5, and 7 of
subframes 2, 6, and 7. If enabled, the M13 will generate an interrupt
every multiframe to request a refresh of this register. The software must
write these registers within 106 µsec to avoid an underrun.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
D3RCFG
DS3 Receive Configuration Register
Access
: read/write
Address
: 1C0H (PCI), 60H (Local bus)
: 0000H
Reset Value
15
11
10
9
8
6
5
4
3
2
1
0
CVM
0
0
0
IVM STTM ECM FEBM
0
AISX MFM MDIS FFM IRCK IRD URD
Note: M13 mode, Full payload mode, loopback code, and AIS mode are controlled by
bits CBP, FPL, LPC, and AISC in register DS3 transmit configuration register
D3TCFG.
CVM
B3ZS Code Word (“00V” or “10V” Acceptance Condition)
This bit selects the B3ZS violations alternate polarity to maintain line
balance.
0
Convert all B3ZS codeword patterns to “000” regardless of
polarity.
1
Convert codeword only if alternate violation polarity rule is
satisfied.
IVM
Interrupt Vector Mode
This bit selects the interrupt vector mode.
0
Interrupt vector flags are set when corresponding condition has
changed.
1
Interrupt vector flags contain actual status of condition.
STTM
Select Transmit Tributary Monitoring for receive test unit
This bit selects the T1/E1 tributary observed by the test unit receiver.
The test unit can be connected to the upstream T1/E1 tributary (T1/E1
tributary going towards the DS3 interface) or to the downstream T1/E1
tributary (T1/E1 tributary coming from the DS3 interface).
0
1
Monitor downstream T1/E1 tributary.
Monitor upstream T1/E1 tributary.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
ECM
Error Counter Mode
DS3 errors are counted in background and copied to foreground (error
counter registers) when condition selected via ECM is met.
0
Counter values are copied to foreground when copy command is
executed. See also register DS3COM.
1
The counter values are copied to the foreground register in one
second intervals. At the same time the background registers are
reset to zero. This operation is synchronous with the periodic one
second interrupt which alerts software to read the register.
FEBM
Far End Block Error (FEBE) Mode
This bit selects the event which leads to FEBE indication. It is available
in C-bit parity mode only.
0
1
Receive multiframe parity error.
Receive multiframe parity error or framing error.
AISX
MFM
AIS X-bit Check Disable
This bit disables checking of the X-bit for AIS and idle detection.
0
1
Check X-bit.
Disable check of X-bit.
Multiframe Framing Mode
This bit selects the M-bit error condition which triggers the DS3 framer to
start a new frame search. To enable reframing in case of M-bit errors
MDIS must be set to ‘0’.
0
Start new F-frame search if M-bit errors are detected in two out
of four consecutive M-frames.
1
Start new F-frame search if M-bit errors are detected in three out
of four consecutive M-frames.
MDIS
Multiframe Reframe Disable
This bit disables reframing due to M-bit errors.
0
1
Enable reframe due to M-bit errors.
Disable reframe due to M-bit errors.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
FFM
F Framing Mode
This bit selects the F-bit error condition which triggers the DS3 framer to
start a new frame search.
0
A new frame search is started when 3 out of 8 contiguous F-bits
are in error.
1
A new frame search is started when 3 out of 16 contiguous F-bits
are in error.
IRCK
IRD
Invert Receive Clock
This bit sets the clock edge for data sampling.
0
1
Sample data on the rising edge of receive clock.
Sample data on the falling edge of receive clock.
Invert Receive Data
This bit enables inversion of receive data.
0
1
Receive data is logic high (not inverted).
Receive data is logic low (inverted).
URD
Unipolar Receive Data
This bit sets the port mode to dual-rail mode or unipolar mode.
0
1
B3ZS (dual rail data input)
Unipolar mode (single rail data input)
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
D3RCOM
DS3 Receive Command Register
Access
: read/write
Address
: 1C4H (PCI), 62H (Local bus)
: 0000H
Reset Value
15
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
C3NC C3C CNCA CCA FRS
C3NC
Copy DS3 Error Counters
Values of DS3 background registers are copied to foreground.
Background registers are NOT cleared. Command is self clearing and
completes before next register access is possible i.e. software can write
command and then immediately read the counters without starting a
delay timer.
Note: Usage of this function in not recommend in ’One Second’ error
counter mode (D3RCFG.ECM = ‘1’).
0
1
No operation.
Copy background counters to foreground.
C3C
Copy and Clear DS3 Error Counters
Values of DS3 background registers are copied to foreground.
Background registers are cleared. Command is self clearing and
completes before next register access is possible i.e. software can write
command and then immediately read the counters without starting a
delay timer.
0
1
No operation.
Copy background counters to foreground. Clear background
counters.
Note: Usage of this function in not recommend in ’One Second’ error
counter mode (D3RCFG.ECM = ‘1’).
CCNA
Copy Error Counters
Only valid for counters which are not operating in ‘One Second’ error
counter mode. Values of DS2 and DS3 background registers are copied
to foreground. Background registers are NOT cleared. Command is self
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
clearing and completes before next register access is possible i.e.
software can write command and then immediately read the counters
without starting a delay timer.
0
1
No operation.
Copy background counters to foreground.
CCA
Copy and Clear DS2/DS3 Error Counters
Only valid for counters which are not operating in ‘One Second’ error
counter mode. Values of DS2 and DS3 background registers are copied
to foreground. Background registers are cleared. Command is self
clearing and completes before next register access is possible i.e.
software can write command and then immediately read the counters
without starting a delay timer.
0
1
No operation.
Copy background counters to foreground. Clear background
counters.
FRS
Force Resynchronization
This bit enables a new frame search on the DS3 input. The command is
self clearing after frame search has begun.
0
1
Normal operation.
Force new frame search.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
D3RIMSK
DS3 Receive Interrupt Mask Register
Access
: read/write
Address
: 1C8H (PCI), 64H (Local bus)
: 1FFFH
Reset Value
15
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
CLKS RSDL TSDL LPCS SEC
N
AIC XBIT IDLES AISS REDS LOSS FAS
r
This register provides the interrupt mask for DS3 status interrupts and DS3 loopback
code interrupts. Generation of an interrupt vector itself does not necessarily result in
assertion of the interrupt pin. For description of interrupt concept and interrupt vectors
see "Layer One Interrupts" on page 136.
The following definition applies:
1
0
The corresponding interrupt vector will not be generated by the device.
The corresponding interrupt vector will be generated.
RSDL
TSDL
LPCS
SEC
Mask ’Receive Spare Data Link Transfer Buffer Full’
Mask ’Transmit Spare Data Link Transfer Buffer Empty’
Mask ’Loopback Code Status’ (flagged in D3RLPCS)
Mask ’1 Second Interrupt’
CLKS
Nr
Mask ’DS3 Clock Status’
Mask ’Nr-bit Image’ (C-bit parity mode only)
Mask ’AIC-bit Image’ (C-bit parity mode)
Mask ’X-bit Image’
AIC
XBIT
IDLES
AISS
REDS
LOSS
FAS
Mask ’DS3 Idle Signal State’
Mask ’DS3 Alarm Indication Signal State’
Mask ’DS3 Red Alarm State’
Mask ’DS3 Input Signal State’
Mask ’Frame Alignment State’
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
D3RESIM
DS3 Receive Error Simulation Register
Access
: read/write
Address
: 1CCH (PCI), 66H (Local bus)
: 0000H
Reset Value
15
4
2
0
0
0
0
0
0
0
0
0
0
0
0
FTMR
0
ESIMC(2:0)
FTMR
Fast Timer
This bit enables alarm timer test function (manufacturing test only).
0
1
Normal Operation
Test Operation
DS3 RED/AIS/Idle timer period reduced by 56.
DS2 READ/AIS timer period reduced by 24.
Second interrupt period reduced to 140 µsec
ESIMC
Error Simulation Code
This bit enables error simulation. During error simulation the device
generates error interrupts and error status messages. Nevertheless the
service is not affected.
0
1
2
3
4
5
6
7
Normal operation (no error simulation).
Simulate one F-bit error/multiframe (106 µsec).
Simulate M-bit error in every other multiframe.
Simulate FEBE event/multiframe (106 µsec).
Simulate P/CP event/multiframe (106 µsec).
Simulate Loss of DS3 input (all zeros).
Simulate B3ZS code violations.
Simulate Loss of Receive Clock
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
D3RTUC
DS3 Receive Test Unit Control Register
Access
: read/write
Address
: 1D0H (PCI), 68H (Local bus)
: 0000H
Reset Value
15
7
6
4
3
2
1
0
0
0
0
0
0
0
0
0
EN
TUDS2(2:0)
TUDS1(1:0)
TURM
EN
Enable Test Unit Receive Clock
This bit enables the receive clock of the test unit. The clock speed is
dependent on the selected test mode.
0
1
Receive clock disabled.
Receive clock enabled.
TUDS2
TUDS1
TURM
Test Unit DS2 Group
This bit field selects the DS2 group the test unit is attached to. Only valid
if TURM is 10B, 01B, or 00B.
0..6 Selects DS2 group 0..6.
Test Unit DS1/E1 Tributary
This bit field selects the DS1/E1 tributary the test unit is attached to. Only
valid if TURM is 00B. The DS2 group is selected via TUDS2.
0..3 DS1/E1 tributary
Test Unit Receive Mode
This bit field selects the interface the test unit is attached to.
00B
01B
10B
11B
DS1/E1 tributary (unframed)
DS2 tributary (unframed, bypass M12)
DS2 payload (framed)
DS3 payload (framed)
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PEF 20256M E
Register Description
D3RSTAT
DS3 Receive Status Register
Access
: read
Address
: 1D4H (PCI), 6AH (Local bus)
: 0841H
Reset Value
15
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LRXC LTXC RSDL TSDL LPCD SEC
N
AIC XBIT IDLES AISS REDS LOSS COFA FAS
r
AICC
Each bit in the DS3 framer receive status register declares a specific condition
dependent on the selected modes. The following convention applies to the individual
bits:
0
1
The named status is not or no longer existing.
The named status is currently effective.
Except for COFA every bit can be used to generate a DS3 interrupt vector. See also
register D3RIMSK which describes how to enable/disable interrupt vector generation
and refer to the description of DS3 framer interrupts on page "Layer One Interrupts" on
page 136.
LRXC
LTXC
RSDL
Loss of Receive DS3 Clock
This bit indicates loss of DS3 receive clock.
Loss of Transmit DS3 Clock
This bit indicates loss of DS3 transmit clock.
Receive Spare Data Link Buffer Full
This bit indicates that the spare data link receive buffer (register
D3RSDL) is full.
TSDL
LPCD
Transmit Spare Data Link Buffer Empty
This bit indicates that the spare data link transmit buffer (register
D3TSDL) is empty.
Loopback Code Detected
This bit indicates a changes in register D3RLPCS.
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PEF 20256M E
Register Description
SEC
1 Second Flag
This bit toggles every second synchronously with the one second
interrupt. It can be used by software to synchronize 1 second events
when the ’One second interrupt’ vector is masked.
Nr/AICC
Nr-bit Image (C-bit parity format only)
This bit contains an image of the DS3 frame overhead bit in block 5 of
subframe 1. It is updated only if its state persists for 3 multiframes and
DS3 frame is aligned.
AIC-bit changed (M13 asynchronous format)
This bit indicates a change of the AIC-bit (first C-bit of the first subframe)
since the last read of this register.
AIC
AIC bit Image (DS3 frame overhead bit in block 3 of subframe 1)
This bit contains an image of the DS3 frame overhead bit in block 3 of
subframe 1. It is updated only if its state persists for 3 multiframes and
DS3 frame is aligned.
XBIT
X bit Image (DS3 frame overhead bit in block 1 of subframes 1 and 2)
This bit contains an image of the DS3 frame overhead bit in block 1 of
subframes 1 and 2. It is updated only if both bits in a DS3 multiframe
have the same value, its state persists for at least 3 multiframes and
when the DS3 framer is in synchronous state.
IDLES
Idle State
This bit indicates that the idle pattern (framed ...1100... with C-bits=’0’ in
subframe 3 and X-bits=’1’) was persistent as per alarm timing
parameters defined in register D3RAP. Idle is considered active in a
multiframe when fewer than 15 errors are detected. At 10-3 error rates, 5
errors per multiframe are typical. The exact time necessary to change
the flag could be greater if the FAS flag is not constant. The frame
alignment state is integrated by incrementing or decrementing a counter
at the end of each multiframe when the FAS flag is set or cleared
respectively.
AISS
AIS Slarm State.
This bit indicates the AIS alarm state. AIS can be a framed ’..1010..’
pattern with C-bits=’0’ and X-bits=’1’ or an unframed all ‘1’ pattern. This
is determined by D3TCFG.AISC. AIS is considered active in a
multiframe when fewer than 15 errors are detected and is declared when
it was persistent as per alarm timing parameters defined in register
D3RAP. At 10-3 error rates, 5 errors per multiframe are typical. The exact
time necessary to change the flag could be greater if the FAS flag is not
constant. The frame alignment state is integrated by incrementing or
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PEF 20256M E
Register Description
decrementing a counter at the end of each multiframe when the FAS flag
is set or cleared respectively.
REDS
Red Slarm State (loss of frame alignment)
This bit indicates that red alarm was persistent as per alarm timing
parameter defined in register D3RAP. The red alarm flag nominally
changes when loss of frame alignment condition persists for either 32 or
128 multiframes. This is determined by bit D3RCFG.SAIT. The exact
time necessary to change the flag could be greater if the FAS flag is not
constant. The frame alignment state is integrated by incrementing or
decrementing a counter at the end of each multiframe when the FAS flag
set or cleared respectively.
LOSS
Loss of DS3 Input Signal
This bit indicates that the received DS3 bit stream contained at least 175
consecutive ‘0’s. It is deasserted when 59 ‘1’ bits are detected in 175
clocks (1/3 density). Following removal of LOS, a 10 msec guard timer
is started. If a new LOS occurs, the release condition is extended so that
the 1/3 density condition must persist for at least 10 msec. This prevents
chatter and excessive interrupts.
COFA
FAS
Change of Frame Alignment.
This bit indicates a change of frame alignment event. It is set when the
DS3 framer found a new frame alignment and when the new frame
position differs from the expected frame position.
DS3 Frame Alignment State
This bit indicates that the DS3 framer is not aligned.
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PEF 20256M E
Register Description
D3RLPCS
DS3 Receive Loopback Code Status Register
Access
: read
Address
: 1D8H (PCI), 6CH (Local bus)
: 0000H
Reset Value
15
6
0
0
0
0
0
0
0
0
0
0
LPCD(6:0)
LPCD
Loopback Detected
LPCD(x) indicates that a loopback request was received. A loopback
request for tributary x is indicated by inverting one of the 3 C-bits of the
xth subframe. The C-bit is determined by D3TCFG.LPC. A command
state change must persist for 5 contiguous multiframes before it will be
reported. This function is available in M13 asynchronous mode only.
0
1
No loopback code being received
Loopback code being received
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PEF 20256M E
Register Description
D3RSDL
DS3 Receive Spare Data Link Register
Access
: read
Address
: 1DCH (PCI), 6EH (Local bus)
: 01FFH
Reset Value
15
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
DL77 DL75 DL73 DL67 DL65 DL63 DL27 DL25 DL23
DL(S)(B)
Overhead Bit for Block B of Subframe S
These bits buffer the spare DL bits received in blocks 3, 5, and 7 of
subframes 2, 6, and 7. If enabled, the M13 will generate an interrupt
every multiframe to synchronize reading of this register. The register
must be read within 106 µsec to avoid an overrun.
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PEF 20256M E
Register Description
D3RCVE
DS3 Receive B3ZS Code Violation Error Counter
Access
: read/write
Address
: 1E0H (PCI), 70H (Local bus)
: 0000H
Reset Value
15
0
CVE(15:0)
CVE(15:0)
B3ZS Code Violation Errors
Error counter mode (Clear on Read or Errored Second) depends on
register D3RCFG.ECM.
Count of B3ZS Code Violation errors. The error counter will not be
incremented during asynchronous state.
D3RFEC
DS3 Receive Framing Bit Error Counter
Access
: read/write
Address
: 1E4H (PCI), 72H (Local bus)
: 0000H
Reset Value
15
0
FEC(15:0)
FEC(15:0)
Framing Bit Error Counter
Error counter mode (Clear on Read or Errored Second) depends on
register D3RCFG.ECM.
Count of F-bit and M-bit errors. Errors are not counted in out of frame
state.
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PEF 20256M E
Register Description
D3RPEC
DS3 Receive Parity Error Counter
Access
: read/write
Address
: 1E8H (PCI), 74H (Local bus)
: 0000H
Reset Value
15
0
PE(15:0)
PE(15:0)
Parity Bit Error Counter
Error counter mode (Clear on Read or Errored Second) depends on
register D3RCFG.ECM.
Count of parity errors (P-bits in DS3 overhead bits). The P-bit is
duplicated in the DS3 frame structure but only one error is counted per
multiframe. Errors are not counted in out of frame state.
D3RCPEC
DS3 Receive Path Parity Error Counter
Access
: read/write
Address
: 1ECH (PCI), 76H (Local bus)
: 0000H
Reset Value
15
0
CPE(15:0)
CPE(15:0)
Path Parity Error Counter
Error counter mode (Clear on Read or Errored Second) depends on
register D3RCFG.ECM.
Count of path parity errors (CP bits in DS3 C-bit parity overhead bits).
CP-bits are triplicated in the DS3 frame structure but only single error
maximum is counted per multiframe. Errors are not counted in out of
frame state.
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PEF 20256M E
Register Description
D3RFEBEC
DS3 Receive FEBE Error Counter
Access
: read/write
Address
: 1F0H (PCI), 78H (Local bus)
: 0000H
Reset Value
15
0
FEBE(15:0)
FEBEC(15:0) FEBE error events
Error counter mode (Clear on Read or Errored Second) depends on
register D3RCFG.ECM.
This register counts the occurence of a received ‘not all ‘1’s’. FEBE-bits
are triplicated in the DS3 frame structure but only one single error
maximum is counted per multiframe. Errors are not counted in out of
frame state.
D3REXZ
DS3 Receive Excessive Zeroes Counter
Access
: read/write
Address
: 1F4H (PCI), 7AH (Local bus)
: 0000H
Reset Value
15
0
EXZ(15:0)
EXZ(15:0)
Exzessive Zeroes
Error counter mode (Clear on Read or Errored Second) depends on
register D3RCFG.ECM.
Violations are 3 zero strings. The error counter will not be incremented
during asynchronous state.
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PEF 20256M E
Register Description
D3RAP
DS3 Alarm Parameters
Access
: read/write
Address
: 1F8H (PCI), 7CH (Local bus)
: 0000H
Reset Value
15
7
5
0
0
0
0
0
0
0
0
0
AIS
0
CV(5:0)
AIS
AIS criteria
This bits sets the error rate for AIS detection. Declaration of AIS depends
on value defined in bit field CV.
0
AIS is recognized when the alarm indication signal is received
with less than 8 errors per multiframe.
1
AIS is recognized when the alarm indication signal is received
with less than 15 errors per multiframe.
CV
Counter Value
This bit specifies the number of frames when the MUNICH256FM
declares AIS, RED or Idle.
0..63 Counter Value.
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PEB 20256M E
PEF 20256M E
Register Description
8.2.3.2 DS2 Control and Status Registers
D2TSEL
DS2 Transmit Group Select Register
Access
: read/write
Address
: 200H (PCI), 80H (Local bus)
: 0000H
Reset Value
15
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GN(2:0)
Note: This register is an indirect access register, which must be programmed before
accessing the register DS2 transmit registers.
GN
Group Number
This bit field selects the DS2 group, which can be accessed via the DS2
transmit registers.
0..6 Group Number.
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PEF 20256M E
Register Description
D2TCFG
DS2 Transmit Configuration Register
Access
: read/write
Address
: 204H (PCI), 82H (Local bus)
: 0000H
Reset Value
15
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LPC(1:0)
E1
LPC
Loopback Code
This bit selects the C-bit which will be inverted when loopback requests
are transmitted.
00
01
10
Invert 1st C-bit.
Invert 2nd C-bit.
Invert 3rd C-bit.
E1
G.747 Select
This bit selects the operation mode of the low speed multiplexer.
0
1
Select M12 mode (4 DS1 into DS2).
Select ITU-T G.747 mode (3 E1 into DS2).
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PEF 20256M E
Register Description
D2TCOM
DS2 Transmit Command Register
Access
: read/write
Address
: 208H (PCI), 84H (Local bus)
: 0000H
Reset Value
15
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
FINSC(1:0) SRA RES
FINSC
Fault Insertion Code
This bit enables transmission of faults for testing purposes.
0
1
2
3
No fault insertion.
Insert F-bit errors at low rate (2 out of 5 F-bits).
Insert F-bit errors at high rate (2 out of 4 F-bits).
Insert M-bit framing bit error (DS1 mode) or P-bit error (ITU-T
G.747)
SRA
Set Remote Alarm
This bit enables transmission of the DS3 remote alarm. In DS1 modes
remote alarm is transmitted in subframe 4, block 1 overhead bit and in
ITU-T G.747 remote alarm is transmitted in bit 2 of “set II”.
0
1
Normal operation.
Enable transmission of remote alarm.
RES
ITU-T G.747 Reserved Bit
This bit sets the value to be transmitted in the reserved bit of
ITU-T G.747 format.
0
1
Transmit reserved bit as ’0’.
Transmit reserved bit as ’1’.
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PEF 20256M E
Register Description
D2TILPC
DS2 Transmit E1/T1 Remote Loopback/Loopback Code InsertionRegister
Access
: read/write
Address
: 20CH (PCI), 86H (Local bus)
: 0000H
Reset Value
15
3
0
0
0
0
0
0
0
0
0
0
0
0
0
LPC(3:0)
LPC
Send Loopback Code for Tributary N
Setting LPC(x) enables transmission of the loopback code in tributary x.
The loopback code inserted is specified in D2TCFG.LPC.
0
1
Disable transmission of loopback code.
Enable transmission of loopback code.
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PEF 20256M E
Register Description
D2RSEL
DS2 Receive Group Select Register
Access
: read/write
Address
: 220H (PCI), 90H (Local bus)
: 0000H
Reset Value
15
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GN(2:0)
Note: This register is an indirect access register, which must be programmed before
accessing the register DS2 transmit registers.
GN
Group Number
This bit field selects the DS2 group number, which can be accessed via
the DS2 receive registers.
0..6 Group Number.
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PEF 20256M E
Register Description
D2RCFG
DS2 Receive Configuration Register
Access
: read/write
Address
: 224H (PCI), 92H (Local bus)
: 0000H
Reset Value
15
3
1
0
0
0
0
0
0
0
0
0
0
0
0
0
ECM
0
MFM FFM
Note: ITU-T G.747 mapping and loopback codes are controlled by bits E1 and LPC in
the DS3 transmit configuration register D2TCFG.
E1/T1 and loopback codes are controlled by E1 and LPC fields of the D2TCFG register.
ECM
Error Counter Mode
DS2 errors are counted in background and copied to foreground (error
counter registers) when condition selected via ECM is met.
0
Counter values are copied to foreground when copy command is
executed. See also register DS3COM.
1
The counter values are copied to the foreground register in one
second intervals. At the same time the background registers are
reset to zero. This operation is synchronous with the periodic one
second interrupt which alerts software to read the register.
MFM
FFM
Multiframe Framing Mode
This bit selects the M-bit error condition which triggers the DS2 framer to
start a new frame search. It is valid in DS1 mode only.
0
F-frame search started if 3 contiguous multiframes have M-bit
errors.
1
Inhibit new F-frame search due to M-bit errors.
F-Framing Mode
This bit selects the F-bit error condition which triggers the DS2 framer to
start a new frame search.
0
A new frame search is started when 2 out of 4 contiguous F-bits
are in error.
1
A new frame search is started when 2 out of 5 contiguous F-bits
are in error.
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PEF 20256M E
Register Description
D2RCOM
DS2 Receive Command Register
Access
: read/write
Address
: 228H (PCI), 94H (Local bus)
: 0000H
Reset Value
15
6
4
1
0
0
0
0
0
0
0
0
0
0
ESIMC(2:0)
0
0
C2NC C2C
ESIMC
Error Simulation Code
This bit field enables error simulation. During error simulation the device
generates error interrupts and error status messages. Nevertheless the
service is not affected.
0
1
2
Normal operation (no error simulation)
Simulate 2 receive F-bit errors/multiframe (186 µsec)
Simulate
2 receive M-bit errors/multiframe (186 µsec) (DS-1 mode)
Receive parity error/multiframe (133 µsec) (ITU-T G.747 mode)
3
4
5
6
Simulate remote alarm
Simulate loss of frame (RED alarm timer)
Simulate AIS (AIS alarm timer)
Simulate receive loop command
C2NC
Copy DS2 Error Counters
Only valid when D2RCFG.ECM is set to ‘0’. Values of DS2 background
registers are copied to foreground. Background registers are NOT
cleared. Command is self clearing and completes before next register
access is possible i.e. software can write command and then
immediately read the counters without starting a delay timer.
0
1
No operation.
Copy background counters to foreground.
C2C
Copy and Clear DS2 Error Counters
Only valid when D2RCFG.ECM is set to ‘0’. Values of DS2 background
registers are copied to foreground. Background registers are cleared.
Command is self clearing and completes before next register access is
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PEF 20256M E
Register Description
possible i.e. software can write command and then immediately read the
counters without starting a delay timer.
0
1
No operation.
Copy background counters to foreground. Clear background
counters.
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PEF 20256M E
Register Description
D2RIMSK
DS2 Receive Interrupt Mask Register
Access
: read/write
Address
: 22CH (PCI), 96H (Local bus)
: 003FH
Reset Value
15
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
LPCS AISS REDS RES RAS FAS
This register provides the interrupt mask for DS2 status interrupts and DS2 loopback
code interrupts. Generation of an interrupt vector itself does not necessarily result in
assertion of the interrupt pin. For description of interrupt concept and interrupt vectors
see "Layer One Interrupts" on page 136.
The following definition applies:
1
0
The corresponding interrupt vector will not be generated by the device.
The corresponding interrupt vector will be generated.
LPCS
AISS
REDS
RES
Mask ’Loopback Code Status’ (flagged in D2RLPCS)
Mask ’AIS State’
Mask ’Red Alarm State’
Mask ’Reserved Bit’
RAS
Mask ’DS2 Remote Alarm State’
Mask ’DS2 Frame Alignment State’
FAS
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PEF 20256M E
Register Description
D2RSTAT
DS2 Receive Status Register
Access
: read
Address
: 230H (PCI), 98H (Local bus)
: 0001H
Reset Value
15
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
AISS REDS RES RAS COFA FAS
Each bit in the DS2 framer receive status register declares a specific condition
dependent on the selected modes. The following convention applies to the individual
bits:
0
1
The named status is not or no longer existing.
The named status is currently effective.
The change of status bit can also be used to generate a DS2 interrupt vector. See also
register D2RIMSK which describes how to enable/disable interrupt vector generation
and refer to the description of DS2 framer interrupts on page "Layer One Interrupts" on
page 136.
AISS
DS2 AIS Alarm State (unframed all ‘1’s pattern)
AIS is considered valid in a multiframe when fewer than 5 zeros are
detected. At 10-3 error rates, 1 zero per multiframe is typical. A valid DS2
signal without any bit errors has at least 5 zeros.
The AIS flag nominally changes when the AIS condition is persistent as
per alarm timing parameters defined in register D2RAP. The exact time
necessary to change the flag could be greater in extremely high error
rates. The AIS state is integrated by incrementing or decrementing a
counter at the end of each multiframe depending on the AIS condition
being valid or invalid respectively.
REDS
DS2 Red Alarm State (loss of frame alignment).
The red alarm flag nominally changes when loss of frame alignment
condition is persistent as per alarm timing parameters defined in register
D2RAP. The exact time necessary to change the flag could be greater if
the FAS flag is not constant because the frame alignment state is
integrated by incrementing or decrementing a counter at the end of each
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PEF 20256M E
Register Description
multiframe when the FAS flag set or cleared respectively. Note that the
framer’s verification algorithm is designed to prevent a bouncing FAS
flag.
RES
RRA
Reserved Bit
This bit indicates the status of bit 3 in set II of ITU-T G.747 mode. Is it
updated if the state persists for at least 8 multiframes. Reserved Bit
changes are not reported when the DS2 framer is not aligned.
Remote Alarm
This bit indicates that remote alarm is active. Changes are reported
when they persist for at least 8 multiframes. In DS1 mode changes on
Mx bit are reported, in ITU-T G.747 mode changes of bit 1 of set II are
reported. Changes are not reported when the DS2 framer is not aligned.
COFA
FAS
Change of Frame Alignment.
This bit indicates a change of frame alignment event. It is set when the
DS2 framer found a new frame alignment and when the new frame
position differs from the expected frame position.
Demultiplexer Loss of Frame Alignment
This bit indicates that the DS2 framer is not aligned.
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PEF 20256M E
Register Description
D2RLPCS
DS2 Receive Loopback Code Status Register
Access
: read
Address
: 234H (PCI), 9AH (Local bus)
: 0000H
Reset Value
15
3
0
0
0
0
0
0
0
0
0
0
0
0
0
LPCD(3:0)
LPCD(N)
Loopback Command Detected
LPCD(x) indicates that a loopback request was received. A loopback
request for tributary x is indicated by inverting one of the 3 C-bits of the
xth subframe. The C-bit is determined by D2TCFG.LPC. A command
state change must persist for 5 contiguous multiframes before it will be
reported.
0
1
No loopback code being received.
Loopback code being received.
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PEF 20256M E
Register Description
D2RFEC
DS2 Receive Framing Bit Error Counters
Access
: read/write
Address
: 238H (PCI), 9CH (Local bus)
: 0000H
Reset Value
15
0
FE(15:0)
FE(15:0)
Framing Bit Errors
Error counter mode (Clear on Read or Errored Second) depends on
register D2RCFG.ECM.
For DS1 mode framing bit errors include F-bit and M-bit errors. For G747
mode, individual bits in the Frame Alignment Signal (FAS) are counted.
Errors are not counted in out of frame state.
D2RPEC
DS2 Receive Parity Bit Error Counter (ITU-T G.747)
Access
: read/write
Address
: 23CH (PCI), 9EH (Local bus)
: 0000H
Reset Value
15
0
PE(15:0)
PE(15:0)
Parity Errors in ITU-T G.747 mode
Error counter mode (Clear on Read or Errored Second) depends on
register D2RCFG.ECM. Errors are not counted in out of frame state.
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PEB 20256M E
PEF 20256M E
Register Description
D2RAP
DS2 Receive Alarm Timer Parameters
Access
: read/write
Address
: 240H (PCI), A0H (Local bus)
: 00H
Reset Value
15
7
6
5
0
0
0
0
0
0
0
0
0
AIS CM
CV(5:0)
AIS
AIS criteria
This bits sets the error rate for AIS detection. Declaration of AIS is
specified by bits CM and CV.
ITU-T G.747:
0
AIS condition is recognized when the alarm indication signal is
received with less than 5 errors in each of 2 consecutive
multiframes.
1
AIS condition is recognized when the alarm indication signal is
received with less than 9 errors in each of 2 consecutive
multiframes.
M12 format:
0
AIS condition is recognized when the alarm indication signal is
received with less than 3 errors in 3156 bits.
1
AIS condition is recognized when the alarm indication signal is
received with less than 9 errors in 3156 bits.
CM
Counter Mode
This bit selects the alarm timer mode. If counter mode is set to
multiframes (‘0’) the value in CV determines the number of multiframes
after which the MUNICH256FM declares AIS or RED. When counter
mode is set to ‘½ milliseconds’ (‘1’) the value in CV determines the time
in CV x 0.5 ms after which AIS or RED is declared.
0
1
Multiframes.
½ Milliseconds.
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Register Description
CV
Counter Value
Dependent on bit CM the counter value specifies the number of frames
or the time in multiples of 0.5 milliseconds when AIS or RED is declared,
i.e. setting CV to 20 and CM to ‘1’ sets the alarm integration time to 10
milliseconds.
0..63 Counter Value.
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Register Description
8.2.4
Test Unit Registers
TUTCFG
Test Unit Transmit Configuration Register
Access
: read/write
Address
: 280H (PCI), C0H (Local bus)
: 0000H
Reset Value
15
13
12
8
6
2
1
0
0
0
INV
FBT(4:0)
0
LEN(4:0)
ZS
MD
INV
Invert output
This bit enables inversion of the test unit output. Bit inversion is done
after the zero suppression insertion point.
0
1
No inversion
Invert pattern generator output
FBT
Feedback Tap
This bit field sets the feedback tap in pseudorandom pattern mode.
PRBS shift register input bit 0 is XOR of shift register bits LEN and FBT.
LEN
ZS
Pattern Generator Length
This bit field sets the pattern generator length to 1..32.
Enable Zero Suppression
This bit enables zero suppression where a ’1’ bit is inserted at the output
if the next 14 bits in the shift register are ’0’.
0
1
No zero suppression
Zero suppression.
MD
Generator Mode
This bit selects the generator mode of the test unit to be either PRBS or
fixed pattern mode.
0
1
Pseudorandom Pattern (PRBS)
Fixed Pattern
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Register Description
TUTCOM
Test Unit Transmit Command Register
Access
: write
Address
: 284H (PCI), C2H (Local bus)
: 0000H
Reset Value
15
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
LDER IN1E STOP STRT
Note: All commands are self clearing i.e. user does not have to clear command. The
maximum command rate is limited by clock rate of unit under test and the
associated synchronization process. Write interval should be > 4 transmit clock
periods e.g. 2.6 µs for T1 tributary test or 634 ns for T2 tributary test.
LDER
Load Error Rate Register
This bit loads the value of the error rate register TUTEIR to the test unit
transmitter. The command can be given while the transmitter is running.
0
1
No function.
Copy value of register TUTEIR to transmit clock region.
IN1E
Insert One Error in Output
This bit enables a single error insertion in the next bit after command was
written.
0
1
No function
Single error insertion.
STOP
Stop Pattern Generation.
This bit stops the test unit transmitter. When stopped output becomes
all ’1’.
0
1
No function.
Stop pattern generation.
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Register Description
STRT
Load/Start Transmitter.
This bit starts the test unit transmitter with the parameters defined in
register TUTCFG. In fixed pattern mode the pattern needs to be
programmed via register TUTFP0/1 prior to starting the transmitter.
0
1
No operation.
Load/Start test unit.
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Register Description
TUTEIR
Test Unit Transmit Error Insertion Rate Register
Access
: read/write
Address
: 288H (PCI), C4H (Local bus)
: 0000H
Reset Value
15
3
2
0
0
0
0
0
0
0
0
0
0
0
0
0
MTST
TXER(2:0)
MTST
Manufacturing test.
Must be written to ‘0’ for normal operation.
Transmit Error Insertion Rate.
TXER
This bit field determines the error insertion rate of the test unit
transmitter.
000 No errors
001 10-1 (1 in
010 10-2 (1 in
011 10-3 (1 in
100 10-4 (1 in
101 10-5 (1 in
10)
100)
1 000)
10 000)
100 000)
110 10-6 (1 in 1 000 000)
111 10-7 (1 in 10 000 000)
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Register Description
TUTFP0
Test Unit Transmit Fixed Pattern Low Word
Access
: read/write
Address
: 28CH (PCI), C6H (Local bus)
: 0000H
Reset Value
15
0
FP(15:0)
FP
Fixed Pattern Low Word
See description below.
TUTFP1
Test Unit Transmit Fixed Pattern High Word
Access
: read/write
Address
: 290H (PCI), C8H (Local bus)
: 0000H
Reset Value
15
0
FP(31:15)
FP
Fixed pattern High Word
The 32 bit fixed pattern is distributed over two 16 bit registers and
contains the pattern which is transmitted repetitively from bit
FP(TUTCFG.LEN) down to FP(0) when test unit is operated in fixed
pattern generator mode.
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Register Description
TURCFG
Test Unit Receive Configuration Register
Access
: read/write
Address
: 2A0H (PCI), D0H (Local bus)
: 0000H
Reset Value
15
13
12
8
6
2
1
0
AIM
0
DAS
FBT(4:0)
0
LEN(4:0)
ZS
MD
AIM
Auxiliary Interrupt Mode
This bit field enables the auxiliary interrupt mask AIM of register
TURIMSK. In normal operation and if not masked every status event
generates an interrupt event. In auxiliary interrupt mode an individual
status event generates one interrupt event and further status events of
the same class, i.e. ’Bit Error Detected’, are masked via an internal
mask. This prevents excessive interrupt floods. See register TURIMSK
for further details.
0
1
Normal Operation
Auxiliary Interrupt Mode
DAS
Disable Automatic Synchronization
This bit disables automatic resynchronization in case of high bit error
rates. If automatic resynchronization is enables the receiver
automatically tries to resynchronize to the received test pattern.
0
1
Enable automatic resynchronization.
Disable automatic resynchronization.
FBT
LEN
Feedback Tap
This bit field sets the feedback tap of the test unit synchronizer (receiver)
in pseudorandom pattern mode. Next input to PRBS reference shift
register (bit 0) is XOR of shift register bits LEN and FBT.
Reference shift register length
This bit field sets the length of the receiver’s test pattern register.
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Register Description
ZS
Enable Zero Suppression
This bit enables zero suppression at the test unit receiver. A ’1’ is
expected and inserted at the input if the next 14 bits in the shift register
are set to ’0’.
0
1
No zero suppression.
Enable zero suppression.
MD
Generator Mode
This bit sets the generator mode of the test unit to either PRBS or fixed
pattern.
0
1
Pseudorandom Pattern (PRBS)
Fixed Pattern
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Register Description
TURCOM
Test Unit Receive Command Register
Access
: write
Address
: 2A4H (PCI), D2H (Local bus)
: 0000H
Reset Value
15
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
RDF RDC CAIM STOP STRT
Note: All commands are self clearing i.e. user does not have to clear command. The
maximum command rate is limited by clock rate of unit under test and the
associated synchronization process. Write interval should be > 4 transmit clock
periods e.g. 2.6 µs for T1 tributary test or 634 ns for DS2 tributary test.
RDF
Copy Receiver’s 32 bit Pattern
This bit loads the test units internal receiver pattern to register TURFP in
fixed pattern mode. In synchrones state TURFP will be loaded with the
pattern received. In asynchronous state TURFP with a 32-bit sample of
the last received bit stream.
0
1
No function.
Update register TURFP with synchronizer pattern.
RDC
Copy bit counter and error counter
This bit loads the test units internal bit counter and error counter to
registers TURBC0,1 and TUREC0,1.
0
1
No function.
Copy counter.
CAIM
STRT
Clear Auxiliary Interrupt Masks.
This bit resets the internal auxililiary mask. See TURCFG.AIM.
0
1
no operation
clear auxiliary interrupts
Start Receiver.
This bit loads and starts the test unit receiver with the parameters
defined in register TURCFG.
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Register Description
0
1
No operation.
Load/Start test unit receiver.
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Register Description
TURERMI
Test Unit Receive Error Measurement Interval Register
Access
: read/write
Address
: 2A8H (PCI), D4H (Local bus)
: 0000H
Reset Value
15
3
2
0
0
0
0
0
0
0
0
0
0
0
0
0
TST
RXMI(2:0)
TST
Test Mode
This bit enables measurement interval timer test.
0
1
Normal operation
Auto test of measurement interval function. End of Measurement
interrupt should be asserted after approximately 4250 receive
clock cycles (if enabled). The lower three bits of register FPAT
should be “111”.
RXMI
Receive Error Rate Measurement Interval
This bit field defines the measurement interval in terms of input bits for
measurement of receive bit error rate.
At the end of the measurement window, contents of background error
counter are automatically copied to foreground error counter and reset
for next measurement interval. An interrupt can be generated at the end
of each measurement interval.
000B Max measurement interval of 232-1
001B 103 bits
010B 104 bits
011B 105 bits
100B 106 bits
101B 107 bits
110B 108 bits
111B 109 bits
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Register Description
TURIMSK
Test Unit Receive Interrupt Mask Register
Access
: read/write
Address
: 2ACH (PCI), D6H (Local bus)
: 001FH
Reset Value
15
12
8
4
3
2
1
0
0
0
0
AIM(4:0)
0
0
0
ERXM BED ALL1 LOS SYN
This register provides the interrupt masks for the test unit interrupts. Generation of an
interrupt vector itself does not necessarily result in assertion of the interrupt pin. For
description of interrupt concept and interrupt vectors see "Layer One Interrupts" on page
136.
The following definition applies:
1
0
The corresponding interrupt vector will not be generated by the device.
The corresponding interrupt vector will be generated.
ERXM
BED
Mask ’End of Receive Error Rate Measurement’
Mask ’Bit Error Detected’
ALL1
LOS
Mask ’All ‘1’ Pattern Received’
Mask ’Loss of Signal’
SYN
Mask ’Change in Receiver Synchronization State’
AIM flags have same layout as the above five mask but are internal masks that are set
automatically following the interrupt in the AIM mode. This mask prevents excessive bus
load in error conditions. AIM flags are cleared by the TURCOM.CAIM command. They
are “read only” flags in this register.
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Register Description
TURSTAT
Test Unit Receive Status Register
Access
: read
Address
: 2B0H (PCI), D8H (Local bus)
: 0021H
Reset Value
15
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
INVS LA1 LA0 LOOS EMI LBE A1
A0 OOS
INV
Inverted Pattern
This bit indicates that the received PRBS sequence is inverted.
0
1
Not Inverted.
Inverted.
LA1
Latched ’Input all ’1’’
This bit indicates that the condition ’Input all ’1’’ was active since last
status register read.
LA0
Latched ’Input all ’0’’
This bit indicates that the condition ’Input all ’0’’ was active since last
status register read.
LOOS
EMI
Latched Out of Synchronization
This bit indicates that the receiver was out of synchronization since last
status register read.
End of Measurement Interval
This bit indicates that the end of the measurement internal was reached
since last read of error counter or that command TURCMD.RDC was
given. The results of the bit error rate test are available in register
TURBC0,1 and TUREC0,1. This flag is cleared when the error counter
is read. Counters will not be overwritten while EMI is ’1’.
LBE
A1
Latched Bit Error Detected Flag
This bit indicates that at least ’1’ one bit error occurred since last read of
this register. It is cleared by status register read.
Input all ‘1’s
This bit indicates that the input contained all ’1’ during the last 32 bits. It
is reset if at least one ’0’ occurs in 32 bits.
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Register Description
A0
Input all ‘0’s
This bit indicates that the input contained all ’0’ during the last 32 bits. It
is reset if at least one ’1’ occurs in 32 bits.
OOS
Receiver Out of Synchronization
This bit indicates the status of the test unit synchronizer.
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Register Description
TURBC0
Test Unit Receive Bit Counter Low Word
Access
: read
Address
: 2B4H (PCI), DAH (Local bus)
: 0000H
Reset Value
15
0
BC(15:0)
BC(31:0)
Bit Counter
See description below.
TURBC1
Test Unit Receive Bit Counter High Word
Access
: read
Address
: 2B8H (PCI), DCH (Local bus)
: 0000H
Reset Value
15
0
BC(31:16)
BC(31:0)
Bit Counter
BC is a 32 bit counter which is split between two 16 bits registers. It
counts receive clock slots when the receiver is enabled. Bits are counted
in a background register which is not directly readable. The values are
transferred to the two 16 bit foreground (readable) registers and cleared
in one of the two ways:
1. Assert command TURCOM.RDC.
2. Automatically at end of measurement interval.
The background register is transferred to the foreground register and
cleared in the same way as the bit error counter (see previous section).
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Register Description
When the error registers are read in response to the “End of
Measurement Interval” interrupt vector , reading this register is not
necessary because the measurement interval would be known.
However the user could assert command TURCOM.RDC to terminate
the measurement interval early and transfer the current bit error count
and bit count to the foreground registers (polling mode).
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Register Description
TUREC0
Test Unit Receive Error Counter Low Word
Access
: read
Address
: 2BCH (PCI), DEH (Local bus)
: 0000H
Reset Value
15
0
EC(15:0)
EC(31:0)
Error Counter
See description below.
TUREC1
Test Unit Receive Error Counter High Word
Access
: read
Address
: 2C0H (PCI), E0H (Local bus)
: 0000H
Reset Value
15
0
EC(31:16)
EC(31:0)
Error Counter
This 32 bit counter counts receive errors detected when receiver is
enabled and in synchronized state. When the ’Bit Error Detected’
interrupt is enabled, it will be asserted and then automatically masked
when this counter is incremented.
Errors are counted in a background register (not directly readable) until:
1. The user asserts command TURCOM.RDC.
2. The end of measurement interval is reached and the last result was
read.
In both cases the value of the background register is copied to
TUREC.EC and the measured values are accessible. An ’End of
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Register Description
Receive Error Rate Measurement’ interrupt vector is optionally
generated.
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Register Description
TURFP0
Test Unit Receive Fixed Pattern Low Word
Access
: read
Address
: 2C4H (PCI), E2H (Local bus)
: 0000H
Reset Value
15
0
FP(15:0)
FP(31:0)
Fixed pattern
See description below.
TURFP1
Test Unit Receive Fixed Pattern High Word
Access
: read
Address
: 2C8H (PCI), E4H (Local bus)
: 0000H
Reset Value
15
0
FP(31:16)
FP(31:0)
Fixed Pattern
This 32 bit field is distributed over two 16 bit registers and is used in the
fixed pattern mode (TURCFG.MD=’1’). The TURCOM.RDF command
will copy the current state of the receiver’s 32 bit pattern generator to this
register. If the receiver is synchronized, bits FP(TURCFG.LEN:0)
contain the fixed pattern being received. Bit 0 is the most recently
received. If not synchronized, the register contains a 32 bit sample of
input data.
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Register Description
8.2.5
Transmit Framer Register
TCMDR
T1/E1 Transmit Command Register
Access
: read/write
: 00H
Address
Reset Value
: 0000H
15
5
4
3
2
1
0
XPRBS
XAIS XRA XLU XLD
0
0
0
0
0
0
0
0
0
0
XAP
XAP
Transmit Auxiliary Pattern
This bit enables transmission of auxiliary pattern in the outgoing bit
stream. The auxiliary pattern is defined as a continuous pattern of ‘01’.
0
1
Disable transmission of auxiliary pattern.
Enable transmission of auxiliary pattern. This function is not
available if bit XAIS is set to ‘1’.
XPRBS
XAIS
Transmit PRBS
This bit enables the transmission of the pseudo-random bit sequence
defined in register TPRBSC.
0
1
Disable transmission of PRBS.
Enable transmission of PRBS.
Transmit AIS
This bit enables transmission of alarm indication signal towards the
remote end. AIS is an all one unframed signal.
0
1
Disable transmission of AIS.
Enable transmission of AIS.
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Register Description
XRA
Transmit Remote Alarm (Yellow Alarm)
This bit enables the transmission of remote alarm in the outgoing bit
stream. Clearing the bit will remove the remote alarm pattern.
T1
0
1
Disable transmission of remote alarm.
Enable transmission of remote alarm. Remote alarm pattern is
selected via register FMR.SRAF.
E1
0
Disable transmission of remote alarm.
Set A-bit in transmitted service word.
1
XLU
XLD
Transmit Line Loopback Actuate (Up) Code
0
1
Normal operation.
A one in this bit position will cause the transmitter to replace
normal transmit data with the line loopback actuate code
continuously until this bit is reset. The line loopback actuate code
will be optionally overwritten by the framing/DL/CRC bits.
Transmit Line Loopback Deactuate (Down) Code
0
1
Normal operation.
A one in this bit position will cause the transmitter to replace
normal transmit data with the line loopback deactuate code
continuously until this bit is reset. The line loopback deactuate
code will be optionally overwritten by the framing/DL/CRC bits.
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Register Description
TFMR
T1/E1 Transmit Mode Register
Access
: read/write
: 01H
Address
Reset Value
: 0000H
15
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
XAS AXRA SRAF T1E1
FM(1:0)
XAS
Automatic Spare Bit Insertion
E1: CRC-4 Multiframe
0
Normal operation. Content of register XSP.XS13 and XSP.XS15
is inserted in the E-Bit of time slot 0 in frame 13 and frame 15
respectively.
1
Submultiframe status will be automatically set in the outgoing
data stream. Each received, errored submultiframe causes bit
one of time slot 0 of frame 13 and frame 15 to be ‘0’. Otherwise
these bits are set to ‘1’.
AXRA
Automatic Transmit Remote Alarm
Setting this bit enables automatic transmission of remote alarm.
0
1
Normal operation.
The Remote Alarm (yellow alarm) bit will be automatically set in
the outgoing data stream if the receiver is in asynchronous state
(FRS.LFA bit is set). In synchronous state the remote alarm bit
will be reset.
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PEF 20256M E
Register Description
SRAF
Select Remote (Yellow) Alarm Format
Setting this bit enables the remote alarm format in T1 mode. This bit has
no function in E1 mode.
T1: F4
1
Bit 2 = 0 in every channel
T1: F12
0
1
FS bit of frame 12.
Bit 2 = 0 in every channel.
T1: ESF
0
Pattern ‘1111 1111 0000 0000…’ in data link channel.
Bit 2 = 0 in every channel.
1
T1E1
FM
T1/E1 mode selection
This bit switches the transmit framer into T1 and E1 mode.
0
1
Select T1 mode.
Select E1 mode.
Select Frame Mode
This bit field determines the framing mode of the transmit framer.
T1
00B
01B
10B
Select ESF format.
Select F12 format.
Select F4 format.
Other Reserved
E1
00B
01B
Select Double frame format.
Select CRC-4 multiframe format.
Other Reserved
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Register Description
TLCR0
T1/E1 Transmit Loop Code Register 0
Access
: read/write
: 02H
Address
Reset Value
: 0000H
15
14
9
8
1
0
FLLB LCS
0
0
0
0
LDCL(1:0)
0
0
0
0
0
0
LACL(1:0)
FLLB
Disable Framed Line Loopback
This bit switches between framed and unframed transmission of line
loopback. In unframed transmission the FS/DL bit the line loopback code
overwrites the FS/DL bits, while in framed transmission the FS/DL bits
will not be overwritten by the line loopback code.
0
1
Set framed line loopback transmission.
Set unframed line loopback transmission.
LCS
Loop Code Select
This bit switches between line loopback code defined in ANSI T1.403 or
a user definable loopback code defined in register TLCR1.
0
1
Select ANSI codes.
Select line loopback code defined in register TLCR1.
LDCL
LACL
Line Loopback Deactuate Code Length
This bit field determines the length of the line loopback deactuate code
specified in register TLCR1. The length of the loopback code can be
specified in a range of 5 to 8 bits.
00B..11BSpecifies code length in the range of 5 to 8 bits.
Line Loopback Actuate Code Length (5-8 bit)
This bit field determines the length of the line loopback actuate code
specified in register TLCR1. The length of the loopback code can be
specified in a range of 5 to 8 bits.
00B..11BSpecifies code length in the range of 5 to 8 bits.
Note: Codes of smaller length might be activated by multiple entry, e.g. code 001: write
001001 to TLCR1 register and define code length of 6 bits.
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Register Description
TLCR1
T1/E1 Transmit Loop Code Register 1
Access
: read/write
: 03H
Address
Reset Value
: 0000H
15
8
7
0
LDC(7:0)
LAC(7:0)
LDC
Line Loopback Deactuate Code
This bit field is sent in the outgoing bit stream if enabled via bit
TCMDR.XLD and TLCR0.LCS.
Note: Most significant bit is sent first. E.g. TCLR0.LDCL = 01B specifies
code length to be six bits long. In this case LDC(5) is sent first.
LAC
Line Loopback Actuate Code
This bit field is sent in the outgoing bit stream if enabled via bit
TCMDR.XLU and TLCR0.LCS.
Note: Most significant bit is sent first. E.g. TCLR0.LACL = 01B specifies
code length to be six bits long. In this case LAC(5) is sent first.
Preliminary Data Sheet
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Register Description
TPRBSC
T1/E1 Transmit PRBS Control Register
Access
: read/write
: 04H
Address
Reset Value
: 001FH
15
12
9
8
4
0
FPRBS
0
0
IPRBS
0
0
PRP(1:0)
0
0
0
FPL(4:0)
FPRBS
Framed PRBS
This bit field enables framed or unframed transmission of the pseudo-
random bit sequence.
0
1
Transmit framed PRBS.
Transmit unframed PRBS.
IPRBS
PRP
Invert PRBS
This bit field enables inversion of the pseudo-random bit sequence in
transmit direction.
0
1
PRBS is not inverted.
PRBS is inverted.
Pseudo-Random Pattern
This bit field determines the generator polynomial for the pseudo-
random bit sequence.
00B
01B
1-B
PRBS is generated according to 215 -1 (ITU-T O. 151)
PRBS is generated according to 220 -1 (ITU-T O. 151)
For PRBS the fixed pattern, defined in TFPR0 and TFPR1, is
selected.
FPL
Fixed Pattern Length
This bit field sets the length of the fixed pattern FP which is located in
register TFPR0 and TFPR1. E.g.: FPL(4:0) = 10010B means pattern
length is equal to 19, which implies that the bits FP(18)..FP(0) form the
PRBS.
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PEF 20256M E
Register Description
TFPR0
T1/E1 Transmit Fixed Pattern Register Low Word
Access
: read/write
: 05H
Address
Reset Value
: 0000H
15
0
FP(15:0)
FP(31:0)
Fixed Pattern Low Bytes
See description below.
TFPR1
T1/E1 Transmit Framer Fixed Pattern Register High Word
Access
: read/write
: 06H
Address
Reset Value
: 0000H
15
0
FP(31:16)
FP(31:0)
Fixed Pattern High Bytes
This bit field together with bit field TFPR0.FP defines a bit sequence,
which can be sent instead of a pseudo-random bit sequence. FP is sent
in the order FP(TPRBSC.FPL-1) down to FP(0) and will be repeated until
deactivated.
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PEF 20256M E
Register Description
TPTSL0
T1/E1 Transmit PRBS Time Slot Number Register Low Word
Access
: read/write
: 07H
Address
Reset Value
: FFFFH
15
0
TSL(15:0)
TSL(31:0)
Time slot 15..0 Select
See description below.
TPTSL1
T1/E1 Transmit PRBS Time Slot Number Register High Word
Access
: read/write
: 08H
Address
Reset Value
: 00FFH
15
0
TSL(31:16)
TSL(31:0)
Time slot 31..16 Select
Selected bits in bit field TSL and TPTSL0.TSL determine those time
slots, which are used for PRBS generation. Time slots can be
programmed arbitrarily. E.g. if TPTSL0.TSL(1) and TPTSL0.TSL(2) are
set to ‘1’, the PRBS is sent continuously over both time slots combined.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
XSP
T1/E1 Transmit Spare Bit Register
Access
: read/write
: 09H
Address
Reset Value
: 0000H
15
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
XS13 XS15
XS13, XS15
Transmit Spare Bit
E1: CRC-4 Multiframe
Dependent on bit FMR.XAS and framer mode spare bits of service word
in CRC-4 multiframe 13 and 15 are replaced by XS13 and XS15.
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PEB 20256M E
PEF 20256M E
Register Description
8.2.6
Receive Framer Registers
RCMDR
T1/E1 Receive Command Register
Access
: read/write
: 00H
Address
Reset Value
: 0000H
15
5
0
4
1
0
0
0
0
0
0
0
0
0
0
0
SIM(3:0)
FRS
SIM
Alarm Simulation
This bit field enables alarm simulation in the receive framer. See codes
for specific function.
0000B Disable alarm simulation.
0001B Simulate loss of signal
Setting this code:
- Generate ’Loss of Signal Status’ interrupt vector.
- Flag ’Loss of Signal’ via bit FSR.LOS.
- Generate PDEN interrupt vector.
- Flag ’Pulse Density Code Violation Detected’ via bit FSR.PDEN/
AUX.
Removing this code:
- Generate ’Loss of Signal Status’ interrupt vector.
- Remove signalling of ’Loss of Signal’.
- Generate PDEN interrupt vector.
- Remove signalling of ’Pulse Density Code Violation Detected’.
0010B Simulate Alarm Indication Signal
Setting this code:
- Generate ’Loss of Frame Alignment’ interrupt vector.
- Flag ’Loss of Frame Alignment’ via bit FRS.LFA.
- Generate ’Alarm Indication Signalled’ interrupt vector.
- Flag ’Alarm Indication Signalled’ via bit FRS.AIS.
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PEF 20256M E
Register Description
Removing this code:
- Generate ’Loss of Frame Alignment Status’ interrupt vector.
- Remove signalling of ’Loss of Frame Alignment’.
- Generate ’Alarm Indication Signal Status’ interrupt vector.
- Remove signalling of ’Alarm Indication Signalled’.
0011B Simulate auxiliary pattern (’...010101...’ pattern)
This sequence simulates also loss of frame (required for auxiliary
pattern).
Setting this code:
- Generate ’Auxiliary Pattern Status’ interrupt vector.
- Generate ’Loss of Frame Alignment Status’ interrupt vector.
- Flag ’Loss of Signal’ via bit FRS.LFA.
- Flag ’Auxiliary Pattern detected’ via bit FRS.PDEN/AUX.
- Flag ’Loss of Multiframe Alignment’ via bit FRS.LMFA (CRC-4
Multiframe mode).
- Increment framing error counter by 3 or 4 depending on
RFMR.SSP
Removing this code:
- Generate ’Auxiliary pattern Status’ interrupt vector.
- Generate ’Loss of Frame Alignment Status’ interrupt vector.
- Remove signalling of ’Loss of Frame Alignment’.
- Remove signalling of FRS.PDEN/AUX.
- Remove signalling of ’Loss of Multiframe Alignment’.
0100B Simulate loss of frame
Setting this code:
- Generate ’Loss of Frame Alignment Status’ interrupt vector.
- Flag ’Loss of Signal’ via bit FRS.LFA.
- Flag ’Loss of Multiframe Alignment’ via bit FRS.LMFA (CRC-4
multiframe mode).
- Increment framing error counter by 2, 3, or 4 (depends on
RFMR.SSP).
- Increment errored seconds (T1 mode only).
Removing this code:
- Generate ’Loss of Frame Alignment Status’ interrupt vector.
- Remove signalling of ’Loss of Frame Alignment’.
- Remove signalling of ’Loss of Multiframe Alignment’.
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PEB 20256M E
PEF 20256M E
Register Description
0101B Simulate remote alarm
Setting this code:
- Generate ’Remote Alarm Status’ interrupt vector.
- Flag ’Received Remote Alarm’ bit FRS.RRA.
Removing this code:
- Generate ’Remote Alarm Status’ interrupt vector.
- Remove signalling of ’Receive Remote Alarm’.
0110B Simulate CRC error (T1 ESF or E1 CRC-4 multiframe mode)
Setting this code:
- Generate CRC interrupt vector.
- Increment CRC error counter.
Removing this code:
- Stop generation of CRC interrupt vector.
- Stop increment of CRC error counter.
FRS
Force Resynchronization
A transition from low to high will force the frame aligner to execute a
resynchronization of the pulse frame. The procedure depends on the
status of bit FMR.SSP.
0
1
No operation.
Change from ’0’ to ’1’ forces resynchronization.
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PEF 20256M E
Register Description
RFMR
T1/E1 Receive Mode Register
Access
: read/write
: 01H
Address
Reset Value
: 0000H
15
11
10
9
8
7
6
5
3
2
1
0
0
0
0
0
LOSR ALMF RRAM AIS3 SSP SSC(1:0)
0
SRAF T1E1
FM(1:0)
LOSR
Loss of Signal Recovery
This bit sets the conditions for ’Loss of Signal’ detection.
T1
0
Loss of signal cleared, when pulse density defined by register
PCR is detected during a time interval declared by register PCD.
1
Loss of signal cleared, when pulse frame density defined by
register PCR is detected during a time interval declared by
register PCD and a pulse density of at least N ‘1’s in every N+1
octets (0<N<24) during recovery interval defined in register PCD
is detected.
E1
0
Loss of signal cleared, when pulse density defined by register
PCR is detected during a time interval declared by register PCD.
1
No function.
ALMF
Automatic Loss of Multiframe
This bit selects condition for automatic loss of multiframe.
T1
0
1
CRC errors do not cause loss of frame alignment.
320 or more CRC errors in one second cause loss of frame
alignment.
E1
0
CRC errors do not cause loss of frame alignment.
1
915 or more CRC-4 errors in one second cause loss of frame
alignment.
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PEF 20256M E
Register Description
RRAM
Receive Remote Alarm Mode
The conditions for remote (yellow) alarm detection can be selected via
this bit to allow detection even in the presence of BER 10-3. Remote
alarm detection is flagged in register FRS.RRA and can be signalled as
an interrupt.
T1: F4
0
Normal operation
Detection:
Bit 2 = ‘0’ in every speech channel per frame.
Release:
The alarm will be reset when above conditions are no longer
detected.
1
Detection with BER 10-3
Detection:
Bit 2 = ‘0’ in 255 consecutive speech channels.
Release:
The alarm will be reset when receiver does not detect the Bit 2 =
’0’ condition for three consecutive pulseframes.
T1: F12
0 Normal operation
Depending on bit FMR0.SRAF:
0
Detection:
FS-bit of frame 12 is forced to ‘1’.
Release:
The alarm will be reset when above conditions are no
longer detected.
1
Detection:
Bit 2 = ‘0’ in every speech channel per frame.
Release:
The alarm will be reset when above conditions are no
longer detected.
1
Detection with BER 10-3
Remote alarm detection depending on bit FMR0.SRAF:
0
Detection:
FS-bit of frame 12 is forced to ‘1’.
Release:
The alarm will be reset when receiver does not detect the
’Fs-bit’ condition for three consecutive multiframes.
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PEB 20256M E
PEF 20256M E
Register Description
1
Detection:
Bit 2 = ‘0’ in 255 consecutive speech channels.
Release:
The alarm will be reset when receiver does not detect the
Bit 2 = ’0’ condition for three consecutive pulseframes.
T1: ESF
0
Normal operation
Remote alarm detection depending on bit FMR0.SRAF:
0
Detection
Pattern ‘1111 1111 0000 0000…’ in data link channel.
Release:
The alarm will be reset when above conditions are no
longer detected.
1
Detection:
Bit 2 = ‘0’ in every speech channel per frame.
Release:
The alarm will be reset when above conditions are no
longer detected.
1
Detection with BER 10-3
Remote alarm detection depending on bit FMR0.SRAF:
0
Detection
Pattern ‘1111 1111 0000 0000…’ in data link channel.
Release:
The alarm will be reset when receiver does not detect ‘DL
pattern’ for three times in a row.
1
Detection:
Bit 2 = ‘0’ in 255 consecutive speech channels.
Release:
The alarm will be reset when receiver does not detect the
Bit 2 = ’0’ condition for three consecutive pulseframes.
AIS3
Select AIS Condition
This bit selects the condition which leads to AIS reporting.
T1: F4, F12
0
AIS (blue alarm) is indicated, when two or less zeros in the
received bit stream are detected in a time interval of 12 frames.
1
AIS (blue alarm) detection is only enabled, when framer is in
asynchronous state. The alarm is indicated, when three or less
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PEF 20256M E
Register Description
zeros within a time interval of 12 frames are detected in the
received bit stream.
T1: ESF
0
AIS (blue alarm) is indicated, when two or less zeros in the
received bit stream are detected in a time interval of 24 frames.
1
AIS (blue alarm) detection is only enabled, when framer is in
asynchronous state. The alarm is indicated, when five or less
zeros within a time interval of 24 frames are detected in the
received bit stream.
SSP
Select Synchronization/Resynchronization Procedure
T1: F12
0
Specified number of errors in FT framing or specified number of
errors in FS framing leads to loss of synchronization (FRS.LFA).
In the case of FS bit framing errors, bit FRS.LMFA is set
additionally. A complete new synchronization procedure is
initiated to regain pulseframe alignment and then multiframe
alignment.
1
Specified number of errors in FT framing has the same effect as
above. Specified number of errors in FS framing only initiates a
new search for multiframe alignment without influencing
pulseframe synchronous state (FRS.LMFA is set).
T1: ESF
0
Synchronization is achieved only on verification of the framing
pattern.
1
Synchronous state is reached when framing pattern and CRC-6
checksum are correctly found.
SSC
Select Synchronization Conditions
T1
Loss of Frame Alignment (FRS.LFA or opt. FRS.LMFA) is declared if
00B
01B
10B
2 out of 4 framing bits
2 out of 5 framing bits
F12
2 out of 6 framing bits
ESF
2 out of 6 framing bits per multiframe period
4 consecutive incorrect multiframe pattern
11B
It depends on the selected multiframe format and optionally on bit
FMR.SSP which framing bits are observed:
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PEB 20256M E
PEF 20256M E
Register Description
F12 SSP = 0: FT bits → FRS.LFA: FS bits → FRS.LFA and
FRS.LMFA SSP = 1:FT → FRS.LFA
FS → FRS.LMFA
ESF ESF framing bits → FRS.LFA
E1
00B
01B
10B
11B
3 out of 4 consecutive FAS or service word errors
4 out of 4 consecutive FAS or service word errors
3 out of 3 FAS errors
4 out of 4 FAS errors
SRAF
Select Remote (Yellow) Alarm Format
This bit is valid for T1 mode only.
T1: F4
0/1
Bit 2 = ‘0’ in every channel.
T1: F12
0
1
FS bit of frame 12.
Bit 2 = ‘0’ in every channel.
T1: ESF
0
1
Pattern ‘1111 1111 0000 0000…’ in data link channel.
Bit 2 = ‘0’ in every channel.
T1E1
FM
T1/E1 Mode Selection
This bit switches the receive framer into T1 or E1 mode.
0
1
Select T1 mode.
Select E1 mode.
Select Frame Mode
This bit field selects the framing mode of the receive framer.
T1
00B
01B
10B
ESF-Format
F12-Format
F4-Format
Other Reserved
E1
00B
01B
10B
Doubleframe
CRC-4
CRC-4 Interworking mode
Other Reserved
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PEF 20256M E
Register Description
RLCR0
T1/E1 Receive Loop Code Register 0
Access
: read/write
: 02H
Address
Reset Value
: 0000H
15
0
14
9
8
1
0
LCS
0
0
0
0
LDCL(1:0)
0
0
0
0
0
0
LACL(1:0)
LCS
Loop Code Select
This bit switches between line loopback code defined in ANSI T1.403 or
a user definable loopback code defined in register RLCR1.
0
1
Select ANSI codes.
Select line loopback code defined in register RLCR1.
LDCL
LACL
Line Loopback Deactuate Code Length
This bit field determines the length of the line loopback deactuate code
specified in register TLCR1. The length of the loopback code can be
specified in a range of 5 to 8 bits.
00B..11BSpecifies code length in the range of 5 to 8 bits.
Line Loopback Actuate Code Length (5-8 bit)
This bit field determines the length of the line loopback actuate code
specified in register TLCR1. The length of the loopback code can be
specified in a range of 5 to 8 bits.
00B..11BSpecifies code length in the range of 5 to 8 bits.
Note: Codes of smaller length might be activated by multiple entry, e.g. code 001: write
001001 to LCR1 register and define code length of 6 bits.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
RLCR1
T1/E1 Receive Loop Code Register 1
Access
: read/write
: 03H
Address
Reset Value
: 0000H
15
8
7
0
LDC(7:0)
LAC(7:0)
LDC
Line Loopback Deactuate Code
This incoming bit stream will be compared against this bit field if enabled
via bit RLCR0.LCS.
Note: Most significant bit is sent first. E.g. TCLR0.LDCL = 01B specifies
code length to be six bits long. In this case LDC(5) is sent first.
LAC
Line Loopback Actuate Code
This incoming bit stream will be compared against this bit field if enabled
via bit RLCR0.LCS.
Note: Most significant bit is sent first. E.g. TCLR0.LACL = 01B specifies
code length to be six bits long. In this case LAC(5) is sent first.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
RPRBSC
T1/E1 Receive PRBS Control Register
Access
: read/write
: 04H
Address
Reset Value
: 001FH
15
13
EPRM
9
8
4
0
0
0
0
0
0
PRP(1:0)
0
0
0
FPL(4:0)
EPRM
Enable PRBS Monitor
This bit enables the PRBS monitoring function. When PRBS monitor is
enabled the pseudo-random pattern synchronizer logs onto the
pseudo-random pattern defined in PRB.
0
1
PRBS monitor is disabled.
PRBS monitor is enabled.
PRP
Pseudo-Random Pattern
00B
01B
11B
The incoming pattern is compared according to 215 -1 (ITU-T
O.151)
The incoming pattern is compared according to 220 -1 (ITU-T
O.151)
The incoming pattern is compared to the fixed pattern, defined in
RFPR0 and RFPR1. The pattern length is defined in FPL.
Other Reserved
FPL
Fixed Pattern Length, e.g.: =10010 means pattern length is equal to 19,
which implies that the bits RFPR1/0.FP(18)..FP(0) form the PRBS.
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PEB 20256M E
PEF 20256M E
Register Description
RFPR0
T1/E1 Receive Fixed Pattern Register Low Word
Access
: read/write
: 05H
Address
Reset Value
: 0000H
15
0
FP(15:0)
FP
Fixed Pattern Low Bytes
See description below.
RFPR1
T1/E1 Receive Fixed Pattern Register High Word
Access
: read/write
: 06H
Address
Reset Value
: 0000H
15
0
FP(31:16)
FP
Fixed Pattern High Bytes
This bit field together with RFPR0.FP defines a bit sequence, which will
be monitored in the PRBS synchronous state. FP is compared in the
order FP(RPRBSC.FPL-1) down to FP(0) and comparison will be
repeated until deactivated.
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PEB 20256M E
PEF 20256M E
Register Description
RPTSL0
T1/E1 Receive PRBS Time Slot Number Register Low Word
Access
: read/write
: 07H
Address
Reset Value
: FFFFH
15
0
TSL(15:0)
TSL
Time slot 15..0 Select
See description below.
RPTSL1
T1/E1 Receive PRBS Time Slot Number Register High Word
Access
: read/write
: 08H
Address
Reset Value
: 00FFH
15
0
TSL(23:16)
TSL
Time slot 31..16 Select
Selected bits in bit field TSL and RPTSL0.TSL determine those time
slots, which are used for PRBS monitoring. Time slots can be
programmed arbitrarily. E.g. if RPTSL0.TSL(1) and RPTSL0.TSL(2) are
set to ‘1’, the PRBS is monitored continuously over both time slots
combined.
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PEB 20256M E
PEF 20256M E
Register Description
IMR
T1/E1 Receive Interrupt Mask Register
Access
: read/write
: 09H
Address
Reset Value
: 0000H
15
11
10
9
8
7
6
5
4
3
2
1
0
PDEN
/AUX
PRBSS
FAS MFAS AISS LOSS RAS ES SEC LLBS
0
0
0
0
T400 CRC
For each framer interrupt vector an interrupt vector generation mask is provided.
Generation of an interrupt vector itself does not necessarily result in assertion of the
interrupt pin. For description of interrupt concept and interrupt vectors see "Layer One
Interrupts" on page 136.
The following definition applies:
1
0
The corresponding interrupt vector is suppressed by the device.
The corresponding interrupt vector is generated.
T400
CRC
Mask ’400 millisecond Timer’
Mask ’CRC Error’
PDEN/AUX
FAS
Mask ’Pulse Density / Auxiliary Pattern’
Mask ’Frame Alignment Status’
Mask ’Multiframe Alignment Status’
Mask ’Alarm Indication Status’
Mask ’Loss of Signal Status’
Mask ’Remote Alarm Status’
Mask ’Errored Second’
MFAS
AIS
LOSS
RAS
ES
SEC
Mask ’One Second Tick’
LLBS
PRBSS
Mask ’Line Loopback Status’
Mask ’PRBS Status’
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
RFMR1
T1/E1 Receive Mode Register 1
Access
: read/write
: 0AH
Address
Reset Value
: 0000H
15
4
2
1
0
0
0
0
0
0
0
0
0
0
0
0
FRST(2:0)
EACM ECM
FRST
Force Resynchronization Timer
This bit field defines the time after which the framer automatically starts
resynchronization if Emulator Automatic Check Mode is enabled.
0..7 Automatic resynchronization after (FRST+1)*8 milliseconds.
Enable Emulator Automatic Check Mode
EACM
ECM
This bit enables automatic resynchronization mode. After loss of frame
the receive framer starts resynchronization after (FRST+1)*8ms when
frame search is not started by system software. If EACM is disabled
system software has to force resynchronization by setting bit
RCMDR.FRS.
Error Counter Mode
0
Unbuffered error counter mode. Counters are updated when
respective error occurs. Counter registers are directly readable
and cleared automatically at the end of a read cycle.
1
Buffered error counter mode. Actual error counts are hidden from
user and updated in background. The counter is copied to the bus
register at one second intervals and reset automatically. This
operation is synchronous with the periodic one second interrupt
which alerts software to read the register.
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PEB 20256M E
PEF 20256M E
Register Description
PCD
T1/E1 Receive Pulse Count Detection Register
Access
: read/write
: 0BH
Address
Reset Value
: 0015H
15
5
0
0
0
0
0
0
0
0
0
0
0
PCD(5:0)
PCD
Pulse Count Detection
A ’Loss of Signal’ alarm will be detected, if the incoming data stream has
zero octets for a programmable number T of consecutive octets. The
number T is programmable via the PCD register and can be calculated
as follows:
T = 8*(PCD+1), 1 ≤ PCD ≤ 63.
E.g. PCD = 21 sets loss of signal threshold to 176 (=(21+1)*8) zeros.
Note: For T1 mode time detection interval has cumulative uncertainty
of 1 per 193 clocks.
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PEB 20256M E
PEF 20256M E
Register Description
PCR
T1/E1 Receive Pulse Count Recovery Register
Access
: read/write
: 0CH
Address
Reset Value
: 0015H
15
5
0
0
0
0
0
0
0
0
0
0
0
PCR(5:0)
PCR
Pulse Count Recovery
’Loss of Signal’ alarm will be cleared, when a programmable pulse
density is detected in the received bit stream. A pulse is a logical ’1’ in
the received bit stream. The number of pulses M which must occur in a
certain time interval, which is programmable via register PCR, can be
calculated as follows:
M = PCR, 1 ≤ PCR ≤ 63.
Additional ’Loss of Signal’ recovery condition may be selected by using
RFMR.LOSR.
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PEB 20256M E
PEF 20256M E
Register Description
FRS
T1/E1 Receive Status Register
Access
: read/write
: 40H
Address
Reset Value
: 0000H
15
0
14
13
12
11
10
9
8
3
2
1
0
PDEN
AUX
LLBDD LLBAD
NMF LOS AIS LFA RRA LMFA FSRF
0
0
0
0
PRBS
Each bit in the framer receive status register declares a specific condition dependent on
the selected modes. The following convention applies to the individual bits:
0
1
The named status is not or no longer existing.
The named status is currently effective.
The change of status bit (except FSRF) can also be used to generate a framer interrupt
vector. See also register IMR which describes how to enable/disable interrupt vector
generation and refer to the description of framer interrupt vector on page "Layer One
Interrupts" on page 136.
NMF
LOS
No Multiframe Found
E1: CRC-4 Interworking
This bit is set, if no multiframe is found after 400 milliseconds.
Loss of Signal (Red Alarm)
This bit is set, when the ’Loss of Signal’ condition has been detected.
T1
Detection
An alarm will be generated if the incoming data stream remain at logical
zero for 168 cycles.
Recovery
The recovery procedure starts after detecting a logical 1. The LOS alarm
is cleared if 21 one’s are detected within 168 bits (12.5%).
E1
see T1 and "Error Performance Monitoring and Alarm Handling" on page
94.
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PEB 20256M E
PEF 20256M E
Register Description
AIS
Alarm Indication Signal (AIS)
This bit is set, when the alarm indication condition defined by bit
RFMR.AIS3 has been detected. The flag stays active for at least one
multiframe. It will be reset with the beginning of the next following
multiframe, if no alarm condition is detected.
LFA
Loss of Frame Alignment
T1
This bit is set, when the ’Loss of Frame Alignment’ condition defined by
bits RFMR.SSP and RFMR.SSC has been detected. The flag is cleared,
when synchronization has been regained.
E1
This bit is set, when the ’Loss of Frame Alignment’ condition defined by
bit RFMR.SSC has been detected. The flag is cleared, when
synchronization has been regained.
RRA
Received Remote Alarm (Yellow Alarm)
Condition for receive remote alarm is defined by bit FMR.RRAM. The
flag is set after detecting remote alarm (yellow alarm).
LMFA
Loss of Multiframe Alignment
T1: F12
This bit is set, when the condition for ’Loss of Multiframe Alignment’
defined by bit RFMR.SSC has been detected. The flag is cleared after
multiframe synchronization has been regained.
E1: CRC-4 Multiframe, CRC-4 Interworking
This bit is set in CRC-4 multiframe or CRC-4 interworking mode, when
double frame alignment is lost. This bit is reset, when the multiframe
pattern is acquired or after 400 milliseconds in CRC-4 interworking
mode, when NMF is asserted.
FSRF
Frame Search Restart Flag
This bit toggles on each new pulse frame search started. This function
can be used to recognize multiple candidates. If FSRF does not toggle,
but LFA and LMFA remain active, the synchronizer has multiple
candidates and cannot determine which one is correct.
Note: This flag can not be used to generate an interrupt vector.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
PDEN/AUX
T1
Pulse Density Code Violation Detected
This bit is set, when the pulse density of the received data stream is
below the requirement defined by ANSI T1.403.
E1
Auxiliary Pattern Detected
This bit is set, when the pattern ’...010101...’ has been detected
concurrent with loss of frame.
LLBDD
LLBAD
PRBS
Line Loop-Back Deactuation Signal Detected
This bit is set, when line loopback deactuate signal is detected and then
received over a period of more than 33,16ms with a bit error rate less
than 1/100. The bit remains set as long as the bit error rate does not
exceed 1/100.
If framing is aligned, the first bit position of any frame is not taken into
account for the error rate calculation. If frame alignment state is not
synchronized, all received data bits are searched for the LLBD pattern.
Line Loop-Back Actuation Signal Detected
This bit is set to one in case the LLB actuate signal is detected and then
received over a period of more than 33,16ms with a bit error rate less
than 1/100. The bit remains set as long as the bit error rate does not
exceed 1/100.
If framing is aligned, the first bit position of any frame is not taken into
account for the error rate calculation. If frame alignment state is not
synchronized, all receive data bits are searched for the LLBA pattern.
PRBS status
This bit is set, when the PRBS receiver is in the synchronous state. It is
set high if the synchronous state is reached even in the presence of a
BER 1/10. A data stream containing all zeros with / without framing bits
is also a valid pseudo-random bit sequence.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
FEC
T1/E1 Receive Framing Error Counter
Access
: read/write
: 41H
Address
Reset Value
: 0000H
15
0
FE(15:0)
FE
Framing Error Counter
The counter will not be incremented during asynchronous state. Error
counter mode (Clear on Read or Errored Second) depends on register
RFMR1.ECM. In errored second mode the counter is 10 bit wide,
otherwise 16 bit.
T1: F12
The counter will be incremented when incorrect FT and FS bits are
received.
T1: ESF
The counter will be incremented when incorrect FAS bits are received.
E1
The counter will be incremented when incorrect FAS words are received.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
CEC
T1/E1 Receive CRC Error Counter
Access
: read/write
: 42H
Address
Reset Value
: 0000H
15
0
CR(15:0)
CR
CRC Errors
The counter will not be incremented during asynchronous state. Error
counter mode (Clear on Read or Errored Second) depends on register
RFMR1.ECM. In errored second mode the counter is 10 bit wide,
otherwise 16 bit.
T1: F12
No function.
T1: ESF
The counter will be incremented when a multiframe has been received
with a CRC error.
E1: Doubleframe
No function.
E1: CRC-4 Multiframe
In CRC-4 multiframe mode the counter will be incremented when a
submultiframe has been received with a CRC error.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
EBC
T1/E1 Receive Errored Block Counter
Access
: read/write
: 43H
Address
Reset Value
: 0000H
15
0
EB(15:0)
EB
E-Bit or Errored Block counter
The counter will not be incremented during asynchronous state. Error
counter mode (Clear on Read or Errored Second) depends on register
RFMR1.ECM. In errored second mode the counter is 10 bit wide,
otherwise 16 bit.
T1
The counter will be incremented once per multiframe if a submultiframe
has been received with a CRC error or an errored frame alignment has
been detected.
E1: Doubleframe
No function.
E1: CRC-4 Multiframe
The counter will be incremented each time the framer receives a CRC-4
multiframe with Si bit in frame 13 or frame 15 set to zero.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
BEC
T1/E1 Receive Bit Error Counter
Access
: read/write
: 44H
Address
Reset Value
: 0000H
15
0
BE(15:0)
BE
Bit Error Counter
Error counter mode (Clear on Read or Errored Second) depends on
register RFMR1.ECM. In errored second mode the counter is 10 bit
wide, otherwise 16 bit.
T1
This bit counter will be incremented with every received PRBS bit error
in the PRBS synchronous state.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
8.2.7
Facility Data Link Registers
Facility data link registers control the signalling channels of T1, E1 as well as the
signalling channels of the DS3 C-bit parity format (Path Maintenance Data Link and Far
End Alarm and Control Channel).
RCR1
Receive Channel Configuration Register 1
Access
: read/write
: 00H
Address
Reset Value
: 0000H
15
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CRC
DIS
RAH2 RAH1 RTF(1:0)
INV RIFTF BFE BRM BRAC RAL2 RAL1 XCRC
RON HDLC
RAH2
RAH1
RTF
Receive Address High Byte 2 Valid
This bit enables byte RAH.RAH2 for address comparison.
0
1
Disable
Enable
Receive Address High Byte 1 Valid
This bit enables byte RAH.RAH1 for address comparison.
0
1
Disable
Enable
RFIFO Threshold Level
This bit field sets the threshold of the receive FIFO and is applied to both
pages of the receive FIFO. A ’Receive Pool Full’ interrupt vector will be
generated, when the programmed threshold is reached. The threshold
value is given as follows:
00B
01B
10B
11B
32 byte threshold
16 byte threshold
4 byte threshold
2 byte threshold
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
INV
Invert data input from Receive Framer
This bit enables data inversion between receive framer and receive
signalling controller.
0
1
Disable data Inversion.
Enable data inversion.
RIFTF
BFE
Report Interframe Time-fill Change
This bit selects, that interframe time-fill changes should be reported.
0
1
Disable IFF status messages.
Enable IFF status messages.
Enable BOM Filter Mode
This bit selects, that byte oriented messages have to be filtered. The
BOM is reported only if 7 out 10 data is received. This bit is valid in BOM
mode only.
0
1
Disable BOM filter mode.
Enable BOM filter mode.
BRM
BOM Receive Mode
This bit switches continuous and 10 byte packet reception of the receive
signalling controller. This bit is valid in BOM mode only.
0
1
Enable continuous reception.
Enable 10 bytes packets.
BRAC
BOM Receiver Active
T1: ESF
This bit switches the BOM receiver to operational state (on) or
inoperational state (off). When BOM Receiver is switched on, an
automatic switching between HDLC mode and BOM mode is enabled. If
eight or more consecutive ’1’s are detected, the BOM mode is entered.
Upon detection of a flag in the data stream, the signalling controller
switches back to HDLC mode.
0
1
Switch BOM receiver off.
Switch BOM receiver on.
RAL2
Receive Address Low Byte 2 Valid
This bit enables byte RAL.RAL2 for address comparison.
0
1
Disable
Enable
Preliminary Data Sheet
360
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PEB 20256M E
PEF 20256M E
Register Description
RAL1
Receive Address Low Byte 1 Valid
This bit enables byte RAL.RAL1 for address comparison.
0
1
Disable
Enable
XCRC
Transfer CRC to RFIFO
This bit defines, that CRC of incoming data packets shall be transferred
to the receive FIFO or not.
0
1
No transfer of CRC to RFIFO.
Transfer of CRC to RFIFO.
CRCDIS
RON
CRC Check Disable
This bit enables or disables the CRC check of incoming data packets.
0
1
Enable CRC check.
Disable CRC check.
Receiver On/Off
This bit switches the receiver of the facility data link channel to
operational (on) or inoperational state (off).
0
1
Switch receiver off.
Switch receiver on.
HLDC
HDLC Mode
This bit identifies the protocol mode of the facility data link receiver.
0
1
Set protocol mode to transparent.
Set protocol mode to HDLC.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
RCR2
Receive Channel Configuration Register 2
Access
: read/write
: 01H
Address
Reset Value
: 0000H
15
14
13
12
10
9
7
6
5
4
3
2
1
0
PAS SAUM SAUP
SACRC(2:0)
SASSM(2:0)
SA8E SA7E SA6E SA5E SA4E SMF T1E1
PAS
Pattern Select for SSM and CRC Count Function
This bit selects the default pattern for synchronization status messages
and bit error indication.
0
1
Use pattern defined in ETS 300233.
Use patterns specified in registers VSSM and VCRC.
SAUM
Sa-bit Update Mode
This bit selects the update mode for the Sa-bits located in register
RSAW1..RSAW3.
E1: Doubleframe
0
1
Sa-bits are updated after eight frames.
Sa-bits are updated only, if Sa data changes. Update is done after
eight frames.
E1: CRC-4 Multiframe
0
1
Sa-bits are updated after every multiframe.
Sa-bits are updated only, if Sa data changes. Update is done on
a multiframe start.
SAUP
Sa-Bit Update
This bit enables the Sa-bit update function.
0
1
Disable update of Sa-bits.
Enable update of Sa-bits using RSAW1..RSAW3 registers.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
SACRC
SASSM
Sa-bit Select for CRC Function
This bit field enables the CRC count function of the selected Sa-bit.
Disable CRC count function.
0
1..5 Enable CRC count function for bit Sa4..Sa8, e.g. SACRC = 2
selects bit Sa8 for CRC count function.
Other Reserved
Sa-bit Select for SSM Function
This bit field enables the synchronization status message function of the
selected Sa-bit. The SSM function checks incoming messages and
reports any change if a synchronization status message has been
received three times in a row.
0
Disable SSM function.
1..5 Enable SSM function for bit Sa4..Sa8, e.g. SASSM = 2 selects
bit Sa8 for SSM function.
Other Reserved
SA8E..SA4E Sa-bit Signalling Enable
Setting one of the bits switches between Sa-bit access or protocol
access of the selected bits.
0
1
Enable Sa-bit access via register RSAW1-3.
Enable protocol access (HDLC, transparent). Selected bits will
be combined to receive protocol data.
SMF
Select Multiframe Format
This bit switches between doubleframe and CRC-4 multiframe format.
0
1
Select doubleframe format.
Select CRC-4 multiframe format.
T1E1
T1/E1 Mode Selection
This bit switches the receive signalling controller into T1 or E1 mode.
0
1
Select T1 mode.
Select E1 mode.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
RFF
Receive FIFO Register
Access
: read
: 02H
Address
Reset Value
: 0000H
15
0
RFIFO(15:0)
RFIFO
Receive FIFO Data
This bit field contains the first 16 bit word of the receive FIFO of the
signalling controller. The receive FIFO itself consists of two pages with
32 bytes, thus 16 words can be stored inside the receive FIFO at a time.
Port status and FIFO operations can be accessed via register PSR and
register HND.
The first bit received is stored in bit 0.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
XCR1
Transmit Channel Configuration Register 1
Access
: read/write
: 03H
Address
Reset Value
: 0000H
15
8
7
4
3
2
1
0
DIS
CRC
PBYTE(7:0)
PCNT(3:0)
INV XON
SF
PBYTE
Preamble Byte
This bit field selects the preamble byte to be sent after interframe time-
fill transmission is stopped.
PCNT
INV
Preamble Count
This bit field selects the amount of preamble repetitions.
Invert Data
This bit enables data inversion between transmit signalling controller
and transmit framer.
0
1
Disable data Inversion.
Enable data inversion.
XON
Transmitter On/Off
This bit switches the transmitter of the facility data link to operational (on)
or inoperational state (off).
0
1
Switch transmitter off.
Switch transmitter on.
DISCRC
Disable CRC
This bit enables CRC generation and transmission on transmission of
HDLC packets.
0
1
Enable CRC generation.
Disable CRC generation.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
SF
Shared Flags
This bit enables transmission of protocol data with shared flags.
0
1
Disable shared flags.
Enable shared flags.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
XCR2
Transmit Channel Configuration Register 2
Access
: read/write
: 04H
Address
Reset Value
: 0000H
15
8
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
IFTF SA8E SA7E SA6E SA5E SA4E SMF T1E1
IFTF
Interframe Time Fill
This bit determines the interframe time of the transmit signalling
controller.
0
1
Interframe time fill is 7EH.
Interframe time fill is FFH.
SA8E..SA4E Sa-bit Signalling Enable
Setting one of the bits switches between normal Sa-bit access or protocol
access of the selected bits.
0
1
Enable Sa-bit access via register XSAW1-3.
Enable protocol access (HDLC, transparent). Selected bits will
be combined for protocol data transmission.
SMF
Select CRC-4 Multiframe Format
This bit switches between doubleframe and multiframe format.
E1
0
1
Select doubleframe format.
Select CRC-4 multiframe format.
T1E1
T1/E1 Mode Selection
This bit switches the receive signalling controller into T1 or E1 mode.
0
1
Select T1 mode.
Select E1 mode.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
XFF
Transmit FIFO Register
Access
: write
: 05H
Address
Reset Value
: 0000H
15
0
XFIFO(15:0)
XFIFO
Transmit FIFO Data
This bit field writes a 16 bit word to the transmit FIFO of the signalling
controller. The transmit FIFO itself consists of two pages with 32 bytes,
thus 16 words can be written to the transmit FIFO at a time. Port status
and FIFO operations can be accessed via register PSR and register
HND.
Data written to the transmit FIFO is sent starting with bit 0 up to bit 15.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
PSR
Port Status register
Access
: read
: 06H
Address
Reset Value
: 0000H
15
14
13
12
8
7
6
5
4
0
XRA XFW
RBC(4:0)
SMODE(1:0) BRFO
STAT(4:0)
XRA
Transmit Repeat Active
This bit indicates that the transmit signalling controller is operating in
repeat mode.
0
1
Normal operation
Repeat operation
XFW
Transmit FIFO Write Enable
This bit indicates that data can be written to XFF.XFIFO. This bit is for
polling use with the same meaning as the ’Transmit Pool Ready’
interrupt vector.
RBC
Receive Byte Count
This bit field indicates the amount of data stored in the receive FIFO.
Valid after a ’Receive Message End’ interrupt vector is generated.
Receive byte count will be cleared, when a ’Receive Message Clear’
command is executed via register HND. A zero byte count in
combination with a ‘Receive Pool Full’ or ’Receive Message End’
interrupt vector means that 32 bytes are available in the receive FIFO.
SMODE
Receiver Status Mode
This bit indicates the status of the receive signalling controller. If BOM
mode is selected via bit RCR1.BRM the receiver switches automatically
between HDLC mode and BOM mode.
10B
01B
HDLC mode
BOM mode
Other Reserved
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
BRFO
BOM Receive FIFO Overflow
0
1
No overflow
RFF overflow
The status word will be cleared after a ’Receive Message Clear’
command is issued.
STAT
Receive FIFO Status
This bit field reports the status of the data stored in the receive FIFO.
HDLC mode
00000B
00001B
00010B
00011B
00100B
00101B
Valid HDLC Frame
Receive Data Overflow
Receive Abort
Not Octet
CRC Error
Channel Off
BOM MODE
00000B
00001B
00010B
00011B
00100B
BOM Filtered data declared
BOM data available
BOM End
BOM filtered data undeclared
BOM header error (ISF, incorrect synchronization format)
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
HND
Handshake Register
Access
: write
: 07H
Address
Reset Value
: 0000H
15
8
5
4
3
2
1
0
ABORT
XRES XREP OBI XHF XTF XME
0
0
0
0
0
0
0
RMC
0
Note: Receive command (bit 8) and transmit commands (bit 5 down to bit 0) can not be
issued at the same time. Doing so will cause the facility data link to omit the
transmit commands.
RMC
Receive Message Complete
This bit is a confirmation from CPU that a data block has been read from
RFIFO following a ’Receive Pool Full’ or ’Receive Message End’
interrupt vector and that the occupied page can now be released.
0
1
No function
Release page of receive FIFO.
Note: If this bit is set, the low byte (transmit commands) of the register
HND is ignored.
ABORT
XRES
Abort Frame
Setting this bit aborts HDLC frames which are transmitted.
0
1
Normal operation
Abort HDLC frame.
Transmitter Reset
This bit resets the signalling controller transmit. However, the contents
of the control register will not be reset.
0
1
Normal operation
Transmitter reset
XREP
Transmission Repeat
Setting this bit together with bit XTF indicates that the contents stored in
XFF.XFIFO shall be repeatedly transmitted by the MUNICH256FM.
0
No cyclic transmission.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
1
Enable cyclic transmission.
OBI
Odd Byte Count Indicator
Setting this bit together with bit XME indicates the number of bytes
written to XFF.XFIFO is odd. This means the lower byte of the last write
transfer to the transmit FIFO is valid only. In HDLC mode the status byte
written to transmit FIFO must be included in calculation.
0
1
Even number of bytes stored in XFF.XFIFO.
Odd number of bytes stored in XFF.XFIFO.
XHF
Transmit HDLC frame
Setting this bit indicates that the contents written to XFF.XFIFO shall be
transmitted as HDLC frame. If data written to XFF.XFIFO completes a
HDLC frame, bit XME must be set together with XHF in order to generate
CRC and flag.
0
1
No function
Transmit data stored in XFF.XFIFO in HDLC format.
XTF
Transmit transparent frame
Setting this bit indicates that the contents written to XFF.XFIFO shall be
transmitted in transparent mode.
0
1
No function
Transmit data stored in XFF.XFIFO fully transparent, i.e. without
bit stuffing and CRC.
XME
Transmit Message End
Setting this bit indicates that the last data block written to XFF.XFIFO
completes the current frame. The last byte of the data block written to the
transmit FIFO is a status word indicating the message status. The
signalling controller terminates the transmission properly by appending
CRC and the closing flag to the data sequence if the status word written
as the last entry to the transmit FIFO does not contain an abort
indication.
•
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
Table 8-8
Signalling Controller Transmit Commands
XRES XREP OBI
XHF
XTF XME Function
1
0
-
-
-
-
-
Reset Port
0
0
1
0
0
Transmit HDLC Frames
Send FIFO content as HDLC frame.
0
0
1
0/1
0/1
1
1
0
0
1
0
End Transmit HDLC
Send FIFO content as HDLC frame.
Add CRC (if enabled) and flag after last
byte stored in FIFO.
0
Repeat HDLC Frame
Send FIFO content as HDLC frame.
Add CRC (if enabled) and flag after last
byte stored in FIFO. Then repeat
transmission of FIFO content.
0
1
0/1
1
0
1
Stop Repeat HDLC Frame
Stop transmission after last byte stored
in FIFO. This command is issued when
repetitive transmission started by
command ’Repeat HDLC Frame’ shall
be stopped.
0
0
0
0
0
0
0
1
1
0
1
Transmit Transparent
Send FIFO content in transparent
mode.
0/1
End Transmit Transparent
Send FIFO content in transparent
mode. End transmission after last byte
stored in FIFO.
0
0
1
1
0/1
0/1
0
0
1
1
0
1
Repeat Transmit Transparent
Send FIFO content in transparent
mode. Repeat transmission of FIFO
content after last byte was sent.
Stop Repeat Transmit Transparent
Stop transparent transmission after
last byte stored in FIFO. This
command is issued when repetitive
transmission started by command
’Repeat transmit transparent’ shall be
stopped.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
MSK
Interrupt Mask Register
Access
: read/write
: 08H
Address
Reset Value
: 0000H
15
11
10
9
8
4
3
2
1
0
0
0
0
0
TXSA ALLS XDU XPR
0
0
0
RSA SSM RPF RME ISF
For each facility data link interrupt vector an interrupt vector generation mask is provided.
Generation of an interrupt vector itself does not necessarily result in assertion of the
interrupt pin. For description of interrupt concept and interrupt vectors see "Layer One
Interrupts" on page 136.
The following definition applies:
1
0
The corresponding interrupt vector will not be generated by the device.
The corresponding interrupt vector will be generated.
Facility Data Link Interrupt Vector Transmit
TXSA
ALLS
XDU
XPR
Mask ’Transmit Sa Data’
Mask ’All Sent’
Mask ’’Transmit Data Underrun’
Mask ’Transmit Pool Ready’
Facility Data Link Interrupt Vector Receive
RSA
SSM
RPF
RME
ISF
Mask ’Receive Sa Data Valid’
Mask ’Synchronization Status Message Received’
Mask ’Receive Pool Full’
Mask ’Receive Message End’
Mask ’Incorrect Synchronization Format’
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
RAL
Receive Address Low
Access
: read/write
Address
: 09H
Reset Value
: 0000H
15
8
7
0
RAL2(7:0)
RAL1(7:0)
RAL2
RAL1
Receive Address Low Byte
This bit field defines the low byte of the second receive address.
Receive Address Low Byte
This bit field defines the low byte of the first receive address.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
RAH
Receive Address High
Access
: read/write
Address
: 0AH
Reset Value
: 0000H
15
8
7
0
RAH2(7:0)
RAH1(7:0)
RAH2
RAH1
Receive Address High Byte
This bit field defines the high byte of the second receive address.
Receive Address High Byte
This bit field defines the high byte of the first receive address.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
RSAW1
Receive Sa Word 1
Access
: read
Address
: 0BH
Reset Value
: 0000H
15
8
7
0
SA5(7:0)
SA4(7:0)
SA5
Received Sa5 Data Byte
This bit field contains data received in Sa5 of an E1 doubleframe or an E1
CRC-4 multiframe.
E1: CRC-4 Multiframe
Received data byte is aligned to a multiframe boundary. SA5(0) is the
data bit receive in frame one, while SA5(7) is the data byte received in
frame 15 of a multiframe.
SA4
Received Sa4 Data Byte
This bit field contains data received in Sa4 of an E1 doubleframe or an E1
multiframe.
E1: CRC-4 Multiframe
Received data byte is aligned to a multiframe boundary. SA4(0) is the
data bit receive in frame one, while SA4(7) is the data byte received in
frame 15 of a multiframe.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
RSAW2
Receive Sa Word 2
Access
: read
Address
: 0CH
Reset Value
: 0000H
15
8
7
0
SA7(7:0)
SA6(7:0)
SA7
Received Sa7 Data Byte
This bit field contains data received in Sa7 of an E1 doubleframe or an E1
CRC-4 multiframe.
E1: CRC-4 Multiframe
Received data byte is aligned to a multiframe boundary. SA7(0) is the
data bit receive in frame one, while SA7(7) is the data byte received in
frame 15 of a multiframe.
SA6
Received Sa6 Data Byte
This bit field contains data received in Sa6 of an E1 doubleframe or an E1
multiframe.
E1: CRC-4 Multiframe
Received data byte is aligned to a multiframe boundary. SA6(0) is the
data bit receive in frame one, while SA6(7) is the data byte received in
frame 15 of a multiframe.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
RSAW3
Receive Sa Word 3
Access
: read
Address
: 0DH
Reset Value
: 0000H
15
8
7
0
0
0
0
0
0
0
0
SADV
SA8(7:0)
SADV
Received Sa4..Sa8 Data Valid
This bit indicates that new Sa data in register RSAW1..RSAW3 is
available. The signalling controller will not update Sa data while this bit is
set. SADV will be cleared on reads to this register.
0
1
No Sa data available.
Sa data available in register RSAW1..RSAW3.
SA8
Received Sa8 Data Byte
This bit field contains data received in Sa8 of an E1 doubleframe or an E1
multiframe.
E1: CRC-4 Multiframe
Received data byte is aligned to a multiframe boundary. SA8(0) is the
data bit receive in frame one, while SA8(7) is the data byte received in
frame 15 of a multiframe.
Preliminary Data Sheet
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PEB 20256M E
PEF 20256M E
Register Description
RSAW4
Receive Sa Word 4
Access
: read
Address
: 0EH
Reset Value
: 0000H
15
7
4
3
0
1
0
0
0
0
0
0
0
0
0
0
SSMD(3:0)
0
SSMV
SSMD
SSM Data Pattern
This bit field contains the received synchronization status message. The
synchronization status message reported depends on bit RCR2.PAS
and, if selected, on pattern enabled in register VSSM. Only valid if SSMV
is set.
SSMV
Synchronization Status Message Valid
This bit indicates that a new synchronization status message has been
received. A new SSM is reported every time a message has been
received three time in a row on the Sa-bit selected via register
RCR2.SASSM. This bit is reset after the user performs a read on this
register.
0
1
No new SSM data available.
New SSM data available.
Preliminary Data Sheet
380
11.99
PEB 20256M E
PEF 20256M E
Register Description
CRC1
CRC Status Counter 1
Access
: read
: 0FH
Address
Reset Value
: 0000H
15
0
CRCS1(15:0)
CRC1
CRC1 counter
The Sa-bit error indication counter CRC1 (16 bits) counts either the
received bit sequences 0001B and 0011B or user programmable values
specified in register VCRC in every submultiframe on a selectable Sa-bit.
In the primary rate access digital section CRC errors are reported from
the TE via Sa6. Incrementing is only possible in the multiframe
synchronous state.
The counter is increased with every received bit error indication if
enabled in register RCR2. The counter will not be incremented once it
reaches FFFFH. A read will clear this counter.
Preliminary Data Sheet
381
11.99
PEB 20256M E
PEF 20256M E
Register Description
CRC2
CRC Status Counter 2
Access
: read
: 10H
Address
Reset Value
: 0000H
15
0
CRCS(15:0)2
CRC2
CRC2 counter
The Sa-bit error indication counter CRC2 (16 bits) counts either the
received bit sequences 0010B and 0011B or user programmable values
specified in register VCRC in every submultiframe on a selectable Sa-bit.
In the primary rate access digital section CRC errors detected at T-
reference points are reported via Sa6. Incrementing is only possible in the
multiframe synchronous state.
The counter is increased with every received bit error indication if
enabled in register RCR2. The counter will not be incremented once it
reaches FFFFH. A read will clear this counter.
Preliminary Data Sheet
382
11.99
PEB 20256M E
PEF 20256M E
Register Description
XSAW1
Transmit Sa Word 1
Access
: read/write
Address
: 11H
Reset Value
: 0000H
15
8
7
0
SA5(7:0)
SA4(7:0)
SA5
Transmit Sa5 Data Byte
This bit field contains data to be transmitted in Sa5 of an E1 doubleframe
or an E1 CRC-4 multiframe. SA5 will be inserted into the data stream, if
selected via bit XCR2.SA5E.
E1: CRC-4 Multiframe
Transmit data will be aligned to a multiframe boundary. SA5(0) is the
data bit transmitted in frame one while SA5(7) is the data bit transmitted
in frame 15 of a multiframe.
SA4
Transmit Sa4 Data Byte
This bit field contains data to be transmitted in Sa4 of an E1 doubleframe
or an E1 CRC-4 multiframe. SA4 will be inserted into the data stream, if
selected via bit XCR2.SA4E.
E1: CRC-4 Multiframe
Transmit data will be aligned to a multiframe boundary. SA4(0) is the
data bit transmitted in frame one while SA4(7) is the data bit transmitted
in frame 15 of a multiframe.
Preliminary Data Sheet
383
11.99
PEB 20256M E
PEF 20256M E
Register Description
XSAW2
Transmit Sa Word 2
Access
: read/write
Address
: 12H
Reset Value
: 0000H
15
8
7
0
SA7(7:0)
SA6(7:0)
SA7
Transmit Sa7 Data Byte
This bit field contains data to be transmitted in Sa7 of an E1 doubleframe
or an E1 multiframe. SA7 will be inserted into the data stream, if selected
via bit XCR2.SA7E.
E1: CRC-4 Multiframe
Transmit data will be aligned to a multiframe boundary. SA7(0) is the
data bit transmitted in frame one while SA7(7) is the data bit transmitted
in frame 15 of a multiframe.
SA6
Transmit Sa6 Data Byte
This bit field contains data to be transmitted in Sa6 of an E1 doubleframe
or an E1 CRC-4 multiframe. SA6 will be inserted into the data stream, if
selected via bit XCR2.SA6E.
E1: CRC-4 Multiframe
Transmit data will be aligned to a multiframe boundary. SA6(0) is the
data bit transmitted in frame one while SA6(7) is the data bit transmitted
in frame 15 of a multiframe.
Preliminary Data Sheet
384
11.99
PEB 20256M E
PEF 20256M E
Register Description
XSAW3
Transmit Sa Word 3
Access
: read/write
Address
: 13H
Reset Value
: 0000H
15
0
14
13
8
7
0
XSAV
XSAR(5:0)
SA8(7:0)
XSAV
Sa Data Valid
This bit indicates that new Sa data has been written to register
XSAW1..XSAW3 from system processor.
0
1
No new Sa data available.
New Sa data available.
XSAR
Sa Data Repetitions
This bit field defines the number of repetitions of the Sa data bytes. A
’Transmit Sa Data’ interrupt vector will be generated after programmed
number of repetitions.
SA8
Transmit Sa8 Data Byte
This bit field contains data to be transmitted in Sa8 of an E1 doubleframe
or an E1 CRC-4 multiframe. SA8 will be inserted into the data stream, if
selected via bit XCR2.SA8E.
E1: CRC-4 Multiframe
Transmit data will be aligned to a multiframe boundary. SA8(0) is the
data bit transmitted in frame one while SA8(7) is the data bit transmitted
in frame 15 of a multiframe.
Preliminary Data Sheet
385
11.99
PEB 20256M E
PEF 20256M E
Register Description
VSSM
Valid SSM Pattern
Access
: read/write
Address
: 14H
Reset Value
: 0000H
15
0
PA(15:0)
PA
Pattern 15..0
Setting one or more of the bits enables the selected pattern for SSM
comparison. E.g. setting PA(3) and PA(1) enables pattern 0010B and
0001B for SSM comparison. Identified SSM pattern are reported via
register RSAW4.
Only valid if RCR2.PAS is set to ’1’.
Preliminary Data Sheet
386
11.99
PEB 20256M E
PEF 20256M E
Register Description
VCRC
Valid CRC Count Pattern
Access
: read/write
: 15H
Address
Reset Value
: 0000H
15
12
11
8
7
4
3
0
CRC22(3:0
CRC21(3:0)
CRC12(3:0)
CRC11(3:0)
CRC22
CRC21
CRC2 Pattern Definition
The bit fields CRC21 and CRC22 determine the Sa-bit error indication
pattern to be reported in register CRC2.
Only valid if RCR2.PAS is set to ’1’.
CRC12
CRC11
CRC1 Pattern Definition
The bit fields CRC11 and CRC12 determine the Sa-bit error indication
pattern to be reported in register CRC1.
Only valid if RCR2.PAS is set to ’1’.
Preliminary Data Sheet
387
11.99
PEB 20256M E
PEF 20256M E
Electrical Characteristics
9
Electrical Characteristics
9.1
Important Electrical Requirements
Both VDD3 and VDD25 can take on any power-on sequence. Within 50 milliseconds of
power-up the voltages must be within their respective absolute voltage limits. At power-
down, within 50 milliseconds of either voltage going outside its operational range, both
voltages must be returned below 0.1V.
9.2
Absolute Maximum Ratings
Absolute Maximum Ratings
Table 9-1
Parameter
Symbol
Limit Values
min max
Unit
Ambient temperature under bias
PEB 20256M E
TA
°C
0
70
PEF 20256M E
-40
85
Junction temperature under bias
Storage temperature
TJ
Tstg
VS
125
°C
°C
V
-65
125
Voltage on any pin with respect to ground
-0.4
VDD3+0.4
Note: Stresses above those listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
9.3
DC Characteristics
a) Power Supply Pins
Table 9-2
DC Characteristics
Parameter
Symbol
Limit Values
Unit Test Condition
min.
2.25
3.0
max.
Core Supply Voltage
I/O Supply Voltage
VDD25
VDD3
2.75
3.6
V
V
Preliminary Data Sheet
388
11.99
PEB 20256M E
PEF 20256M E
Electrical Characteristics
Parameter
Symbol
Limit Values
Unit Test Condition
min.
max.
< tbd
< 2
Core
operational
ICC25
mA
mA
supply
current
VDD25
power down ICCPD25
(no clocks)
I/O supply operational
current
ICC3
< tbd
< 2
mA Inputs at VSS/VDD3
No output loads.
power down ICCPD3
mA
VDD3
(no clocks)
Sum of Input leakage
current and
ILI
< 10
µA
Output leakage current
(Outputs Hi-z)
ILO
Power Dissipation
P
<3
W
b) Non-PCI Interface Pins
Table 9-3
DC Characteristics (Non-PCI Interface Pins)
TA = -40 to 85°C, VDD3 = 3.3 V ± 0.3 V, VDD25 = 2.5 V ± 0.25 V, VSS = 0 V
Parameter
Symbol
Limit Values
min. max.
-0.4 0.8
Unit Test Condition
L-input voltage
H-input voltage
L-output voltage
H-output voltage
VIL
VIH
V
V
2.0
VDD3+0.4
VOL
VOH
0.45
V
V
I
I
QL = 2 mA
2.4
QH = -400 µA
c) PCI Interface Pins
Table 9-4
DC Characteristics (PCI Interface Pins)
TA = -40 to 85°C, VDD3 = 3.3 V ± 0.3 V, VDD25 = 2.5 V ± 0.25 V, VSS = 0 V
Parameter
Symbol
Limit Values
min. max.
-0.5 0.3VDD3
Unit Test Condition
L-input voltage
H-input voltage
VIL
VIH
V
V
0.5VDD3 VDD3+0.5
Preliminary Data Sheet
389
11.99
PEB 20256M E
PEF 20256M E
Electrical Characteristics
Parameter
Symbol
Limit Values
Unit Test Condition
min.
max.
0.1VDD3
L-output voltage
H-output voltage
VOL
VOH
V
V
I
I
QL = 1500 µA
QH = -500 µA
0.9VDD3
9.4
AC Characteristics
a) Non-PCI interface pins
TA = -40 to 85°C, VDD3 = 3.3 V ± 0.3 V, VDD25 = 2.5 V ± 0.25 V, VSS = 0 V
Inputs are driven to 2.4 V for a logical ‘1’ and to 0.4 V for a logical ‘0’. Timing
measurements are made at 2.0 V for a logical ‘1’ and at 0.8 V for a logical ‘0’.
The AC testing input/output waveforms are shown below.
•
2.4
2.0
0.8
2.0
0.8
Device
Under
Test
test points
0.45
C
load = 50pF
Figure 9-1
Input/Output Waveform for AC Tests
b) PCI interface pins
PCI interface pins are measured as pins compliant to the 3.3V signalling environment
according to the PCI Specification Rev. 2.1.
Preliminary Data Sheet
390
11.99
PEB 20256M E
PEF 20256M E
Electrical Characteristics
9.4.1
PCI Bus Interface Timing
•
tcyc
thigh
tlow
0.6 VDD3
0.5 VDD3
0.4 VDD3
0.4 VDD3, p-to-p
(minimum)
0.3 VDD3
0.2 VDD3
Figure 9-2
PCI Clock Cycle Timing
Table 9-5
PCI Clock Characteristics
Symbol
Parameter
Limit Values
Unit
min.
15
6
max.
CLK cycle time
tcyc
thigh
tlow
ns
ns
CLK high time
CLK low time
6
ns
CLK slew rate (see note)
1.5
4
V/ns
Note: Rise and fall times are specified in terms of the edge rate measured in V/ns. This
slew rate must be met across the minimum peak-to-peak portion of the clock
waveform shown in Figure 9-3.
•
Vth
Clock
Vtest
th
Inputs valid
Vtl
tsu
Vth
Vtl
Input delay
Vtest
Vtest
Vmax
Figure 9-3
PCI Input Timing Measurement Conditions
Preliminary Data Sheet
391
11.99
PEB 20256M E
PEF 20256M E
Electrical Characteristics
•
Vth
Vtl
Clock
Vtest
tval
Output delay
Vtest
toff
ton
Tri-state output
Vtest
Vtest
Figure 9-4
PCI Output Timing Measurement Conditions
PCI Interface Signal Characteristics
Table 9-6
Parameter
Symbol
Limit Values
Unit
Notes
min.
max.
CLK to signal valid - bussed
signals
tval
2
6
ns
1, 2
1, 2
CLK to REQ valid
Float to active delay
Active to float delay
tval
ton
toff
tsu
2
2
6
ns
ns
14
Input setup time to CLK - bussed
signals
3
2
2
Input setup time to CLK - GNT
Input hold time from CLK
tsu
th
5
0
Note:
1. Minimum times are measured for 3.3V signalling environment according to the PCI
Specification Rev. 2.1.
2. REQ and GNT are point-to-point signals. All other signals are bussed.
Preliminary Data Sheet
392
11.99
PEB 20256M E
PEF 20256M E
Electrical Characteristics
9.4.2
SPI Interface Timing
•
SPCS
SPCLK
1
3
4
2
5
6
SPSO
SPSI
7
8
Figure 9-5
SPI Interface Timing
SPI Interface Timing
Table 9-7
•
No. Parameter
Limit Values
Unit
Notes
min.
500
500
500
500
max.
1
2
3
4
5
6
7
8
SPCS low to SPCLK delay
ns
ns
ns
ns
ns
ns
ns
ns
1
SPCLK to SPCS delay
SPCLK high time
SPCLK low time
SPCS to SPSO delay
SPCLK to SPSO delay
SPSI to SPCLK setup time
SPSI to SPCLK hold time
100
100
100
100
Note:
1
SPI clock is related to PCI clock where the SPI frequency is 1/78 of the PCI
frequency. All timings for SPI interface are calculated with a PCI clock running at 33
MHz.
Preliminary Data Sheet
393
11.99
PEB 20256M E
PEF 20256M E
Electrical Characteristics
9.4.3
Local Microprocessor Interface Timing
9.4.3.1 Intel Bus Interface Timing (Slave Mode)
•
LA
20
22
21
LCS0
LRD
LRDY
LD
32
23
24
25
28
26
27
29
Figure 9-6
Intel Read Cycle Timing (Slave Mode)
•
LA
20
22
21
LCS0
LWR
LRDY
32
23
24
25
31
26
30
LD
Figure 9-7
Intel Write Cycle Timing (Slave Mode)
Preliminary Data Sheet
394
11.99
PEB 20256M E
PEF 20256M E
Electrical Characteristics
Table 9-8
Intel Bus Interface Timing
No. Parameter
Limit Values
Unit
min.
20
0
max.
20 LA to LRD, LWR setup time
21 LA to LRD, LWR hold time
22 LCS0 to LRD, LWR setup time
23 LCS0 to LRD, LWR hold time
24 LCS0 low to LRDY active delay
25 LRD, LWR high to LRDY high delay
26 LCS0 high to LRDY float delay
27 LRD low to LD active delay
28 LRD high to LD float delay
29 LRDY low to LD valid delay
30 LD to LWR setup time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
0
20
20
20
20
20
20
20
5
31 LD to LWR hold time
32 LRD, LWR minimum high time
20
Preliminary Data Sheet
395
11.99
PEB 20256M E
PEF 20256M E
Electrical Characteristics
9.4.3.2 Intel Bus Interface Timing (Master Mode)
•
LCLK
60a
60b
61b
LA
61a
LCS2,1
62a
62b
LBHE
63a
65
63b
LRD
LRDY
LD
66
67a
67b
Figure 9-8
Intel Read Cycle Timing (Master Mode, LRDY controlled)
•
LCLK
60a
61a
62a
63a
60b
61b
62b
63b
LA
LCS2,1
LBHE
LWR
LRDY
LD
65
66
69a
69b
Figure 9-9
Intel Write Cycle Timing (Master Mode, LRDY controlled)
Preliminary Data Sheet
396
11.99
PEB 20256M E
PEF 20256M E
Electrical Characteristics
•
WS*tCYC
LCLK
LA
60a
61a
62a
63a
60b
61b
LCS2,1
LBHE
LRD
62b
63b
68a
68b
LD
Figure 9-10 Intel Read Cycle Timing (Master Mode, Wait state controlled)
•
WS*tCYC
LCLK
60a
61a
62a
63a
69a
60b
61b
62b
63b
69b
LA
LCS2,1
LBHE
LWR
LD
Figure 9-11 Intel Write Cycle Timing (Master Mode, Wait state controlled)
Preliminary Data Sheet
397
11.99
PEB 20256M E
PEF 20256M E
Electrical Characteristics
•
LCLK
Read/
Write
70
71
LHOLD
LHLDA
72
Figure 9-12 Intel Bus Arbitration Timing
Table 9-9
Intel Bus Interface Timing (Master Mode)
No. Parameter
Limit Values
Unit
min.
2
max.
10
60a LCLK to LA active delay
60b LCLK to LA float delay
ns
ns
2
10
61a LCLK to LCS2,1 active delay
61b LCLK to LCS2,1 float delay
62a LCLK to LBHE active delay
62b LCLK to LBHE float delay
63a LCLK to LRD, LWR active delay
63b LCLK to LRD, LWR float delay
65 LRDY low to LRD, LWR high delay
66 LRDY to LRD, LWR hold time
67a LD to LRDY setup time
2
10
ns
2
10
ns
2
10
ns
2
10
ns
2
10
ns
2
10
ns
2
tCYC
ns
0
0
ns
67b LD to LRDY hold time
0
ns
68a LD to LCLK setup time
10
5
ns
68b LD to LCLK hold time
ns
69a LCLK to LD delay
2
10
10
10
ns
69b LCLK to LD float delay
2
ns
70 LCLK to LHOLD delay
2
ns
71 LHLDA asserted to Read/Write Cycle start
72 LHLDA minimum pulse width
1
tCYC
tCYC
2
Note: tCYC is the clock period of the PCI clock.
Preliminary Data Sheet
398
11.99
PEB 20256M E
PEF 20256M E
Electrical Characteristics
9.4.3.3 Motorola Bus Interface Timing (Slave Mode)
•
LA
40
42
41
LCS0
54
43
45
LDS
44
LRDWR
LDTACK
46
47
48
49
50
51
LD
Figure 9-13 Motorola Read Cycle Timing (Slave Mode)
•
LA
40
42
41
LCS0
LDS
54
43
45
44
LRDWR
LDTACK
46
47
48
52
53
LD
Figure 9-14 Motorola Write Cycle Timing (Slave Mode)
Preliminary Data Sheet
399
11.99
PEB 20256M E
PEF 20256M E
Electrical Characteristics
Table 9-10 Motorola Bus Interface Timing
No. Parameter
Limit Values
Unit
min.
20
0
max.
40 LA to LDS setup time
ns
41 LA to LDS hold time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
42 LCS0 to LDS setup time
43 LCS0 to LDS hold time
20
0
44 LRDWR to LDS setup time
45 LRDWR to LDS hold time
46 LCS0 low to LDTACK active delay
47 LDS high to LDTACK high delay
48 LCS0 high to LDTACK float delay
49 LDS low to LD active delay
50 LDS high to LD float delay
51 LDTACK low to LD valid delay
52 LD to LDS setup time
20
0
20
20
20
20
20
20
20
5
53 LD to LDS hold time
54 LDS minimum high time
20
Preliminary Data Sheet
400
11.99
PEB 20256M E
PEF 20256M E
Electrical Characteristics
9.4.3.4 Motorola Bus Interface Timing (Master Mode)
•
LCLK
LA
80a
81a
82a
83a
84a
80b
81b
82b
83b
84b
LCS2,1
LSIZE0
LRDWR
LDS
85
86
LDTACK
LD
87a
87b
Figure 9-15 Motorola Read Cycle Timing (Master Mode, LDTACK controlled)
•
LCLK
80a
81a
82a
83a
84a
80b
81b
82b
83b
84b
LA
LCS2,1
LSIZE0
LRDWR
LDS
85
86
LDTACK
LD
89a
89b
Figure 9-16 Motorola Write Cycle Timing (Master Mode, LDTACK controlled)
Preliminary Data Sheet
401
11.99
PEB 20256M E
PEF 20256M E
Electrical Characteristics
•
WS*tCYC
LCLK
LA
80a
81a
82a
83a
84a
80b
81b
82b
83b
84b
LCS2,1
LSIZE0
LRDWR
LDS
88a
88b
LD
Figure 9-17 Motorola Read Cycle Timing (Master Mode, Wait state controlled)
•
WS*tCYC
LCLK
80a
81a
82a
83a
84a
89a
80b
81b
82b
83b
84b
89b
LA
LCS2,1
LSIZE0
LRDWR
LDS
LD
Figure 9-18 Motorola Write Cycle Timing (Master Mode, Wait state controlled)
Preliminary Data Sheet
402
11.99
PEB 20256M E
PEF 20256M E
Electrical Characteristics
•
LCLK
Read/
Write
90
91
LBR
LBG
92
94
93
LBGACK
Figure 9-19 Motorola Bus Arbitration Timing
Table 9-11 Motorola Bus Interface Timing (Master Mode)
No. Parameter
Limit Values
Unit
min.
2
max.
10
10
10
10
10
10
10
10
10
10
80a LCLK to LA active delay
80b LCLK to LA float delay
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCYC
ns
ns
ns
ns
ns
ns
2
81a LCLK to LCS2,1 active delay
81b LCLK to LCS2,1 float delay
82a LCLK to LSIZE0 active delay
82b LCLK to LSIZE0 float delay
83a LCLK to LRDWR active delay
83b LCLK to LRDWR float delay
84a LCLK to LDS active delay
84b LCLK to LDS float delay
85 LDTACK low to LDS high delay
86 LDTACK to LDS hold time
87a LD to LDTACK setup time
87b LD to LDTACK hold time
88a LD to LCLK setup time
88b LD to LCLK hold time
2
2
2
2
2
2
2
2
2
0
0
0
10
5
89a LCLK to LD delay
2
10
Preliminary Data Sheet
403
11.99
PEB 20256M E
PEF 20256M E
Electrical Characteristics
No. Parameter
Limit Values
Unit
min.
max.
10
89b LCLK to LD float delay
90 LCLK to LBR delay
2
2
1
0
1
2
ns
ns
10
91 LBGACK to LBR delay
92 LBG to LBGACK hold time
93 LBG to LBGACK delay
94 LCLK to LBGACK delay
tCYC
ns
tCYC
ns
10
Note: tCYC is the clock period of the PCI clock.
Preliminary Data Sheet
404
11.99
PEB 20256M E
PEF 20256M E
Electrical Characteristics
9.4.4
Serial Interface Timing
9.4.4.1 DS3 Serial Interface Timing
Note: The clock input timings are calculated assuming a PCI clock frequency of 33 MHz
or more.
•
100
101
102
TC44
RC44
103
104
Figure 9-20 Clock Input Timing
Table 9-12 Clock Input Timing
No. Parameter
Limit Values
Unit
min.
max.
100 Clock frequency
101 Clock high timing
102 Clock low timing
103 Clock fall time
104 Clock rise time
nom. 44.736
MHz
ns
7.5
7.5
ns
2
2
ns
ns
Preliminary Data Sheet
405
11.99
PEB 20256M E
PEF 20256M E
Electrical Characteristics
•
TC44
RC44
(Note 1)
110
110
TC44O
Figure 9-21 DS3 Transmit Cycle Timing
Note:
1. Actual clock reference depends on selected clock mode:
•
TC44O
(Note 2)
TC44O
(Note 3)
111
TD44, TD44P/N
Figure 9-22 DS3 Transmit Data Timing
Note:
2. Timing for transmit data which is updated on the rising edge of TC44O.
3. Timing for transmit data which is updated on the falling edge of TC44O.
Table 9-13 DS3 Transmit Cycle Timing
No. Parameter
Limit Values
Unit
min.
2
max.
15
110 RC44, TC44 to TC44O delay
ns
ns
111 TC44O to TD44, TD44P/TD44N delay
-5
5
Preliminary Data Sheet
406
11.99
PEB 20256M E
PEF 20256M E
Electrical Characteristics
•
RC44
(Note 1)
RC44
(Note 2)
130
131
RD44, RD44P/N
Figure 9-23 DS3 Receive Cycle Timing
Note:
1. Timing for data which is sampled on the rising edge of the receive clock.
2. Timing for data which is sampled on the falling edge of the receive clock.
Table 9-14 DS3 Receive Cycle Timing
No. Parameter
Limit Values
Unit
min.
max.
130 RD44, RD44P/RD44N to RC44 setup time
131 RD44, RD44P/RD44N to RC44 hold time
5
5
ns
ns
Preliminary Data Sheet
407
11.99
PEB 20256M E
PEF 20256M E
Electrical Characteristics
•
CLK
RLOS
RLOF
RAIS
132
132
132
132
RRED
Figure 9-24 DS3 Status Signal Timing
Note: Status signals are generated synchronous to the PCI clock.
Table 9-15 DS3 Status Signal Timing
No. Parameter
Limit Values
Unit
min.
max.
132 CLK to RLOS/RLOF/RAIS/RRED delay
2
10
ns
Preliminary Data Sheet
408
11.99
PEB 20256M E
PEF 20256M E
Electrical Characteristics
9.4.4.2 Overhead Bit Timing
•
TOVHCK
150
TOVHSYN
(Output Mode)
153
154
156
TOVHD
155
TOVHEN
Figure 9-25 DS3 Transmit Overhead Timing
•
TC44O
151
152
TOVHSYN
(Input Mode))
Figure 9-26 DS3 Transmit Overhead Synchronization Timing
Table 9-16 DS3 Transmit Overhead Timing
No. Parameter
Limit Values
Unit
min.
max.
150 TOVHCK to TOVHSYN delay
151 TOVHSYN to TCLKO44 setup time
152 TOVHSYN to TCLKO44 hold time
153 TOVD to TOVHCK setup time
154 TOVD to TOVHCK hold time
155 TOVHEN to TOVHCK setup time
156 TOVHEN to TOVHCK hold time
75
ns
ns
ns
ns
ns
ns
ns
5
5
25
5
25
5
Preliminary Data Sheet
409
11.99
PEB 20256M E
PEF 20256M E
Electrical Characteristics
•
ROVHCK
ROVHSYN
ROVHD
157
158
Figure 9-27 DS3 Receive Overhead Timing
Table 9-17 DS3 Receive Overhead Timing
No. Parameter
Limit Values
Unit
min.
max.
75
157 ROVHCK to ROVHSYN delay
158 ROVHCK to ROVHD delay
ns
ns
75
Preliminary Data Sheet
410
11.99
PEB 20256M E
PEF 20256M E
Electrical Characteristics
9.4.4.3 Stuff Bit Timing
•
TSBCK
TSBD
160
161
Figure 9-28 DS3 Transmit Stuff Bit Timing
Table 9-18 DS3 Transmit Stuff Timing
No. Parameter
Limit Values
Unit
min.
25
max.
160 TSBD to TSBCK setup time
161 TSBD to TSBCK hold time
ns
ns
5
•
RSBCK
162
RSBD
Figure 9-29 DS3 Receive Stuff Bit Timing
Table 9-19 DS3 Receive Stuff Bit Timing
No. Parameter
Limit Values
Unit
min.
max.
162 RSBCK to RSBD delay
75
ns
Preliminary Data Sheet
411
11.99
PEB 20256M E
PEF 20256M E
Electrical Characteristics
9.4.4.4 T1/E1 Tributary Timing
•
105
106
107
CTCLK
108
109
Figure 9-30 T1/E1 Tributary Clock Input Timing
Table 9-20 T1/E1 Tributary Clock Input Timing
No. Parameter
Limit Values
min. typ max.
Unit
Tributaries operated in E1 Mode
105 Clock frequency
106 Clock high timing
107 Clock low timing
108 Clock fall time
2.048 MHz ± 50 ppm
40
40
10
10
ns
ns
ns
ns
109 Clock rise time
Tributaries operated in T1 Mode
105 Clock frequency
106 Clock high timing
107 Clock low timing
108 Clock fall time
1.544 MHz ± 130 ppm
40
40
10
10
ns
ns
ns
ns
109 Clock rise time
Preliminary Data Sheet
412
11.99
PEB 20256M E
PEF 20256M E
Electrical Characteristics
•
CTCLK
CTCLK
CTFS
120
121
Figure 9-31 T1/E1 Tributary Synchronization Timing
Table 9-21 T1/E1 Tributary Synchronization Timing
No. Parameter
Limit Values
Unit
min.
max.
120 CTFS to CTCLK setup time
121 CTFS to CTCLK hold time
5
5
ns
ns
Preliminary Data Sheet
413
11.99
PEB 20256M E
PEF 20256M E
Electrical Characteristics
9.4.4.5 Test Port Timing
•
170
171
172
TTCLK
173
174
Figure 9-32 T1/E1 Test Transmit Clock Timing
Table 9-22 T1/E1 Test Transmit Clock Timing
No. Parameter
Limit Values
min. typ max.
Unit
Test port operated in E1 Mode
170 Clock period
2.048 MHz ± 50 ppm
171 Clock high timing
172 Clock low timing
173 Clock fall time
100
100
10
ns
ns
ns
ns
174 Clock rise time
Test port operated in T1 Mode
170 Clock period
10
1.544 MHz ± 130 ppm
171 Clock high timing
172 Clock low timing
173 Clock fall time
100
100
10
ns
ns
ns
ns
174 Clock rise time
10
Preliminary Data Sheet
414
11.99
PEB 20256M E
PEF 20256M E
Electrical Characteristics
•
TTCLK
TTD
175
176
Figure 9-33 T1/E1 Test Transmit Data Timing
Table 9-23 T1/E1 Test Transmit Data Timing
No. Parameter
Limit Values
Unit
min.
25
max.
175 TTD(x) to TTC(x) setup time
176 TTD(x) to TTC(x) hold time
ns
ns
75
•
180
181
182
TRCLK
Figure 9-34 T1/E1 Test Receive Clock Timing
Table 9-24 T1/E1 Test Receive Clock Timing
No. Parameter
Limit Values
Unit
min.
typ
max.
Test port operated in E1 Mode
180 Clock period
469
156
312
2056
335
ns
ns
ns
181 Clock high timing
182 Clock low timing
Test Port operated in T1 Mode
180 Clock period
1900
625
310
310
1587
495
ns
ns
ns
181 Clock high timing
182 Clock low timing
1275
Preliminary Data Sheet
415
11.99
PEB 20256M E
PEF 20256M E
Electrical Characteristics
•
TRCLK
TRD
185
Figure 9-35 T1/E1 Test Receive Data Timing
Table 9-25 Test T1/E1 Receive Data Timing
No. Parameter
Limit Values
Unit
min.
max.
185 RTC(x) to RTD(x) delay
-5
25
ns
Preliminary Data Sheet
416
11.99
PEB 20256M E
PEF 20256M E
Electrical Characteristics
9.4.5
JTAG Interface Timing
•
TRST
200
201
202
TCK
203
205
204
206
TMS
TDI
207
TDO
Figure 9-36 JTAG Interface Timing
Table 9-26 JTAG Interface Timing
No. Parameter
Limit Values
min. max.
Unit
200 TCK period
120
60
60
20
20
20
20
50
ns
ns
ns
ns
ns
ns
ns
ns
201 TCK high time
202 TCK low time
203 TMS setup time
204 TMS hold time
205 TDI setup time
206 TDI hold time
207 TDO valid time
Preliminary Data Sheet
417
11.99
PEB 20256M E
PEF 20256M E
Electrical Characteristics
9.4.6
Reset Timing
•
power-on
VDD3
CLK
RST
221
220
Figure 9-37 Reset Timing
Table 9-27 Reset Timing
No. Parameter
Limit Values
Unit
min.
120
2
max.
220 RST pulse width
ns
221 Number of CLK cycles during RST active
CLK
cycles
Preliminary Data Sheet
418
11.99
PEB 20256M E
PEF 20256M E
Package Outline
10
Package Outline
•
Preliminary Data Sheet
419
11.99
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