PEB1760 [INFINEON]

Mapper/Framer for STM-4/STS-12 and STM-1/STS-3; 映射器/成帧器对于STM -4 / STS-12和STM -1 / STS-3


型号：	PEB1760
厂家：	Infineon
描述：	Mapper/Framer for STM-4/STS-12 and STM-1/STS-3 映射器/成帧器对于STM -4 / STS-12和STM -1 / STS-3
文件：	总2页 (文件大小：207K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

P R O D U C T B R I E F

Mapper/Framer for STM-4/STS-12

and STM-1/STS-3

The MetroMapper™ 622 is a mapper/framer capa-

ble of mapping datacom traffic into SONET/SDH

transport payloads. On the line side, the

MetroMapper™ 622 supports protected

STS-12/STM-4 and STS-3/STM-1 interfaces. On

the client side, up to sixteen Ethernet interfaces

(10/100 Mbps), two 1 GE and one OIF SPI-3 inter-

face with up to 64 logical channels are provided.

The Ethernet traffic or the packets coming from

the SPI-3 interface are encapsulated by either the

GFP-F, LAPS (X.85/.86) or PPP mapping scheme.

Low-order and high-order virtual concatenation

(VCAT) with Link Capacity Adjustment Schemes

(LCAS) for up to 64 virtual concatenated channels

is supported. MetroMapper™ 622 provides Ether-

net IEEE802.1q VLAN operations and enables

Ethernet over MPLS.

MetroMapper™ 622

Applications

I Provides full performance moni-

toring for high- and low-order

paths

- N × VC-3, N × STS1 SPE

(N ≤ 12)

I Access / edge aggregation

I MSPP

- N × VC-4, N × STS3c SPE

(N ≤ 4)

I Provides high-order and low-order

virtual concatenation according to

ITU-T G.707

I ADM

I Provides flexible mapping of any

VCG into any VC-4/STS-3

I Mapper mode: packets are

mapped between Ethernet and

SDH/SONET interfaces

I Packet mode: packets from the

SPI-3 interface are forwarded to

SDH/SONET and Ethernet inter-

faces, and vice versa

I Supports up to 64 virtual concate- I Fully integrated support for the

nated groups (VCG)

LinkCapacity Adjustment Scheme

(LCAS) protocol according to

ITU-T G. 7042

I Flexible concatenation of up to

12 high-order paths and up to

64 low-order paths into any virtual

concatenation group

I Provides hitless increase and

decrease of multiple members

VCG

I Supports up to 336 VT1.5 or

252 TU12 low-order paths

I Provides following mapping

schemes:

Features

Framer

SPI-3 Interface

I 64 logical channels each of them

running in 32-bit mode

I Packet mode with variable block

length

I Multi-Rate SONET/SDH framer

with STS/AU and VT/TU pointer

processing capabilities

I Processes a single

- AU-4 / VC-4 / TUG-3

- AU-3 / VC-3 or STS-1 / STS-SPE

I External buffer for up to 48 ms

differential delay compensation

I Different VCG group types are

defined:

STS-12/STM-4 or a quad

STS-3/STM-1

I Supports 1+1 line protection

I Payload Pointer interpretation and

generation

- N × VC-12, N × VC-11,

N × VT1.5 SPE, N × VT2 SPE

(N ≤ 64)

I Fully SONET/SDH compliant

M e t r o M a p p e r ™ 6 2 2

P E B 1 7 6 0

N e v e r s t o p t h i n k i n g .

P R O D U C T B R I E F

Features (cont’d)

I VLAN update include tag, retag and

I All Ethernet ports may operate in MAC

or PHY mode:

replace of VLAN IDs

Encapsulation/Decapsulation

I Provides GFP-F mapping according

to T1X1.5 / ITU-T G. 7041

I PPP processing according to

IETF RFC 1662

I 0 or 1 VLAN can be inserted/removed

I Supports VLAN double tagging

I IETF Ethernet Martini MPLS label

encapsulation per port/VLAN pair

I Supports IP/MPLS and Ethernet

packets

- PHY mode allows glueless connec-

tions to another MAC/Ethernet

switch

I Each Ethernet port maps to a single

VCG

I LAPS processing according to ITU-T

X.85+X.86

Diagnostics

I Per port tunneling mode

I Per port Ethernet MAC termination

mode with packet classification as

Ethernet, IP, MPLS or Layer-2 control

packets

I 64 logical channels, each of them can

be independently configured to oper-

ate in one of the three encapsulation

protocols

I Various loop back modes for system

debugging implemented

- Per SDH/SONET port Rx to Tx

- Per Ethernet port in to out

- SPI-3 input to SPI-3 output

I PPP protocol support: MPLS Unicast

& IP Version 4/6

Ethernet

Interfaces

I LAPS protocol support: Ethernet and

IP Version 4/6

I Two Gigabit Ethernet MACs with TBI

Interfaces

I Source synchronous STS-12/STM-4

or quad STS-3/STM-1 interfaces for

working and protected links operating

at 155 MHz I/Os

I FCS generation/checking

I Optional payload scrambling

I Idle frame insertion/deletion

I GFP Client management frame inser-

tion/detection

I Sixteen Ethernet/Fast Ethernet with

integrated SS-SMII Interfaces

I Per port MIB statistic counter per

direction

I OIF compliant SPI-3 interface

I Two TBI interfaces for GE

I 16 SS-SMII interfaces for FE

I Depending on application, up to

5 SRAM interfaces 32/36 bits data

bus

I MAC pause frame control per port via:

- Flexible leaky bucket implementation

- Current RxFIFO threshold level

- Under software control

I Comprehensive statistic counters for

packets

I Packet import/export from/to CPU

interface

I Flow control makes use of external

memory for both directions

I Fixed Rx Buffer size: 32 kB for FE and

256 kB for GE ports

I 66 MHz CPU interface

I IEEE 1149.1 JTAG boundary scan

interface

Layer 2

I Supported on both SDH and Ethernet

ports

I 1.5 V Core

I Received flow control frames are

passed through or discarded

I Jumbo packets supported

I IEEE802.1q VLAN tag operations per

port/VLAN pair

I 2.5 V and 3.3 V IOs

I 1020 pin FCBGA package

I Up to 4096 port/VLAN pairs in total

Application Example

Quad STM-1

Single STM-4

SMII

TDM

working &

MetroMapper^TM622

protect

SMII

Ethernet

Switch

SMII

STM-4 / STS-12

VC-LCAS

TBI

Mapper&Framer

Up to 2 TBI or 16 SMII

Ethernet over SDH/SONET

How to reach us:

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gerous substances. For information on the types in question

please contact your nearest Infineon Technologies Office.

Published by

Infineon Technologies AG,

St.-Martin-Strasse 53,

D-81669 München

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support devices or systems with the express written approval

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reasonably be expected to cause the failure of that life-support

device or system, or to affect the safety or effectiveness of that

device or system. Life support devices or systems are intended

to be implanted in the human body, or to support and/or main-

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may be endangered.

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descriptions and charts stated herein.

Information

For further information on technology, delivery terms

and conditions and prices please contact your nearest

Infineon Technologies Office.

Template: pb_tmplt.fm/4/2003-07-01

Ordering No. B115-H8290-X-X-7600

Printed in Germany

Published by Infineon Technologies AG

PS 1003.5

R&L

PEB1760 [INFINEON]

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