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IRFR3711ZTRL [INFINEON]

High Frequency Synchronous Buck Converters for Computer Processor Power; 高频同步降压转换器，用于计算机处理器电源
IRFR3711ZTRL
型号： IRFR3711ZTRL
厂家： Infineon    Infineon
描述：

High Frequency Synchronous Buck Converters for Computer Processor Power
高频同步降压转换器，用于计算机处理器电源

晶体 转换器 晶体管 功率场效应晶体管 开关 脉冲 计算机
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中文：  中文翻译
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PD - 94651B  
IRFR3711Z  
IRFU3711Z  
HEXFET® Power MOSFET  
Applications  
l High Frequency Synchronous Buck  
Converters for Computer Processor Power  
l High Frequency Isolated DC-DC  
Converters with Synchronous Rectification  
for Telecom and Industrial Use  
VDSS RDS(on) max  
Qg  
18nC  
5.7m:  
20V  
Benefits  
l Very Low RDS(on) at 4.5V VGS  
l Ultra-Low Gate Impedance  
l Fully Characterized Avalanche Voltage  
and Current  
D-Pak  
I-Pak  
IRFR3711Z  
IRFU3711Z  
Absolute Maximum Ratings  
Parameter  
Drain-to-Source Voltage  
Max.  
20  
Units  
V
VDS  
V
Gate-to-Source Voltage  
± 20  
93  
GS  
Continuous Drain Current, VGS @ 10V  
Continuous Drain Current, VGS @ 10V  
Pulsed Drain Current  
I
I
I
@ TC = 25°C  
@ TC = 100°C  
D
D
66  
A
370  
79  
DM  
Maximum Power Dissipation  
Maximum Power Dissipation  
P
P
@TC = 25°C  
W
D
D
@TC = 100°C  
39  
Linear Derating Factor  
Operating Junction and  
0.53  
W/°C  
°C  
T
-55 to + 175  
J
T
Storage Temperature Range  
STG  
Soldering Temperature, for 10 seconds  
300 (1.6mm from case)  
Thermal Resistance  
Parameter  
Junction-to-Case  
Typ.  
–––  
–––  
–––  
Max.  
1.9  
Units  
RθJC  
RθJA  
RθJA  
Junction-to-Ambient (PCB Mount)  
Junction-to-Ambient  
50  
°C/W  
110  
Notes  through ꢀ are on page 11  
www.irf.com  
1
3/2/04  
IRFR/U3711Z  
Static @ TJ = 25°C (unless otherwise specified)  
Parameter  
Min. Typ. Max. Units  
Conditions  
BVDSS  
Drain-to-Source Breakdown Voltage  
20  
–––  
–––  
V
VGS = 0V, ID = 250µA  
∆ΒVDSS/∆TJ  
RDS(on)  
Breakdown Voltage Temp. Coefficient –––  
13  
––– mV/°C Reference to 25°C, ID = 1mA  
mΩ  
Static Drain-to-Source On-Resistance  
–––  
–––  
1.55  
–––  
–––  
–––  
–––  
–––  
48  
4.5  
6.2  
2.0  
-5.4  
–––  
–––  
–––  
5.7  
7.8  
V
GS = 10V, ID = 15A  
VGS = 4.5V, ID = 12A  
VGS(th)  
Gate Threshold Voltage  
2.45  
V
V
DS = VGS, ID = 250µA  
∆VGS(th)/∆TJ  
IDSS  
Gate Threshold Voltage Coefficient  
Drain-to-Source Leakage Current  
––– mV/°C  
1.0  
150  
100  
µA  
V
V
DS = 16V, VGS = 0V  
DS = 16V, VGS = 0V, TJ = 125°C  
IGSS  
Gate-to-Source Forward Leakage  
Gate-to-Source Reverse Leakage  
Forward Transconductance  
Total Gate Charge  
nA VGS = 20V  
GS = -20V  
––– -100  
V
gfs  
–––  
18  
–––  
27  
S
VDS = 10V, ID = 12A  
Qg  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
Qgs1  
Qgs2  
Qgd  
Qgodr  
Qsw  
Qoss  
td(on)  
tr  
Pre-Vth Gate-to-Source Charge  
Post-Vth Gate-to-Source Charge  
Gate-to-Drain Charge  
5.1  
1.8  
6.5  
4.6  
8.3  
9.8  
12  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
VDS = 10V  
nC  
VGS = 4.5V  
ID = 12A  
Gate Charge Overdrive  
See Fig. 16  
Switch Charge (Qgs2 + Qgd)  
Output Charge  
nC  
V
V
DS = 10V, VGS = 0V  
Turn-On Delay Time  
Rise Time  
DD = 15V, VGS = 4.5V  
13  
ID = 12A  
ns Clamped Inductive Load  
td(off)  
tf  
Turn-Off Delay Time  
Fall Time  
15  
5.2  
Ciss  
Coss  
Crss  
Input Capacitance  
Output Capacitance  
Reverse Transfer Capacitance  
––– 2160 –––  
V
V
GS = 0V  
–––  
–––  
700  
360  
–––  
–––  
pF  
DS = 10V  
ƒ = 1.0MHz  
Avalanche Characteristics  
Parameter  
Single Pulse Avalanche Energy  
Typ.  
–––  
–––  
–––  
Max.  
Units  
mJ  
A
EAS  
IAR  
140  
12  
Avalanche Current  
Repetitive Avalanche Energy  
EAR  
7.9  
mJ  
Diode Characteristics  
Parameter  
Continuous Source Current  
Min. Typ. Max. Units  
Conditions  
MOSFET symbol  
93  
IS  
–––  
–––  
(Body Diode)  
A
showing the  
ISM  
Pulsed Source Current  
–––  
–––  
370  
integral reverse  
(Body Diode)  
p-n junction diode.  
VSD  
trr  
Diode Forward Voltage  
–––  
–––  
–––  
–––  
19  
1.0  
28  
14  
V
T = 25°C, I = 12A, V = 0V  
J S GS  
Reverse Recovery Time  
Reverse Recovery Charge  
Forward Turn-On Time  
ns T = 25°C, I = 12A, VDD = 10V  
J F  
Qrr  
ton  
di/dt = 100A/µs  
9.4  
nC  
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)  
2
www.irf.com  
IRFR/U3711Z  
1000  
100  
10  
1000  
100  
10  
VGS  
10V  
VGS  
10V  
TOP  
TOP  
4.5V  
3.7V  
3.5V  
3.3V  
3.0V  
2.7V  
4.5V  
3.7V  
3.5V  
3.3V  
3.0V  
2.7V  
BOTTOM 2.5V  
BOTTOM 2.5V  
2.5V  
1
2.5V  
20µs PULSE WIDTH  
Tj = 175°C  
20µs PULSE WIDTH  
Tj = 25°C  
1
0.1  
0.1  
1
10  
0.1  
1
10  
V
, Drain-to-Source Voltage (V)  
V
, Drain-to-Source Voltage (V)  
DS  
DS  
Fig 1. Typical Output Characteristics  
Fig 2. Typical Output Characteristics  
2.0  
1000  
I
= 30A  
D
V
= 10V  
GS  
T
= 25°C  
J
T
= 175°C  
J
1.5  
1.0  
0.5  
100  
10  
1
V
= 10V  
20µs PULSE WIDTH  
DS  
2.0  
3.0  
V
4.0  
5.0  
6.0  
7.0  
8.0  
-60 -40 -20  
T
0
20 40 60 80 100 120 140 160 180  
, Gate-to-Source Voltage (V)  
, Junction Temperature (°C)  
GS  
J
Fig 3. Typical Transfer Characteristics  
Fig 4. Normalized On-Resistance  
vs. Temperature  
www.irf.com  
3
IRFR/U3711Z  
10000  
12  
10  
8
V
= 0V,  
f = 1 MHZ  
GS  
I = 12A  
D
V
= 18V  
C
= C + C  
,
C
SHORTED  
DS  
VDS= 10V  
iss  
gs gd  
ds  
C
= C  
rss  
gd  
C
= C + C  
oss  
ds  
gd  
Ciss  
1000  
6
Coss  
Crss  
4
2
100  
0
1
10  
, Drain-to-Source Voltage (V)  
100  
0
10  
20  
30  
40  
V
Q
Total Gate Charge (nC)  
DS  
G
Fig 6. Typical Gate Charge vs.  
Fig 5. Typical Capacitance vs.  
Gate-to-Source Voltage  
Drain-to-Source Voltage  
1000  
100  
10  
1000.0  
OPERATION IN THIS AREA  
LIMITED BY R (on)  
DS  
100.0  
10.0  
1.0  
T
= 175°C  
J
100µsec  
1msec  
T
= 25°C  
J
Tc = 25°C  
Tj = 175°C  
Single Pulse  
10msec  
V
= 0V  
GS  
1
0.1  
0.1  
1.0  
10.0  
100.0  
1000.0  
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
V
, Drain-toSource Voltage (V)  
V
, Source-toDrain Voltage (V)  
DS  
SD  
Fig 8. Maximum Safe Operating Area  
Fig 7. Typical Source-Drain Diode  
Forward Voltage  
4
www.irf.com  
IRFR/U3711Z  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
100  
80  
60  
40  
20  
0
LIMITED BY PACKAGE  
I
= 250µA  
D
25  
50  
75  
100  
125  
150  
175  
-75 -50 -25  
0
25 50 75 100 125 150 175  
, Temperature ( °C )  
T
, Case Temperature (°C)  
T
C
J
Fig 9. Maximum Drain Current vs.  
Fig 10. Threshold Voltage vs. Temperature  
Case Temperature  
10  
1
D = 0.50  
0.20  
0.10  
R1  
R1  
R2  
R2  
R3  
R3  
Ri (°C/W) τi (sec)  
0.1  
0.01  
0.05  
τ
JτJ  
τ
τ
Cτ  
0.805  
0.606  
0.492  
0.000237  
0.001005  
0.101628  
0.02  
0.01  
τ
1τ1  
τ
2 τ2  
3τ3  
Ci= τi/Ri  
Ci i
 
Ri  
SINGLE PULSE  
Notes:  
1. Duty Factor D = t1/t2  
( THERMAL RESPONSE )  
2. Peak Tj = P dm x Zthjc + Tc  
0.001  
1E-006  
1E-005  
0.0001  
0.001  
0.01  
0.1  
t
, Rectangular Pulse Duration (sec)  
1
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case  
www.irf.com  
5
IRFR/U3711Z  
15V  
600  
500  
400  
300  
200  
100  
0
I
D
7.7A  
8.9A  
12A  
TOP  
DRIVER  
+
L
V
DS  
BOTTOM  
D.U.T  
AS  
R
G
V
DD  
-
I
A
V
GS  
0.01  
Ω
t
p
Fig 12a. Unclamped Inductive Test Circuit  
V
(BR)DSS  
t
p
25  
50  
75  
100  
125  
150  
175  
Starting T , Junction Temperature (°C)  
J
Fig 12c. Maximum Avalanche Energy  
Vs. Drain Current  
LD  
I
AS  
VDS  
Fig 12b. Unclamped Inductive Waveforms  
+
-
VDD  
D.U.T  
Current Regulator  
VGS  
Same Type as D.U.T.  
Pulse Width < 1µs  
Duty Factor < 0.1%  
50KΩ  
.2µF  
12V  
.3µF  
Fig 14a. Switching Time Test Circuit  
VDS  
+
V
DS  
D.U.T.  
-
90%  
V
GS  
3mA  
10%  
VGS  
I
I
D
G
Current Sampling Resistors  
td(on)  
td(off)  
tr  
tf  
Fig 13. Gate Charge Test Circuit  
Fig 14b. Switching Time Waveforms  
6
www.irf.com  
IRFR/U3711Z  
Driver Gate Drive  
P.W.  
P.W.  
D =  
Period  
D.U.T  
Period  
+
*
=10V  
V
GS  
ƒ
Circuit Layout Considerations  
• Low Stray Inductance  
• Ground Plane  
• Low Leakage Inductance  
Current Transformer  
-
D.U.T. I Waveform  
SD  
+
‚
-
Reverse  
Recovery  
Current  
Body Diode Forward  
„
Current  
-
+
di/dt  
D.U.T. V Waveform  
DS  
Diode Recovery  
dv/dt  

V
DD  
VDD  
Re-Applied  
Voltage  
• dv/dt controlled by RG  
• Driver same type as D.U.T.  
• ISD controlled by Duty Factor "D"  
• D.U.T. - Device Under Test  
RG  
+
-
Body Diode  
Forward Drop  
Inductor Curent  
I
SD  
Ripple ≤ 5%  
* VGS = 5V for Logic Level Devices  
Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel  
HEXFET® Power MOSFETs  
Id  
Vds  
Vgs  
Vgs(th)  
Qgs1  
Qgs2  
Qgd  
Qgodr  
Fig 16. Gate Charge Waveform  
www.irf.com  
7
IRFR/U3711Z  
Power MOSFET Selection for Non-Isolated DC/DC Converters  
Synchronous FET  
Control FET  
The power loss equation for Q2 is approximated  
by;  
Special attention has been given to the power losses  
in the switching elements of the circuit - Q1 and Q2.  
Power losses in the high side switch Q1, also called  
the Control FET, are impacted by the Rds(on) of the  
MOSFET, but these conduction losses are only about  
one half of the total losses.  
P = P  
+ P + P*  
drive output  
loss  
conduction  
P = Irms 2 × Rds(on)  
loss ( )  
Power losses in the control switch Q1 are given  
by;  
+ Q × V × f  
(
)
g
g
Qoss  
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput  
+
×V × f + Q × V × f  
in rr in  
(
)
2  
This can be expanded and approximated by;  
*dissipated primarily in Q1.  
P
= I 2 × Rds(on)  
(
)
loss  
rms  
For the synchronous MOSFET Q2, Rds(on) is an im-  
portant characteristic; however, once again the im-  
portance of gate charge must not be overlooked since  
it impacts three critical areas. Under light load the  
MOSFET must still be turned on and off by the con-  
trol IC so the gate drive losses become much more  
significant. Secondly, the output charge Qoss and re-  
verse recovery charge Qrr both generate losses that  
are transfered to Q1 and increase the dissipation in  
that device. Thirdly, gate charge will impact the  
MOSFETs’ susceptibility to Cdv/dt turn on.  
Qgd  
ig  
Qgs2  
ig  
+ I ×  
× V × f + I ×  
× V × f  
in  
in  
+ Q × V × f  
(
Qoss  
)
g
g
+
×V × f  
in  
2
This simplified loss equation includes the terms Qgs2  
The drain of Q2 is connected to the switching node  
of the converter and therefore sees transitions be-  
tween ground and Vin. As Q1 turns on and off there is  
a rate of change of drain voltage dV/dt which is ca-  
pacitively coupled to the gate of Q2 and can induce  
a voltage spike on the gate that is sufficient to turn  
the MOSFET on, resulting in shoot-through current .  
The ratio of Qgd/Qgs1 must be minimized to reduce the  
potential for Cdv/dt turn on.  
and Qoss which are new to Power MOSFET data sheets.  
Qgs2 is a sub element of traditional gate-source  
charge that is included in all MOSFET data sheets.  
The importance of splitting this gate-source charge  
into two sub elements, Qgs1 and Qgs2, can be seen from  
Fig 16.  
Qgs2 indicates the charge that must be supplied by  
the gate driver between the time that the threshold  
voltage has been reached and the time the drain cur-  
rent rises to Idmax at which time the drain voltage be-  
gins to change. Minimizing Qgs2 is a critical factor in  
reducing switching losses in Q1.  
Qoss is the charge that must be supplied to the out-  
put capacitance of the MOSFET during every switch-  
ing cycle. Figure A shows how Qoss is formed by the  
parallel combination of the voltage dependant (non-  
linear) capacitance’s Cds and Cdg when multiplied by  
the power supply input buss voltage.  
Figure A: Qoss Characteristic  
8
www.irf.com  
IRFR/U3711Z  
D-Pak (TO-252AA) Package Outline  
Dimensions are shown in millimeters (inches)  
2.38 (.094)  
2.19 (.086)  
6.73 (.265)  
6.35 (.250)  
1.14 (.045)  
0.89 (.035)  
- A -  
1.27 (.050)  
5.46 (.215)  
0.58 (.023)  
0.46 (.018)  
0.88 (.035)  
5.21 (.205)  
4
6.45 (.245)  
5.68 (.224)  
6.22 (.245)  
5.97 (.235)  
10.42 (.410)  
9.40 (.370)  
1.02 (.040)  
1.64 (.025)  
LEAD ASSIGNMENTS  
1 - GATE  
1
2
3
2 - DRAIN  
0.51 (.020)  
MIN.  
- B -  
3 - SOURCE  
4 - DRAIN  
1.52 (.060)  
1.15 (.045)  
0.89 (.035)  
0.64 (.025)  
3X  
0.58 (.023)  
0.46 (.018)  
1.14 (.045)  
0.76 (.030)  
2X  
0.25 (.010)  
M A M B  
NOTES:  
2.28 (.090)  
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.  
2 CONTROLLING DIMENSION : INCH.  
4.57 (.180)  
3 CONFORMS TO JEDEC OUTLINE TO-252AA.  
4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,  
SOLDER DIP MAX. +0.16 (.006).  
D-Pak (TO-252AA) Part Marking Information  
Notes : T his part marking information applies to devices produced before 02/26/2001  
EXAMPLE: THIS IS AN IRFR120  
WIT H AS S E MBLY  
LOT CODE 9U1P  
INTERNATIONAL  
RECTIFIER  
LOGO  
DATE CODE  
YEAR = 0  
IRFU120  
016  
1P  
WEEK = 16  
9U  
ASSEMBLY  
LOT CODE  
Notes: This part marking information applies to devices produced after 02/26/2001  
EXAMPLE: THIS IS AN IRFR120  
PART NUMBER  
WIT H AS S E MBLY  
LOT CODE 1234  
ASSEMBLED ON WW 16, 1999  
IN THE ASSEMBLY LINE "A"  
INTERNATIONAL  
RECTIFIER  
LOGO  
DATE CODE  
YEAR 9 = 1999  
WE E K 16  
IRFU120  
916A  
34  
12  
LINE A  
AS S E MB L Y  
LOT CODE  
www.irf.com  
9
IRFR/U3711Z  
I-Pak (TO-251AA) Package Outline  
Dimensions are shown in millimeters (inches)  
6.73 (.265)  
6.35 (.250)  
2.38 (.094)  
2.19 (.086)  
- A -  
0.58 (.023)  
0.46 (.018)  
1.27 (.050)  
5.46 (.215)  
0.88 (.035)  
5.21 (.205)  
LEAD ASSIGNMENTS  
1 - GATE  
4
2 - DRAIN  
6.45 (.245)  
5.68 (.224)  
3 - SOURCE  
4 - DRAIN  
6.22 (.245)  
5.97 (.235)  
1.52 (.060)  
1.15 (.045)  
1
2
3
- B -  
NOTES:  
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.  
2 CONTROLLING DIMENSION : INCH.  
2.28 (.090)  
1.91 (.075)  
9.65 (.380)  
8.89 (.350)  
3 CONFORMS TO JEDEC OUTLINE TO-252AA.  
4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,  
SOLDER DIP MAX. +0.16 (.006).  
1.14 (.045)  
0.76 (.030)  
1.14 (.045)  
0.89 (.035)  
3X  
0.89 (.035)  
0.64 (.025)  
3X  
0.25 (.010)  
M A M B  
0.58 (.023)  
0.46 (.018)  
2.28 (.090)  
2X  
I-Pak (TO-251AA) Part Marking Information  
Notes : T his part marking information applies to devices produced before 02/26/2001  
EXAMPLE: THIS IS AN IRFR120  
INTERNATIONAL  
DAT E CODE  
YEAR = 0  
WITH ASSEMBLY  
LOT CODE 9U1P  
RECTIFIER  
LOGO  
IRFU120  
016  
1P  
WE E K = 16  
9U  
AS S E MB L Y  
LOT CODE  
Notes: This part marking information applies to devices producedafter 02/26/2001  
PART NUMBER  
EXAMPLE: THIS IS AN IRFR120  
WITH ASSEMBLY  
INTERNATIONAL  
RECTIFIER  
LOGO  
DATE CODE  
YEAR 9 = 1999  
WEE K 19  
IRFU120  
919A  
78  
LOT CODE 5678  
ASSEMBLED ON WW 19, 1999  
IN THE ASSEMBLY LINE "A"  
56  
LINE A  
AS S E MB L Y  
LOT CODE  
10  
www.irf.com  
IRFR/U3711Z  
D-Pak (TO-252AA) Tape & Reel Information  
Dimensions are shown in millimeters (inches)  
TR  
TRL  
TRR  
16.3 ( .641 )  
15.7 ( .619 )  
16.3 ( .641 )  
15.7 ( .619 )  
12.1 ( .476 )  
11.9 ( .469 )  
8.1 ( .318 )  
7.9 ( .312 )  
FEED DIRECTION  
FEED DIRECTION  
NOTES :  
1. CONTROLLING DIMENSION : MILLIMETER.  
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).  
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.  
13 INCH  
16 mm  
NOTES :  
1. OUTLINE CONFORMS TO EIA-481.  
Notes:  
„ Calculated continuous current based on maximum allowable  
 Repetitive rating; pulse width limited by  
max. junction temperature.  
junction temperature. Package limitation current is 30A.  
‚ Starting TJ = 25°C, L = 1.9mH, RG = 25Ω,  
ꢀ When mounted on 1" square PCB (FR-4 or G-10 Material).  
For recommended footprint and soldering techniques refer to  
application note #AN-994.  
I
AS = 12A.  
ƒ Pulse width ≤ 400µs; duty cycle ≤ 2%.  
Data and specifications subject to change without notice.  
This product has been designed and qualified for the Industrial market.  
Qualification Standards can be found on IR’s Web site.  
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105  
TAC Fax: (310) 252-7903  
Visit us at www.irf.com for sales contact information.3/04  
www.irf.com  
11  
Note: For the most current drawings please refer to the IR website at:  
http://www.irf.com/package/  

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