IRFR3707ZPBFTRR_技术文档

PD - 95443B

IRFR3707ZPbF

IRFU3707ZPbF

Applications

HEXFET^®Power MOSFET

l High Frequency Synchronous Buck

Converters for Computer Processor Power

l High Frequency Isolated DC-DC

Converters with Synchronous Rectification

for Telecom and Industrial Use

V_DSSR_DS(on)max

Qg

9.5m

30V

9.6nC

l Lead-Free

Benefits

l Very Low R_DS(on)at 4.5V V_GS

l Ultra-Low Gate Impedance

l Fully Characterized Avalanche Voltage

and Current

D-Pak

IRFR3707ZPbF

I-Pak

IRFU3707ZPbF

Absolute Maximum Ratings

Parameter

Max.

Units

V_DS

V

30

Drain-to-Source Voltage

V

± 20

Gate-to-Source Voltage

GS

I

@ T_C= 25°C

A

56

Continuous Drain Current, V_GS@ 10V

Pulsed Drain Current

D

@ T_C= 100°C

39

220

DM

P

@T_C= 25°C

W

50

25

Maximum Power Dissipation

Linear Derating Factor

D

@T_C= 100°C

0.33

W/°C

°C

T

-55 to + 175

Operating Junction and

J

T

Storage Temperature Range

Soldering Temperature, for 10 seconds

STG

300 (1.6mm from case)

Thermal Resistance

Parameter

Typ.

–––

Max.

3.0

Units

°C/W

R_θ

JC

JA

Junction-to-Case

R_θ

50

Junction-to-Ambient (PCB Mount)

Junction-to-Ambient

110

Notes through ꢀ are on page 11

www.irf.com

1

05/14/08

IRFR/U3707ZPbF

Static @ T_J= 25°C (unless otherwise specified)

Parameter

Drain-to-Source Breakdown Voltage

Min. Typ. Max. Units

30 ––– –––

Conditions

V_GS= 0V, I_D= 250µA

BV_DSS

V

∆ΒV_DSS/∆T_J

R_DS(on)

Breakdown Voltage Temp. Coefficient ––– 0.023 ––– V/°C Reference to 25°C, I_D= 1mA

Ω

m

Static Drain-to-Source On-Resistance

–––

7.5

10

9.5

V_GS= 10V, I_D= 15A

_GS= 4.5V, I_D= 12A

12.5

V

V_GS(th)

Gate Threshold Voltage

1.35 1.80 2.25

V

V_DS= V_GS, I_D= 25µA

∆V_GS(th)/∆T_J

I_DSS

Gate Threshold Voltage Coefficient

Drain-to-Source Leakage Current

–––

71

-5.0

–––

9.6

2.6

0.90

3.5

2.6

4.4

5.8

8.0

11

––– mV/°C

1.0

150

100

-100

–––

14

µA V_DS= 24V, V_GS= 0V

V_DS= 24V, V_GS= 0V, T_J= 125°C

nA V_GS= 20V

I_GSS

Gate-to-Source Forward Leakage

Gate-to-Source Reverse Leakage

Forward Transconductance

Total Gate Charge

V

_GS= -20V

gfs

Q_g

S

V_DS= 15V, I_D= 12A

–––

Q_gs1

Q_gs2

Q_gd

Q_godr

Q_sw

Q_oss

t_d(on)

t_r

Pre-Vth Gate-to-Source Charge

Post-Vth Gate-to-Source Charge

Gate-to-Drain Charge

–––

V

_DS= 15V

_GS= 4.5V

nC

V

I_D= 12A

Gate Charge Overdrive

Switch Charge (Q_gs2+ Q_gd)

See Fig. 16

Output Charge

nC V_DS= 15V, V_GS= 0V

_DD= 16V, V_GS= 4.5V

Turn-On Delay Time

Rise Time

V

I_D= 12A

t_d(off)

t_f

Turn-Off Delay Time

Fall Time

12

ns Clamped Inductive Load

3.3

C_iss

C_oss

C_rss

Input Capacitance

Output Capacitance

Reverse Transfer Capacitance

––– 1150 –––

V_GS= 0V

–––

260

120

–––

pF

V_DS= 15V

ƒ = 1.0MHz

Avalanche Characteristics

Parameter

Typ.

–––

Max.

Units

mJ

A

Single Pulse Avalanche Energy

E_AS

I_AR

42

12

Avalanche Current

Repetitive Avalanche Energy

E_AR

5.0

mJ

Diode Characteristics

Parameter

Min. Typ. Max. Units

Conditions

MOSFET symbol

D

S

56

I_S

–––

Continuous Source Current

(Body Diode)

A

showing the

integral reverse

G

I_SM

–––

220

Pulsed Source Current

(Body Diode)

p-n junction diode.

V_SD

t_rr

–––

25

1.0

38

26

V

T = 25°C, I = 12A, V = 0V

Diode Forward Voltage

Reverse Recovery Time

Reverse Recovery Charge

Forward Turn-On Time

J S GS

ns T = 25°C, I = 12A, V_DD= 15V

J

F

Q_rr

t_on

di/dt = 100A/µs

17

nC

Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

2

www.irf.com

IRFR/U3707ZPbF

10000

1000

100

10

1000

100

10

VGS

10V

VGS

10V

TOP

6.0V

4.5V

4.0V

3.3V

2.8V

2.5V

2.2V

6.0V

4.5V

4.0V

3.3V

2.8V

2.5V

2.2V

BOTTOM

1

2.2V

0.1

1

2.2V

0.01

0.001

20µs PULSE WIDTH

Tj = 175°C

20µs PULSE WIDTH

Tj = 25°C

0.1

1

10

0.1

1

10

V

, Drain-to-Source Voltage (V)

V

, Drain-to-Source Voltage (V)

DS

Fig 1. Typical Output Characteristics

Fig 2. Typical Output Characteristics

1000

2.0

1.5

1.0

0.5

I

= 30A

D

V

= 10V

GS

100

10

T

= 175°C

J

1

T = 25°C

J

0.1

0.01

V

= 10V

DS

20µs PULSE WIDTH

0

2

4

6

8

-60 -40 -20

T

0

20 40 60 80 100 120 140 160 180

V

, Gate-to-Source Voltage (V)

, Junction Temperature (°C)

GS

J

Fig 3. Typical Transfer Characteristics

Fig 4. Normalized On-Resistance

vs. Temperature

www.irf.com

3

IRFR/U3707ZPbF

10000

6.0

5.0

4.0

3.0

2.0

1.0

0.0

V

= 0V,

= C

f = 1 MHZ

GS

I = 12A

D

C

+ C , C

SHORTED

iss

gs

gd

ds

= C

V

= 24V

= 15V

rss

oss

gd

= C + C

DS

ds

gd

C

iss

1000

C

oss

C

rss

V

100

1

10

100

0

2

4

6

8

10

12

, Drain-to-Source Voltage (V)

DS

Q

Total Gate Charge (nC)

G

Fig 6. Typical Gate Charge vs.

Fig 5. Typical Capacitance vs.

Gate-to-Source Voltage

Drain-to-Source Voltage

1000.00

100.00

10.00

1.00

1000

100

10

OPERATION IN THIS AREA

LIMITED BY R

(on)

DS

T

= 175°C

J

100µsec

1msec

T = 25°C

J

1

10msec

Tc = 25°C

Tj = 175°C

V

= 0V

Single Pulse

GS

0.10

0.1

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2

, Source-to-Drain Voltage (V)

0

1

10

100

1000

V

, Drain-to-Source Voltage (V)

SD

DS

Fig 8. Maximum Safe Operating Area

Fig 7. Typical Source-Drain Diode

Forward Voltage

4

www.irf.com

IRFR/U3707ZPbF

2.5

2.0

1.5

1.0

60

50

40

30

20

10

0

Limited By Package

I

= 250µA

D

-75 -50 -25

0

25 50 75 100 125 150 175 200

, Temperature ( °C )

25

50

75

100

125

150

175

T

J

T

, Case Temperature (°C)

C

Fig 9. Maximum Drain Current vs.

Fig 10. Threshold Voltage vs. Temperature

Case Temperature

10

D = 0.50

1

0.20

0.10

0.05

R₁

R₂

R₃

Ri (°C/W) τi (sec)

0.1

0.01

τ

^Jτ_J

τ

0.823

1.698

0.481

0.000128

0.000845

0.016503

^Cτ

0.02

0.01

τ

¹τ₁

τ

²τ₂

³τ₃

Ci= τi/Ri

SINGLE PULSE

( THERMAL RESPONSE )

Notes:

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zthjc + Tc

0.001

1E-006

1E-005

0.0001

0.001

0.01

0.1

t

, Rectangular Pulse Duration (sec)

1

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

www.irf.com

5

IRFR/U3707ZPbF

15V

200

180

160

140

120

100

80

I

D

TOP

3.7A

5.6A

DRIVER

L

V

DS

BOTTOM 12A

D.U.T

AS

R

+

-

G

V

DD

I

A

2V0_GV_S

Ω

0.01

t

p

Fig 12a. Unclamped Inductive Test Circuit

60

40

V

(BR)DSS

20

t

p

0

25

50

75

100

125

150

175

Starting T , Junction Temperature (°C)

J

Fig 12c. Maximum Avalanche Energy

vs. Drain Current

L_D

I

AS

V_DS

Fig 12b. Unclamped Inductive Waveforms

+

-

V_DD

D.U.T

Current Regulator

Same Type as D.U.T.

V_GS

Pulse Width < 1µs

Duty Factor < 0.1%

50KΩ

.2µF

12V

.3µF

Fig 14a. Switching Time Test Circuit

V_DS

+

V

DS

D.U.T.

-

90%

V

GS

3mA

10%

V_GS

I

D

G

Current Sampling Resistors

t_d(on)

t_d(off)

t_r

t_f

Fig 13. Gate Charge Test Circuit

Fig 14b. Switching Time Waveforms

6

www.irf.com

IRFR/U3707ZPbF

Driver Gate Drive

P.W.

Period

D.U.T

Period

D =

P.W.

+

*

=10V

V

GS

Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

• Low Leakage Inductance

Current Transformer

-

D.U.T. I Waveform

SD

+

-

Reverse

Recovery

Current

Body Diode Forward

Current

di/dt

-

+

D.U.T. V Waveform

DS

Diode Recovery

dv/dt

V

DD

V_DD

Re-Applied

Voltage

• dv/dt controlled by R_G

R_G

+

-

Body Diode

Forward Drop

• Driver same type as D.U.T.

• I_SDcontrolled by Duty Factor "D"

• D.U.T. - Device Under Test

Inductor Curent

I

SD

Ripple ≤ 5%

* V_GS= 5V for Logic Level Devices

Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET^®Power MOSFETs

Id

Vds

Vgs

Vgs(th)

Qgs1

Qgs2

Qgd

Qgodr

Fig 16. Gate Charge Waveform

www.irf.com

7

IRFR/U3707ZPbF

Power MOSFET Selection for Non-Isolated DC/DC Converters

Synchronous FET

Control FET

The power loss equation for Q2 is approximated

by;

Special attention has been given to the power losses

in the switching elements of the circuit - Q1 and Q2.

Power losses in the high side switch Q1, also called

the Control FET, are impacted by the R_ds(on)of the

MOSFET, but these conduction losses are only about

one half of the total losses.

P = P

+ P + P^*

loss

conduction

drive

output

P = I_rms²× R_ds(on)

loss ( )

Power losses in the control switch Q1 are given

by;

+ Q × V × f

(

)

g

⎛

⎜

Q_oss

⎞

⎠

P_loss= P_conduction+ P_switching+ P_drive+ P_output

+

×V × f + Q × V × f

(

)

in

rr

in

⎝ 2

This can be expanded and approximated by;

*dissipated primarily in Q1.

P

= I ²× R_{ds(on )}

(

)

loss

rms

For the synchronous MOSFET Q2, R_ds(on)is an im-

portant characteristic; however, once again the im-

portance of gate charge must not be overlooked since

it impacts three critical areas. Under light load the

MOSFET must still be turned on and off by the con-

trol IC so the gate drive losses become much more

significant. Secondly, the output charge Q_ossand re-

verse recovery charge Q_rrboth generate losses that

are transfered to Q1 and increase the dissipation in

that device. Thirdly, gate charge will impact the

MOSFETs’ susceptibility to Cdv/dt turn on.

⎛

Q_gd

i_g

⎞

Q_gs2

i_g

⎞

⎟

⎜

⎟

⎜

+ I ×

× V × f + I ×

× V × f

in

⎝

⎠

⎝

⎠

+ Q × V × f

(

)

g

⎛ Q_oss

⎞

⎠

+

×V × f

in

⎝

2

This simplified loss equation includes the terms Q_gs2

The drain of Q2 is connected to the switching node

of the converter and therefore sees transitions be-

tween ground and V_in. As Q1 turns on and off there is

a rate of change of drain voltage dV/dt which is ca-

pacitively coupled to the gate of Q2 and can induce

a voltage spike on the gate that is sufficient to turn

the MOSFET on, resulting in shoot-through current .

The ratio of Q_gd/Q_gs1must be minimized to reduce the

potential for Cdv/dt turn on.

and Q_osswhich are new to Power MOSFETdata sheets.

Q_gs2is a sub element of traditional gate-source

charge that is included in all MOSFET data sheets.

The importance of splitting this gate-source charge

into two sub elements, Q_gs1and Q_gs2, can be seen from

Fig 16.

Q_gs2indicates the charge that must be supplied by

the gate driver between the time that the threshold

voltage has been reached and the time the drain cur-

rent rises to I_dmaxat which time the drain voltage be-

gins to change. Minimizing Q_gs2is a critical factor in

reducing switching losses in Q1.

Q_ossis the charge that must be supplied to the out-

put capacitance of the MOSFET during every switch-

ing cycle. Figure A shows how Q_ossis formed by the

parallel combination of the voltage dependant (non-

linear) capacitances C_dsand C_dgwhen multiplied by

the power supply input buss voltage.

Figure A: Q_ossCharacteristic

8

www.irf.com

IRFR/U3707ZPbF

D-Pak (TO-252AA) Package Outline

D-Pak (TO-252AA) Part Marking Information

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

www.irf.com

9

IRFR/U3707ZPbF

I-Pak (TO-251AA) Package Outline (Dimensions are shown in millimeters (inches)

I-Pak (TO-251AA) Part Marking Information

OR

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

10

www.irf.com

IRFR/U3707ZPbF

D-Pak (TO-252AA) Tape & Reel Information

Dimensions are shown in millimeters (inches)

TR

TRL

TRR

16.3 ( .641 )

15.7 ( .619 )

16.3 ( .641 )

15.7 ( .619 )

12.1 ( .476 )

11.9 ( .469 )

8.1 ( .318 )

7.9 ( .312 )

FEED DIRECTION

NOTES :

1. CONTROLLING DIMENSION : MILLIMETER.

2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).

3. OUTLINE CONFORMS TO EIA-481 & EIA-541.

13 INCH

16 mm

NOTES :

1. OUTLINE CONFORMS TO EIA-481.

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

Notes:

Repetitive rating; pulse width limited by

max. junction temperature.

Starting T_J= 25°C, L = 0.58mH, R_G= 25Ω,

I_AS= 12A.

Calculated continuous current based on maximum allowable

junction temperature. Package limitation current is 30A.

ꢀ When mounted on 1" square PCB (FR-4 or G-10 Material).

For recommended footprint and soldering techniques refer to

application note #AN-994.

Pulse width ≤ 400µs; duty cycle ≤ 2%.

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information. 05/2008

www.irf.com

11


型号：	IRFR3707ZPBFTRR
厂家：	Infineon
描述：	Transistor
文件：	总11页 (文件大小：363K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IRFR3707ZPBFTRR [INFINEON]

相关型号：

IRFR3707ZTRL

IRFR3707ZTRLPBF

IRFR3707ZTRPBF

IRFR3707ZTRR

IRFR3707ZTRRPBF

IRFR3708

IRFR3708

IRFR3708PBF

IRFR3708PBF

IRFR3708TRL

IRFR3708TRLPBF

IRFR3708TRPBF