IFX9201SG [INFINEON]
6 A H-Bridge with SPI;
| 型号： | IFX9201SG |
| 厂家： | 
Infineon |
| 描述： | 6 A H-Bridge with SPI |
| 文件： | 总27页 (文件大小：1511K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IFX9201SG
6 A H-Bridge with SPI
Data Sheet
Rev. 1.1, 2015-02-15
Automotive Power
IFX9201SG
Table of Contents
Table of Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
2.2
2.3
3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4
Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Output Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Protection and Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Current Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Short Circuit to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Short Circuit to Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Short Circuit over Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Overtemperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Undervoltage Shut-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Open Load Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
5
General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1
5.2
5.3
6
7
8
9
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Data Sheet
2
Rev. 1.1, 2015-02-15
6 A H-Bridge with SPI
IFX9201SG
1
Overview
Features
•
•
•
•
•
•
•
•
•
•
RDSon of 100 mΩ per switch typ. at Tj=25 °C
Logic inputs 3.3 V and 5.0 V TTL/CMOS-compatible
Low standby current
Chopper current limitation
Short circuit shut down with latch behavior
Overtemperature shut down with latch behavior
VS undervoltage shutdown
Open load detection in ON and OFF state
Detailed SPI diagnosis or simple error flag
Green product (RoHS compliant)
PG-DSO-12-17
Description
The IFX9201SG is a general purpose 6 A H-Bridge, designed for the control of DC motors or other inductive loads.
The outputs can be pulse width modulated at frequencies up to 20kHz. PWM/DIR control reduces the number of
PWM capable pins needed on the microcontroler side.
For load currents above the current limitation threshold (8A typ.) the H-Bridge goes into chopper current limitation
mode. It is protected against short circuits and overtemperature and provides extensive diagnosis via SPI or basic
feedback via error flag. Open load can be detected when the bridge is disabled or during PWM operation of
inductive loads.
The robust PG-DSO-12-17 package provides excellent thermal capabilites due to the thick copper heat slug.
Thanks to the protruding edges of the heatslug the package is well suited for automatic optical solder inspection.
The IFX9201SG is not qualified and manufactured according to the requirements of Infineon Technologies with
regards to automotive and/or transportation applications. For automotive applications please refer to the
TLE9201SG.
Type
Package
Marking
IFX9201SG
PG-DSO-12-17
IFX9201SG
Data Sheet
3
Rev. 1.1, 2015-02-15
IFX9201SG
Pin Configuration
2
Pin Configuration
2.1
Pin Assignment
(top view)
DIR
VSO
SO
1
2
3
4
5
6
12
11
10
9
PWM
DIS
SCK
CSN
SI
VS
OUT1
GND
8
7
OUT2
heat slug (GND)
Figure 1
Pin Assignment IFX9201SG
2.2
Pin Definitions and Functions
Pin
1
Symbol
Function
Direction input to define direction of the motor current
DIR
2
VSO
SO
Supply pin for SO output. Connect to 5V or 3.3V depending on desired logic level
3
SPI serial output
4
VS
Supply voltage
5
OUT1
GND
OUT2
SI
Output 1
6
Ground
7
Output 2
8
SPI serial input
9
CSN
SCK
DIS
SPI chip select (low active)
SPI clock input
10
11
12
Disable. Disables the outputs (all MOSFETS off)
Pulse width modulation input
PWM
Data Sheet
4
Rev. 1.1, 2015-02-15
IFX9201SG
Pin Configuration
2.3
Terms
IVS
VS
IDIS
IDIR
VVS
DIS
DIR
VDIS
IPWM
PWM
VDIR
VPWM
IOUT1
OUT1
OUT2
ICSN
ISCK
ISI
CSN
SCK
SI
IOUT2
ISO
VOUT2
SO
VOUT1
IVSO
VSO
VCSN
VSCK
VVSO
VSI
VSO
GND
Figure 2
Terms IFX9201SG
Data Sheet
5
Rev. 1.1, 2015-02-15
IFX9201SG
Block Diagram
3
Block Diagram
VS
internal
Supply
Charge
Pump
DIS
Gate Driver
DIR
Control
Logic
PWM
Current
Monitor
OUT1
OUT2
CSN
SCK
SI
Temperature
Monitor
SO
VSO
GND
Figure 3
Block Diagram
Data Sheet
6
Rev. 1.1, 2015-02-15
IFX9201SG
Block Description
4
Block Description
4.1
Power Supply
All internal supply voltages are derived from the pin VS. A charge pump provides the gate voltage for the high side
switches. The charge pump does not require an external capacitor.
The output buffer of the digital output SO is supplied by the pin VSO. Therefore the output level at SO can be easily
configured for 3.3 V or 5 V logic by connecting VSO to the respective voltage.
4.2
Sleep Mode
In order to minimize current consumption during inactive phases the device can be put into sleep mode by pulling
the VSO pin to GND. This functionality can also be used to provide a second switch off path for the outputs similar
to an enable pin, simply by driving VSO directly from a microcontroller output.
Since VSO is supplying also the output buffer of the SO signal it has to be ensured that the microcontroller output
can provide sufficient current. Alternatively an external mosfet or a driver stage could be used to switch the VSO
supply voltage. To account for dynamic switching currents it might be advisable to buffer VSO with a small
capacitor (see Figure 7 “Application Example VSO as Enable Input” on Page 24).
Please note that the push pull stage of the SO output provides a current return path to VSO via the bulk diode of
the highside mosfet. Therefore it has to be ensured that the voltage at SO never exceeds the voltage at VSO by
more than 0.3V.
-
VSO
sleep_mode
+
v_vso_sleep
SO
spi_serial_out
Figure 4-1 SO output buffer
Data Sheet
7
Rev. 1.1, 2015-02-15
IFX9201SG
Block Description
4.3
Output Stages
The output stages consist of four n-channel mosfets in H-bridge configuration. The outputs are protected against
short circuits and over temperature.
The bridge is controlled using the inputs PWM and DIR. The signal at DIR is defining the direction of the driven
DC motor whereas the PWM signal sets the duty cycle.
The outputs can be set tristate (i.e. high side and low side switches are turned off) by setting DIS to high level.
HS1
ON
HS2
OFF
HS1
ON
HS2
OFF
IL
IL
M
M
LS2
ON
LS2
OFF
LS1
OFF
LS1
OFF
DIR=1, PWM=1
Forward
DIR=1, PWM=0
Freewheeling Through HS 2
Body Diode (Forward)
HS1
OFF
HS2
ON
HS1
OFF
HS2
ON
IL
IL
M
M
LS2
OFF
LS2
OFF
LS1
ON
LS1
OFF
DIR=0, PWM=1
Reverse
DIR=0, PWM=0
Freewheeling Through HS 1
Body Diode (Reverse)
Figure 4-2 Operation Modes
Table 4-1 Output Truth Table
DIS
1
PWM
DIR
X
OUT1
OUT2
Comment
X
1
1
0
0
Z
H
L
Z
L
disabled, outputs tristate
forward / clockwise
0
1
0
0
H
Z
H
reverse / counterclockwise
freewheeling in HS (forward)
freewheeling in HS (reverse)
0
1
H
Z
0
0
Data Sheet
8
Rev. 1.1, 2015-02-15
IFX9201SG
Block Description
4.4
Protection and Diagnostics
Both output stages of the IFX9201SG are equipped with fault diagnostic functions:
•
•
•
•
Short to supply voltage (SCVS)
Short to ground (SCG)
Open load (OL)
Over-temperature (OT)
4.5
Current Limitation
To limit the output current a chopper current limitation is integrated. Current measurement for current limitation is
done in the high side path.
ttrans
tb
HS1
LS1
HS2
LS2
IL
M
time
Figure 4-3 Chopper Current Limitation
Figure 4-3 shows the behavior of the current limitation for over current detection in HS1. It applies accordingly
also for HS2.
When the current in high-side switch of OUT1 (HS1) exceeds the limit IL longer than the blanking time tb, the low
side switch of OUT2 (LS2) is switched off, independent of the input signal at PWM. This leads to freewheeling
through the bulk diode of HS2 and therefore to a decrease of the load current. As soon as the current falls below
IL, OUT2 is switched back to normal operation, i.e. the outputs follow the inputs according to the truth table. To
avoid high switching frequencies in case of low inductive loads the minimum time between two transitions is limited
to ttrans
.
Data Sheet
9
Rev. 1.1, 2015-02-15
IFX9201SG
Block Description
4.6
Short Circuit to Ground
short circuit detected
both outputs off
current tracking
current limitation,
freewheeling in HS
ISC
IL
t<tb
tb
tsdf
IOUT
time
Short
PWM
DIR
OUT1
OUT2
tristate
tristate
tristate
Figure 4-4 Short to Ground Detection
The short circuit to ground detection is activated when the current through one of the high side switches rises over
the threshold ISC and remains higher than ISC for at least the filter time tsdf within the blanking time tb. Both outputs
will be switched off and the failure will be reported in the SPI diagnosis register. The outputs can be re-activated
by disabling and enabling the bridge via the disable signal DIS, pulling VSO to GND or by a reset command via
SPI.
4.7
Short Circuit to Supply
A short circuit to the supply voltage VS is detected in the same way as a short circuit to ground, only in the low
side switch instead of the high side switch.
4.8
Short Circuit over Load
Short circuit over load will trigger the short circuit detection either of the high side or the low side switch (whichever
is faster).
4.9
Overtemperature
In case of high DC-currents, insufficient cooling or high ambient temperature, the chip temperature may rise above
the thermal shut-down temperature TjSD. In that case, all output transistors are turned off. Overtemperature
shutdown is latching.
The outputs can be re-activated as soon as the junction temperature has fallen below the switch-on temperature
TjSO
.
Data Sheet
10
Rev. 1.1, 2015-02-15
IFX9201SG
Block Description
4.10
Undervoltage Shut-Down
If the supply voltage at the VS pins falls below the undervoltage detection threshold VUV_OFF, the outputs are turned
off. The undervoltage detection is not latching. That means that as soon as VS rises above VUV_ON again, the
device is returning to normal operation.
4.11
Open Load Detection
4.11.1
Open Load Detection in OFF state
When the bridge is disabled (DIS=high) the open load in OFF detection becomes active. Two diagnostic current
sources will then be connected to the outputs, a pull up current source at OUT1 and a pull down current source at
OUT2. The pull down current source is stronger than the pull up current source and therefore will pull down OUT1
if a load is present. If no load is present OUT1 will be pulled high by the pull up current source. This is detected
by a comparator and reported in the SPI diagnosis register.
Please note that capacitors that might be placed at the outputs for EMC reasons first have to be discharged by
the pull down current source at OUT2 for the open load detection to work properly.
Also, if current is flowing through the load at the time of disabling the freewheeling current will force the outputs
towards supply voltage VS. This may lead to an erroneous reporting of open load.
Therefore the first diagnostic reading after disabling should be discarded and a second reading should be taken
after the load is deenergized and the output capacitors are discharged completely.
The open load detection can be disabled by setting the OLDIS bit in the CTRL_REG register. This will disconnect
the diagnostic current sources and suppress the reporting of open load in the DIA_REG register.
5V int.
OUT2
OUT1
M
OL
+
-
Vref_OL
Figure 4-5 Open Load Detection in OFF state
4.11.2
Open Load Detection in ON state
The IFX9201SG contains an open load diagnosis during operation for inductive loads. It evaluates whether
freewheeling occurs in the switching phase. In order to avoid inadvertent triggering of the open load diagnosis a
failure counter is implemented. There have to be at least 5 occurances of the internal open load signal (i.e. 5 PWM
pulses without freewheeling detected) before open load is reported in the SPI diagnosis register.
Depending on the operation conditions and on external circuitry like the output capacitors it is possible that open
load is indicated although the load is present. This might be the case for example during a direction change or for
small load currents respectively small PWM duty cycles. Therefore it is recommended to evaluate the open load
diagnosis only in known suitable operating conditions and to ignore it otherwise.
The open load diagnosis is not latching.
Data Sheet
11
Rev. 1.1, 2015-02-15
IFX9201SG
Block Description
4.12
Serial Peripheral Interface (SPI)
For diagnosis purposes the IFX9201SG is equipped with a “Serial Peripheral Interface“ (SPI).
The SPI of several IFX9201SGs can be connected in daisy chain configuration in order to save microcontroller
interface pins.
The IFX9201SG is configured as a “slave” device. This means that the µC as the master is providing the chip
select (CSN) and clock signal (SCK).
A data transfer on the SPI bus is initiaded with a falling edge on CSN and is terminated by a rising edge on CSN.
The data on the serial input pin SI is sampled with the falling edge of SCK, the serial data output at SO is
determined by the rising clock edge. The data is transferred “MSB first”.
The word length of the SPI is 8 bit. Please note that there is no check for the number of clocks within a SPI frame.
Any low pulse at CSN will be regarded as one frame.
4.12.1
Error Flag
Between the falling edge of CSN and the first rising edge of SCK an additional error flag signal is set
asynchronously at the SO pin. The error flag signal set to high whenever the output stages are shut down (tristate)
due to a failure or due to disabling of the output stages. Additionally the EF signal is OR’ed with the SI input signal.
By connecting the SO of one device to the SI of the next device the EF signal can be routed through similar to a
SPI daisy chain configuration.
This flag can be used for simple error feedback without SPI communication by connecting SCK and CSN to GND
permanently (see Figure 5 “Application Example H-Bridge with Error Flag” on Page 22).
CSN
1
3
8
9
2
SCK
SI
10
5
6
Command n
7
6
5
4
3
1
0
2
SI: Data will be accepted on the falling edge of SCK-Signal
Answer to Command n-1
7
4
7
6
5
4
3
1
0
2
EF
SO
Z
Z
EF
SO: State will change on the rising edge of SCK-Signal
Figure 4-6 SPI Timing Definition (drawing not to scale)
Data Sheet
12
Rev. 1.1, 2015-02-15
IFX9201SG
Block Description
4.12.2
SPI Register Description
The IFX9201SG provides detailed diagnosis and the option to control the outputs via SPI. Following commands
are available (x=don’t care, d=data):
Table 4-2 SPI Command Set
Command
RD_DIA
Input Byte
000x xxxx
100x xxxx
001x xxxx
011x xxxx
111d dddd
110d dddd
Description
Read Diagnosis Register
RES_DIA
Reset Diagnosis Register
RD_REV
Read Device Revision Number
Read Control Register
RD_CTRL
WR_CTRL
WR_CTRL_RD_DIA
Write Control - sets and returns Control Register values
Write Control and Read Diagnosis- sets Control Register values and
returns Diagnosis Register values
The first SPI response provided after power up is the device revision number (RD_REV). For any unspecified
commands the device will respond with the content of the diagnosis register (RD_DIA).
The registers are addressed wordwise.
Data Sheet
13
Rev. 1.1, 2015-02-15
IFX9201SG
Block Description
4.12.2.1 Control Register
Control Register
CTRL_REG
Offset
01H
Reset Value
00H
ControlRegister
7
5
4
OLDIS
rw
3
2
1
0
CMD
rw
SIN
rw
SEN
rw
SDIR
SPWM
rw
rw
Field
Bits
Type
Description
CMD
7:5
rw
Command
011: RD_CTRL
110: WR_CTRL_RD_DIA
111: WR_CTRL
OLDIS
SIN
4
3
rw
rw
Open Load Disconnect
1: Open load current source disconnected.
SPI control
0: Control outputs via PWM/DIR inputs
1: Control outputs via SPI
Note: can only be set if DIS=0 and PWM=0 and DIR=0.
Any change of the DIS, PWM or DIR signals will reset
this bit and revert to standard control via PWM/DIR
SEN
2
rw
1: Enable outputs in case of SPI control (SIN=1)
0: Disable outputs in case of SPI control (SIN=1)
SDIR
1
0
rw
rw
DIR Signal in case of SPI control (SIN=1)
PWM Signal in case of SPI control (SIN=1)
SPWM
Data Sheet
14
Rev. 1.1, 2015-02-15
IFX9201SG
Block Description
4.12.2.2 Diagnosis Register
Diagnosis Register
DIA_REG
Offset
00H
Reset Value
DFH
Diagnosis Register
7
EN
r
6
OT
r
5
TV
r
4
CL
r
3
DIA4
r
2
DIA3
r
1
0
DIA2
DIA1
r
r
Field
Bits
Type
Description
EN
7
r
1= outputs enabled by low signal on pin DIS
0 = outputs disabled by high signal on pin DIS
OT
6
5
4
3
2
1
0
r
r
r
r
r
r
r
0 = overtemperature shutdown
Always 0 - used for transmission validation
0 = current limitation active
Diagnosis bit 4
TV
CL
DIA4
DIA3
DIA2
DIA1
Diagnosis bit 3
Diagnosis bit 2
Diagnosis bit 1
Diagnosis Truth Table
The short circuit and VS undervoltage diagnosis is coded in the DIA bits according to the following truth table.
Together with transmission validation bit TV (always 0) it is ensured that there is always at least one 1->0 change
at SO during a valid transmission. Therefore a “stuck at” failure of the SO pin can be detected.
Table 4-3 Encoding of Diagnosis Bits (sorted by hex value, only listed combinations are valid)
Type
DIA4 DIA3 DIA2 DIA1 Hex Comment
No failure
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
0
1
1
0
0
1
1
0
1
1
0
1
1
0
1
0
1
0
1
1
0
1
1
0xF -
Short to GND at OUT1 (SCG1)
Short to VS at OUT1 (SCVS1)
Open Load (OL)
0xE latched
0xD latched
0xC not latched
0xB latched
0xA latched
0x9 latched
0x7 latched
0x6 latched
0x5 latched
0x3 not latched
Short to GND at OUT2 (SCG2)
Short to GND at OUT1 and OUT2 (SCG1, SCG2)
Short to VS at OUT1 and short to GND at OUT2 (SCVS1, SCG2) 1
Short to Supply at OUT2 (SCVS2)
Short to GND at OUT1 and short to VS at OUT2 (SCG1, SCVS2) 0
0
Short to VS at OUT1 and OUT2 (SCVS1, SCVS2)
VS Undervoltage (VS_UV)
0
0
Data Sheet
15
Rev. 1.1, 2015-02-15
IFX9201SG
Block Description
Reset Behavior of Diagnosis Register
The diagnosis register is reset by the following events
Table 4-4 Diagnosis Reset Types
Name Type
Comment
POR
ENR
Power On Reset Reset due to power up, undervoltage or sleep mode
Enable Reset
Reset due to disabling/enabling of the outputs by DIS pin or bit SEN in CTRL_REG
Reset by sending the RES_DIA command via SPI
SPIR SPI Reset
A change of the DIR signal will lead to a reset of current limitation (CL) or open load in on (OL) error messages.
The open load in on failure will also be reset automatically if the open load condition no longer persits, i.e.
freewheeling is detected for five or more consecutive pulses.
4.12.2.3 Revision Register
The Revision Register contains the device revision corresponding to the mask set.
Revision Register
REV_REG
Offset
01H
Reset Value
00H
Revision Register
7
0
r
6
0
r
5
1
r
4
0
r
3
0
REV
r
Field
Bits
7
Type
Description
fixed to 0
fixed to 0
fixed to 1
fixed to 0
0
r
r
r
r
r
0
6
1
5
0
4
REV
3:0
Device Revision corresponding to mask set
Data Sheet
16
Rev. 1.1, 2015-02-15
IFX9201SG
General Product Characteristics
5
General Product Characteristics
5.1
Absolute Maximum Ratings
Table 1
Absolute Maximum Ratings1)
Tj = -40 °C to 125 °C; (unless specified otherwise)
Parameter
Symbol
Values
Unit
Note /
Number
Test Condition
Min.
-40
Typ. Max.
Junction temperature
Storage temperature
Supply voltage
Tj
–
–
–
–
–
–
150
150
40
°C
°C
V
–
–
–
–
–
P_5.1.1
P_5.1.2
P_5.1.4
P_5.1.5
P_5.1.6
Ts
-55
VVS
VVSO
VIN
-0.3
-0.3
-0.3
-0.3
Supply for logic output
Voltage at logic inputs
5.5
5.5
V
V
Voltage at logic output SO VSO
VVSO
V
both conditions must P_5.1.7
be observed
+0.3
-0.3
–
5.5
ESD Susceptibility
ESD Susceptibility to GND VESD
acc. HBM
-2
–
–
–
2
kV
V
HBM2)
CDM3)
P_5.1.8
P_5.1.9
ESD Susceptibility to GND VESD
acc. CDM
-500
-750
500
750
ESD Susceptibility to GND VESD
V
CDM3), Corner Pins P_5.1.10
acc. CDM, Corner Pins
1) Not subject to production test, specified by design.
2) ESD susceptibility HBM according to EIA/JESD22-A114-B (1.5kΩ, 100pF)
3) ESD susceptibility, Charged Device Model “CDM” EIA/JESD22-C101
Notes
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not
designed for continuous repetitive operation.
Data Sheet
17
Rev. 1.1, 2015-02-15
IFX9201SG
General Product Characteristics
5.2
Functional Range
Table 2
Functional Range1)
Parameter
Symbol
Values
Typ.
Unit Note /
Test Condition
Number
Min.
Max.
36
Supply voltage range
VS
VUV_OFF
–
–
–
–
V
–
P_5.2.1
P_5.2.2
P_5.2.3
P_5.2.4
VS supply voltage slew rate dVS/dt -10
10
V/µs
V
–
–
–
SO buffer supply voltage
Junction Temperature
VSO
Tj
2.9
-40
5.5
125
°C
1) Not subject to production test, specified by design.
Note:Within the functional or operating range, the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the Electrical Characteristics table.
5.3
Thermal Resistance
Note:This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go
to www.jedec.org.
Table 3
Thermal Resistance1)
Symbol
Parameter
Values
Typ.
–
Unit Note /
Test Condition
Number
Min.
Max.
Junction to Case
RthJC
RthJA
–
–
2
–
K/W
K/W
–
2)
P_5.3.1
P_5.3.2
Junction to Ambient
30
1) Not subject to production test, specified by design.
2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm board with 2 inner copper layers (2 × 70 µm Cu, 2 × 35 µm
Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
Data Sheet
18
Rev. 1.1, 2015-02-15
IFX9201SG
Electrical Characteristics
6
Electrical Characteristics
Table 4
Electrical Characteristics
VVS = 8 V to 36 V; VVSO = 5.0 V; Tj = -40 °C to 125 °C; (unless specified otherwise)
Parameter
Symbol
Values
Unit
Note / Test Condition
Number
Min. Typ. Max.
Supply
Supply Current
IVS
–
–
5
13
30
mA
µA
f
V
PWM = 2 kHz; IOUT = 0 A; P_6.0.1
VS = 13.5 V;
Supply Current Sleep Mode IVS
19
V
V
VS = 13.5 V; VVSO = 0 V; P_6.0.2
OUTx = 0 V; Tj = 25 °C
VSO Sleep Mode Threshold VVSO_sleep 0.5
–
–
–
2.0
100
1.0
V
–
P_6.0.4
VSO Input Current, CSN high IVSO
VSO Input Current, CSN low IVSO
VS Undervoltage
–
–
µA
mA
I
I
SO = 0 A; VCSN > 2 V
SO = 0 A; VCSN = 0 V
P_6.0.5
P_6.0.6
Undervoltage at VS
Undervoltage at VS
Undervoltage at VS
VUV OFF
3.5
3.6
100
–
4.2
4.4
200
1
5.0
5.2
500
–
V
Switch Off Threshold
Switch On Threshold
Hysteresis
P_6.0.7
P_6.0.8
P_6.0.9
P_6.0.10
VUV ON
VUV HY
V
mV
µs
VS Undervoltage Detection tUV
–
Filter Time 1)
Inputs PWM, DIR, SCK, SI
Low level
Vinput_L
Vinput_H
–
–
0.8
–
V
–
P_6.0.11
P_6.0.12
P_6.0.13
P_6.0.14
P_6.0.15
High level
2.0
–
V
–
Hysteresis
Vinput_HYS 0.1
0.3
38
–
–
V
–
Pull Down Current
Input Capacity1)
Iin_pd
Cin
9
–
85
15
µA
pF
Vin = 5.5 V
V
V
bias = 2 V;
test = 20 mVpp;
f = 1 MHz
Inputs DIS, CSN
Low level
Vinput_L
Vinput_H
–
–
0.8
–
V
–
P_6.0.16
P_6.0.17
P_6.0.18
P_6.0.19
P_6.0.20
High level
2.0
–
V
–
Hysteresis
Vinput_HYS 0.1
0.3
38
–
–
V
–
Pull Up Current
Input Capacity1)
Iin_pu
Cin
9
–
85
15
µA
pF
Vin = 0 V
V
V
bias = 2 V;
test = 20 mVpp;
f = 1 MHz
Data Sheet
19
Rev. 1.1, 2015-02-15
IFX9201SG
Electrical Characteristics
Table 4
Electrical Characteristics
VVS = 8 V to 36 V; VVSO = 5.0 V; Tj = -40 °C to 125 °C; (unless specified otherwise)
Parameter
Symbol
Values
Unit
Note / Test Condition
Number
Min. Typ. Max.
Output SO
Low level
High level
VSO_L
VSO_H
0.0
–
–
0.4
V
V
I
I
SO = -1 mA
SO = 1 mA ;
P_6.0.21
P_6.0.22
VVSO
-
VVSO
0.75
2.9 V < VVSO < 5.5 V
Tristage Leakage Current
Output Capacity1)
ISO
-5
–
–
–
5
µA
pF
0V < VSO < VVSO
;
P_6.0.23
P_6.0.24
V
VSO = 5.5 V
CSO
19
V
V
bias = 2 V;
test = 20 mVpp;
f = 1 MHz
Power Outputs OUT1, OUT2
On resistance low side
ROUTL
ROUTH
–
100
–
–
mΩ
mΩ
mΩ
mΩ
µA
I
I
I
I
OUT = 2 A; Tj = 25 °C
OUT = 2 A; Tj = 125 °C
OUT = 2 A; Tj = 25 °C
OUT = 2 A; Tj = 125 °C
P_6.0.25
P_6.0.26
P_6.0.27
–
200
–
On resistance high side
Leakage current
–
100
–
–
200
25
IOUT1(off)
IOUT2(off)
-25
–
V
VS = 13.5 V;
Outputs off; OLDIS high
VVS = 13.5 V;
-100
–
–
25
µA
V
Sleep Mode
Free-wheel diode forward
voltage
UD
0.9
1.0
ID = 2 A
P_6.0.28
Output Switching Times 2)
Voltage Slew Rate HS
Voltage Slew Rate LS
PWM Frequency1)
dVOUT/dt 0.20
dVOUT/dt 1.15
–
–
–
1.62
8.1
20
V/µs
V/µs
kHz
V
R
VS = 13.5 V;
Load = 6.8 Ω
P_6.0.29
P_6.0.31
P_6.0.33
fPWM
0
–
Output Delay Times 2)
Output on-delay HS
Output off-delay HS
Output on-delay LS
Output off-delay LS
Disable delay time
td_on(HS)
td_off(HS)
td_on(LS)
td_off(LS)
td_dis
–
–
–
–
–
–
–
–
–
80
80
10
10
80
80
3
µs
µs
µs
µs
µs
µs
µs
ms
V
R
VS = 13.5 V;
Load = 6.8 Ω
P_6.0.34
P_6.0.35
P_6.0.36
P_6.0.37
P_6.0.38
P_6.0.39
P_6.0.40
–
–
–
–
Enable delay time
td_en
–
Disable/Enable filter time1)
Wake Up delay time1)
Chopper Current Limitation
Current Limit
Blanking time1)
Minimum transition time1)
tf_en
0.4
–
twu
1
VSO high --> OUT high P_6.0.41
IL
6.0
5
8.0
8
10.0
13
–
A
V
–
–
VS = 13.5 V
P_6.0.42
P_6.0.43
P_6.0.44
tb
µs
µs
ttrans
–
95
Data Sheet
20
Rev. 1.1, 2015-02-15
IFX9201SG
Electrical Characteristics
Table 4
Electrical Characteristics
VVS = 8 V to 36 V; VVSO = 5.0 V; Tj = -40 °C to 125 °C; (unless specified otherwise)
Parameter
Symbol
Values
Unit
Note / Test Condition
Number
Min. Typ. Max.
Short Circuit Detection
Short circuit detection
threshold high side switch
ISC_H
ISC_L
8.0
8.0
11.5 14.5
11.5 14.5
A
A
V
VS = 13.5 V
P_6.0.45
P_6.0.46
Short circuit detection
threshold low side switch
Current tracking high side
Current tracking low side
I
I
SC_H - IL 2.0
SC_L - IL 1.8
4.0
3.5
2
5.2
5.2
–
A
P_6.0.47
P_6.0.48
P_6.0.49
A
Short Circuit detection filter tsdf
–
µs
–
time1)
Open Load Detection in OFF State
Pull up Current at OUT1
Pull down Current at OUT2 IOUT2_OL
Ratio of current sources
IOUT1_OL
60
140
350
2.5
–
200
500
3.5
–
µA
µA
–
V
V
–
VS = 13.5 V; VOUT1 = 0V P_6.0.50
200
VS = VOUT2 = 13.5 V
P_6.0.51
P_6.0.52
P_6.0.53
Ratio_IOL 1.8
Open load detection in OFF tf_OL
40
µs
–
filter time1)
SPI Timing (see Figure 4-6)1)
Cycle-time (1)
tcyc
tlead
tlag
tv
490
50
–
–
–
–
–
–
ns
ns
ns
ns
Referred to master
Referred to master
Referred to master
P_6.0.54
P_6.0.55
P_6.0.56
P_6.0.57
Enable Lead Time (2)
Enable Lag Time (3)
Data Valid (4) 3)
150
–
–
–
–
150
230
CL = 200 pF
CL = 350 pF
Referred to IFX9201SG
Data Setup Time (5)
Data Hold Time (6)
Disable Time (7)
tsu
th
40
40
–
–
–
–
–
–
–
–
ns
ns
ns
µs
ns
ns
Referred to master
Referred to master
P_6.0.58
P_6.0.59
–
tdis
td
100
–
Referred to IFX9201SG P_6.0.60
Transfer Delay (8)
Disable Lead Time (9)
Disable Lag Time (10)
Thermal Shutdown
2
Referred to master
Referred to master
Referred to master
P_6.0.61
P_6.0.62
P_6.0.63
tdld
tdlg
250
250
–
–
Thermal Shutdown Junction TjSD
150
125
175
–
–
–
°C
°C
–
–
P_6.0.64
P_6.0.65
Temperature1)
Thermal Switch-On Junction TjSO
Temperature1)
1) Not subject to production test, specified by design.
2) Output switching times are measured between 20% and 80% of the output swing
3) VSO timing thresholds are 20% / 80% of VVSO for 4.5V<VVSO<5.5V and 30% / 70% of VVSO for 2.9V<VVSO<4.5V
Data Sheet
21
Rev. 1.1, 2015-02-15
IFX9201SG
Application Information
7
Application Information
Note:The following information is given as a hint for the implementation of the device only and shall not be
regarded as a description or warranty of a certain functionality, condition or quality of the device. The function
of the described circuits must be verified in the real application
Supply Voltage
Vs<
100uF
100nF
40V
VS
3. 3 or 5V digital supply
VSO
OUT1
OUT2
DIS
PWM
DIR
CSN
SCK
SI
M
<33 nF
<33 nF
µC
SO
GND
Figure 4
Application Example H-Bridge with SPI interface
Supply Voltage
Vs<
100uF
100nF
40V
VS
3. 3 or 5V digital supply
VSO
OUT1
OUT2
DIS
PWM
DIR
CSN
SCK
SI
M
<33 nF
<33 nF
µC
SO
GND
Figure 5
Application Example H-Bridge with Error Flag
Data Sheet
22
Rev. 1.1, 2015-02-15
IFX9201SG
Application Information
VS
VSO
OUT1
OUT2
DIS
PWM
DIR
CSN
SCK
SI
M
<33 nF
<33 nF
µC
SO
GND
VS
VSO
OUT1
OUT2
DIS
PWM
DIR
CSN
SCK
SI
M
<33 nF
<33 nF
SO
GND
Figure 6
SPI Daisy Chain Konfiguration (other signals omitted for clarity)
Data Sheet
23
Rev. 1.1, 2015-02-15
IFX9201SG
Application Information
Supply Voltage
Vs<
40V
100uF
100nF
VS
3.3 or 5V digital supply
OUT1
OUT2
DIS
PWM
DIR
M
CSN
SCK
SI
<33 nF
<33 nF
µC
SO
VSO (EN)
GND
1nF
Figure 7
Application Example VSO as Enable Input
Reverse polarity protection via main relay
VS
main
relay
100µF
100nF
power
switch
supply
Reverse polarity protection using P -FET
10V
VS
100µF
100nF
10k
supply
Figure 8
Examples for Reverse Polarity Protection
The IFX9201SG is not protected against reverse polarity. External measures have to be taken to ensure the right
polarity of the supply voltage.
Data Sheet
24
Rev. 1.1, 2015-02-15
IFX9201SG
Package Outlines
8
Package Outlines
Figure 9
PG-DSO-12-17
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e
Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
For further information on alternative packages, please visit our website:
http://www.infineon.com/packages.
Dimensions in mm
Data Sheet
25
Rev. 1.1, 2015-02-15
IFX9201SG
Revision History
9
Revision History
Revision
0.1
Date
Changes
2014-04-16
2014-07-08
2014-08-19
Initial Product Proposal
0.2
Target Data Sheet
0.3
P_5.2.1: Supply voltage range max. changed to 36V
Table 4: Voltage range for electrical characteristics changed to VVS = 8V to 36V
1.0
1.1
2015-01-30
2015-02-15
Data Sheet
Device description updated in Overview page (page 3)
Disclaimer updated
Data Sheet
26
Rev. 1.1, 2015-02-15
Edition 2015-02-15
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2015 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
The Infineon Technologies component described in this data sheet may be used in life-support devices or systems
and/or automotive, aviation and aerospace applications or systems only with the express written approval of
Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-
support, automotive, aviation and aerospace device or system or to affect the safety or effectiveness of that device
or system. Life support devices or systems are intended to be implanted in the human body or to support and/or
maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user
or other persons may be endangered.
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