HYS64V4200GU-10 [INFINEON]
3.3V 4M x 64/72-Bit 1 BANK SDRAM Module 3.3V 8M x 64/72-Bit 2 BANK SDRAM Module; 3.3V 4M ×64 /72- 1位BANK SDRAM模块3.3V 8M ×64 /72- 2位BANK SDRAM模块
| 型号： | HYS64V4200GU-10 |
| 厂家： | 
Infineon |
| 描述： | 3.3V 4M x 64/72-Bit 1 BANK SDRAM Module 3.3V 8M x 64/72-Bit 2 BANK SDRAM Module |
| 文件： | 总15页 (文件大小：78K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V 4M x 64/72-Bit 1 BANK SDRAM Module
3.3V 8M x 64/72-Bit 2 BANK SDRAM Module
HYS64(72)V4200GU
HYS64(72)V8220GU
PC66 & PC100 168 pin unbuffered DIMM Modules
• 168 Pin unbuffered 8 Byte Dual-In-Line SDRAM Modules
for PC main memory applications
• One bank 4M x 64, 4Mx72 and two bank 8M x 64, 8M x 72 organisation
• Optimized for byte-write non-parity and ECC applications
• JEDEC standard Synchronous DRAMs (SDRAM)
• Fully PC board layout compatible to INTEL’s Rev. 1.0 module specification
• SDRAM Performance:
-8
-8B
100
-10
66
Units
MHz
fCK
tAC
Clock frequency (max.)
Clock access time
100
6
6
8
ns
• Programmed Latencies :
Product Speed
CL
2
tRCD
tRP
-8
PC100
PC100
PC66
2
2
2
2
3
2
-8B
-10
3
2
• Single +3.3V(± 0.3V ) power supply
• Programmable CAS Latency, Burst Length and Wrap Sequence
(Sequential & Interleave)
• Auto Refresh (CBR) and Self Refresh
• Decoupling capacitors mounted on substrate
• All inputs, outputs are LVTTL compatible
2
• Serial Presence Detect with E PROM
• Utilizes 4M x16 SDRAMs in TSOPII-54 packages
• 4096 refresh cycles every 64 ms
• 133,35 mm x 29,31 mm x 4,00 mm card size with gold contact pads
Semiconductor Group
1
8.98
HYS64(72)V4200/8220GU
SDRAM-Modules
The HYS64(72)V4200 and HYB64(72)V8220 are an industry standard 168-pin 8-byte Dual in-line Memory Module
(DIMM) which are organised as 4M x 64, 4M x 72 in an one bank and 8M x 64, 8M x72 in two banks high speed
memory arrays designed with 64Mbit Synchronous DRAMs (SDRAMs Die Rev.B) for non-parity and ECC
application. The DIMMs use -8 and -8B speed sort 4M x 16 SDRAM devices in TSOP54 packages to meet the
PC100 requirements and -10 parts for 66 MHz bus speed applications. Decoupling capacitors are mounted on the
PC board. The PC board design is according to INTEL’s module specification.
The DIMMs have a serial presence detect, implemented with a serial E2PROM using the two pin I2C protocol. The
first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user.
All SIEMENS 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 133,35 mm long footprint,
with t.d.b. height.
Ordering Information
Type
Ordering Code
Package
Descriptions
Module
Height
100 Mhz 4M x 64 1 bank SDRAM module
100 MHz 4M x 72 1 bank SDRAM module
100 Mhz 8M x 64 2 bank SDRAM module
100 MHz 8M x 72 2 bank SDRAM module
100 Mhz 4M x 64 1 bank SDRAM module
100 Mhz 8M x 64 2 bank SDRAM module
66 Mhz 4M x 64 1 bank SDRAM module
66 MHz 4M x 72 1 bank SDRAM module
66 Mhz 8M x 64 2 bank SDRAM module
66 MHz 8M x 72 2 bank SDRAM module
HYS 64V4200GU-8
HYS 72V4200GU-8
HYS 64V8220GU-8
HYS 64V8220GU-8
PC100-222-620
PC100-222-620
PC100-222-620
PC100-222-620
L-DIM-168-31
L-DIM-168-31
L-DIM-168-31
L-DIM-168-31
L-DIM-168-31
L-DIM-168-31
L-DIM-168-31
L-DIM-168-31
L-DIM-168-31
L-DIM-168-31
1,15”
1,15”
1,15”
1,15”
1,15”
1,15”
1,15”
1,15”
1,15”
1,15”
HYS 64V4200GU-8B PC100-323-620
HYS 64V8220GU-8B PC100-323-620
HYS 64V4200GU-10 PC66-222-620
HYS 72V4200GU-10 PC66-222-620
HYS 64V8220GU-10 PC66-222-620
HYS 64V8220GU-10 PC66-222-620
Pin Names
A0-A11
Address Inputs
CLK0 - CLK3
Clock Input
(RA0~ RA11 / CA0 ~ CA7, CA10)
BA0 , BA1
Bank Select
DQMB0 - DQMB7 Data Mask
DQ0 - DQ63 Data Input/Output
CS0 - CS3
Vcc
Chip Select
CB0-CB7
Check Bits (x 72 organisation
Power (+3.3 Volt)
only)
RAS
CAS
WE
Row Address Strobe
Column Address Strobe
Read / Write Input
Vss
SCL
Ground
Clock for Presence Detect
SDA
Serial Data Out for Pres. Detect
No Connection
CKE0, CKE1 Clock Enable
N.C. / DU
Address Format:
Part Number
Rows
12
Columns Bank Select
Refresh
4k
Period
64 ms
64 ms
64 ms
64 ms
Interval
15,6 µs
15,6 µs
15,6 µs
15,6 µs
4M x 64
4M x 72
8M x 64
8M x 72
HYS64V4200GU
HYS72V4200GU
HYS64V8220GU
HYS72V8220GU
8
8
8
8
2
2
2
2
12
4k
12
4k
12
4k
Semiconductor Group
2
HYS64(72)V4200/8220GU
SDRAM-Modules
Pin Configuration
PIN #
Symbol
PIN #
Symbol
PIN #
Symbol
PIN #
Symbol
1
VSS
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VCC
DQ14
DQ15
NC (CB0)
NC (CB1)
VSS
NC
43
VSS
85
VSS
127
VSS
2
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
DU
86
DQ32
DQ33
DQ34
DQ35
VCC
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
CKE0
CS3
3
CS2
87
4
DQMB2
DQMB3
DU
88
DQMB6
DQMB7
NC
5
89
6
90
7
VCC
91
VCC
NC
8
NC
92
9
NC
93
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
NC (CB2)
NC (CB3)
VSS
94
CB6
95
CB7
96
VSS
DQ16
DQ17
DQ18
DQ19
VCC
97
DQ41
DQ42
DQ43
DQ44
DQ45
VCC
DQ46
DQ47
NC (CB4)
NC (CB5)
VSS
DQ48
DQ49
DQ50
DQ51
VCC
DQ52
NC
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
DQ20
NC
DU
DU
CKE1
VSS
NC
VSS
DQ21
DQ22
DQ23
VSS
DQ53
DQ54
DQ55
VSS
NC
NC
NC
VCC
WE
VCC
CAS
DQ24
DQ25
DQ26
DQ27
VCC
DQ56
DQ57
DQ58
DQ59
VCC
DQ60
DQ61
DQ62
DQ63
VSS
DQMB0
DQMB1
CS0
DQMB4
DQMB5
CS1
DU
RAS
VSS
A0
DQ28
DQ29
DQ30
DQ31
VSS
VSS
A1
A2
A3
A4
A5
A6
A7
A8
CLK2
NC
A9
CLK3
NC
A10
BA0
BA1
WP
NC
SA0
VCC
VCC
CLK0
SDA
VCC
CLK1
NC
SA1
SCL
SA2
VCC
VCC
Note : Pinnames in brackets are for the x72 ECC versions
Semiconductor Group
3
HYS64(72)V4200/8220GU
SDRAM-Modules
CS0
CS
CS
LDQM
LDQM
DQMB0
DQ(7:0)
DQMB4
DQ0-DQ7
UDQM
DQ0-DQ7
DQ32-DQ39
UDQM
DQMB5
DQMB1
DQ(15:8)
DQ8-DQ15
DQ8-DQ15
D2
DQ40-DQ47
D0
CS
LDQM
CB(7:0)
DQ0-DQ7
Vcc
UDQM
DQ8-DQ15
D4
CS2
CS
CS
LDQM
LDQM
DQMB2
DQMB6
DQ(23:16)
DQ0-DQ7
DQ0-DQ7
DQ(55:48)
UDQM
UDQM
DQMB3
DQMB7
DQ(31:24)
DQ8-DQ15
DQ8-DQ15
D3
DQ(63:56)
D1
E2PROM (256wordx8bit)
SA0
SA1
SA2
SCL
SA0
A0-A11, BA0, BA1
VCC
D0 - D3, (D4)
D0 - D3, (D4)
D0 - D3, (D4)
SDA
WP
SA1
SA2
SCL
47k
C
VSS
RAS, CAS, WE
D0 - D3, (D4)
Clock Wiring
4M x 64
CLK0 2 SDRAM+15pF 3 SDRAM+10pF
CLK1 Termination Termination
CLK2 2 SDRAM+15pF 2 SDRAM+15pF
CLK3 Termination Termination
4M x 72
CKE0
D0 - D3, (D4)
CLK1,CLK3
10 pF
notes: 1) all resistors are 10 Ohms
2) D4 is only used in the x72 ECC version
3) DIMM may combine bytes 0 with 4, 1 with 5, 2 with 6 and 3 with 7 to obtain most advantagous
board layout to obtain minimum DQ trance length
Block Diagram for 4M x 64 and 4M x 72 1 bank SDRAM DIMM modules (HYS64V4200GU)
Semiconductor Group
4
HYS64(72)V4200/8220GU
SDRAM-Modules
CS0
CS1
CS
LDQM
CS
LDQM
CS
CS
LDQM
LDQM
DQMB4
DQMB0
DQ(7:0)
DQ(39:32)
DQ0-DQ7
UDQM
DQ0-DQ7
UDQM
DQ0-DQ7
UDQM
DQ0-DQ7
UDQM
DQMB5
DQMB1
DQ(15:8)
DQ8-DQ15 DQ8-DQ15
D0 D4
DQ8-DQ15 DQ8-DQ15
D2 D6
DQ(47:40)
CS
LDQM
CS
LDQM
Vcc
CB(7:0)
DQ0-DQ7
UDQM
DQ0-DQ7
UDQM
Vcc
DQ8-DQ15
DQ8-DQ15
D9
D8
CS2
CS3
CS
LDQM
CS
LDQM
CS
CS
LDQM
LDQM
DQMB6
DQMB2
DQ(23:16)
DQ(55:48)
DQ0-DQ7
UDQM
DQ0-DQ7
UDQM
DQ0-DQ7
UDQM
DQ0-DQ7
UDQM
DQMB7
DQMB3
DQ(31:24)
DQ8-DQ15 DQ8-DQ15
D1 D5
DQ8-DQ15 DQ8-DQ15
DQ(63:56)
D3
D7
E2PROM (256wordx8bit)
SA0
SA1
SA2
SCL
SA0
SA1
SA2
SCL
A0-A11, BA0, BA1
VCC
D0 - D7, (D8,D9)
SDA
WP
D0 - D7, (D8,D9)
D0 - D7, (D8,D9)
47k
C
VSS
RAS, CAS, WE
D0 - D7, (D8,D9)
Clock Wiring
8M x 64
8M x 72
CKE0
VDD
D0 - D3, (D8)
CLK0 2 SDRAM+15pF 3 SDRAM+10pF
CLK1 2 SDRAM+15pF 3 SDRAM+10pF
CLK2 2 SDRAM+15pF 2 SDRAM+15pF
CLK3 2 SDRAM+15pF 2 SDRAM+15pF
10k
CKE1
D4 - D7,(D9)
notes: 1) all resistors are 10 Ohms
2) D8 & D9 are only used in the x72 ECC version
3) DIMM may combine bytes 0 with 4, 1 with 5, 2 with 6 and 3 with 7 to obtain most advantagous
board layout to obtain minimum DQ trance length
Semiconductor Group
5
HYS64(72)V4200/8220GU
SDRAM-Modules
DC Characteristics
TA = 0 to 70 °C; VSS = 0 V; VDD,VDDQ = 3.3 V ± 0.3 V
Parameter
Symbol
Limit Values
Unit
min.
max.
Vcc+ 0.3
0.8
Input high voltage
VIH
VIL
2.0
– 0.5
2.4
V
Input low voltage
V
Output high voltage (IOUT = – 2.0 mA)
Output low voltage (IOUT = 2.0 mA)
VOH
VOL
II(L)
–
V
–
0.4
V
Input leakage current, any input
– 10
10
µA
(0 V < VIN < 3.6 V, all other inputs = 0 V)
Output leakage current
IO(L)
– 10
10
µA
(DQ is disabled, 0 V < VOUT < VCC)
Capacitance
TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz
Parameter
Symbol
Limit Values
max. max.
Unit
4M x 72
8M x 72
Input capacitance (A0 to A11, RAS, CAS, WE) CI1
tbd.
tbd.
pF
pF
pF
pF
pF
pF
Input capacitance (CS0 -CS3, )
Input capacitance (CLK0 - CLK3)
Input capacitance (CKE0, CKE1)
Input capacitance (DQMB0 - DQMB7)
CI2
CICL
CI3
CI4
CIO
tbd.
tbd.
tbd.
tbd.
tbd.
tbd.
tbd.
tbd.
Input / Output capacitance
tbd.
tbd.
(DQ0-DQ63,CB0-CB7)
Input Capacitance (SCL,SA0-2)
Input/Output Capacitance
C
C
8
8
pF
pF
sc
10
10
sd
Semiconductor Group
6
HYS64(72)V4200/8220GU
SDRAM-Modules
o
Operating Currents (T = 0 to 70 C, Vdd = 3.3V ± 0.3V 1)
A
(Recommended Operating Conditions unless otherwise noted)
Symb.
Note
Parameter & Test Condition
OPERATING CURRENT
-8/-8B
max.
-10
trc=trcmin., tck=tckmin.
Ouputs open, Burst Length = 4, CL=3
All banks operated in random access,
all banks operated in ping-pong manner
to maximize gapless data access
ICC1
130
2
90
2
mA
mA
1
1
PRECHARGE STANDBY CURRENT in tck = min.
Power Down Mode
ICC2P
tck = Infinity
ICC2PS
ICC2N
1
1
mA
mA
1
1
CS =VIH (min.), CKE<=Vil(max)
PRECHARGE STANDBY CURRENT in tck = min.
35
30
Non-Power Down Mode
tck = Infinity
ICC2NS
ICC3N
ICC3P
5
45
8
5
40
8
mA
mA
mA
1
1
1
CS = VIH (min.), CKE>=Vih(min)
NO OPERATING CURRENT
CKE>=VIH(min.)
CKE<=VIL(max.)
tck = min., CS = VIH(min),
active state ( max. 4 banks)
BURST OPERATING CURRENT
tck = min.,
Read command cycling
ICC4
ICC5
100
130
70
90
mA 1,2
AUTO REFRESH CURRENT
tck = min.,
1
mA
Auto Refresh command cycling
SELF REFRESH CURRENT
Self Refresh Mode, CKE=0.2V
standard version
ICC6
1
1
mA
1
Semiconductor Group
7
HYS64(72)V4200/8220GU
SDRAM-Modules
AC Characteristics 3)4)
TA = 0 to 70 °C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 1 ns
Symbol
Note
Parameter
Limit Values
-8B
Unit
-8
-10
PC100-222 PC100-323
PC66
min. max. min. max. min. max.
Clock and Clock Enable
Clock Cycle Time
tCK
fCK
tAC
CAS Latency = 3
CAS Latency = 2
10
10
–
–
10
12
–
–
10
15
–
–
ns
ns
System Frequency
CAS Latency = 3
CAS Latency = 2
–
–
100
100
–
–
100
83
–
–
100 MHz
66 MHz
Clock Access Time
4,5)
CAS Latency = 3
CAS Latency = 2
–
–
6
6
–
–
6
7
–
–
8
9
ns
ns
6)
6)
7)
7)
8)
Clock High Pulse Width
tCH
3
3
–
–
–
–
–
3
3
–
–
–
–
–
3.5
3.5
3
–
–
–
–
–
ns
ns
ns
ns
ns
Clock Low Pulse Width
Input Setup time
tCL
tCS
2
2
Input Hold Time
tCH
1
1
1
CKE Setup Time
tCKSP
2.5
2.5
3
(Power down mode)
9)
CKE Setup Time
(Self Refresh Exit)
tCKSR
tT
8
1
–
–
10
1
–
–
8
1
–
–
ns
ns
Transition time (rise and fall)
Common Parameters
RAS to CAS delay
Precharge Time
tRCD
tRP
tRAS
tRC
tRRD
tCCD
20
20
–
–
20
30
–
–
30
30
–
–
ns
ns
Active Command Period
Cycle Time
50 100k 60 100k 70 100k ns
–
–
–
80
20
1
–
–
–
80
20
1
–
–
–
70
16
1
ns
Bank to Bank Delay Time
ns
CAS to CAS delay time (same
bank)
CLK
Semiconductor Group
8
HYS64(72)V4200/8220GU
SDRAM-Modules
Symbol
Note
Parameter
Limit Values
-8B
Unit
-8
-10
PC100-222 PC100-323
PC66
min. max. min. max. min. max.
Refresh Cycle
8)
9)
Refresh Period (4096 cycles)
Self Refresh Exit Time
tREF
–
64
–
–
64
–
–
64 ms
tSREX
10
10
10
–
ns
Read Cycle
4)
Data Out Hold Time
tOH
tLZ
tHZ
3
0
3
–
–
–
8
2
3
0
3
–
3
0
3
–
–
–
ns
ns
Data Out to Low Impedance
Data Out to High Impedance
10)
10
2
10 ns
DQM Data Out Disable Latency tDQZ
2
CLK
Write Cycle
–
2
–
2
–
Data input to Precharge
tDPL
2
CLK
(write recovery)
–
–
5
0
–
–
5
–
–
Data In to Active/refresh
DQM Write Mask Latency
tDAL
5
0
CLK
CLK
tDQW
0
Semiconductor Group
9
HYS64(72)V4200/8220GU
SDRAM-Modules
Notes:
1. These parameters depend on the cycle rate. These values are measured at 100 MHz for -8 and
-8B and at 66 MHz for -10 modules. Input signals are changed once during tck, excepts for ICC6
and for standby currents when tck=infinity. All values are shown per memory component.
2. These parameters are measured with continous data stream during read access and all DQ
toggling. CL=3 and BL=4 assumed and the VDDQ current is excluded.
3. All AC characteristics are shown for device level.
An initial pause of 100µs is required after power-up, then a Precharge All Banks command must
be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can
begin.
4. AC timing tests have V = 0.4 V and V = 2.4 V with the timing referenced to the 1.4 V crossover
il
ih
point. The transition time is measured between V and V . All AC measurements assume t =1ns
ih
il
T
with the AC output load circuit show. Specified tac and toh parameters are measured with a 50
pF only, without any resistive termination and with a input signal of 1V / ns edge rate between
0.8V and 2.0 V.
tCH
+ 1.4 V
2.4 V
CLOCK
50 Ohm
0.4 V
tCL
t
T
Z=50 Ohm
tSETUP tHOLD
I/O
50 pF
1.4V
INPUT
tAC
tAC
I/O
tLZ
tOH
50 pF
Measurement conditions for
tac and toh
1.4V
OUTPUT
tHZ
fig.1
5. If clock rising time is longer than 1ns, a time (t /2 -0.5) ns has to be added to this parameter.
T
6. Rated at 1.5 V
7. If t is longen than 1 ns, a time (t -1) ns has to be added to this parameter.
T
T
8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh
commands must be given to “wake-up“ the device.
9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after
CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied
once the Self Refresh Exit command is registered.
10.Referenced to the time which the output achieves the open circuit condition, not to output voltage
levels.
Semiconductor Group
10
HYS64(72)V4200/8220GU
SDRAM-Modules
A serial presence detect storage device - E2PROM - is assembled onto the module. Information about the module
configuration, speed, etc. is written into the E2PROM device during module production using a serial presence
detect protocol ( I2C synchronous 2-wire bus)
SPD-Table for PC100 modules:
Byte#
Description
SPD Entry
Value
Hex
4Mx64 4Mx64 4Mx72 8Mx64 8Mx64 8Mx72
-8
80
08
04
0C
-8B
-8
80
08
04
0C
-8
80
08
04
0C
-8B
-8
80
08
04
0C
0
1
2
3
Number of SPD bytes
Total bytes in Serial PD
Memory Type
128
256
80
80
08
08
SDRAM
12
04
04
Number of Row Addresses (wit-
hout BS bits)
0C
0C
4
Number of Column Addresses
(for 16 SDRAM)
8
08
08
08
08
08
08
5
6
7
8
9
Number of DIMM Banks
Module Data Width
1 / 2
64
01
40
00
01
A0
60
01
40
00
01
A0
60
01
48
00
01
A0
60
02
40
00
01
A0
60
02
40
00
01
A0
60
02
48
00
01
A0
60
Module Data Width (cont’d)
Module Interface Levels
SDRAM Cycle Time at CL=3
0
LVTTL
10.0 ns
6.0 ns
10 SDRAM Access time from Clock
at CL=3
11 Dimm Config (Error Det/Corr.)
12 Refresh Rate/Type
none
00
80
00
80
02
80
00
80
00
80
02
80
Self-Refresh,
15.6µs
13 S D R A M w i dt h , P r im a r y
x 16
1 0
00
1 0
00
1 0
08
1 0
00
1 0
00
1 0
08
14 Error Checking SDRAM data
width
n/a / x8
15 Minimum clock delay for back-to-
back random column address
t
ccd = 1 CLK
01
8F
01
8F
01
8F
01
8F
01
8F
01
8F
16 Burst Length supported
1, 2, 4, 8 & full
page
17 Number of SDRAM banks
18 Supported CAS Latencies
19 CS Latencies
4
04
06
01
01
00
04
06
01
01
00
04
06
01
01
00
04
06
01
01
00
04
06
01
01
00
04
06
01
01
00
CL = 2 & 3
CS latency = 0
WL = 0
20 WE Latencies
21 SDRAM DIMM module attributes
non buffered/
non reg.
22 SDRAM Device Attributes :Gene- Vcc tol +/- 10%
ral
06
A0
60
FF
FF
14
06
C0
70
FF
FF
1E
06
A0
60
FF
FF
14
06
A0
60
FF
FF
14
06
C0
70
FF
FF
1E
06
A0
60
FF
FF
14
23 Minimum Clock Cycle Time at
CAS Latency = 2
10.0 / 12.0ns
24 Maximum data access time from
Clock for CL=2
6.0 / 7.0ns
25 Minimum Clock Cycle Time at CL not supported
= 1
26 Maximum Data Access Time
from Clock at CL=1
not supported
27 Minimum Row Precharge Time
20 / 30 ns
Semiconductor Group
11
HYS64(72)V4200/8220GU
SDRAM-Modules
Byte#
Description
SPD Entry
Value
Hex
4Mx64 4Mx64 4Mx72 8Mx64 8Mx64 8Mx72
-8
-8B
-8
-8
-8B
-8
28 Minimum Row Active to Row
Active delay tRRD
16 ns
20 ns
10
14
10
10
14
10
29 Minimum RAS to CAS delay
tRCD
14
14
14
14
14
14
30 Minimum RAS pulse width tRAS
31 Module Bank Density (per bank)
32 SDRAM input setup time
45 ns
32 MByte
2 ns
2D
08
20
10
20
10
FF
2D
08
20
10
20
10
FF
2D
08
20
10
20
10
FF
2D
08
20
10
20
10
FF
2D
08
20
10
20
10
FF
2D
08
20
10
20
10
FF
33 SDRAM input hold time
1 ns
34 SDRAM data input setup time
35 SDRAM data input hold time
2 ns
1 ns
62-61 Superset information (may be
used in future)
62 SPD Revision
Revision 1.2
100 MHz
12
D7
XX
12
15
XX
12
E9
XX
12
D8
XX
12
16
XX
12
EA
XX
63 Checksum for bytes 0 - 62
64- Manufacturers information (optio-
125 nal)
(FFh if not used)
126 Max. Frequency Specification
127 100 Mhz support details
128+ Unused storage locations
64
AF
FF
64
AD
FF
64
AF
FF
64
FF
FF
64
FD
FF
64
FF
FF
Semiconductor Group
12
HYS64(72)V4200/8220GU
SDRAM-Modules
SPD-Table for PC66 modules:
Byte#
Description
SPD Entry
Value
Hex
4Mx64 4Mx72 8Mx64 8Mx72
-10
80
08
04
0C
08
-10
80
08
04
0C
08
-10
80
08
04
0C
08
-10
80
08
04
0C
08
0
1
2
3
4
Number of SPD bytes
128
256
Total bytes in Serial PD
Memory Type
SDRAM
12
Number of Row Addresses (without BS bits)
Number of Column Addresses
(for x16 SDRAM)
8
5
6
7
8
9
Number of DIMM Banks
Module Data Width
1 / 2
64
01
40
00
01
A0
70
00
80
01
48
00
01
A0
70
02
80
02
40
00
01
A0
70
00
80
02
48
00
01
A0
70
02
80
Module Data Width (cont’d)
Module Interface Levels
SDRAM Cycle Time at CL=3
0
LVTTL
10.0 ns
7.0 ns
none
10 SDRAM Access time from Clock at CL=3
11 Dimm Config (Error Det/Corr.)
12 Refresh Rate/Type
Self-Refresh,
15.6µs
13 SDRAM width, Primary
x16
10
00
01
10
08
01
10
00
01
10
08
01
14 Error Checking SDRAM data width
n/a / x8
15 Minimum clock delay for back-to-back ran-
dom column address
tccd = 1 CLK
16 Burst Length supported
1, 2, 4, 8 & full
page
8F
8F
8F
8F
17 Number of SDRAM banks
18 Supported CAS Latencies
19 CS Latencies
4
04
06
01
01
00
04
06
01
01
00
04
06
01
01
00
04
06
01
01
00
CL = 2 & 3
CS latency = 0
WL = 0
20 WE Latencies
21 SDRAM DIMM module attributes
non buffered/
non reg.
22 SDRAM Device Attributes :General
Vcc tol +/- 10%
15.0 ns
06
F0
06
F0
06
F0
06
F0
23 Minimum Clock Cycle Time at CAS Latency
= 2
24 Maximum data access time from Clock for
CL=2
8.0 ns
80
80
80
80
25 Minimum Clock Cycle Time at CL = 1
not supported
not supported
FF
FF
FF
FF
FF
FF
FF
FF
26 Maximum Data Access Time from Clock at
CL=1
27 Minimum Row Precharge Time
24 ns
20 ns
18
14
18
14
18
14
18
14
28 Minimum Row Active to Row Active delay
tRRD
Semiconductor Group
13
HYS64(72)V4200/8220GU
SDRAM-Modules
SPD cont’d:
Byte#
Description
SPD Entry
Value
Hex
4Mx64 4Mx72 8Mx72 8Mx72
-8
18
3C
08
25
10
25
10
FF
-8
18
3C
08
25
10
25
10
FF
-8
18
3C
08
25
10
25
10
FF
-8
18
3C
08
25
10
25
10
FF
29 Minimum RAS to CAS delay tRCD
30 Minimum RAS pulse width tRAS
31 Module Bank Density (per bank)
32 SDRAM input setup time
24 ns
60 ns
32 MByte
2.5 ns
1 ns
33 SDRAM input hold time
34 SDRAM data input setup time
35 SDRAM data input hold time
2.5 ns
1 ns
32-61 Superset information
(may be used in future)
62 SPD Revision
Revision 1.2
66 MHz
12
7C
XX
12
8E
XX
12
7D
XX
12
8F
XX
63 Checksum for bytes 0 - 62
64- Manufacturers information (optional)
125 (FFh if not used)
126 Max. Frequency Specification
127 Support details
66
AF
FF
66
AF
FF
66
FF
FF
66
FF
FF
128+ Unused storage locations
Semiconductor Group
14
HYS64(72)V4200/8220GU
SDRAM-Modules
L-DIM-168-31
SDRAM DIMM Module package
133,35
127,35
4,0
x)
84
1
10 11
40 41
42,18
+ 0.1
1,27
-
66,68
A
C
B
85
94 95
124 125
168
x)
6,35
6,35
1,27
1,0 + 0.5
-
+
0,2 0,15
-
2,0
2,0
Detail C
Detail A
Detail B
DM168-31.WMF
x) on ECC modules only
Semiconductor Group
15
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