HYS64V64220GBDL [INFINEON]
144 pin SO-DIMM SDRAM Modules; 144针SO-DIMM SDRAM模块
| 型号： | HYS64V64220GBDL |
| 厂家： | 
Infineon |
| 描述： | 144 pin SO-DIMM SDRAM Modules |
| 文件： | 总13页 (文件大小：442K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
144 pin SO-DIMM SDRAM Modules
512 MB PC100 / PC133
HYS64V64220GBDL-7/7.5/8-D
•
u144 Pin Eight Byte Small Outline Dual-In-Line Synchronous DRAM Modules
for notebook applications
•
•
•
Two bank 64M x 64 non-parity module organisation
suitable for use in PC100 and PC133 applications
Performance:
-7
-7.5
-8
PC133
2-2-2
PC133
3-3-3
PC100
2-2-2
Units
fCK
tAC
Clock frequency (max.)
133
5.4
133
5.4
100
6
MHz
ns
Clock access time
CAS latency = 2 & 3
•
•
Single +3.3V( 0.3V ) power supply
Programmable CAS Latency, Burst Length and Wrap Sequence
(Sequential & Interleave)
•
•
•
•
•
•
•
•
Auto Refresh (CBR) and Self Refresh
Decoupling capacitors mounted on substrate
All inputs, outputs are LVTTL compatible
Serial Presence Detect with E2PROM
Uses sixteen 256Mbit SDRAM (32Mb x8 ) components in P-TFBGA packages
8196 refresh cycles every 64 ms
Gold contact pad, JEDEC MO-190 outline dimensions
This module family is fully pin and functional compatible
with the latest INTEL SO-DIMM specification
•
Importante Notice:
This SO-DIMM module is based on 256Mbit SDRAM technology and can be
used in applications only, where 256Mbit addressing is supported.
INFINEON Technologies
1
2002-08-06
HYS64V64220GBDL-7/7.5/8-D
144 pin SO-DIMM SDRAM Modules
This INFINEON module is an industry standard 144 pin 8-byte Synchronous DRAM (SDRAM) Small
Outline Dual In-line Memory Modules (SO-DIMM) which is organised as 64Mx64 high speed array
in two memory banks designed for use in non-parity applications. These SO-DIMMs use back side
protected P-TFBGA package technology. Decoupling capacitors are mounted on the board.
The DIMMs use serial presence detects implemented via a serial E2PROM using the two pin I2C
protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are
available to the end user.
All INFINEON 144-pin SO-DIMMs provide a high performance, flexible 8-byte interface in a 67,6
mm long footprint.
Product Spectrum
SDRAMs RowAddr.
used
Bank
Select
Column Refresh Period
Addr.
64M x 64
HYS64V64220GBDL-7-D 16 32Mx8
13
13
13
BA0, BA1
BA0, BA1
BA0, BA1
10
10
10
8k
8k
8k
64 ms
64 ms
64 ms
64M x 64 HYS64V64220GBDL-7.5-D 16 32Mx8
64M x 64
HYS64V64220GBDL-8-D 16 32Mx8
Note: All partnumbers end with a place code (not shown), designating the die revision. Consult factory for current
revision. Example: HYS64V64220GBDL-8-D, indicating Rev.D dies are used for SDRAM components.
Card Dimensions
Organisation
64M x 64
PCB-Board
L x H x T [mm]
L-DIM-144-14
67.60 x 29.21 x 3.80
Pin Names
A0-A12
BA0,BA1
DQ0 - DQ63
RAS
Address Inputs
Bank Selects
Data Input/Output
Row Address Strobe
Column Address Strobe
Read / Write Input
Clock Enable
CAS
WE
CKE0, CKE1
CLK0, CLK1
DQMB0 - DQMB7
CS0, CS1
VDD
Clock Input
Data Mask
Chip Select
Power (+3.3 Volt)
Ground
Vss
SCL
Clock for Presence Detect
SDA
Serial Data Out for Presence Detect
No Connection
N.C.
Infineon Technologies
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2002-08-06
HYS64V64220GBDL-7/7.5/8-D
144 pin SO-DIMM SDRAM Modules
Pin Configuration
Front
Side
Back
Side
Front
Side
Back
Side
PIN #
PIN #
PIN #
PIN #
1
VSS
2
VSS
73
NC
Vss
NC
NC
74
CLK1
3
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
Vss
4
DQ32
DQ33
DQ34
DQ35
VDD
DQ36
DQ37
DQ38
DQ39
Vss
75
76
Vss
5
6
77
78
NC
7
8
79
80
NC
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
81
VDD
DQ16
DQ17
DQ18
DQ19
Vss
82
VDD
DQ48
DQ49
DQ50
DQ51
Vss
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
83
84
85
86
87
88
89
90
91
92
93
DQ20
DQ21
DQ22
DQ23
VDD
A6
94
DQ52
DQ53
DQ54
DQ55
VDD
A7
DQMB0
DQMB1
VDD
A0
DQMB4
DQMB5
VDD
A3
95
96
97
98
99
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
A1
A4
A2
A5
A8
BA0
Vss
Vss
Vss
Vss
DQ8
DQ9
DQ10
DQ11
VDD
DQ12
DQ13
DQ14
DQ15
Vss
DQ40
DQ41
DQ42
DQ43
VDD
DQ44
DQ45
DQ46
DQ47
Vss
A9
BA1
A10
A11
VDD
DQMB2
DQMB3
Vss
VDD
DQMB6
DQMB7
Vss
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
Vss
DQ56
DQ57
DQ58
DQ59
VDD
DQ60
DQ61
DQ62
DQ63
Vss
NC
NC
NC
NC
CLK0
VDD
RAS
WE
CKE0
VDD
CAS
CKE1
A12
CS0
CS1
SDA
SCL
(A13)
VDD
VDD
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HYS64V64220GBDL-7/7.5/8-D
144 pin SO-DIMM SDRAM Modules
CS1
CS0
CS
CS
CS
CS
DQMB0
DQ(7:0)
DQM
DQM
DQM
DQM
DQMB4
DQ0-DQ7
DQ0-DQ7
DQ0-DQ7
DQ0-DQ7
DQ(39:32)
DQM
DQM
DQM
DQM
DQMB1
DQMB5
DQ(15:8)
DQ(47:40)
DQ0-DQ7
DQ0-DQ7
DQ0-DQ7
DQ0-DQ7
D6
D0
D4
D2
CS
CS
CS
CS
DQM
DQM
DQMB2
DQM
DQM
DQMB6
DQ(23:16)
DQ(55:48)
DQ0-DQ7
DQ0-DQ7
DQ0-DQ7
DQ0-DQ7
DQMB3
DQM
DQM
DQMB7
DQM
DQM
DQ(31:24)
DQ(63:56)
DQ0-DQ7
DQ0-DQ7
D5
DQ0-DQ7
DQ0-DQ7
D7
D1
D3
D0 - D7
A0-A12,BA0,BA1
VDD
E2PROM (256wordx8bit)
D0 - D7
D0 - D7
SA0
SA1
C
VSS
SA2
SCL
SDA
RAS, CAS, WE
D0 - D7
CKE0
CKE1
D0 - D3
D4 - D7
8 Loads
8 Loads
CLK0
CLK1
Note: 1. DQ wiring may differ from the description in this
drawing, however DQ/DQMB/CKE/CS relationship
is maintained as shown.
2. In this design each of the D0 - D7 components
are represented by two 32M x 8 chips. These two
chips effectively work as a single 32M x 16 device.
3. All resistors are 10 Ohm.
Block Diagram for two bank 64M x 64 SDRAM DIMM - Module
Infineon Technologies
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2002-08-06
HYS64V64220GBDL-7/7.5/8-D
144 pin SO-DIMM SDRAM Modules
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
Unit
min.
– 1.0
– 1.0
-55
–
max.
4.6
Input / Output voltage relative to VSS
Power supply voltage on VDD
Storage temperature range
Power dissipation
VIN, VOUT
VDD
TSTG
PD
V
4.6
V
+125
16
oC
W
mA
Data out current (short circuit)
IOS
–
50
Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded.
Functional operation should be restricted to recommended operation conditions.
Exposure to higher than recommended voltage for extended periods of time affect device reliability
DC Characteristics
TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V 0.3 V
Parameter
Symbol
Limit Values
Unit
min.
2.0
max.
Input high voltage
VIH
VIL
VDD+0.3
V
Input low voltage
– 0.5
2.4
0.8
–
V
Output high voltage (IOUT = – 4.0 mA)
Output low voltage (IOUT = 4.0 mA)
VOH
VOL
II(L)
V
–
0.4
20
V
Input leakage current, any input
(0 V < VIN < 3.6 V, all other inputs = 0 V)
– 20
µA
Output leakage current
(DQ is disabled, 0 V < VOUT < VDD
IO(L)
– 20
20
µA
)
Capacitance
TA = 0 to 70 °C; VDD = 3.3 V 0.3 V, f = 1 MHz
Parameter
Symbol
Limit
Values
Unit
64M x 64
max.
Input capacitance (A0 to A11, BA0, BA1)
Input capacitance (RAS, CAS, WE)
Input Capacitance (CLK0, CLK1)
Input capacitance (CS0, CS1)
CI1
CI2
CI3
CI4
CI5
CI6
CIO
Csc
Csd
85
85
70
60
15
50
18
8
pF
pF
pF
pF
pF
pF
pF
pF
pF
Input capacitance (DQMB0-DQMB7)
Input capacitance (CKE0, CKE1)
Input / Output capacitance (DQ0-DQ63)
Input Capacitance (SCL,SA0-2)
Input/Output Capacitance (SDA)
10
Infineon Technologies
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HYS64V64220GBDL-7/7.5/8-D
144 pin SO-DIMM SDRAM Modules
Operating Currents per memory bank
(TA = 0 to 70oC, VDD = 3.3V 0.3V)
(Recommended Operating Conditions unless otherwise noted)
Symb.
64Mx64
512Mbyte
Note
Parameter & Test Condition
PC133
PC100
OPERATING CURRENT
trc=trcmin.,
All banks operated in random access,
all banks operated in ping-pong manner
1, 2
1
ICC1
1840
16
1360
mA
PRECHARGE STANDBY CURRENT
in Power Down Mode
tck = min.
tck = min.
ICC2P
16
mA
mA
CS =VIH (min.), CKE<=Vil(max)
PRECHARGE STANDBY CURRENT
in Non-Power Down Mode
1
240
ICC2N
320
CS = VIH (min.), CKE>=Vih(min)
NO OPERATING CURRENT
CKE>=VIH(min.) ICC3N
CKE<=VIL(max.) ICC3P
1
1
400
80
360
80
mA
mA
tck = min., CS = VIH(min),
active state ( max. 4 banks)
BURST OPERATING CURRENT
tck = min.,
Read command cycling
1, 2
1
ICC4
1200
800
mA
mA
AUTO REFRESH CURRENT
tck = min., trc = trcmin.
Auto Refresh command cycling
ICC5
ICC6
1920
14
1760
14
SELF REFRESH CURRENT
Self Refresh Mode, CKE=0.2V
tck =infinity
1
mA
Notes:
1. These parameters depend on the cycle rate. These values are measured at 133 MHz operation frequency for PC133
and at 100MHz for PC100 modules. Input signals are changed once during tck, excepts for ICC6 and for standby currents
when tck=infinity.
2. These parameters are measured with continuous data stream during read access and all DQ toggling. CL=3 and BL=4
is assumed and the data-out current is excluded.
Infineon Technologies
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HYS64V64220GBDL-7/7.5/8-D
144 pin SO-DIMM SDRAM Modules
AC Characteristics 9)10)
A = 0 to 70 oC; VSS = 0 V; VDD, VDDQ = 3.3 V 0.3 V, tT = 1 ns
T
TA = 0 to 70 °C; VSS = 0 V; V
= 3.3 V 0.3 V, tT = 1 ns
DD
Symbol
Unit
Parameter
Limit Values
-7
PC133-
222
-7.5
PC133-
333
-8
PC100-
222
min. max. min. max. min. max.
Clock and Clock Enable
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
7
7.5
–
–
7.5
10
–
–
8
10
–
–
ns
ns
tCK
tCK
tAC
Clock Frequency
CAS Latency = 3
CAS Latency = 2
–
–
143
133
–
–
133
100
–
–
125 MHz
100 MHz
Access Time from Clock
2,
3,
6
CAS Latency = 3
CAS Latency = 2
–
–
5.4
5.4
–
–
5.4
6
–
–
6
6
ns
ns
Clock High Pulse Width
tCH
tCL
tT
2.5
2.5
0.3
–
–
2.5
2.5
–
–
3
3
–
–
ns
ns
Clock Low Pulse Width
Transition time
1.2 0.3
1.2 0.5
10 ns
Setup and Hold Times
Input Setup Time
Input Hold Time
4
4
4
4
tIS
tIH
1.5
0.8
1.5
0.8
2
–
–
–
–
–
1.5
0.8
1.5
0.8
2
–
–
–
–
–
2
1
2
1
2
–
–
–
–
–
ns
ns
CKE Setup Time
CKE Hold Time
tCKS
tCKH
tRSC
ns
ns
Mode Register Set-up to Active
delay
CLK
Power Down Mode Entry Time
tSB
0
7
0
7.5
0
8
ns
Common Parameters
Row to Column Delay Time
Row Precharge Time
5
5
tRCD
tRP
15
15
–
–
20
20
–
–
20
20
–
–
ns
ns
Infineon Technologies
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HYS64V64220GBDL-7/7.5/8-D
144 pin SO-DIMM SDRAM Modules
AC Characteristics 9)10)
A = 0 to 70 oC; VSS = 0 V; VDD, VDDQ = 3.3 V 0.3 V, tT = 1 ns
T
TA = 0 to 70 °C; VSS = 0 V; V
= 3.3 V 0.3 V, tT = 1 ns
DD
Symbol
Unit
Parameter
Limit Values
-7
PC133-
222
-7.5
PC133-
333
-8
PC100-
222
min. max. min. max. min. max.
100k
–
100k
–
5
5
Row Active Time
Row Cycle Time
tRAS
tRC
37 100k 45
48
70
70
ns
ns
ns
60
63
–
67
67
Row Cycle Time during Auto
Refresh
tRFC
5
Activate(a) to Activate(b)
Command period
tRRD
tCCD
14
1
–
–
15
1
–
–
16
1
–
–
ns
CAS(a) to CAS(b) Command
period
CLK
Refresh Cycle
Refresh Period (8192 cycles)
Self Refresh Exit Time
tREF
–
1
64
–
–
1
64
–
–
1
64 ms
CLK
tSREX
Read Cycle
Data Out Hold Time
tOH
3
–
3
–
3
–
ns
2,
6
Data Out to Low Impedance Time
Data Out to High Impedance Time
DQM Data Out Disable Latency
tLZ
tHZ
0
3
–
–
7
2
0
3
–
–
7
2
0
3
–
–
8
2
ns
ns
tDQZ
CLK
Write Cycle
7
8
Last Data Input to Precharge
(Write without AutoPrecharge)
tWR
tDAL,min
tDQW
14
0
–
–
15
0
–
–
15
0
–
–
ns
Last Data Input to Activate
(Write with AutoPrecharge)
CLK
CLK
DQM Write Mask Latency
Infineon Technologies
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HYS64V64220GBDL-7/7.5/8-D
144 pin SO-DIMM SDRAM Modules
Notes
1. For proper power-up see the operation section of the component sheet.
2. AC timing tests for LV-TTL versions have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to
the 1.4 V crossover point. The transition time is measured between VIH and VIL. All AC
measurements assume tT = 1 ns with the AC output load circuit shown in figure below. Specified
tAC and tOH parameters are measured with a 50 pF only, without any resistive termination and
with an input signal of 1V / ns edge rate between 0.8 V and 2.0 V.
t CH
2.4
0.4
V
V
1 .4 V
C L O C K
tT
tC L
tIH
tIS
IN PU T
1 .4 V
tAC
tA C
tL Z
t OH
O U TPU T
1.4 V
I/O
50 pF
tH Z
Measurement conditions for
IO.vsd
tAC and tOH
3. If clock rising time is longer than 1 ns, a time (tT/2 − 0.5) ns has to be added to this parameter.
4. If tT is longer than 1 ns, a time (tT − 1) ns has to be added to this parameter.
5. These parameter account for the number of clock cycles and depend on the operating frequency
of the clock, as follows: the number of clock cycles = specified value of timing period (counted in
fractions as a whole number)
6. Access time from clock tAC is 4.6 ns for PC133 components with no termination and 0 pF load,
Data out hold time tOH is 1.8 ns for PC133 components with no termination and 0 pF load.
7. It is recommended to use two clock cycles between the last data-in and the precharge command
in case of a write command without Auto-Precharge. One clock cycle between the last data-in
and the precharge command is also supported, but restricted to cycle times tck greater or equal
the specified twr value, where tck is equal to the actual system clock time
8. When a Write command with AutoPrecharge has been issued, a time of tdal(min) has be fullfilled
before the next Activate Command can be applied. For each of the terms, if not already an
integer, round up to the next highest integer. tck is equal to the actual system clock time.
9. All AC characteristics shown are for SDRAM components. An initial pause of 100µs is required
after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh
(CBR) cycles before the Mode Register Set Operation can begin.
10.AC timing tests have Vil = 0.4 V and Vih = 2.4 V with the timing referenced to the 1.4 V crossover
point. The transition time is measured between Vih and Vil. All AC measurements assume tT=1ns
Infineon Technologies
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144 pin SO-DIMM SDRAM Modules
with the AC output load circuit shown.Specified tac and toh parameters are measured with a
50pF only, without any resistive termination and with a input signal of 1V / ns edge rate between
0.8V and 2.0 V.
Infineon Technologies
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144 pin SO-DIMM SDRAM Modules
Serial Presence Detects
A serial presence detect storage device - E2PROM - is assembled onto the module. Information
about the module configuration, speed, etc. is written into the E2PROM device during module
production using a serial presence detect protocol ( I2C synchronous 2-wire bus)
SPD-Table:
Byte#
Description
SPD Entry Value
Hex
64Mx64
-7
64Mx64
-7.5
64Mx64
-8
0
1
2
3
Number of SPD bytes
128
256
80
08
04
0D
Total bytes in Serial PD
Memory Type
SDRAM
12
Number of Row Addresses
(without BS)
4
5
Number of Column Addresses
Number of DIMM Banks
Module Data Width
10
0A
02
40
00
01
75
54
2
6
64
0
7
Module Data Width (cont’d)
Module Interface Levels
SDRAM Cycle Time at CL=3
8
LVTTL
9
7.5ns / 10.0 ns
5.4ns / 6.0 ns
75
54
A0
60
10
SDRAM Access time from Clock at
CL=3
11
12
13
14
15
Dimm Config (Error Det/Corr.)
Refresh Rate/Type
none
Self-Refresh, 7,6µs
x8
00
82
08
00
01
SDRAM width, Primary
Error Checking SDRAM data width
n/a
Minimum clock delay for back-to-
back random column address
tccd = 1 CLK
16
17
18
19
20
21
Burst Length supported
Number of SDRAM banks
Supported CAS Latencies
CS Latencies
1, 2, 4 & 8
2
0F
04
06
01
01
00
2, & 3
CS latency = 0
Write latency = 0
WE Latencies
SDRAM DIMM module attributes
non buffered/non
reg.
22
23
24
SDRAM Device Attributes :General
SDRAM Cycle Time at CL = 2
VDD tol +/- 10%
7.5ns / 10.0 ns
5.4ns / 6.0 ns
0E
75
54
A0
60
SDRAM Access Time from Clock at
CL=2
25
26
SDRAM Cycle Time at CL = 1
not supported
not supported
00
00
FF
FF
FF
FF
SDRAM Access Time from Clock at
CL=1
27
Minimum Row Precharge Time
20 ns
0F
14
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144 pin SO-DIMM SDRAM Modules
SPD-Table (cont’d):
Byte#
Description
SPD Entry Value
Hex
Hex
Hex
64Mx64
-7
64Mx64
-7.5
64Mx64
-8
28
Minimum Row Active to Row Active
delay
14/15/16 ns
0E
0F
10
29
30
31
32
33
34
35
Minimum RAS to CAS delay
Minimum Ras pulse width
Module Bank Density (per bank)
SDRAM input setup time
15/20 ns
42/45 ns
256 MB
2 ns
0F
2A
14
2D
40
15
08
15
08
FF
12
37
XX
32
15
08
15
08
00
20
10
20
10
FF
SDRAM input hold time
1 ns
SDRAM data input setup time
SDRAM data input hold time
2 ns
1 ns
36-61 Superset information
62
63
SPD Revision
Revision 1.2
PC100
Checksum for bytes 0 - 62
0E
9A
64- Manufactures’s information (optional)
125
126 Frequency Specification
127 Details
64
C7
FF
128+ Unused storage locations
00
FF
Infineon Technologies
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144 pin SO-DIMM SDRAM Modules
Package Outlines
512 MByte SO-DIMM Module package (JEDEC MO-190)
(144 pin, dual in-line memory module)
0.15
67.6
3.8 max.
63.6
Detail of Contacts
heat spreader
0.6
1
59
61
143
144
0.1
1
(3.3)
0.8
23.2
24.5
32.8
2.5
4.6
1.5
60
1.8
(3.7)
Detail of Chamfer
2
62
4
0.2
0.15
-
L-DIM-144-14
Note: All tolerances according to JEDEC standard
Infineon Technologies
13
2002-08-06
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