HYB39S128800DT-6 [INFINEON]
Synchronous DRAM, 16MX8, 5ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-54;
| 型号： | HYB39S128800DT-6 |
| 厂家： | 
Infineon |
| 描述： | Synchronous DRAM, 16MX8, 5ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-54 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总52页 (文件大小：451K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HYB 39S128400/800/160DT(L)
128-MBit Synchronous DRAM
128-MBit Synchronous DRAM
Preliminary Target Specification 10.01
High Performance:
•
•
Multiple Burst Read with Single Write
Operation
-6
-7
-7.5 -8
Units
Automatic and Controlled Precharge
Command
fCK
166 143 133 125 MHz
tCK3
tAC3
tCK2
tAC2
6
7
7.5
5.4
10
6
8
ns
ns
ns
ns
•
•
•
•
•
•
Data Mask for Read/Write Control (x4, x8)
Data Mask for byte control (x16)
5
5.4
7.5
5.4
6
Auto Refresh (CBR) and Self Refresh
Power Down and Clock Suspend Mode
4096 Refresh Cycles / 64 ms
7.5
5.4
10
6
•
•
•
•
•
•
Single Pulsed RAS Interface
Random Column Address every CLK
(1-N Rule)
Fully Synchronous to Positive Clock Edge
0 to 70 °C operating temperature
•
•
•
Single 3.3 V ± 0.3 V Power Supply
LVTTL Interface
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2, 3
Plastic Packages:
P-TSOPII-54 400mil x 875 mil width
(x4, x8, x16)
Programmable Wrap Sequence: Sequential
or Interleave
•
-6
-7
for PC 166 3-3-3 applications
for PC 133 2-2-2 applications
•
Programmable Burst Length:
1, 2, 4, 8 and full page
-7.5 for PC 133 3-3-3 applications
-8 for PC100 2-2-2 applications
The HYB 39S128400/800/160DT(L) are four bank Synchronous DRAM’s organized as
4
banks × 8MBit x4, 4 banks × 4MBit x8 and 4 banks × 2Mbit x16 respectively. These synchronous
devices achieve high speed data transfer rates by employing a chip architecture that prefetches
multiple bits and then synchronizes the output data to a system clock. The chip is fabricated using
the Infineon advanced 0.17 micron process technology.
The device is designed to comply with all industry standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur
at higher a rate than is possible with standard DRAMs. A sequential and gapless data rate is
possible depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single
3.3 V ± 0.3 V power supply and are available in TSOPII packages.
INFINEON Technologies
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10.01
HYB 39S128400/800/160DT(L)
128-MBit Synchronous DRAM
Ordering Information
Type
Function Code Package
Description
166MHz 4B × 8M x4 SDRAM
143MHz 4B × 8M x4 SDRAM
133 MHz 4B × 8M x4 SDRAM
100 MHz 4B × 8M x4 SDRAM
166 MHz 4B × 4M x8 SDRAM
143 MHz 4B × 4M x8 SDRAM
133 MHz 4B × 4M x8 SDRAM
100 MHz 4B × 4M x8 SDRAM
166 MHz 4B × 2M x16 SDRAM
143 MHz 4B × 2M x16 SDRAM
133 MHz 4B × 2M x16 SDRAM
100 MHz 4B × 2M x16 SDRAM
HYB 39S128400DT-6
HYB 39S128400DT-7
HYB 39S128400DT-7.5
HYB 39S128400DT-8
HYB 39S128800DT-6
HYB 39S128800DT-7
HYB 39S128800DT-7.5
HYB 39S128800DT-8
HYB 39S128160DT-6
HYB 39S128160DT-7
HYB 39S128160DT-7.5
HYB 39S128160DT-8
HYB 39S128160DTL-8
PC166-333-520 P-TSOP-54 (400mil)
PC133-222-520 P-TSOP-54 (400mil)
PC133-333-520 P-TSOP-54 (400mil)
PC100-222-620 P-TSOP-54 (400mil)
PC166-333-520 P-TSOP-54 (400mil)
PC133-222-520 P-TSOP-54 (400mil)
PC133-333-520 P-TSOP-54 (400mil)
PC100-222-620 P-TSOP-54 (400mil)
PC166-333-520 P-TSOP-54 (400mil)
PC133-222-520 P-TSOP-54 (400mil)
PC133-333-520 P-TSOP-54 (400mil)
PC100-222-620 P-TSOP-54 (400mil)
PC100-222-620 P-TSOP-54 (400mil)
100 MHz 4B × 2M x16 SDRAM
Low Power (“L”) version
133 MHz 4B × 2M x16 SDRAM
Low Power (“L”) version
HYB 39S128160DTL-7.5 PC133-333-520 P-TSOP-54 (400mil)
133 MHz 4B × 2M x16 SDRAM
Low Power (“L”) version
HYB 39S128160DTL-7
PC133-222-520 P-TSOP-54 (400mil)
Pin Definitions and Functions
CLK
CKE
Clock Input
DQ
Data Input/Output
Data Mask
Clock Enable
DQM, LDQM,
UDQM
CS
Chip Select
VDD
VSS
Power (+ 3.3 V)
Ground
RAS
Row Address Strobe
CAS
Column Address Strobe VDDQ
Power for DQ’s (+ 3.3 V)
Ground for DQ’s
Not connected
WE
Write Enable
Address Inputs
Bank Select
VSSQ
A0 - A11
BA0, BA1
N.C.
INFINEON Technologies
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10.01
HYB 39S128400/800/160DT(L)
128-MBit Synchronous DRAM
8 M x 16
16 M x 8
32 M x 4
VDD
VDD
VDD
VSS
VSS
VSS
1
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
DQ0
VDDQ
DQ0
VDDQ
N.C.
VDDQ
2
3
N.C.
VSSQ
DQ7
VSSQ
DQ15
VSSQ
DQ1
DQ2
VSSQ
N.C.
DQ1
VSSQ
N.C.
DQ0
VSSQ
4
5
6
N.C.
DQ3
VDDQ
N.C.
DQ6
VDDQ
DQ14
DQ13
VDDQ
DQ3
DQ4
VDDQ
N.C.
DQ2
VDDQ
N.C.
N.C.
VDDQ
7
N.C.
N.C.
VSSQ
N.C.
DQ5
VSSQ
DQ12
DQ11
VSSQ
8
9
DQ5
DQ6
VSSQ
N.C.
DQ3
VSSQ
N.C.
DQ1
VSSQ
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
N.C.
DQ2
VDDQ
N.C.
DQ4
VDDQ
DQ10
DQ9
VDDQ
DQ8
VSS
DQ7
VDD
N.C.
VDD
N.C.
VDD
N.C.
VSS
N.C.
VSS
LDQM N.C.
N.C.
WE
CAS
RAS
CS
N.C.
DQM
CLK
CKE
N.C.
A11
A9
N.C.
DQM
CLK
CKE
N.C.
A11
A9
N.C.
UDQM
CLK
CKE
N.C.
A11
A9
WE
CAS
RAS
CS
WE
CAS
RAS
CS
BA0
BA1
A10
A0
BA0
BA1
A10
A0
BA0
BA1
A10
A0
A8
A8
A8
A7
A7
A7
A1
A2
A3
VDD
A1
A2
A3
VDD
A1
A2
A3
VDD
A6
A5
A4
VSS
A6
A5
A4
VSS
A6
A5
A4
VSS
TSOPII-54 (10.16 mm x 22.22 mm, 0.8 mm pitch)
SPP04121
Pin Configuration for x4, x8 & x16 Organized 128M-DRAMs
INFINEON Technologies
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10.01
HYB 39S128400/800/160DT(L)
128-MBit Synchronous DRAM
Functional Block Diagrams
Column Addresses
Row Addresses
A0 - A9, A11, AP,
BA0, BA1
A0 - A11,
BA0, BA1
Column Address
Counter
Column Address
Buffer
Row Address
Buffer
Refresh Counter
Row
Decoder
Row
Decoder
Row
Decoder
Row
Decoder
Memory
Array
Memory
Array
Memory
Array
Memory
Array
Bank 0
Bank 1
Bank 2
Bank 3
4096
x 2048
x 4 Bit
4096
x 2048
x 4 Bit
4096
x 2048
x 4 Bit
4096
x 2048
x 4 Bit
Input Buffer Output Buffer
DQ0 - DQ3
Control Logic &
Timing Generator
SPB04122
Block Diagram: 32M x4 SDRAM (12 / 11 / 2 addressing)
INFINEON Technologies
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10.01
HYB 39S128400/800/160DT(L)
128-MBit Synchronous DRAM
Column Addresses
Row Addresses
A0 - A9, AP,
BA0, BA1
A0 - A11,
BA0, BA1
Column Address
Counter
Column Address
Buffer
Row Address
Buffer
Refresh Counter
Row
Decoder
Row
Decoder
Row
Decoder
Row
Decoder
Memory
Array
Memory
Array
Memory
Array
Memory
Array
Bank 0
Bank 1
Bank 2
Bank 3
4096
x 1024
x 8 Bit
4096
x 1024
x 8 Bit
4096
x 1024
x 8 Bit
4096
x 1024
x 8 Bit
Input Buffer Output Buffer
DQ0 - DQ7
Control Logic &
Timing Generator
SPB04123
Block Diagram: 16M x8 SDRAM (12 / 10 / 2 addressing)
INFINEON Technologies
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10.01
HYB 39S128400/800/160DT(L)
128-MBit Synchronous DRAM
Column Addresses
Row Addresses
A0 - A8, AP,
BA0, BA1
A0 - A11,
BA0, BA1
Column Address
Counter
Column Address
Buffer
Row Address
Buffer
Refresh Counter
Row
Decoder
Row
Decoder
Row
Decoder
Row
Decoder
Memory
Array
Memory
Array
Memory
Array
Memory
Array
Bank 0
Bank 1
Bank 2
Bank 3
4096 x 512
x 16 Bit
4096 x 512
x 16 Bit
4096 x 512
x 16 Bit
4096 x 512
x 16 Bit
Input Buffer Output Buffer
DQ0 - DQ15
Control Logic &
Timing Generator
SPB04124
Block Diagram: 8M x16 SDRAM (12 / 9 / 2 addressing)
INFINEON Technologies
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10.01
HYB 39S128400/800/160DT(L)
128-MBit Synchronous DRAM
Signal Pin Description
Pin
Type Signal Polarity Function
CLK
Input
Pulse Positive The system clock input. All of the SDRAM inputs are
Edge
sampled on the rising edge of the clock.
CKE
CS
Input
Level Active
High
Activates the CLK signal when high and deactivates the
CLK signal when low, thereby initiating either the Power
Down mode, Suspend mode, or the Self Refresh mode.
Input
Input
Pulse Active
Low
CS enables the command decoder when low and disables
the command decoder when high. When the command
decoder is disabled, new commands are ignored but
previous operations continue.
RAS
CAS
WE
Pulse Active
Low
When sampled at the positive rising edge of the clock,
CAS, RAS, and WE define the command to be executed by
the SDRAM.
A0 - A11 Input
Level
–
During a Bank Activate command cycle, A0 - A11 define
the row address (RA0 - RA11) when sampled at the rising
clock edge.
During a Read or Write command cycle, A0-An define the
column address (CA0 - CAn) when sampled at the rising
clock edge.CAn depends upon the SDRAM organization:
32M x4 SDRAM CA0 - CA9, CA11
(Page Length = 2048 bits)
16M x8 SDRAM CA0 - CA9
(Page Length = 1024 bits)
8M x16 SDRAM CA0 = CA8 (Page Length = 512 bits)
In addition to the column address, A10(= AP) is used to
invoke the autoprecharge operation at the end of the burst
read or write cycle. If A10 is high, autoprecharge is
selected and BA0, BA1 defines the bank to be precharged.
If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10 (= AP) is used in
conjunction with BA0 and BA1 to control which bank(s) to
precharge. If A10 is high, all four banks will be precharged
regardless of the state of BA0 and BA1. If A10 is low, then
BA0 and BA1 are used to define which bank to precharge.
BA0, BA1 Input
Level
Level
–
–
Bank Select Inputs. Selects which bank is to be active.
DQx
Input
Data Input/Output pins operate in the same manner as on
conventional DRAMs.
Output
INFINEON Technologies
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10.01
HYB 39S128400/800/160DT(L)
128-MBit Synchronous DRAM
Signal Pin Description (cont’d)
Pin
Type Signal Polarity Function
DQM
LDQM
UDQM
Input
Pulse Active
High
The Data Input/Output mask places the DQ buffers in a
high impedance state when sampled high. In Read mode,
DQM has a latency of two clock cycles and controls the
output buffers like an output enable. In Write mode, DQM
has a latency of zero and operates as a word mask by
allowing input data to be written if it is low but blocks the
write operation if DQM is high.
One DQM input is present in x4 and x8 SDRAMs, LDQM
and UDQM controls the lower and upper bytes in x16
SDRAMs.
VDD
VSS
Supply –
Supply –
–
–
Power and ground for the input buffers and the core logic.
VDDQ
VSSQ
Isolated power supply and ground for the output buffers to
provide improved noise immunity.
INFINEON Technologies
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10.01
HYB 39S128400/800/160DT(L)
128-MBit Synchronous DRAM
Operation Definition
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at
the positive edge of the clock. The following list shows the truth table for the operation commands.
Operation
Device
State
CKE CKE DQM BA0 AP= Addr CS
RAS CAS WE
n-1
n
BA1 A10 A11,
A9-0
Bank Active
Bank Precharge
Precharge All
Write
Idle3
Any
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
V
V
X
V
V
V
V
V
X
X
X
X
X
V
L
V
X
X
V
V
V
V
V
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
H
L
L
H
L
L
L
H
H
H
L
H
L
Any
H
L
L
L
Active3
H
H
H
H
L
L
Write with Autoprecharge Active3
Read
Active3
Read with Autoprecharge Active3
H
L
L
L
L
H
H
L
H
V
X
X
X
X
X
L
Mode Register Set
No Operation
Idle
L
Any
Active
Any
Idle
H
H
X
L
H
H
X
L
H
L
Burst Stop
Device Deselect
Auto Refresh
X
H
H
X
X
Self Refresh Entry
Self Refresh Exit
Idle
L
L
Idle
(Self
Refr.)
X
H
X
H
L
H
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
Power Down Entry
(Precharge or active
standby)
Idle
H
L
X
H
X
H
X
H
Active4
Power Down Exit
Any
(Power
Down)
H
L
X
H
X
H
X
L
H
Data Write/Output Enable Active
Data Write/Output Disable Active
Notes:
H
H
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
1. V = Valid, x = Don’t Care, L = Low Level, H = High Level.
2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock
before the commands are provided.
3. This is the state of the banks designated by BA0, BA1 signals.
4. Power Down Mode can not entry in the burst cycle. When this command is asserted in the burst
mode cycle than the device is in clock suspend mode.
INFINEON Technologies
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10.01
HYB 39S128400/800/160DT(L)
128-MBit Synchronous DRAM
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus (Ax)
Operation Mode
CAS Latency
BT
Burst Length Mode Register (Mx)
Operation Mode
BA1 BA0 M11 M10 M9 M8 M7
Burst Type
M3
Mode
Type
Burst Read/
Burst Write
0
1
Sequential
Interleave
0
0
0
0
0
0
0
0
0
1
0
0
0
0
Burst Read/
Single Write
CAS Latency
M6 M5 M4
Burst Length
M2 M1 M0
Latency
Length
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Sequential
Interleave
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
1
2
4
8
2
3
Reserved
Reserved
Full Page
Reserved
SPD04125_FP
Address Inputs for Mode Register Set Operation
INFINEON Technologies
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10.01
HYB 39S128400/800/160DT(L)
128-MBit Synchronous DRAM
Power On and Initialization
The default power on state of the mode register is supplier specific and may be undefined. The
following power on and initialization sequence guarantees the device is preconditioned to each
users specific needs. Like a conventional DRAM, the Synchronous DRAM must be powered up and
initialized in a predefined manner. During power on, all VDD and VDDQ pins must be built up
simultaneously to the specified voltage when the input signals are held in the “NOP” state. The
power on voltage must not exceed VDD + 0.3 V on any of the input pins or VDD supplies. The CLK
signal must be started at the same time. After power on, an initial pause of 200 µs is required
followed by a precharge of all banks using the precharge command. To prevent data contention on
the DQ bus during power on, it is required that the DQM and CKE pins be held high during the initial
pause period. Once all banks have been precharged, the Mode Register Set Command must be
issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR) are also
required.These may be done before or after programming the Mode Register. Failure to follow these
steps may lead to unpredictable start-up modes.
Programming the Mode Register
The Mode register designates the operation mode at the read or write cycle. This register is divided
into 4 fields. A Burst Length Field to set the length of the burst, an Addressing Selection bit to
program the column access sequence in a burst cycle (interleaved or sequential), a CAS Latency
Field to set the access time at clock cycle and a Operation mode field to differentiate between
normal operation (Burst read and burst Write) and a special Burst Read and Single Write mode.
After the initial power up, the mode set operation must be done before any activate command . Any
content of the mode register can be altered by re-executing the mode set command. All banks must
be in precharged state and CKE must be high at least one clock before the mode set operation. After
the mode register is set, a Standby or NOP command is required. Low signals of RAS, CAS, and
WE at the positive edge of the clock activate the mode set operation. Address input data at this
timing defines parameters to be set as shown in the previous table.
Read and Write Operation
When RAS is low and both CAS and WE are high at the positive edge of the clock, a RAS cycle
starts. According to address data, a word line of the selected bank is activated and all of sense
amplifiers associated to the wordline are set. A CAS cycle is triggered by setting RAS high and CAS
low at a clock timing after a necessary delay, tRCD, from the RAS timing. WE is used to define either
a read (WE = H) or a write (WE = L) at this stage.
SDRAM provides a wide variety of fast access modes. In a single CAS cycle, serial data read or
write operations are allowed at up to a 143 MHz data rate. The numbers of serial data bits are the
burst length programmed at the mode set operation, i.e., one of 1, 2, 4, 8 and full page. Column
addresses are segmented by the burst length and serial data accesses are done within this
boundary. The first column address to be accessed is supplied at the CAS timing and the
subsequent addresses are generated automatically by the programmed burst length and its
sequence. For example, in a burst length of 8 with interleave sequence, if the first address is ‘2’,
then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5.
Full page burst operation is only possible using sequential burst type and page length is a function
of the I/O organisation and column addressing. Full page burst operation does not self terminate
INFINEON Technologies
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10.01
HYB 39S128400/800/160DT(L)
128-MBit Synchronous DRAM
once the burst length has been reached. In other words, unlike burst length of 2, 4, and 8, full page
burst continues until it is terminated using another command.
Similar to the page mode of conventional DRAM’s, burst read or write accesses on any column
address are possible once the RAS cycle latches the sense amplifiers. The maximum tRAS or the
refresh interval time limits the number of random column accesses. A new burst access can be
done even before the previous burst ends. The interrupt operation at every clock cycle is supported.
When the previous burst is interrupted, the remaining addresses are overridden by the new address
with the full burst length. An interrupt which accompanies an operation change from a read to a write
is possible by exploiting DQM to avoid bus contention.
When two or more banks are activated sequentially, interleaved bank read or write operations are
possible. With the programmed burst length, alternate access and precharge operations on two or
more banks can realize fast serial data access modes among many different pages. Once two or
more banks are activated, column to column interleave operation can be performed between
different pages.
Burst Length and Sequence
Burst
Length
Starting
Address
(A2 A1 A0)
Sequential Burst
Addressing
(decimal)
Interleave Burst
Addressing
(decimal)
2
4
xx0
xx1
0, 1
1, 0
0, 1
1, 0
x00
x01
x10
x11
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
8
000
001
010
011
100
101
110
111
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
0
2
3
4
5
6
7
0
1
3
4
5
6
7
0
1
2
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
1
0
3
2
5
4
7
6
2
3
0
1
6
7
4
5
3
2
1
0
7
6
5
4
4
5
6
7
0
1
2
3
5
4
7
6
1
0
3
2
6
7
4
5
2
3
0
1
7
6
5
4
3
2
1
0
Full Page
nnn
Cn, Cn+1, Cn+2 .....
not supported
Refresh Mode
SDRAM has two refresh modes, Auto Refresh and Self Refresh. Auto Refresh is similar to the CAS
-before-RAS refresh of conventional DRAMs. All of banks must be precharged before applying any
refresh mode. An on-chip address counter increments the word and the bank addresses and no
bank information is required for both refresh modes.
The chip enters the Auto Refresh mode, when RAS and CAS are held low and CKE and WE are
held high at a clock timing. The mode restores word line after the refresh and no external precharge
INFINEON Technologies
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10.01
HYB 39S128400/800/160DT(L)
128-MBit Synchronous DRAM
command is necessary. A minimum tRC time is required between two automatic refreshes in a burst
refresh mode. The same rule applies to any access command after the automatic refresh operation.
The chip has an on-chip timer and the Self Refresh mode is available. It enters the mode when RAS,
CAS, and CKE are low and WE is high at a clock timing. All of external control signals including the
clock are disabled. Returning CKE to high enables the clock and initiates the refresh exit operation.
After the exit command, at least one tRC delay is required prior to any access command.
DQM Function
DQM has two functions for data I/O read and write operations. During reads, when it turns to “high”
at a clock timing, data outputs are disabled and become high impedance after two clock delay (DQM
Data Disable Latency tDQZ). It also provides a data mask function for writes. When DQM is activated,
the write operation at the next clock is prohibited (DQM Write Mask Latency tDQW = zero clocks).
Suspend Mode
During normal access mode, CKE is held high enabling the clock. When CKE is low, it freezes the
internal clock and extends data read and write operations. One clock delay is required for mode
entry and exit (Clock Suspend Latency tCSL).
Power Down
In order to reduce standby power consumption, a power down mode is available. All banks must be
precharged and the necessary Precharge delay (tRP) must occur before the SDRAM can enter the
Power Down mode. Once the Power Down mode is initiated by holding CKE low, all of the receiver
circuits except CLK and CKE are gated off. The Power Down mode does not perform any refresh
operations, therefore the device can’t remain in Power Down mode longer than the Refresh period
(tREF) of the device. Exit from this mode is performed by taking CKE “high”. One clock delay is
required for power down mode entry and exit.
Auto Precharge
Two methods are available to precharge SDRAMs. In an automatic precharge mode, the CAS
timing accepts one extra address, CA10, to determine whether the chip restores or not after the
operation. If CA10 is high when a Read Command is issued, the Read with Auto-Precharge function
is initiated. If CA10 is high when a Write Command is issued, the Write with Auto-Precharge function
is initiated. The SDRAM automatically enters the precharge operation a time delay equal to tWR
(Write recovery time) after the last data in.
Precharge Command
There is also a separate precharge command available. When RAS and WE are low and CAS is
high at a clock timing, it triggers the precharge operation. Three address bits, BA0, BA1 and A10 are
used to define banks as shown in the following list. The precharge command can be imposed one
clock before the last data out for CAS latency = 2, two clocks before the last data out for CAS
latency = 3 and three clocks before the last data out for CAS latency = 4. Writes require a time delay
tWR from the last data out to apply the precharge command.
INFINEON Technologies
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10.01
HYB 39S128400/800/160DT(L)
128-MBit Synchronous DRAM
Bank Selection by Address Bits
A10
0
BA0 BA1
0
0
1
1
x
0
1
0
1
x
Bank 0
Bank 1
Bank 2
Bank 3
all Banks
0
0
0
1
Burst Termination
Once a burst read or write operation has been initiated, there are several methods in which to
terminate the burst operation prematurely. These methods include using another Read or Write
Command to interrupt an existing burst operation, use a Precharge Command to interrupt a burst
cycle and close the active bank, or using the Burst Stop Command to terminate the existing burst
operation but leave the bank open for future Read or Write Commands to the same page of the
active bank. When interrupting a burst with another Read or Write Command care must be taken to
avoid DQ contention. The Burst Stop Command, however, has the fewest restrictions making it the
easiest method to use when terminating a burst operation before it has been completed. If a Burst
Stop command is issued during a burst write operation, then any residual data from the burst write
cycle will be ignored. Data that is presented on the DQ pins before the Burst Stop Command is
registered will be written to the memory.
Capacitance
TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz
Parameter
Symbol
Values
min. max.
Unit
Input Capacitance (CLK)
CI1
CI2
2.5
2.5
3.5
3.8
pF
pF
Input Capacitance
(A0 - A11, BA0, BA1, RAS, CAS, WE, CS, CKE, DQM)
Input/Output Capacitance (DQ)
CIO
4.0
6.0
pF
INFINEON Technologies
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10.01
HYB 39S128400/800/160DT(L)
128-MBit Synchronous DRAM
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
max.
Unit
min.
Input / Output voltage relative to VSS
Power supply voltage
VIN, VOUT
VDD,VDDQ
TA
– 1.0
4.6
4.6
+70
+150
1
V
– 1.0
0
V
Operating Temperature
oC
oC
W
mA
Storage temperature range
TSTG
-55
–
Power dissipation per SDRAM component
Data out current (short circuit)
PD
IOS
–
50
Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded.
Functional operation should be restricted to recommended operation conditions.
Exposure to higher than recommended voltage for extended periods of time affect device reliability
Recommended Operation Conditions and DC Eletrical Characteristics
TA = 0 to 70 oC;
Parameter
Symbol
Limit Values
Unit Notes
min.
3.0
2.0
– 0.3
2.4
–
typ.
max.
Supply Voltage
Input high voltage
Input low voltage
VDD,VDDQ
VIH
3.3
3.6
V
V
1
3.0
0
VDDQ+0.3
1, 2
1, 2
1
VIL
0.8
–
V
Output high voltage (IOUT = – 4.0 mA) VOH
–
V
Output low voltage (IOUT = 4.0 mA)
VOL
IIL
–
0.4
5
V
1
Input leakage current, any input
– 5
–
mA
(0 V < VIN < VDD, all other inputs = 0 V)
Output leakage current
IOL
– 5
–
5
mA
(DQs are disabled, 0 V < VOUT < VDDQ
)
.
Notes:
1. All voltages are referenced to VSS
2. Vih may overshoot to VDDQ + 2.0 V for pulse width of < 4ns with 3.3V. Vil may undershoot to -2.0 V for pulse
width < 4.0 ns with 3.3V. Pulse width measured at 50% points with amplitude measured peak to DC
reference.
INFINEON Technologies
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10.01
HYB 39S128400/800/160DT(L)
128-MBit Synchronous DRAM
Operating Currents
TA = 0 to 70 °C, VDD = 3.3 V ± 0.3 V
(Recommended Operating Conditions unless otherwise noted)
Parameter & Test Condition
Symb. -6
-7/-7.5 -8
max.
Unit Note
Operating current
–
ICC1
t
CK = tCK(MIN.)
3
All banks operated in random
140
130
120
mA
access,
all banks operated in ping-pong
manner
3
Precharge standby current
in Power Down Mode
tCK = min
ICC2P
1
mA
CS = VIH (MIN.), CKE ≤ VIL(MAX.)
3
Precharge standby current
in Non Power Down Mode
CS = VIH (MIN.), CKE ≥ VIH(MIN.)
t
CK = min
ICC2N
45
40
40
35
30
mA
3
CKE ≥ VIH(MIN.)
CKE ≤ VIL(MAX.)
No operating current
ICC3N
ICC3P
35
8
mA
tCK = min., CS = VIH (MIN.),
3
mA
active state (max. 4 banks)
Burst Operating Current
–
ICC4
ICC5
ICC6
3, 4
tCK = min
100
140
90
80
mA
Read command cycling
3
Auto Refresh Current
–
130
120
mA
tCK = min, trc = trcmin.
Auto Refresh command cycling
Self Refresh Current
Self Refresh Mode
CKE = 0.2 V, tck=infinity
standard
version
1.0
0.5
mA
mA
L-version
Notes
3. These parameters depend on the cycle rate. These values are measured at 166 Mhz for -6, at 133 MHz for -
7 & -7.5 and at 100 MHz for -8 parts with the outputs open. Input signals are changed once during tCK
.
3. These parameters are measured with continuous data stream during read access and all DQ toggling. CL = 3
and BL = 4 is assumed and the VDDQ current is excluded.
INFINEON Technologies
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10.01
HYB 39S128400/800/160DT(L)
128-MBit Synchronous DRAM
1, 2
AC Characteristics
TA = 0 to 70 °C; VSS = 0 V; VDD,
V
DDQ = 3.3 V ± 0.3 V, tT = 1 ns
Note
Parameter
Symb.
Limit Values
-7 -7.5
min. max min. max min. max min. max
Unit
-6
-8
.
.
.
Clock and Clock Enable
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
–
6
7.5
–
–
7
7.5
–
–
7.5
10
–
–
8
10
–
–
ns
ns
tCK
Clock frequency
–
CAS Latency = 3 tCK
CAS Latency = 2
–
–
166
133
–
–
143
133
–
–
133
100
–
–
125 MHz
100 MHz
2, 3, 6
Access Time from Clock
CAS Latency = 3
CAS Latency = 2
–
–
5
5.4
–
–
5.4
5.4
–
–
5.4
6
–
–
6
6
ns
ns
tAC
Clock High Pulse Width
tCH
tCL
tT
2
2
–
–
2.5
2.5
–
–
2.5
2.5
–
–
3
3
–
–
ns
ns
ns
–
–
–
Clock Low Pulse Width
Transition Time
0.3 1.2 0.3 1.2 0.3 1.2 0.5 10
Setup and Hold Times
Input Setup Time
Input Hold Time
4
4
4
4
TBD
tIS
–
–
–
–
–
6
1.5
0.8
1.5
0.8
2
–
–
–
–
–
7
1.5
0.8
1.5
0.8
2
–
2
1
2
1
2
0
–
–
–
–
–
8
ns
tIH
TBD
TBD
TBD
TBD
0
–
ns
CKE Setup Time
CKE Hold Time
tCKS
tCKH
–
ns
–
ns
Mode Register Set-up Time tRSC
–
CLK
ns
–
–
Power Down Mode Entry
Time
tSB
0
0
7.5
Common Parameters
5
5
5
5
5
Row to Column Delay Time tRCD
15
15
36
60
60
–
–
–
–
–
15
15
37
63
63
–
20
20
45
67
67
–
–
20
20
–
–
ns
ns
Row Precharge Time
Row Active Time
Row Cycle Time
tRP
–
100k
tRAS
tRC
100k 48
100k ns
–
–
–
–
70
70
–
–
ns
ns
Row Cycle Time during Auto tRCF
Refresh
INFINEON Technologies
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10.01
HYB 39S128400/800/160DT(L)
128-MBit Synchronous DRAM
AC Characteristics (cont’d)1, 2
TA = 0 to 70 °C; VSS = 0 V; VDD,
V
DDQ = 3.3 V ± 0.3 V, tT = 1 ns
Symb. Limit Values
-7 -7.5
min. max min. max min. max min. max
Note
Parameter
Unit
-6
-8
.
.
.
5
Activate(a) to Activate(b)
Command Period
tRRD
12
1
–
–
14
1
–
15
1
–
16
1
–
ns
CAS(a) to CAS(b) Command tCCD
–
–
–
CLK
–
Period
Refresh Cycle
Refresh Period
(4096 cycles)
tREF
–
64
–
64
–
64
–
64
ms
–
Self Refresh Exit Time
tSREX
1
–
1
–
1
–
1
–
CLK
Read Cycle
2, 5, 6
Data Out Hold Time
tOH
TB
D
–
–
6
2
3
0
3
–
–
–
7
2
3
0
3
–
–
–
7
2
3
0
3
–
–
–
8
2
ns
Data Out to Low Impedance tLZ
Time
0
3
–
ns
–
–
–
Data Out to High Impedance tHZ
Time
ns
DQM Data Out Disable
Latency
tDQZ
CLK
Write Cycle
7
8
Write Recovery Time
tWRK
12
–
12
–
12
–
12
0
–
–
ns
Auto precharge write
recovery + precharge time
tDAL,min
(twr/tck) + (trp/tck)
CLK
DQM Write Mask Latency
tDQW
0
–
0
–
CLK
–
INFINEON Technologies
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10.01
HYB 39S128400/800/160DT(L)
128-MBit Synchronous DRAM
Notes
1. For proper power-up see the operation section of this data sheet.
2. AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover
point. The transition time is measured between VIH and VIL. All AC measurements assume
tT = 1 ns with the AC output load circuit shown in figure below. Specified tAC and tOH parameters
are measured with a 50 pF only, without any resistive termination and with a input signal of 1V /
ns edge rate between 0.8 V and 2.0 V.
tCH
2.4 V
0.4 V
1.4 V
CLOCK
tT
tCL
tIH
tIS
INPUT
1.4 V
tAC
tAC
tLZ
tOH
OUTPUT
1.4 V
I/O
50 pF
tHZ
Measurement conditions for
AC and tOH
IO.vsd
t
3. If clock rising time is longer than 1 ns, a time (tT/2 − 0.5) ns has to be added to this parameter.
4. If tT is longer than 1 ns, a time (tT − 1) ns has to be added to this parameter.
5. These parameter account for the number of clock cycles and depend on the operating frequency
of the clock, as follows:
the number of clock cycles = specified value of timing period (counted in fractions as a whole
number)
6. Access time from clock tac is 4.6 ns for PC133 components with no termination and 0 pF load,
Data out hold time toh is 1.8 ns for PC133 components with no termination and 0 pF load.
7. The write recovery time twr = 12 ns allows to use one clock cycle between the last data-in and
the precharge command for frequencies equal or lower than 83 MHz. For operation frequencies
higher than 83 MHz two clock cycles are neccessary between the last data-in and the precharge
command.
8. When a Write command with Auto Precharge has been issued a time of tdal(min) has be fullfilled
before the next Activate command can be applied. For each of the terms, if not allready an
integer, round up to the next highest integer. tck is equal to the actual system clock time.
INFINEON Technologies
19
10.01
HYB 39S128400/800/160DT(L)
128-MBit Synchronous DRAM
Package Outlines
Plastic Package, P-TSOPII-54
400 mil, 0.8 mm lead pitch
(
)
Thin Small Outline Package, SMD
15˚±5˚
15˚±5˚
2)
10.16±0.13
0.8
0.5±0.1
11.76±0.2
0.1 54x
26x 0.8 = 20.8
3)
+0.1
M
0.2
54x
0.35
-0.05
54
28
27
1
2.5 max
1)
22.22±0.13
GPX09039
Index Marking
1) Does not include plastic or metal protrusion of 0.15 max per side
2) Does not include plastic protrusion of 0.25 max per side
3) Does not include dambar protrusion of 0.13 max per side
INFINEON Technologies
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10.01
HYB39S128400/800/160DT(L)
128-MBit Synchronous DRAM
Timing Diagrams
1. Bank Activate Command Cycle
2. Burst Read Operation
3. Read Interrupted by a Read
4. Read to Write Interval
4.1 Read to Write Interval
4.2 Minimum Read to Write Interval
4.3 Non-Minimum Read to Write Interval
5. Burst Write Operation
6. Write and Read Interrupt
6.1 Write Interrupted by a Write
6.2 Write Interrupted by Read
7. Burst Write & Read with Auto-Precharge
7.1 Burst Write with Auto-Precharge
7.2 Burst Read with Auto-Precharge
8. AC- Parameters
8.1 AC Parameters for a Write Timing
8.2 AC Parameters for a Read Timing
9. Mode Register Set
10. Power on Sequence and Auto Refresh (CBR)
11. Clock Suspension (using CKE)
11. 1 Clock Suspension During Burst Read CAS Latency = 2
11. 2 Clock Suspension During Burst Read CAS Latency = 3
11. 3 Clock Suspension During Burst Write CAS Latency = 2
11. 4 Clock Suspension During Burst Write CAS Latency = 3
12. Power Down Mode and Clock Suspend
13. Self Refresh ( Entry and Exit )
14. Auto Refresh ( CBR )
15. Random Column Read ( Page within same Bank)
15.1 CAS Latency = 2
15.2 CAS Latency = 3
16. Random Column Write ( Page within same Bank)
16.1 CAS Latency = 2
16.2 CAS Latency = 3
17. Random Row Read ( Interleaving Banks) with Precharge
17.1 CAS Latency = 2
17.2 CAS Latency = 3
18. Random Row Write ( Interleaving Banks) with Precharge
18.1 CAS Latency = 2
18.2 CAS Latency = 3
19. Precharge Termination of a Burst
20. Full Page Burst Operation
20.1 Full Page Burst Read, CAS Latency = 2
18.2 Full Page Burst Write, CAS Latency = 3
INFINEON Technologies
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HYB39S128400/800/160DT(L)
128-MBit Synchronous DRAM
1. Bank Activate Command Cycle
(CAS latency = 3)
T0
T1
T
T
T
T
T
CLK
Bank B
Row Addr.
Bank B
Col. Addr.
Bank A
Row Addr.
Bank B
Row Addr.
Address
tRCD
NOP
tRRD
Write B
with Auto
Precharge
Bank B
Activate
Bank A
Activate
Bank B
Activate
Command
NOP
NOP
tRC
"H" or "L"
SPT03784
2. Burst Read Operation
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Command
Read A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CAS
latency = 2
tCK2, DQ’s
DOUT A0 DOUT A1 DOUT A2 DOUT A3
CAS
latency = 3
tCK3, DQ’s
DOUT A0 DOUT A1 DOUT A2 DOUT A3
SPT03712
INFINEON Technologies
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HYB39S128400/800/160DT(L)
128-MBit Synchronous DRAM
3. Read Interrupted by a Read
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Command
Read A
Read B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CAS
latency = 2
DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3
t
CK2, DQ’s
CAS
latency = 3
tCK3, DQ’s
DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3
SPT03713
4. Read to Write Interval
4.1 Read to Write Interval
(Burst Length = 4, CAS latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Minimum delay between the Read and Write
Commands = 4 + 1 = 5 cycles
Write latency tDQW of DQMx
DQMx
tDQZ
Command
DQ’s
NOP
Read A
NOP
NOP
NOP
NOP
Write B
DIN B0
NOP
NOP
DOUT A0
DIN B1
DIN B2
Must be Hi-Z before
the Write Command
"H" or "L"
SPT03787
INFINEON Technologies
23
HYB39S128400/800/160DT(L)
128-MBit Synchronous DRAM
4 2. Minimum Read to Write Interval
(Burst Length = 4, CAS latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
tDQW
DQM
tDQZ
1 Clk Interval
Bank A
Activate
Command
NOP
NOP
NOP
Read A
Write A
NOP
NOP
NOP
Must be Hi-Z before
the Write Command
CAS
latency = 2
tCK2, DQ’s
DIN A0
DIN A1
DIN A2
DIN A3
"H" or "L"
SPT03939
4. 3. Non-Minimum Read to Write Interval
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
tDQW
DQM
tDQZ
Command
NOP
Read A
NOP
NOP
Read A
NOP
Write B
NOP
NOP
Must be Hi-Z before
the Write Command
CAS
latency = 2
tCK2, DQ’s
DOUT A0 DOUT A1
DOUT A0
DIN B0
DIN B0
DIN B1
DIN B1
DIN B2
DIN B2
CAS
latency = 3
tCK3, DQ’s
"H" or "L"
SPT03940
INFINEON Technologies
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HYB39S128400/800/160DT(L)
128-MBit Synchronous DRAM
5. Burst Write Operation
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Command
DQ’s
NOP
Write A
DIN A0
NOP
NOP
NOP
NOP
NOP
NOP
NOP
don’t care
DIN A1
DIN A2
DIN A3
The first data element and the Write
are registered on the same clock edge.
Extra data is ignored after
termination of a Burst.
SPT03790
INFINEON Technologies
25
HYB39S128400/800/160DT(L)
128-MBit Synchronous DRAM
6. Write and Read Interrupt
6.1 Write Interrupted by a Write
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Write A
Command
DQ’s
NOP
Write B
NOP
NOP
NOP
NOP
NOP
NOP
1 Clk Interval
DIN A0
DIN B0
DIN B1
DIN B2
DIN B3
SPT03791
6.2 Write Interrupted by a Read
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Command
NOP
Write A
DIN A0
DIN A0
Read B
don’t care
don’t care
NOP
NOP
NOP
NOP
NOP
NOP
CAS
latency = 2
DOUT B0 DOUT B1 DOUT B2 DOUT B3
t
CK2, DQ’s
CAS
latency = 3
tCK3, DQ’s
don’t care
DOUT B0 DOUT B1 DOUT B2 DOUT B3
Input data must be removed from the DQ’s
at least one clock cycle before the Read data
appears on the outputs to avoid data contention.
Input data for the Write is ignored.
SPT03719
INFINEON Technologies
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HYB39S128400/800/160DT(L)
128-MBit Synchronous DRAM
7. Burst Write and Read with Auto Precharge
7.1 Burst Write with Auto-Precharge
(Burst Length = 2, CAS latency = 2, 3 )
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
CAS Latency = 2:
Command
Bank A
Active
Write A
Activate
NOP
NOP
tWR
NOP
NOP
tRP
NOP
NOP
Auto Precharge
*
DIN A0
NOP
DIN A1
DQ’s
CAS Latency = 3:
Command
Bank A
Active
Write A
Auto Precharge
Activate
NOP
NOP
NOP
NOP
NOP
NOP
tWR
tRP
*
DIN A0 DIN A1
DQ’s
Begin Auto Precharge
*
Bank can be reactivated after trp
7.2 Burst Read with Auto-Precharge
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Read A
with AP
Command
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tRP
*
CAS
latency = 2
DOUT A0 DOUT A1
DOUT A0
DOUT A2
DOUT A3
DQ’s
tRP
*
CAS
latency = 3
DOUT A1
DOUT A2
DOUT A3
DQ’s
Begin Auto Precharge
*
SPT03721_2
Bank can be reactivated after trp
INFINEON Technologies
27
HYB39S128400/800/160DT(L)
128-MBit Synchronous DRAM
8. AC Parameters
8.1 AC Parameters for a Write Timing
Burst Length = 4, CAS Latency = 2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CH
t
CK2
t
CL
t
Begin Auto
Precharge
Bank B
CKH
t
Begin Auto
Precharge
Bank A
CKS
t
t
CS
CH
CS
RAS
CAS
WE
BS
t
AH
RBy
RBy
RAz
RAz
RBx
RBx
RAy
RAy
RAx
RAx
AP
t
AS
RAy
CAx
CBx
WR
Addr.
DQM
t
DS
t
t
RP
t
t
WR
RCD
t
t
DH
t
RRD
RP
t
RC
Hi-Z
Ay0 Ay1 Ay2 Ay3
Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3
DQ
Activate
Command
Bank A
Activate
Command
Bank A
Write
Command
Bank A
Activate
Command
Bank B
Precharge Activate
Command Command Command
Activate
Bank A
Bank A
Bank B
Write with
Write with
Auto Precharge
Command
Bank B
Auto Precharge
Command
Bank A
SPT03910_2
INFINEON Technologies
28
HYB39S128400/800/160DT(L)
128-MBit Synchronous DRAM
8.2 AC Parameters for a Read Timing
Burst Length = 2, CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
CLK
CKE
tCH
tCK2
tCL
tCKH
tCS
Begin Auto
Precharge
Bank B
tCKS
tCH
CS
RAS
CAS
WE
BS
tAH
AP
RAx
RBx
RBx
RAy
RAy
tAS
Addr.
RAx
CAx
tRRD
RBx
tRAS
tRC
DQM
DQ
tAC2
tLZ
tHZ
tRP
tAC2
tOH
Ax0
tRCD
tHZ
Bx1
Hi-Z
Ax1
Bx0
Activate
Command
Bank A
Activate
Command
Bank B
Read with
Precharge
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A
Auto Precharge
Command
Bank B
SPT03911_2
INFINEON Technologies
29
HYB39S128400/800/160DT(L)
128-MBit Synchronous DRAM
9. Mode Register Set
CAS Latency = 2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
RSC
CS
RAS
CAS
WE
BS
AP
Address Key
Addr.
Precharge
Command
All Banks
Any
Command
Mode Register
Set Command
SPT03912_2
INFINEON Technologies
30
HYB39S128400/800/160DT(L)
128-MBit Synchronous DRAM
10. Power on Sequence and Auto Refresh (CBR)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High Level
is required
2 Clock min.
Minimum of 8 Refresh Cycles are required
CS
RAS
CAS
WE
BS
AP
Address Key
Addr.
DQM
t RP
t RC
Hi-Z
DQ
Precharge
Command
All Banks
8th Auto Refresh
Command
Mode Register
Set Command
Any
Command
Inputs must be
stable for 200
1st Auto Refresh
Command
µ
s
SPT03913
INFINEON Technologies
31
HYB39S128400/800/160DT(L)
128-MBit Synchronous DRAM
11. Clock Suspension ( Using CKE)
11.1 Clock Suspension During Burst Read CAS Latency = 2
Burst Length = 4, CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK2
CKE
CS
RAS
CAS
WE
BS
AP
RAx
Addr.
DQM
RAx
CAx
tCSL
tHZ
tCSL
tCSL
Hi-Z
DQ
Ax0
Ax1
Ax2
Ax3
Activate
Command Command
Bank A Bank A
Read
Clock
Suspend
1 Cycle
Clock
Suspend
2 Cycles
Clock
Suspend
3 Cycles
SPT03914
INFINEON Technologies
32
HYB39S128400/800/160DT(L)
128-MBit Synchronous DRAM
11.2 Clock Suspension During Burst Read CAS Latency = 3
Burst Length = 4, CAS Latency = 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK3
CKE
CS
RAS
CAS
WE
BS
AP
RAx
Addr.
DQM
RAx
CAx
tCSL
tCSL
tCSL
tHZ
Hi-Z
DQ
Ax0
Ax1
Ax2
Ax3
Activate
Command
Bank A
Read
Command
Bank A
Clock
Suspend
1 Cycle
Clock
Suspend
2 Cycles
Clock
Suspend
3 Cycles
SPT03915
INFINEON Technologies
33
HYB39S128400/800/160DT(L)
128-MBit Synchronous DRAM
11.3 Clock Suspension During Burst Write CAS Latency = 2
Burst Length = 4, CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK2
CKE
CS
RAS
CAS
WE
BS
AP
RAx
Addr.
DQM
DQ
RAx
CAx
Hi-Z
DAx0
DAx1
DAx2
DAx3
Activate
Command
Bank A
Clock
Suspend
1 Cycle
Clock
Suspend
2 Cycles
Clock
Suspend
3 Cycles
Write
Command
Bank A
SPT03916
INFINEON Technologies
34
HYB39S128400/800/160DT(L)
128-MBit Synchronous DRAM
11.4 Clock Suspension During Burst Write CAS Latency = 3
Burst Length = 4, CAS Latency = 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK3
CKE
CS
RAS
CAS
WE
BA
A8/AP
Addr.
DQMx
DQ
RAx
RAx
CAx
Hi-Z
DAx0
DAx1
DAx2
DAx3
Activate
Command
Bank A
Clock
Suspend
1 Cycle
Clock
Suspend
2 Cycles
Clock
Suspend
3 Cycles
Write
Command
Bank A
SPT03917
INFINEON Technologies
35
HYB39S128400/800/160DT(L)
128-MBit Synchronous DRAM
12. Power Down Mode and Clock Suspend
Burst Length = 4, CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CKS
t CKS
t CK2
CKE
CS
RAS
CAS
WE
BS
AP
RAx
Addr.
DQM
RAx
CAx
tHZ
Hi-Z
DQ
Ax0 Ax1
Ax2
Ax3
Activate
Command
Bank A
Active
Standby
Read
Command
Bank A
Clock Mask
Start
Clock Mask
End
Precharge
Command
Bank A
Precharge
Standby
Any
Command
Clock Suspend
Mode Entry
Clock Suspend
Mode Exit
Power Down
Mode Entry
Power Down
Mode Exit
SPT03918
INFINEON Technologies
36
HYB39S128400/800/160DT(L)
128-MBit Synchronous DRAM
13. Self Refresh (Entry and Exit)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
t
CKS
CKS
CS
RAS
CAS
WE
BS
AP
Addr.
t
SREX
RC*)
t
DQM
DQ
Hi-Z
All Banks
must be idle
Self Refresh
Entry
Begin Self Refresh
Exit Command
Any
Command
Self Refresh Exit
Command issued
Self Refresh
Exit
*) minimum RAS cycle
time depends on CAS
Latency and trc
SPT03919-2
INFINEON Technologies
37
HYB39S128400/800/160DT(L)
128-MBit Synchronous DRAM
14. Auto Refresh (CBR)
Burst Length = 4, CAS Latency = 2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
CKE
CS
RAS
CAS
WE
BS
RAx
AP
RAx
CAx
Addr.
t
t
RC
RC
t
(Minimum Interval)
RP
DQM
DQ
Hi-Z
Ax0 Ax1 Ax2 Ax3
Auto Refresh
Command
Precharge Auto Refresh
Command Command
All Banks
Activate
Command Command
Bank A Bank A
Read
SPT03920_2
INFINEON Technologies
38
HYB39S128400/800/160DT(L)
128-MBit Synchronous DRAM
15. Random Column Read (Page within same Bank)
15.1 CAS Latency = 2
Burst Length = 4, CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK2
CKE
CS
RAS
CAS
WE
BS
AP
RAw
RAz
Addr.
DQM
DQ
RAw
CAw
CAx
CAy
RAz
CAz
Hi Z
Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3
Az0 Az1 Az2 Az3
Activate
Command
Bank A
Read
Command
Bank A
Read
Command
Bank A
Read
Command
Bank A
Precharge
Command Command Command
Bank A Bank A Bank A
Activate
Read
SPT03921
INFINEON Technologies
39
HYB39S128400/800/160DT(L)
128-MBit Synchronous DRAM
15.2 CAS Latency = 3
Burst Length = 4, CAS Latency = 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK3
CKE
CS
RAS
CAS
WE
BS
AP
RAw
RAz
Addr.
DQM
RAw
CAw
CAx
CAy
RAz
CAz
Hi Z
DQ
Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3
Activate
Command
Bank A
Read
Command
Bank A
Read
Read
Precharge
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A SPT03922
Command Command
Bank A
Bank A
INFINEON Technologies
40
HYB39S128400/800/160DT(L)
128-MBit Synchronous DRAM
16. Random Column write (Page within same Bank)
16.1 CAS Latency = 2
Burst Length = 4, CAS Latency = 2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
CKE
CS
RAS
CAS
WE
BS
RBw
RBw
RBz
RBz
AP
CBy
CBw
CBx
CBz
Addr.
DQM
DQ
Hi Z
DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3
DBz0 DBz1 DBz2 DBz3
Activate
Command Command
Bank B Bank B
Write
Write
Command Command
Bank B Bank B
Write
Precharge Activate
Command Command Command
Bank B Bank B Bank B
Read
SPT03923_2
INFINEON Technologies
41
HYB39S128400/800/160DT(L)
128-MBit Synchronous DRAM
16.2. CAS Latency = 3
Burst Length = 4, CAS Latency = 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK3
CKE
CS
RAS
CAS
WE
BS
AP
RBz
RBz
Addr.
DQM
DQ
RBz
CBz
CBx
CBy
RBz
CBz
Hi Z
DBw0 DBw1 DBw2 DBw3 DBx0
DBx1 DBy0
Write
DBy1 DBy2 DBy3
DBz0
DBz1
Activate
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Precharge
Command
Bank B
Activate
Command
Bank B
Write
Command
Bank BSPT03924
Command
Bank B
INFINEON Technologies
42
HYB39S128400/800/160DT(L)
128-MBit Synchronous DRAM
17. Random Row Read (Interleaving Banks) with Precharge
17.1 CAS Latency = 2
Burst Length = 8, CAS Latency = 2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
High
CKE
CS
RAS
CAS
WE
BS
RBx
RBx
RAx
RAx
RBy
RBy
AP
CBx
CAx
CBy
Addr.
t
t
RP
RCD
DQM
DQ
t
AC2
Hi-Z
Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Ax3 Ax4 Ax5 Ax6 Ax7
By0 By1
Activate
Command Command
Bank B Bank B
Read
Activate
Command
Bank A
Precharge Activate
CommandCommand
Read
Command
Bank B
Bank B
Bank B
Read
Command
Bank A
SPT03925_2
INFINEON Technologies
43
HYB39S128400/800/160DT(L)
128-MBit Synchronous DRAM
17.2 CAS Latency = 3
Burst Length = 8, CAS Latency = 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK3
CKE
CS
High
RAS
CAS
WE
BS
AP
RBx
RBx
RAx
RAx
RBy
Addr.
CBx
CAx
RBy
CBy
tAC3
tRCD
t RP
DQM
DQ
Hi-Z
Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Ax3 Ax4 Ax5 Ax6 Ax7 By0
Activate
Command
Bank B
Read
Command
Bank B
Activate
Command
Bank A
Read
Command Command
Bank A Bank B
Precharge
Activate
Command
Bank B
Read
Command
Bank B
Precharge
Command
Bank A
SPT03926
INFINEON Technologies
44
HYB39S128400/800/160DT(L)
128-MBit Synchronous DRAM
18. Random Row Write (Interleaving Banks) with Precharge
18.1 CAS Latency = 2
Burst Length = 8, CAS Latency = 2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
High
CKE
CS
RAS
CAS
WE
BS
RAx
RBx
RBx
RAy
RAy
AP
RAx
CAx
CBx
WR
CAy
Addr.
t
t
WR
t
t
RP
RCD
DQM
DQ
Hi-Z
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3 DAy4
Activate
Command Command
Bank A Bank A
Write
Activate
Command Command
Bank B Bank B
Write
Activate
Command
Bank A
Precharge
Command
Bank B
Precharge
Write
Command
Bank A
Command
Bank A
SPT03927_2
INFINEON Technologies
45
HYB39S128400/800/160DT(L)
128-MBit Synchronous DRAM
18.2 CAS Latency = 3
Burst Length = 8, CAS Latency = 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK3
CKE
CS
High
RAS
CAS
WE
BS
AP
RAx
RAx
RBx
RBx
RAy
Addr.
CAx
CBx
RAy
CAy
tRCD
tWR
t RP
tWR
DQM
DQ
Hi-Z
DAx0
DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0
DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0
DAy1 DAy2 DAy3
Activate
Command
Bank A
Write
Command
Bank A
Activate
Command
Bank B
Write
Command
Bank B
Precharge
Command
Bank A
Activate
Command
Bank A
Write
Command
Bank A
Precharge
Command
Bank B
SPT03928
INFINEON Technologies
46
HYB39S128400/800/160DT(L)
128-MBit Synchronous DRAM
19. Precharge termination of a Burst
19.1 CAS Latency = 2
Burst Length = 8 or Full Page, CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK2
CKE
CS
High
RAS
CAS
WE
BS
AP
RAx
RAx
RAy
RAy
RAz
Addr.
CAx
CAy
RAz
CAz
t RP
t RP
t RP
DQM
DQ
Hi Z
DAx0
DAx1 DAx2 DAx3
Ay0 Ay1 Ay2
Az0 Az1 Az2
Activate
Command
Bank A
Write
Command
Bank A
Precharge
Command
Bank A
Read
Command
Bank A
Precharge
Command
Bank A
Read
Command
Bank A
Precharge
Command
Bank A
Precharge Termination
of a Write Burst.
Write Data is masked.
Activate
Command
Bank A
Activate
Command
Bank A
Precharge Termination
of a Read Burst.
SPT03933
INFINEON Technologies
47
HYB39S128400/800/160DT(L)
128-MBit Synchronous DRAM
20. Full Page Burst Operation
20.1 Full Page Burst Read, CAS Latency = 2
Burst Length = Full Page, CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK2
High
CKE
CS
RAS
CAS
WE
BS
AP
RAx
RAx
RBx
RBx
RBy
Addr.
CAx
CBx
RBy
t RP
DQM
DQ
Hi-Z
Ax
Ax +1 Ax + 2 Ax -2
Ax -1
Ax
Ax +1
Bx
Bx +1 Bx +2 Bx +3 Bx+4 Bx+5 Bx +6
Activate
Command Command Command
Bank A Bank A Bank B
Read
Activate
Read
Command
Bank B
Burst Stop Precharge
Command Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval.
Full Page burst operation does not
Activate
Command
Bank B
terminate when the burst length is satisfied;
the burst counter increments and continues
bursting beginning with the starting address.
SPT03929
INFINEON Technologies
48
HYB39S128400/800/160DT(L)
128-MBit Synchronous DRAM
20. Full Page Burst Operation
20.2 Full Page Burst Write, CAS Latency = 3
Burst Length = Full Page, CAS Latency = 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK3
High
CKE
CS
RAS
CAS
WE
BS
AP
RAx
RAx
RBx
RBx
RBy
Addr.
CAx
CBx
RBy
tRRD
DQM
DQ
Hi-Z
Ax
Ax +1 Ax +2 Ax -2
Ax -1
Ax
Ax +1
Bx
Bx +1 Bx+2 Bx+3 Bx+4 Bx+5
Activate
Command
Bank A
Activate
Command
Bank B
Read
Command
Bank B
Burst Stop Precharge
Command Command
Bank B
Activate
Command
Bank B
Read
Command
Bank A
The burst counter wraps
from the highest order
page address back to zero
during this time interval.
Full Page burst operation does not
terminate when the burst length is satisfied;
the burst counter increments and continues
bursting beginning with the starting address.
SPT03930
INFINEON Technologies
49
HYB39S128400/800/160DT(L)
128-MBit Synchronous DRAM
TABLE OF CONTENTS
128-MBit Synchronous DRAM
Ordering Information
page 1
page 2
Pin Definitions and Functions
Pin Configuration for x4, x8 & x16 Organized 128M-DRAMs
Functional Block Diagrams
Block Diagram: 32M x4 SDRAM (12 / 11 / 2 addressing
Block Diagram: 16M x8 SDRAM (12 / 10 / 2 addressing)
Block Diagram: 8M x16 SDRAM (12 / 9 / 2 addressing)
Signal Pin Description
page 2
page 3
page 4
page 4
page 5
page 6
page 7
Operation Definition
page 9
Address Inputs for Mode Register Set Operation
Power On and Initialization
Programming the Mode Register
Read and Write Operation
Refresh Mode
page 10
page 11
page 11
page 11
page 12
page 13
page 13
page 13
page 13
page 13
page 14
page 14
page 15
page 15
page 15
page 15
page 16
page 17
page 20
page 21
page 22
Burst Length and Sequence
DQM Function
Power Down
Auto Precharge
Precharge Command
Burst Termination.
Bank Selection by Address Bits
Electrical Characteristics
Absolute Maximum Ratings
Recommended Operation and DC Characteristics
Capacitance
Operating Currents
AC Characteristics
Package Outlines
Table of Content
Timing DIagrams
INFINEON Technologies
50
HYB39S128400/800/160DT(L)
128-MBit Synchronous DRAM
Attention please !
As far as patents or other rights of third parties are concerned, liability is only
assumed for components, not for applications, processes and circuits
implemented within components or assemblies. This infomation describes
the type of components and shall not be considered as assured
characteristics. Terms of delivery and rights to change design reserved.
For questions on technology, delivery and prices please contact INFINEON
Technologies Offices in Munich or the INFINEON Technologies Sales Offices
and Representatives worldwide.
Due to technical requirements components may contain dangerous
substances. For information on the types in question please contact your
nearest INFINEON Technologies office or representative.
Packing
Please use the recycling operators known to you. We can help you - get in
touch with your nearest sales office. By agreement we will take packing
material back, if it is sorted. You must bear the costs of transport. For packing
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we shall have to invoice you for any costs incurred.
Components used in life-support devices or systems must be expressly
authorized for such purpose!
1
Ciritcal components of INFINEON Technologies, may only be used in life-
2
support devices or systems with the express written approval of INFINEON
Technologies.
1. A critical component is a component used in a life-support device or system
whose failure can reasonably be expected to cause the failure of that life-
support device or system, or to affect the safety or effectiveness of that device
or system.
2. Life support devices or systems are intended (a) to be implanted in the
human body, or (b) to support and/or maintain and sustain human life. If they
fail, it is reasonable to assume that the health of the user may be endangered.
INFINEON Technologies
51
HYB39S128400/800/160DT(L)
128-MBit Synchronous DRAM
INFINEON Technologies
52
相关型号：
HYB39S128800DT-7.5
Synchronous DRAM, 16MX8, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-54
INFINEON
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