C517_技术文档

0LFURFRPSXWHUꢀ&RPSRQHQWV

ꢅꢆ%LWꢀ&026ꢀ0LFURFRQWUROOHU

&ꢇꢂꢈ$

'DWDꢀ6KHHWꢀꢁꢂꢃꢄꢄ

'DWDꢀ6KHHW

ꢁꢂꢃꢄꢄ

C517A Data Sheet

Revision History :

01.99

Previous Releases :

08.97 (Original Version)

Subjects (changes since last revision)

Page

(previous

version)

(new

version)

All sections All sections V_CCis changed to V_DDand I_CCis changed to I_DD.

2

"with wake-up capability through INT0 pin" is removed.

P-LCC-84 package is added under the feature list.

Table 1; deleted and replaced by “Ordering Information” paragraph

“Additional Literature”;deleted.

2 to 3

5

Figure 4; added.

5

6

Table 1; modified, column “P-LCC-84” is added.

"or by a short low pulse at pin P3.2/INT0" is removed.

"Short low pulse at pin P3.2/INT0" is removed.

“Absolute Maximum Ratings” is changed to tabular form.

Fifth line; “During overload conditions ...” changed to “During absolute

maximum rating conditons ...”.

47

48

49

50

52

49

50

51

53

55

62

-

52

53

54

56

58

65

69

“Operating Conditions” is added.

“V_CC= 5 V + 10% ... “ is replaced by “(Operating Conditions apply)”.

Notes (7); modified.

“V_CC= 5 V + 10% ... “ is replaced by “(Operating Conditions apply)”.

First line; “C517A-1RM” is replaced by “C517A-4RM/4RN”

Figure 38; added.

Edition 01.99

This edition was realized using the software system FrameMaker .

Published by : Siemens AG, Semiconductor Group, Product Definition 8-Bit Microcontroller Components,

Balanstraße 73, D-81541 München .

©

“Enhanced Hooks Technology“ is a trademark and patent of Metalink Corporation, licensed to Siemens.

As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for

applications, processes and circuits implemented within components or assemblies.

The information describes the type of component and shall not be considered as assured characteristics.

Terms of delivery and rights to change design reserved.

For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or

the Siemens Companies and Representatives worldwide.

Due to technical requirements components may contain dangerous substances. For information on the type in

question please contact your nearest Siemens Office, Components Group.

Siemens AG is an approved CECC manufacturer.

Packing

Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales

office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport.

For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have ti invoice

you for any costs incurred.

C517A

8-Bit CMOS Microcontroller

Advance Information

• Full upward compatibility with SAB 80C517A/83C517A-5

• Up to 24 MHz external operating frequency

– 500 ns instruction cycle at 24 MHz operation

• Superset of the 8051 architecture with 8 datapointers

• On-chip emulation support logic (Enhanced Hooks Technology ^TM

• 32K byte on-chip ROM (with optional ROM protection)

– alternatively up to 64K byte external program memory

• Up to 64K byte external data memory

)

• 256 byte on-chip RAM

• Additional 2K byte on-chip RAM (XRAM)

• Seven 8-bit parallel I/O ports

• Two input ports for analog/digital input

(further features are on next page)

Oscillator

Watchdog

Timer

XRAM

2K x 8

RAM

256 x 8

Port 0

Port 1

Port 2

Port 3

I/O

T0

T1

Compare

Timer

CPU

(8 Datapointer)

CCU

T2

MDU

Power

Saving

Modes

10-Bit

A/D Converter

ROM

32k x 8

8 Bit

USART

8 Bit

UART

Port 8 Port 7 Port 6 Port 5 Port 4

Analog/ Analog/

Digital Digital

I/O

Input

MCA03317

Figure 1

C517A Functional Units

Semiconductor Group

1

C517A

Features (continued) :

• Two full duplex serial interfaces (USART)

– 4 operating modes, fixed or variabie baud rates

– programmable baud rate generators

• Four 16-bit timer/counters

– Timer 0 / 1 (C501 compatible)

– Timer 2 for 16-bit reload, compare, or capture functions

– Compare timer for compare/capture functions

• Powerful 16-bit compare/capture unt (CCU) with up to 21 high-speed or PWM output channels

and 5 capture inputs

• 10-bit A/D converter

– 12 multiplexed analog inputs

– Built-in self calibration

• Extended watchdog facilities

– 15-bit programmable watchdog timer

– Oscillator watchdog

• Power saving modes

– Slow down mode

– Idle mode (can be combined with slow down mode)

– Software power-down mode

– Hardware power-down mode

• 17 interrupt sources (7 external, 10 internal) selectable at 4 priority levels

• P-MQFP-100 and P-LCC-84 packages

• Temperature Ranges : SAB-C517A

SAF-C517A

T_A= 0 to 70 °C

T_A= -40 to 85 °C

T_A= -40 to 110 °C

SAH-C517A

Ordering Information

The ordering code for Siemens microcontrollers provides an exact reference to the required

product. This ordering code identifies:

• the derivative itself, i.e. its function set

• the specified temperature range

• the package and the type of delivery.

For the available ordering codes for the C517A please refer to the

„Product Information Microcontrollers“, which summarizes all available microcontroller variants.

Note: The ordering codes for the Mask-ROM versions are defined for each product after

verification of the respective ROM code.

Semiconductor Group

2

C517A

VV_C_D_C_DV_SS

Port 7

8-bit Analog/

Digital Input

Port 0

8-Bit Digital I/O

Port 8

4-bit Analog/

Digital Input

Port 1

8-Bit Digital I/O

XTAL1

XTAL2

ALE

Port 2

8-Bit Digital I/O

PSEN

EA

Port 3

8-Bit Digital I/O

C517A

RESET

PE/SWD

OWE

Port 4

8-Bit Digital I/O

Port 5

8-Bit Digital I/O

RO

HWPD

Port 6

8-Bit Digital I/O

V_AREF

V_AGND

MCL03318

Figure 2

Logic Symbol

Semiconductor Group

3

C517A

1

CC4/INT2/P1.4

N.C.

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

P7.7/AIN7

2

V_AGND

3

N.C.

V_AREF

4

N.C.

5

N.C.

6

CC3/INT6/P1.3

CC2/INT5/P1.2

CC1/INT4/P1.1

CC0/INT3/P1.0

V_SS

N.C.

7

N.C.

8

RESET

P4.7/CM7

P4.6/CM6

P4.5/CM5

P4.4/CM4

P4.3/CM3

PE/SWD

P4.2/CM2

P4.1/CM1

P4.0/CM0

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

V_DD

V_CC

XTAL2

XTAL1

P2.0/A8

P2.1/A9

P2.2/A10

P2.3/A11

P2.4/A12

P2.5/A13

P2.6/A14

P2.7/A15

PSEN

C517A

V

DD

CC

V_SS

RO

P8.3/AIN11

P8.2/AIN10

P8.1/AIN9

P8.0/AIN8

P6.7

ALE

EA

N.C.

P0.0/AD0

P0.1/AD1

N.C.

P6.6

P6.5

N.C.

P0.2/AD2

N.C.

MCP03319

Figure 3

Pin Configuration P-MQFP-100 Package (Top View)

ꢀ

Semiconductor Group

4

C517A

V_AGND

P7.7/AIN7

P7.6/AIN6

P7.5/AIN5

P7.4/AIN4

P7.3/AIN3

P7.2/AIN2

P7.1/AIN1

P7.0/AIN0

P3.0/RxD0

P3.1/TxD0

P3.2/INT0

P3.3/INT1

P3.4/T0

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

P6.4

P6.3

P6.2/TxD1

P6.1/RxD1

P6.0/ADST

OWE

P5.0/CCM0

P5.1/CCM1

P5.2/CCM2

P5.3/CCM3

P5.4/CCM4

P5.5/CCM5

P5.6/CCM6

P5.7/CCM7

HWPD

P0.7/AD7

P0.6/AD6

P0.5/AD5

P0.4/AD4

P0.3/AD3

P0.2/AD2

&ꢁꢂꢃ$

P3.5/T1

P3.6/WR

P3.7/RD

P1.7/T2

P1.6/CLKOUT

P1.5/T2EX

P1.4/INT2/CC4

Figure 4

Pin Configuration P-LCC-84 Package (Top View)

Semiconductor Group

5

C517A

Table 1

Pin Definitions and Functions

6\PERO

3LQꢀ1XPEHU

,ꢄ2ꢅꢆ )XQFWLRQ

3ꢇ04)3ꢇꢂꢈꢈ

3ꢇ/&&ꢇꢉꢊ

36 - 29

P1.0 - P1.7

9 - 6, 1,

100 - 98

I/O

Port 1

is an 8-bit quasi-bidirectional I/O port with

internal pullup resistors. Port 1 pins that

have 1’s written to them are pulled high by

the internal pullup resistors, and in that state

can be used as inputs. As inputs, port 1 pins

being externally pulled low will source

current (I _IL, in the DC characteristics)

because of the internal pullup resistors. The

port is used for the low-order address byte

during program verification. Port 1 also

contains the interrupt, timer, clock, capture

and compare pins that are used by various

options. The output latch corresponding to a

secondary function must be programmed to

a one (1) for that function to operate (except

when used for the compare functions). The

secondary functions are assigned to the port

1 pins as follows :

9

36

35

34

33

32

31

P1.0 / INT3 / CC0 Interrupt 3 input /

compare 0 output /

capture 0 input

P1.1 / INT4 / CC1 Interrupt 4 input /

compare 1 output /

capture 1 input

P1.2 / INT5 / CC2 Interrupt 5 input /

compare 2 output /

capture 2 input

P1.3 / INT6 / CC3 Interrupt 6 input /

compare 3 output /

8

7

6

capture 3 input

P1.4 / INT2 / CC4 Interrupt 2 input /

compare 4 output /

1

capture 4 input

100

P1.5 / T2EX

Timer 2 external

reload / trigger input

System clock output

Counter 2 input

99

98

30

29

P1.6 / CLKOUT

P1.7 / T2

*) I = Input,

O = Output

Semiconductor Group

6

C517A

Table 1

Pin Definitions and Functions (cont’d)

6\PERO

3LQꢀ1XPEHU

3ꢇ04)3ꢇꢂꢈꢈ 3ꢇ/&&ꢇꢉꢊ

,ꢄ2ꢅꢆ )XQFWLRQ

V_SS

10, 62

37, 83

–

Ground (0V)

during normal, idle, and power down

operation.

V_DD

11, 63

12

38, 84

39

–

Supply voltage

during normal, idle, and power down mode.

XTAL2

is the input to the inverting oscillator

amplifier and input to the internal clock

generator circuits.

To drive the device from an external clock

source, XTAL2 should be driven, while

XTAL1 is left unconnected. Minimum and

maximum high and low times as well as rise/

fall times specified in the AC characteristics

must be observed.

XTAL1

13

40

–

XTAL1

is the output of the inverting oscillator

amplifier. This pin is used for the oscillator

operation with crystal or ceramic resonator.

P2.0 - P2.7

14 - 21

41 - 48

I/O

Port 2

is an 8-bit quasi-bidirectional I/O port with

internal pullup resistors. Port 2 pins that

have 1's written to them are pulled high by

the internal pullup resistors, and in that state

can be used as inputs. As inputs, port 2 pins

being externally pulled low will source

current (I _IL, in the DC characteristics)

because of the internal pullup resistors.

Port 2 emits the high-order address byte

during fetches from external program

memory and during accesses to external

data memory that use 16-bit addresses

(MOVX @DPTR). In this application it uses

strong internal pullup resistors when issuing

1's. During accesses to external data

memory that use 8-bit addresses

(MOVX @Ri), port 2 issues the contents of

the P2 special function register.

*) I = Input

O = Output

Semiconductor Group

7

C517A

Table 1

Pin Definitions and Functions (cont’d)

6\PERO

3LQꢀ1XPEHU

3ꢇ04)3ꢇꢂꢈꢈ 3ꢇ/&&ꢇꢉꢊ

,ꢄ2ꢅꢆ )XQFWLRQ

PSEN

22

49

O

The Program Store Enable

output is a control signal that enables the

external program memory to the bus during

external fetch operations. It is activated

every six oscillator periods except during

external data memory accesses. The signal

remains high during internal program

execution.

ALE

EA

23

24

50

51

O

The Address Latch enable

output is used for latching the address into

external memory during normal operation. It

is activated every six oscillator periods

except during an external data memory

access.

I

External Access Enable

When held high, the C517A executes

instructions from the internal ROM as long

as the PC is less than 8000 . When held

H

low, the C517A fetches all instructions from

external program memory. For the C517A-L

this pin must be tied low. For the C517A-4R,

if the device is protected (see section 4.6 in

the User Manual) then this pin is only

latched during reset.

P0.0 - P0.7

26, 27,

30 - 35

52 - 59

I/O

Port 0

is an 8-bit open-drain bidirectional I/O port.

Port 0 pins that have 1’s written to them

float, and in that state can be used as high-

impedance inputs. Port 0 is also the

multiplexed low-order address and data bus

during accesses to external program and

data memory. In this application it uses

strong internal pullup resistors when issuing

1’s. Port 0 also outputs the code bytes

during program verification in the C517A-

4R. External pullup resistors are required

during program verification.

*) I = Input

O = Output

Semiconductor Group

8

C517A

Table 1

Pin Definitions and Functions (cont’d)

6\PERO

3LQꢀ1XPEHU

3ꢇ04)3ꢇꢂꢈꢈ 3ꢇ/&&ꢇꢉꢊ

,ꢄ2ꢅꢆ )XQFWLRQ

HWPD

36

60

I

Hardware Power Down

A low level on this pin for the duration of one

machine cycle while the oscillator is running

resets the C517A. A low level for a longer

period will force the part into hardware

power down mode with the pins floating.

There is no internal pullup resistor

connected to this pin.

P5.0 - P5.7

44 - 37

68 - 61

I/O

Port 5

is a quasi-bidirectional I/O port with internal

pull-up resistors. Port 5 pins that have 1 s

written to them are pulled high by the

internal pull-up resistors, and in that state

can be used as inputs. As inputs, port 5 pins

being externally pulled low will source

current (I_IL, in the DC characteristics)

because of the internal pull-up resistors.

This port also serves the alternate function

"Concurrent Compare" and "Set/Reset

Compare". The secondary functions are

assigned to the port 5 pins as follows:

CCM0 to CCM7 P5.0 to P5.7 :

concurrent compare or

Set/Reset lines

OWE

45

69

I

Oscillator Watchdog Enable

A high level on this pin enables the oscillator

watchdog. When left unconnected this pin is

pulled high by a weak internal pull-up

resisitor. The logic level at OWE should not

be changed during normal operation. When

held at low level the oscillator watchdog

function is turned off. During hardware

power down the pullup resistor is switched

off.

*) I = Input

O = Output

Semiconductor Group

9

C517A

Table 1

Pin Definitions and Functions (cont’d)

6\PERO

3LQꢀ1XPEHU

3ꢇ04)3ꢇꢂꢈꢈ 3ꢇ/&&ꢇꢉꢊ

,ꢄ2ꢅꢆ )XQFWLRQ

P6.0 - P6.7

46 - 50,

54 - 56

70 - 77

I/O

Port 6

is a quasi-bidirectional I/O port with internal

pull-up resistors. Port 6 pins that have 1 s

written to them are pulled high by the

internal pull-up resistors, and in that state

can be used as inputs. As inputs, port 6 pins

being externally pulled low will source

current (I _IL, in the DC characteristics)

because of the internal pull-up resistors.

Port 6 also contains the external A/D

converter start control pin and the transmit

and receive pins for the serial interface 1.

The output latch corresponding to a

secondary function must be programmed to

a one (1) for that function to operate.

The secondary functions are assigned to the

pins of port 6, as follows :

46

47

48

70

71

72

P6.0 ADST

P6.1 RxD1

P6.2 TxD1

external A/D converter

start pin

receiver data input of serial

interface 1

transmitter data input of

serial interface 1

P8.0 - P8.3

57 - 60

78 - 81

I

Port 8

is a 4-bit unidirectional input port. Port pins

can be used for digital input, if voltage levels

meet the specified input high/low voltages,

and for the higher 4-bit of the multiplexed

analog inputs of the A/D converter,

simultaneously.

P8.0 - P8.3

AIN8 - AIN11 analog

input 8 - 11

RO

61

82

O

Reset Output

This pin outputs the internally synchronized

reset request signal. This signal may be

generated by an external hardware reset, a

watchdog timer reset or an oscillator

watchdog reset. The RO output signal is

active low.

*) I = Input

O = Output

Semiconductor Group

10

C517A

Table 1

Pin Definitions and Functions (cont’d)

6\PERO

3LQꢀ1XPEHU

3ꢇ04)3ꢇꢂꢈꢈ 3ꢇ/&&ꢇꢉꢊ

,ꢄ2ꢅꢆ )XQFWLRQ

P4.0 - P4.7

64 - 66,

68 - 72

1 - 3,

5 - 9

I/O

Port 4

is an 8-bit quasi-bidirectional I/O port with

internal pull-up resistors. Port 4 pins that

have 1’s written to them are pulled high by

the internal pull-up resistors, and in that

state can be used as inputs. As inputs, port

4 pins being externally pulled low will source

current (I _IL, in the DC characteristics)

because of the internal pull-up resistors.

Port 4 also serves as alternate compare

functions. The output latch corresponding to

a secondary function must be programmed

to a one (1) for that function to operate. The

secondary functions are assigned to the

pins of port 4 as follows :

P4.0 - P4.7 CM0 - CM7 Compare

channel 0 - 7

PE/SWD

67

4

I

Power saving mode enable / Start

watchdog timer

A low level at this pin allows the software to

enter the power saving modes (idle mode,

slow down mode, and power down mode).

In case the low level is also seen during

reset, the watchdog timer function is off on

default.

Usage of the software controlled power

saving modes is blocked, when this pin is

held at high level. A high level during reset

performs an automatic start of the watchdog

timer immediately after reset.

When left unconnected this pin is pulled

high by a weak internal pull-up resistor.

During hardware power down the pullup

resisitor is switched off.

*) I = Input

O = Output

Semiconductor Group

11

C517A

Table 1

Pin Definitions and Functions (cont’d)

6\PERO

3LQꢀ1XPEHU

3ꢇ04)3ꢇꢂꢈꢈ 3ꢇ/&&ꢇꢉꢊ

,ꢄ2ꢅꢆ )XQFWLRQ

P3.0 - P3.7

90 - 97

21 - 28

I/O

Port 3

is an 8-bit quasi-bidirectional I/O port with

internal pullup resistors. Port 3 pins that

have 1’s written to them are pulled high by

the internal pullup resistors, and in that state

can be used as inputs. As inputs, port 3 pins

being externally pulled low will source

current (I _IL, in the DC characteristics)

because of the internal pullup resistors. Port

3 also contains the interrupt, timer, serial

port and external memory strobe pins that

are used by various options. The output

latch corresponding to a secondary function

must be programmed to a one (1) for that

function to operate. The secondary

functions are assigned to the pins of port 3,

as follows:

90

91

21

22

P3.0 / RxD0

Receiver data input

(asynch.) or data

input/output (synch.)of

serial interface 0

Transmitter data output

(asynch.) or clock output

(synch.) of serial interface

0

P3.1 / TxD0

92

93

23

24

P3.2 / INT0

P3.3 / INT1

External interrupt 0 input /

timer 0 gate control input

External interrupt 1 input /

timer 1 gate control input

Timer 0 counter input

Timer 1 counter input

WR control output; latches

the data byte from port 0

into the external data

memory

94

95

96

25

26

27

P3.4 / T0

P3.5 / T1

P3.6 / WR

97

28

P3.7 / RD

RD control output; enables

the external data memory

*) I = Input

O = Output

Semiconductor Group

12

C517A

Table 1

Pin Definitions and Functions (cont’d)

6\PERO

3LQꢀ1XPEHU

3ꢇ04)3ꢇꢂꢈꢈ 3ꢇ/&&ꢇꢉꢊ

,ꢄ2ꢅꢆ )XQFWLRQ

RESET

73

10

I

RESET

A low level on this pin for the duration of two

machine cycles while the oscillator is

running resets the C517A. A small internal

pullup resistor permits power-on reset using

only a capacitor connected to V_SS

.

V_AREF

78

11

–

I

Reference voltage for the A/D converter

Reference ground for the A/D converter

V_AGND

79

12

P7.0 - P7.7

87 - 80

20-13

Port 7

is an 8-bit unidirectional input port. Port pins

can be used for digital input, if voltage levels

meet the specified input high/low voltages,

and for the lower 8-bit of the multiplexed

analog inputs of the A/D converter,

simultaneously.

P7.0 - P7.7

AIN0 - AIN7

analog

input0 - 7

N.C.

2 - 5, 25,

28, 29,

51 - 53,

74 - 77

88, 89

–

Not connected

These pins of the P-MQFP-100 package

must not be connected.

*) I = Input

O = Output

Semiconductor Group

13

C517A

Oscillator Watchdog

OSC & Timing

RAM

256 x 8

XRAM

2k x 8

ROM

32k x 8

XTAL1

XTAL2

ALE

PSEN

CPU

8 Datapointer

EA

Emulation

Support

Logic

PE/SWD

RESET

HWPD

Programmable

Watchdog Timer

Port 0

8-Bit Digital I/O

Timer 0

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

RO

OWE

Timer 1

Timer 2

Port 1

8-Bit Digital I/O

Port 2

8-Bit Digital I/O

Capture

Compare Unit

Compare Timer

Port 3

8-Bit Digital I/O

Serial Channel 0

Programmable

Baud Rate Generator

Port 4

8-Bit Digital I/O

Serial Channel 1

Port 5

8-Bit Digital I/O

Programmable

Baud Rate Generator

Port 6

8-Bit Digital I/O

Interrupt Unit

Port 7

8-Bit Analog/

Digital Input

V_AREF

V_AGND

A/D Converter

10 Bit

Port 8

4-Bit Analog/

Digital Input

Analog

MUX

S & H

C517A

MCB03320

Figure 5

Block Diagram of the C517A

Semiconductor Group

14

C517A

CPU

The C517A is efficient both as a controller and as an arithmetic processor. It has extensive facilities

for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program

memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15% three-

byte instructions. With a 12 MHz crystal, 58% of the instructions are executed in 1µs (24 MHz : 500

ns).

Special Function Register PSW (Address D0 )

H

Reset Value : 00

H

Bit No. MSB

LSB

D0

D7

D6

D5

D4

D3

D2

D1

H

D0

CY

AC

F0

RS1

RS0

OV

F1

P

PSW

H

Bit

Function

CY

Carry Flag

Used by arithmetic instruction.

AC

F0

Auxiliary Carry Flag

Used by instructions which execute BCD operations.

General Purpose Flag

RS1

RS0

Register Bank select control bits

These bits are used to select one of the four register banks.

RS1

RS0

Function

Bank 0 selected, data address 00 -07

0

1

0

1

0

1

H

Bank 1 selected, data address 08 -0F

H

Bank 2 selected, data address 10 -17

H

Bank 3 selected, data address 18 -1F

H

OV

Overflow Flag

Used by arithmetic instruction.

General Purpose Flag

Parity Flag

F1

P

Set/cleared by hardware after each instruction to indicate an odd/even

number of "one" bits in the accumulator, i.e. even parity.

Semiconductor Group

15

C517A

Memory Organization

The C517A CPU manipulates operands in the following five address spaces:

– up to 64 Kbyte of program memory (32K on-chip program memory for C517A-4R)

– up to 64 Kbyte of external data memory

– 256 bytes of internal data memory

– 2K bytes of internal XRAM data memory

– a 128 byte special function register area

Figure 6 illustrates the memory address spaces of the C517A.

FFFF

H

FFFF

H

int.

(XMAP0 = 0)

ext.

(XMAP0 = 1)

ext.

Indirect

Address

Direct

Address

F800

H

8000

F7FF

FF

80

FF

80

H

Special

Function

Regs.

Internal

RAM

7FFF

0000

H

int.

(EA = 1)

ext.

(EA = 0)

ext.

7F

H

Internal

RAM

0000

00

H

"Code Space"

"Data Space"

"Internal Data Space"

MCB03321

Figure 6

C517A Memory Map

Semiconductor Group

16

C517A

Reset and System Clock

The reset input is an active low input at pin RESET. Since the reset is synchronized internally, the

RESET pin must be held low for at least two machine cycles (24 oscillator periods) while the

oscillator is running. A pullup resistor is internally connected to V_DDto allow a power-up reset with

an external capacitor only. An automatic reset can be obtained when V_DDis applied by connecting

the RESET pin to V_SSvia a capacitor. Figure 7 shows the possible reset circuitries.

a)

b)

&

RESET

+

C517A

c)

RESET

+

C517A

MCS03323

Figure 7

Reset Circuitries

Semiconductor Group

17

C517A

Figure 8 shows the recommended oscillator circiutries for crystal and external clock operation.

Crystal Oscillator Mode

C

Driving from External Source

N.C.

XTAL1

XTAL2

XTAL1

3.5 - 24

MHz

External Oscillator

Signal

XTAL2

C

Crystal Mode:

C = 20 pF 10 pF

(Incl. Stray Capacitance)

MCS03245

Figure 8

Recommended Oscillator Circuitries

Semiconductor Group

18

C517A

Enhanced Hooks Emulation Concept

The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative

way to control the execution of C500 MCUs and to gain extensive information on the internal

operation of the controllers. Emulation of on-chip ROM based programs is possible, too.

Each production chip has built-in logic for the supprt of the Enhanced Hooks Emulation Concept.

Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation

and production chips are identical.

The Enhanced Hooks Technology^TM¹⁾, which requires embedded logic in the C500 allows the C500

together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces

costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate

all operating modes of the different versions of the C500 microcontrollers. This includes emulation

of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in

single step mode and to read the SFRs after a break.

ICE-System interface

to emulation hardware

RESET

SYSCON

PCON

RSYSCON

RPCON

EA

ALE

PSEN

EH-IC

TCON

RTCON

C500

MCU

Enhanced Hooks

Interface Circuit

Port 0

Port 2

Port 1

opt.

I/O Ports

RPORT RPORT

Port 3

2

0

TEA TALE TPSEN

Target System Interface

MCS03254

Figure 9

Basic C500 MCU Enhanced Hooks Concept Configuration

Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks

Emulation Concept to control the operation of the device during emulation and to transfer

informations about the programm execution and data transfer between the external emulation

hardware (ICE-system) and the C500 MCU.

1 “Enhanced Hooks Technology“ is a trademark and patent of Metalink Corporation licensed to Siemens.

Semiconductor Group

19

C517A

Special Function Registers

The registers, except the program counter and the four general purpose register banks, reside in

the special function register area.

The 94 special function registers (SFRs) in the standard and mapped SFR area include pointers

and registers that provide an interface between the CPU and the other on-chip peripherals. All SFRs

with addresses where address bits 0-2 are 0 (e

.g. 80 , 88 , 90 , 98 , ..., F8 , FF ) are bitaddressable. The SFRs of the C517A are listed in

H

table 2 and table 3. In table 2 they are organized in groups which refer to the functional blocks of

the C517A. Table 3 illustrates the contents of the SFRs in numeric order of their addresses.

Semiconductor Group

20

C517A

Table 2

Special Function Registers - Functional Blocks

Block

Symbol

Name

Address Contents after

Reset

1)

CPU

ACC

B

Accumulator

B-Register

E0

F0

83

82

92

00

H

1)

H

DPH

DPL

DPSEL

PSW

SP

Data Pointer, High Byte

Data Pointer, Low Byte

Data Pointer Select Register

Program Status Word Register

Stack Pointer

3)

XXXX X000

00

07

H

B

1)

D0

H

81

H

A/D-

ADCON0 ²⁾A/D Converter Control Register 0

D8

DC

D9

DA

00

H

0XXX 0000

00

H

3)

Converter ADCON1 A/D Converter Control Register 1

H

B

ADDATH

ADDATL

A/D Converter Data Register, High Byte

A/D Converter Data Register, Low Byte

H

3

00XX XXXX

H

B

1)

Interrupt

System

IEN0²⁾

IEN1²⁾

IEN2

IP0 ²⁾

IP1

Interrupt Enable Register 0

Interrupt Enable Register 1

Interrupt Enable Register 2

Interrupt Priority Register 0

Interrupt Priority Register 1

A8

B8

00

H

00

H

3)

9A

A9

B9

XX00 00X0

H

B

00

H

3)

XX00 0000

B

1)

IRCON0²⁾Interrupt Request Control Register 0

C0

D1

88

00

H

IRCON1

TCON

T2CON

S0CON

CTCON

Interrupt Request Control Register 1

Timer 0/1 Control Register

Timer 2 Control Register

Serial Channel 0 Control Register

Compare Timer Control Register

00

H

2)

1)

00

H

2)

1)

C8

00

H

1)

98

E1

00

H

2)

3)

0X00 0000

B

3)

MUL/DIV ARCON

Arithmetic Control Register

EF

E9

EA

0XXXXXXX

H

B

3)

Unit

MD0

MD1

MD2

MD3

MD4

MD5

Multiplication/Division Register 0

Multiplication/Division Register 1

Multiplication/Division Register 2

Multiplication/Division Register 3

Multiplication/Division Register 4

Multiplication/Division Register 5

XX

H

EB

EC

ED

EE

H

1)

2)

Timer 0 / TCON

Timer 0/1 Control Register

Timer 0, High Byte

Timer 1, High Byte

Timer 0, Low Byte

Timer 1, Low Byte

Timer Mode Register

88

00

H

Timer 1

TH0

TH1

TL0

8C

8D

8A

00

H

TL1

TMOD

8B

89

1) Bit-addressable special function registers

2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.

3) “X“ means that the value is undefined and the location is reserved

Semiconductor Group

21

C517A

Table 2

Special Function Registers - Functional Blocks (cont’d)

Block

Symbol

Name

Address Contents after

Reset

Compare/ CCEN

Compare/Capture Enable Register

Compare/Capture 4 Enable Register

Compare/Capture Register 1, High Byte

Compare/Capture Register 2, High Byte

Compare/Capture Register 3, High Byte

Compare/Capture Register 4, High Byte

Compare/Capture Register 1, Low Byte

Compare/Capture Register 2, Low Byte

Compare/Capture Register 3, Low Byte

Compare/Capture Register 4, Low Byte

Compare Enable Register

Compare Register 0, High Byte

Compare Register 1, High Byte

Compare Register 2, High Byte

Compare Register 3, High Byte

Compare Register 4, High Byte

Compare Register 5, High Byte

Compare Register 6, High Byte

Compare Register 7, High Byte

Compare Register 0, Low Byte

Compare Register 1, Low Byte

Compare Register 2, Low Byte

Compare Register 3, Low Byte

Compare Register 4, Low Byte

Compare Register 5, Low Byte

Compare Register 6, Low Byte

Compare Register 7, Low Byte

Compare Input Select

C1

C9

C3

C5

C7

CF

C2

C4

C6

00

H

Capture

Unit

(CCU)

Timer 2

CC4EN

CCH1

CCH2

CCH3

CCH4

CCL1

CCL2

CCL3

CCL4

CMEN

CMH0

CMH1

CMH2

CMH3

CMH4

CMH5

CMH6

CMH7

CML0

CML1

CML2

CML3

CML4

CML5

CML6

CML7

CMSEL

CRCH

CRCL

H

CE

F6

H

D3

D5

D7

E3

H

E5

E7

F3

F5

D2

D4

D6

E2

H

E4

E6

F2

F4

F7

Comp./Rel./Capt. Register High Byte

Comp./Rel./Capt. Register Low Byte

CB

CA

A1

H

COMSETL Compare Set Register Low Byte

COMSETH Compare Set Register, High Byte

COMCLRL Compare Clear Register, Low Byte

COMCLRH Compare Clear Register, High Byte

H

A2

A3

A4

A5

A6

E1

SETMSK

Compare Set Mask Register

CLRMSK Compare Clear Mask Register

CTCON ²⁾Compare Timer Control Register

0X00 0000

00

)

3

B

CTRELH

CTRELL

TH2

TL2

T2CON

Compare Timer Rel. Register, High Byte

Compare Timer Rel. Register, Low Byte

Timer 2, High Byte

Timer 2, Low Byte

Timer 2 Control Register

DF

H

DE

00

H

CD

CC

C8

00

H

00

H

2)

1)

00

H

2)

1)

IRCON0

Interrupt Request Control Register 0

C0

00

H

1) Bit-addressable special function registers

2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.

3) “X“ means that the value is undefined and the location is reserved

Semiconductor Group

22

C517A

Table 2

Special Function Registers - Functional Blocks (cont’d)

Block

Symbol

Name

Address Contents after

Reset

1)

Ports

P0

P1

P2

P3

P4

P5

P6

P7

P8

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

80

90

A0

B0

E8

F8

FA

DB

DD

FF

–

H

1)

H

1)

H

Port 7, Analog/Digital Input

Port 8, Analog/Digital Input, 4-bit

–

XRAM

Serial

XPAGE

Page Address Register for Extended

On-Chip RAM

91

00

H

SYSCON ²⁾System/XRAM Control Register

B1

XXXX XX01

3)

H

B

ADCON0 ²⁾A/D Converter Control Register

Channels PCON ²⁾

S0BUF

D8

00

H

00

XX

00

1)

H

Power Control Register

87

99

98

H

3

Serial Channel 0 Buffer Register

Serial Channel 0 Control Register

Serial Channel 0 Reload Reg., Low Byte

Serial Channel 0 Reload Reg., High Byte

Serial Channel 1 Buffer Register

Serial Channel 1 Control Register

Serial Channel 1 Reload Reg., Low Byte

Serial Channel 1 Reload Reg., High Byte

)

1)

S0CON

S0RELL

S0RELH

S1BUF

S1CON

AA

BA

9C

9B

9D

D9

H

3)

XXXXXX11

XX

0X00 0000

00

B

3

)

H

3)

B

S1RELL

S1RELH

H

3)

BB

XXXX XX11

1)

Watchdog IEN0 ²⁾

IEN1 ²⁾

Interrupt Enable Register 0

Interrupt Enable Register 1

Interrupt Priority Register 0

A8

B8

00

H

1)

00

H

IP0 ²⁾

A9

00

H

00

H

WDTREL Watchdog Timer Reload Register

Pow.Sav. PCON ²⁾

Power Control Register

Modes

86

87

00

H

1) Bit-addressable special function registers

2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.

3) “X“ means that the value is undefined and the location is reserved.

Semiconductor Group

23

C517A

Table 3

Contents of the SFRs, SFRs in numeric order of their addresses

Addr Register Content Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

after

Reset¹⁾

2)

80

81

82

83

P0

FF

07

.7

.6

.5

.4

.3

.2

.1

.0

H

SP

H

DPL

DPH

00

WDT-

PSEL

WDTREL 00

87

88

89

PCON

TCON

TMOD

TL0

00

SMOD PDS

TF1 TR1

GATE C/T

IDLS

TF0

M1

.5

SD

TR0

M0

.4

GF1

IE1

GF0

IT1

PDE

IE0

M1

.1

IDLE

IT0

M0

.0

H

2)

GATE C/T

8A

.7

T2

.6

.3

.2

H

8B

TL1

.5

.4

.3

.2

.1

.0

8C

8D

90

TH0

.5

.4

.3

.2

.1

.0

H

TH1

.5

.4

.3

.2

.1

.0

H

2)

P1

FF

CLK-

OUT

T2EX INT2

INT6

INT5

INT4

INT3

H

91

92

XPAGE

DPSEL

00

.7

.6

.5

.4

.3

.2

.1

.0

H

XXXX-

X000

–

.2

.1

.0

B

2)

98

99

S0CON

S0BUF

IEN2

00

H

SM0

.7

SM1

.6

SM20 REN0 TB80

RB80 TI0

.2 .1

RI0

.0

H

XX

H

.5

.4

.3

H

9A

XX00-

00X0

–

ECR

ECS

ECT

ECMP –

ES1

H

B

9B

S1CON

S1BUF

0X00-

0000

SM

–

SM21 REN1 TB81

RB81 TI1

RI1

B

9C

9D

A0

XX

H

.7

.6

.5

.4

.3

.2

.1

.0

H

S1RELL 00

H

2)

H

P2

FF

H

COMSETL

COMSETH

COMCLRL

A1

A2

A3

00

1) X means that the value is undefined and the location is reserved

2) Shaded registers are bit-addressable special function registers

Semiconductor Group

24

C517A

Table 3

Contents of the SFRs, SFRs in numeric order of their addresses (cont’d)

Addr Register Content Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

after

Reset¹⁾

COMCLRH

A4

A5

A6

A8

A9

00

.7

.6

.5

.4

.3

.2

.1

.0

H

SETMSK 00

CLRMSK 00

.7

.6

.5

.4

.3

.2

.1

.0

.7

.6

.5

.4

.3

.2

.1

.0

2)

IEN0

IP0

00

EAL

WDT

ET2

ES0

.4

ET1

.3

EX1

.2

ET0

.1

EX0

.0

OWDS WDTS .5

AA

B0

S0RELL D9

.7

.6

.5

T1

–

.4

.3

.2

.1

.0

H

2)

P3

FF

RD

–

WR

–

T0

–

INT1

–

INT0

–

TxD0

RxD0

H

XMAP1 XMAP0

B1

SYSCON XXXX-

H

XX01

B

2)

B8

B9

IEN1

IP1

00

EXEN2 SWDT EX6

EX5

.4

EX4

.3

EX3

.2

EX2

.1

EADC

.0

H

XX00-

0000

–

.5

B

BA

BB

C0

S0RELH XXXX-

–

.1

.0

H

XX11

B

S1RELH XXXX-

–

.1

.0

H

XX11

B

IRCON0 00

H

EXF2 TF2

IEX6

IEX5

IEX4

IEX3

IEX2

IADC

H

2)

C1

CCEN

00

COCA COCA COCA COCA COCA COCA COCA COCA

H

H3

.7

L3

.6

H2

L2

.4

H1

.3

L1

.2

H0

.1

L0

C2

C3

C4

C5

C6

C7

CCL1

CCH1

CCL2

CCH2

CCL3

CCH3

T2CON

00

.5

.0

H

.5

.0

.5

.0

.5

.0

.5

.0

.5

.0

C8

T2PS I3FR

I2FR

T2R1 T2R0 T2CM T2I1

T2I0

2)

C9

CC4EN

00

COCO COCO COCO COCO COCO COCA COCA COMO

EN1 N2 N1 N0 EN0 H4 L4

H

1) X means that the value is undefined and the location is reserved

2) Shaded registers are bit-addressable special function registers

Semiconductor Group

25

C517A

Table 3

Contents of the SFRs, SFRs in numeric order of their addresses (cont’d)

Addr Register Content Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

after

Reset¹⁾

CA

CB

CRCL

CRCH

TL2

00

.7

CY

.6

AC

.5

F0

.4

.3

.2

.1

F1

.0

P

H

.4

.3

.2

H

CC

CD

CE

.4

.3

.2

H

TH2

.4

.3

.2

CCL4

CCH4

PSW

.4

.3

.2

H

CF

.4

.3

.2

D0

2)

RS1

RS0

OV

H

D1

D2

D3

D4

D5

D6

D7

IRCON1 00

ICMP7 ICMP6 ICMP5 ICMP4 ICMP3 ICMP2 ICMP1 ICMP0

H

CML0

CMH0

CML1

CMH1

CML2

CMH2

00

.7

BD

.6

.5

.4

.3

.2

.1

.0

.6

.3

.2

.1

.0

.6

.3

.2

.1

.0

.6

.3

.2

.1

.0

.6

.3

.2

.1

.0

.6

.3

.2

.1

.0

D8

2)

ADCON0 00

CLK

ADEX BSY

ADM

MX2

MX1

MX0

D9

ADDATH 00

.9

.1

.8

.0

.7

.6

.5

.4

.3

.2

H

DA

ADDATL 00XX-

XXXX

–

H

B

DB

P7

–

.7

.6

–

.5

–

.4

–

.3

.2

.1

.0

H

DC

ADCON1 0XXX- ADCL

MX3

MX2

MX1

MX0

H

0000

B

DD

DE

P8

–

.3

.2

.1

.0

H

CTRELL 00

CTRELH 00

.7

.6

.5

.4

.3

H

DF

E0

.5

.4

.3

2)

ACC

00

.5

.4

.3

H

E1

CTCON 0X00.

0000

T2PS1 –

ICR

ICS

CTF

CLK2 CLK1 CLK0

H

B

E2

CML3

00

.7 .6

.5

.4

.3

.2 .1 .0

H

1) X means that the value is undefined and the location is reserved

2) Shaded registers are bit-addressable special function registers

Semiconductor Group

26

C517A

Table 3

Contents of the SFRs, SFRs in numeric order of their addresses (cont’d)

Addr Register Content Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

after

Reset¹⁾

E3

E4

E5

E6

E7

E8

E9

CMH3

CML4

CMH4

CML5

CMH5

P4

00

.7

.6

.5

.4

.3

.2

.1

.0

H

.7

.6

.5

.4

.3

.2

.1

.0

.7

.6

.5

.4

.3

.2

.1

.0

.7

.6

.5

.4

.3

.2

.1

.0

.7

.6

.5

.4

.3

.2

.1

.0

2)

FF

CM7

.7

CM6

.6

CM5

.5

CM4

.4

CM3

.3

CM2

.2

CM1

.1

CM0

.0

H

MD0

MD1

MD2

MD3

MD4

MD5

XX

H

EA

EB

.7

.6

.5

.4

.3

.2

.1

.0

H

.7

.6

.5

.4

.3

.2

.1

.0

H

EC

ED

EE

.7

.6

.5

.4

.3

.2

.1

.0

H

.7

.6

.5

.4

.3

.2

.1

.0

.7

.6

.5

.4

.3

.2

.1

.0

H

EF

ARCON 0XXX.

XXXX

MDEF MDOV SLR

SC.4

SC.3

SC.2

SC.1

SC.0

B

2)

F0

B

00

.7

.6

.5

.4

.3

.2

.1

.0

H

F2

F3

F4

F5

F6

F7

F8

CML6

CMH6

CML7

CMH7

CMEN

CMSEL

P5

2)

FF

CCM7 CCM6 CCM5 CCM4 CCM3 CCM2 CCM1 CCM0

.7 .6 .5 .4 .3 TxD1 RxD1 ADST

H

FA

P6

FF

H

1) X means that the value is undefined and the location is reserved

2) Shaded registers are bit-addressable special function registers

Semiconductor Group

27

C517A

Digital I/O Ports

The C517A allows for digital I/O on 56 lines grouped into 7 bidirectional 8-bit ports. Each port bit

consists of a latch, an output driver and an input buffer. Read and write accesses to the I/O ports P0

through P6 are performed via their corresponding special function registers P0 to P6.

The output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external

memory. In this application, port 0 outputs the low byte of the external memory address, time-

multiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory

address when the address is 16 bits wide. Otherwise, the port 2 pins continue emitting the P2 SFR

contents.

Analog Input Ports

Ports 7 (8-bit) and 8 (4-bit) are input ports only and provide two functions. When used as digital

inputs, the corresponding SFR P7 and P8 contains the digital value applied to the port 7/8 lines.

When used for analog inputs the desired analog channel is selected by a four-bit field in SFR

ADCON1. Of course, it makes no sense to output a value to these input-only ports by writing to the

SFR P7 or P8. This will have no effect.

lf a digital value is to be read, the voltage levels are to be held within the input voltage specifications

(V_IL/V_IH). Since P7 and P8 are not bit-addressable, all input lines of P7 and P8 are read at the same

time by byte instructions.

Nevertheless, it is possible to use port 7 and 8 simultaneously for analog and digital input. However,

care must be taken that all bits of P7 and P8 that have an undetermined value caused by their

analog function are masked.

Semiconductor Group

28

C517A

Timer / Counter 0 and 1

Timer/Counter 0 and 1 can be used in four operating modes as listed in table 4 :

Table 4

Timer/Counter 0 and 1 Operating Modes

Mode Description

TMOD

Input Clock

external (max)

_OSC/24x32

M1

M0

internal

0

8-bit timer/counter with a

0

f

_OSC/12x32

f

divide-by-32 prescaler

1

2

16-bit timer/counter

1

0

8-bit timer/counter with

8-bit autoreload

f

_OSC/12

f_OSC/24

3

Timer/counter 0 used as one

8-bit timer/counter and one

8-bit timer

1

Timer 1 stops

In the “timer” function (C/T = ‘0’) the register is incremented every machine cycle. Therefore the

count rate is f_OSC/12.

In the “counter” function the register is incremented in response to a 1-to-0 transition at its

corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a

falling edge the max. count rate is f_OSC/24. External inputs INT0 and INT1 (P3.2, P3.3) can be

programmed to function as a gate to facilitate pulse width measurements. Figure 10 illustrates the

input clock logic.

f _OSC

f _OSC/12

÷

12

C/T

TMOD

0

1

P3.4/T0

P3.5/T1

max f _OSC/24

Timer 0/1

Input Clock

TR 0/1

TCON

Control

&

Gate

=1

TMOD

_

<

1

P3.2/INT0

P3.3/INT1

MCS01768

Figure 10

Timer/Counter 0 and 1 Input Clock Logic

Semiconductor Group

29

C517A

Cpmpare / Capture Unit (CCU)

The compare/capture unit is one of the C517A’s most powerful peripheral units for use in all kinds

of digital signal generation and event capturing like pulse generation, pulse width modulation, pulse

width measuring etc. The CCU consists of two 16-bit timer/counters with automatic reload feature

and an array of 13 compare or compare/capture registers. A set of six control registers is used for

flexible adapting of the CCU to a wide variety of user’s applications.

The block diagram in figure 11 shows the general configuration of the CCU. All CC1 to CC4

registers and the CRC register are exclusively assigned to timer 2. Each of the eight compare

registers CM0 through CM7 can either be assigned to timer 2 or to the faster compare timer, e.g. to

provide up to 8 PWM output channels. The assignment of the CMx registers - which can be done

individually for every single register - is combined with an automatic selection of one of the two

possible compare modes.

(CTREL)

"Internal Bus"

16-bit Reload

(CM0)

Port

Control

Logik

P4-

I/O-

Latch

Compare Timer

8x

16-bit

Max.Clock =

f

_OSC/2

Compare

P5-

I/O-

Latch

Shadow

Latch

CC4EN

(CM7)

Timer 2

Capt./Comp. 4 (CC4)

Max.Clock = f_OSC/12

Capt./Comp. 3 (CC3)

Capt./Comp. 2 (CC2)

Port

Control

Logik

P1-

I/O-

Latch

Capt./Comp.1 (CC1)

16-bit Rel.Capt.(CRC)

Comp.

MCB01577

Figure 11

Timer 2 Block Diagram

Semiconductor Group

30

C517A

The main functional blocks of the CCU are :

– Timer 2 with f_OSC/12 input clock, 2-bit prescaler, 16-bit reload, counter/gated timer mode and

overflow interrupt request.

– Compare timer with f_OSC/2 input clock, 3-bit prescaler, 16-bit reload and overflow interrupt

request.

– Compare/(reload/)capture register array consisting of four different kinds of registers:

one 16-bit compare/reload/capture register,

three 16-bit compare/capture registers,

one 16-bit compare/capture register with additional "concurrent compare" feature,

eight 16-bit compare registers with timer-overflow controlled loading.

Table 5 shows the possible configurations of the CCU and the corresponding compare modes

which can be selected. The following sections describe the function of these configurations.

Table 5

CCU Configurations

Assigned

Timer

Compare

Register

Compare Output at Possible Modes

Timer 2

CRCH/CRCL

CCH1/CCL1

CCH2/CCL2

CCH3/CCL3

CCH4/CCL4

P1.0/INT3/CC0

P1.1/INT4/CC1

P1.2/INT5/CC2

P1.3/INT6/CC3

P1.4/INT2/CC4

Compare mode 0, 1 + Reload

Compare mode 0, 1 / capture

CCH4/CCL4

P1.4/INT2/CC4

P5.0/CCM0

to

Compare mode 1

“Concurrent compare“

P5.7/CCM7

CMH0/CML0

to

CMH7/CML7

P4.0/CM0

to

P4.7/CM7

Compare mode 0

Compare mode 2

Compare mode 1

COMSET

COMCLR

P5.0/CCM0

to

P5.7/CCM7

Compare

Timer

CMH0/CML0

to

P4.0/CM0

to

CMH7/CML7

P4.7/CM7

Semiconductor Group

31

C517A

Timer 2 Operation

Timer Mode : In timer function, the count rate is derived from the oscillator frequency. A prescaler

offers the possibility of selecting a count rate of 1/12 or 1/24 of the oscillator frequency.

Gated Timer Mode : In gated timer function, the external input pin P1.7/T2 operates as a gate to the

input of timer 2. lf T2 is high, the internal clock input is gated to the timer. T2 = 0 stops the counting

procedure. The external gate signal is sampled once every machine cycle.

Event Counter Mode : In the event counter function. the timer 2 is incremented in response to a 1-

to-0 transition at its corresponding external input pin P1.7/T2. In this function, the external input is

sampled every machine cycle. The maximum count rate is 1/24 of the oscillator frequency.Reload

of Timer 2 : Two reload modes are selectable:

In mode 0, when timer 2 rolls over from all 1’s to all 0’s, it not only sets TF2 but also causes the timer

2 registers to be loaded with the 16-bit value in the CRC register, which is preset by software.

In mode 1, a 16-bit reload from the CRC register is caused by a negative transition at the correspon-

ding input pin P1.5/T2EX.

Programmable

Prescaler

OSC

T2PS T2PS1

SFR T2CON

T2I1

T2I0

No input selected

0

1

0

1

0

1

Timer stop

Timer function

Counter function

via ext. input P1.7/T2

P1.7/T2

Timer 2

Input Clock

Gated timer function

by ext. input P1.7/T2

TL2

(8 Bits)

TH2

(8 Bits)

TF2

_

<

1

Interrupt

Sync

P1.5/T2EX

EXF2

EXEN2

_

<

1

Reload

MCB03328

Figure 12

Block Diagram of Timer 2

Semiconductor Group

32

C517A

Compare Timer Operation

The compare timer receives its input clock from a programmable prescaler which provides input

frequencies, ranging from f_OSC/2 up to f_OSC/256. The compare timer is, once started, a free-running

16-bit timer, which on overflow is automatically reloaded by the contents of a 16-bit reload register.

The compare timer has - as any other timer in the C517A - their own interrupt request flags CTF.

These flags are set when the timer count rolls over from all ones to the reload value. Figure 13

shows the block diagram of compare timer and compare timer 1.

f _OSC/2

3-Bit Prescaler

Compare Timer

/2

/4

/8

/16

/32

/64

/128

Control (CTCON)

16

To Compare

Circuitry

To Interrupt

Circuitry

16-Bit Compare Timer

16-Bit Reload (CTREL)

CTF

Overflow

MCB00783

Figure 13

Compare Timer Block Diagram

Semiconductor Group

33

C517A

Compare Modes

The compare function of a timer/register combination operates as follows : the 16-bit value stored

in a compare or compare/capture register is compared with the contents of the timer register; if the

count value in the timer register matches the stored value, an appropriate output signal is generated

at a corresponding port pin and an interrupt can be generated.

Compare Mode 0

In compare mode 0, upon matching the timer and compare register contents, the output signal

changes from low to high. lt goes back to a low level on timer overflow. As long as compare mode

0 is enabled, the appropriate output pin is controlled by the timer circuit only and writing to the port

will have no effect. Figure 14 shows a functional diagram of a port circuit when used in compare

mode 0. The port latch is directly controlled by the timer overflow and compare match signals. The

input line from the internal bus and the write-to-latch line of the port latch are disconnected when

compare mode 0 is enabled.

Port Circuit

Read Latch

V_DD

V_CC

Compare Register

Circuit

Compare Reg.

S

Q

Port

Internal

Bus

16 Bit

Comparator

D

Port

Latch

Write to

Latch

Compare

Match

CLK

16 Bit

Timer Register

Timer Circuit

R

Timer

Overflow

Read Pin

MCS02661

Figure 14

Port Latch in Compare Mode 0

Compare Mode 1

If compare mode 1 is enabled and the software writes to the appropriate output latch at the port, the

new value will not appear at the output pin until the next compare match occurs. Thus, it can be

choosen whether the output signal has to make a new transition (1-to-0 or 0-to-1, depending on the

actual pin-level) or should keep its old value at the time when the timer value matches the stored

compare value.

In compare mode 1 (see figure 15) the port circuit consists of two separate latches. One latch

(which acts as a "shadow latch") can be written under software control, but its value will only be

transferred to the port latch (and thus to the port pin) when a compare match occurs.

Semiconductor Group

34

C517A

Port Circuit

Read Latch

V

DD

CC

Compare Register

Circuit

Compare Reg.

Internal

Bus

D

Q

D

Q

Port

16 Bit

Comparator

16 Bit

Shadow

Latch

Port

Latch

Compare

Match

Write to

Latch

CLK

Timer Register

Timer Circuit

Read Pin

MCS02662

Figure 15

Compare Function in Compare Mode 1

Compare Mode 2

In the compare mode 2 the port 5 pins are under control of compare/capture register CC4, but under

control of the compare registers COMSET and COMCLR. When a compare match occurs with

register COMSET, a high level appears at the pins of port 5 when the corresponding bits in the mask

register SETMSK are set. When a compare match occurs with register COMCLR, a low level

appears at the pins of port 5 when the corresponding bits in the mask register CLRMSK are set.

Port Circuit

Read Latch

COMSET

16 Bit

Comparator

V

_CD_CD

Compare

Signal

SETMSK

Bits

16 Bit

S

D

Q

Port

Internal

Bus

Port

Latch

TH2

TL2

Write to

Latch

Timer 2

CLK

R

16 Bit

Comparator

16 Bit

COMCLR

Compare

Signal

CLRMSK

Bits

Read Pin

MCS02663

Figure 16

Compare Function of Compare Mode 2

Semiconductor Group

35

C517A

Multiplication / Division Unit (MDU)

This on-chip arithmetic unit of the C517A provides fast 32-bit division, 16-bit multiplication as well

as shift and normalize features. All operations are unsigned integer operations. Table 6 describes

the five general operations the MDU is able to perform.

Table 6

MDU Operation Characteristics

Operation

Result

Remainder

Execution Time

1)

32bit/16bit

16bit/16bit

16bit x 16bit

32-bit normalize

32-bit shift L/R

32bit

16bit

32bit

–

16bit

–

6 t_CY

4 t_CY

6 t_CY

1)

2)

–

6 t_CY

1) 1 t_CY= 12 t_CLCL= 1 machine cycle = 500 ns at 24 MHz oscillator frequency

2) The maximal shift speed is 6 shifts per machine cycle

The MDU consists of seven special function registers (MD0-MD5, ARCON) which are used as

operand, result, and control registers. The three operation phases are shown in figure 17.

Figure 17

Operating Phases of the MDU

Semiconductor Group

36

C517A

For starting an operation, registers MD0 to MD5 and ARCON must be written to in a certain

sequence according table 7 and 8. The order the registers are accessed determines the type of the

operation. A shift operation is started by a final write operation to SFR ARCON.

Table 7

Programming the MDU for Multiplication and Division

Operation

32Bit/16Bit

16Bit/16Bit

16Bit x 16Bit

First Write

MD0 D’endL

MD1 D’end

MD2 D’end

MD3 D’endH

MD4 D’orL

MD5 D’orH

MD0 D’endL

MD1 D’endH

MD0 M’andL

MD4 M’orL

MD4 D’orL

MD5 D’orH

MD1 M’andH

MD5 M’orH

Last Write

First Read

MD0 QuoL

MD1 Quo

MD2 Quo

MD3 QuoH

MD4 RemL

MD5 RemH

MD0 QuoL

MD1 QuoH

MD0 PrL

MD1

MD4 RemL

MD5 RemH

MD2

Last Read

MD3 PrH

Abbrevations :

D’end

D’or

M’and

M’or

Pr

Rem

Quo

...L

: Dividend, 1st operand of division

: Divisor, 2nd operand of division

: Multiplicand, 1st operand of multiplication

: Multiplicator, 2nd operand of multiplication

: Product, result of multiplication

: Remainder

: Quotient, result of division

: means, that this byte is the least significant of the 16-bit or 32-bit operand

: means, that this byte is the most significant of the 16-bit or 32-bit operand

...H

Table 8

Programming athe MDU for a Shift or Normalize Operation

Operation

Normalize, Shift Left, Shift Right

First write

MD0

least significant byte

MD1

.

MD2

.

MD3

ARCON

most significant byte

start of conversion

Last write

First read

MD0

MD1

MD2

MD3

least significant byte

.

Last read

most significant byte

Semiconductor Group

37

C517A

Serial Interfaces 0 and 1

The C517A has two serial interfaces which are functionally nearly identical concerning the

asynchronous modes of operation. The two channels are full-duplex, meaning they can transmit

and receive simultaneously. The serial channel 0 is completely compatible with the serial channel

of the C501 (one synchronous mode, three asynchronous modes). Serial channel 1 has the same

functionality in its asynchronous modes, but the synchronous mode and the fixed baud rate UART

mode is missing.

The operating modes of the serial interfaces is illustrated in table 9. The possible baudrates can be

calculated using the formulas given in table 10.

Table 9

Operating Modes of Serial Interface 0 and 1

Mode

S0CON

S1CON Description

SM

Serial

Interface

SM0

SM1

0

–

Shift register mode

Serial data enters and exits through R×D0;

T×D0 outputs the shift clock; 8-bit are

transmitted/received (LSB first); fixed baud rate

1

2

0

1

0

–

8-bit UART, variable baud rate

10 bits are transmitted (through T×D0) or

received (at R×D0)

9-bit UART, fixed baud rate

11 bits are transmitted (through T×D0) or

received (at R×D0)

3

1

–

1

–

0

9-bit UART, variable baud rate

Like mode 2

1

A

9-bit UART; variable baud rate

11 bits are transmitted (through T×D1) or

received (at R×D1)

B

–

1

8-bit UART; variable baud rate

10 bits are transmitted (through T×D1) or

received (at R×D1)

Semiconductor Group

38

C517A

For clarification some terms regarding the difference between "baud rate clock" and "baud rate"

should be mentioned. In the asynchronous modes the serial interfaces require a clock rate which is

16 times the baud rate for internal synchronization. Therefore, the baud rate generators/timers have

to provide a "baud rate clock" (output signal in figure 18 and figure 19) to the serial interface

which - there divided by 16 - results in the actual "baud rate". Further, the abrevation f_OSCrefers to

the oscillator frequency (crystal or external clock operation).

The variable baud rates for modes 1 and 3 of the serial interface 0 can be derived from either timer

1 or a decdicated baud rate generator (see figure 18). The variable baud rates for modes A and B

of the serial interface 1 are derived from a decdicated baud rate generator as shown in figure 19.

Timer 1 Overflow

S0CON.7

S0CON.6

(SM0/

ADCON0.7

PCON.7

(SMOD)

(BD)

Baud

Mode 1

Mode 3

SM1)

0

1

0

Rate

÷ 2

Baud

Rate

Clock

f _OSC/2

Generator

Mode 2

1

(S0RELH

S0RELL)

Mode 0

Only one mode

can be selected

÷ 6

Note : The switch configuration shows the reset state.

MCS03329

Figure 18

Serial Interface 0 : Baud Rate Generation Configuration

Baud Rate Generator

S1RELL

S1RELH

.1 .0

Baud

Rate

Clock

f

_OSC/2

Input Clock

Owerflow

10-Bit Timer

MCS03331

Figure 19

Serial Interface 1 : Baud Rate Generator Configuration

The baud rate generator block in figure 18 has the same structure (10-bit auto-reload timer) as the

baud rate generator block which is shown in detail in figure 19.

Semiconductor Group

39

C517A

Table 10 below lists the values/formulas for the baud rate calculation of serial interface 0 and 1 with

its dependencies of the control bits BD and SMOD.

Table 10

Serial Interfaces - Baud Rate Dependencies

Serial Interface

Operating Modes

Active Control

Bits

Baud Rates

SMOD BD

Mode 0 (Shift Register)

–

0

Fixed baud rate clock fosc/12

Mode 1 (8-bit UART)

Mode 3 (9-bit UART)

X

Timer 1 overflow is used for baud rate

generation; SMOD controls a divide-by-2 option.

Baud rate = 2^SMODx timer 1 overflow rate / 32

1

Baud rate generator is used for baud rate

generation; SMOD controls a divide-by-2 option

Baud rate = 2^SMODx oscillator frequency /

64 x (baud rate gen. overflow rate)

Mode 2 (9-bit UART)

X

–

Fixed baud rate clock fosc/32 (SMOD=1) or fosc/

64 (SMOD=0)

Mode A (9-bit UART)

Mode B (8-bit UART)

Baud rate generator is used for baud rate

generation; SMOD controls a divide-by-2 option

Baud rate = oscillator frequency /

32 x (baud rate gen. overflow rate)

Semiconductor Group

40

C517A

10-Bit A/D Converter

The C517A provides an A/D converter with the following features:

– 12 multiplexed input channels (port 7, 8), which can also be used as digital inputs

– 10-bit resolution

– Single or continuous conversion mode

– Internal or external start-of-conversion trigger capability

– Interrupt request generation after each conversion

– Using successive approximation conversion technique via a capacitor array

– Built-in hidden calibration of offset and linearity errors

The A/D converter operates with a successive approximation technique and uses self calibration

mechanisms for reduction and compensation of offset and linearity errors. The externally applied

reference voltage range has to be held on a fixed value within the specifications. The main

functional blocks of the A/D converter are shown in figure 20.

Semiconductor Group

41

C517A

internal

Bus

IEN1 (B8

)

H

EXEN2 SWDT

EX6

EX5

EX4

IEX4

P8.3

P7.3

MX3

ADM

EX3

IEX3

P8.2

P7.2

MX2

EX2

IEX2

P8.1

P7.1

MX1

EADC

IADC

P8.0

P7.0

MX0

IRCON0 (C0

EXF2

)

H

TF2

IEX6

_

IEX5

_

P8 (DD

_

)

H

_

P7 (DB

P7.7

)

P7.6

P7.5

_

P7.4

_

ADCON1 (DC

ADCL

)

H

_

ADCON0 (D8

)

H

BD

CLK

ADEX

BSY

ADDATH ADDATL

(D9 (DA

Single/

Continuous Mode

)

H

Port 7

Port 8

_

.2

_

MUX

.3

.4

.5

.6

.7

.8

S&H

A/D

Converter

Clock

Prescaler

÷8, ÷4

f_OSC/2

Conversion

Clock f_ADC

Input

LSB

.1

V

Clock f_IN

AREF

MSB

V

AGND

Start of

Conversion

P6.0/ADST

Write to ADDATL

internal

Bus

Shaded bit locations are not used in ADC-functions

MCB03332

Figure 20

A/D Converter Block Diagram

Semiconductor Group

42

C517A

Interrupt System

The C517A provides 17 interrupt sources with four priority levels. Ten interrupts can be generated

by the on-chip peripherals (timer 0, timer 1, timer 2, compare timer, compare match/set/clear, A/D

converter, and serial interface 0 and 1) and seven interrupts may be triggered externally (P3.2/INT0,

P3.3/INT1, P1.4/INT2, P1.0/INT3, P1.1/INT4, P1.2/INT5, P1.3/INT6).

This chapter shows the interrupt structure, the interrupt vectors and the interrupt related special

function registers. Figure 21 to 23 give a general overview of the interrupt sources and illustrate the

request and the control flags which are described in the next sections.

Semiconductor Group

43

C517A

Highest

Priority Level

P3.2/

INT0

IE0

0003

0083

0043

EX0

H

TCON.1

IT0

Lowest

Priority Level

IEN0.0

TCON.0

RI1

_

<

1

S1CON.0

UART 1

ES1

TI1

IEN2.0

S1CON.1

A/D Converter

IADC

EADC

IRCON0.0

IEN1.0

IP1.0

IP0.0

Timer 0

Overflow

TF0

000B

004B

ET0

H

TCON.5

IEN0.1

P1.4/

INT2/

CC4

IEX2

EX2

IRCON0.1

I2FR

T2CON.5

IEN1.1

EAL

IP1.1

IP0.1

MCS03333

IEN0.7

Bit addressable

Request Flag is

cleared by hardware

Figure 21

Interrupt Structure, Overview (Part 1)

Semiconductor Group

44

C517A

Highest

Priority Level

P3.3/

INT1

IE1

0013

0093

0053

EX1

H

TCON.3

IT1

Lowest

Priority Level

IEN0.2

TCON.2

Match in CM0-CM7

ICMP0-7

ECMP

IEN2.2

IRCON1.0-7

P1.0/

INT3/

CC0

IEX3

EX3

IRCON0.2

I3FR

IEN1.2

T2CON.5

IP1.2

IP0.2

Timer 1

Overflow

TF1

001B

009B

005B

ET1

H

TCON.7

IEN0.3

Compare Timer

Overflow

CTF

ECT

CTCON.3

IEN2.3

P1.1/

INT4/

CC1

IEX4

EX4

IRCON0.3

IEN1.3

EAL

IP1.3

IP0.3

IEN0.7

MCS03334

Bit addressable

Request Flag is

cleared by hardware

Figure 22

Interrupt Structure, Overview (Part 2)

Semiconductor Group

45

C517A

Highest

Priority Level

RI0

_

<

1

S0CON.0

USART 0

0023

00A3

0063

ES0

H

TI0

Lowest

Priority Level

IEN0.4

S0CON.1

Match in COMSET

ICS

ECS

CTCON.4

IEN2.4

P1.2/

INT5/

CC2

IEX5

EX5

IRCON0.4

IEN1.4

IP1.4

IP0.4

Timer 2

Overflow

TF2

_

<

1

IRCON0.6

002B

00AB

006B

P1.5/

T2EX

ET2

H

EXF2

IEN0.5

EXEN2

IEN1.7

IRCON0.7

ICR

Match in COMCLR

ECR

CTCON.5

IEN2.5

P1.3/

INT6/

CC3

IEX6

EX6

IRCON0.5

IEN1.5

EAL

IP1.5

IP0.5

MCS03335

IEN0.7

Bit addressable

Request Flag is

cleared by hardware

Figure 23

Interrupt Structure, Overview (Part 3)

Semiconductor Group

46

C517A

Table 11

Interrupt Source and Vectors

Interrupt Source

External Interrupt 0

Timer 0 Overflow

External Interrupt 1

Timer 1 Overflow

Serial Channel 0

Interrupt Vector Address

Interrupt Request Flags

0003

H

IE0

000B

H

TF0

0013

H

IE1

001B

H

TF1

0023

H

RI0 / TI0

TF2 / EXF2

IADC

Timer 2 Overflow / Ext. Reload

A/D Converter

002B

H

0043

H

External Interrupt 2

External Interrupt 3

External Interrupt 4

External Interrupt 5

External Interrupt 6

Serial Channel 1

004B

H

IEX2

0053

H

IEX3

005B

H

IEX4

0063

H

IEX5

006B

H

IEX6

0083

H

RI1 / TI1

ICMP0 - ICMP7

Compare Match Interupt of

Compare Registers CM0-CM7

assigned to Timer 2

0093

H

Compare Timer Overflow

009B

H

CTF

ICS

Compare Match Interupt of

Compare Register COMSET

00A3

H

Compare Match Interupt of

Compare Register COMCLR

00AB

H

ICR

Semiconductor Group

47

C517A

Fail Save Mechanisms

The C517A offers enhanced fail safe mechanisms, which allow an automatic recovery from

software upset or hardware failure :

– a programmable watchdog timer (WDT), with variable time-out period from 512 µs up to

approx. 1.1 s at 12 MHz. (256 µs up to approx. 0.65 s at 24 MHz)

– an oscillator watchdog (OWD) which monitors the on-chip oscillator and forces the

microcontroller into reset state in case the on-chip oscillator fails; it also provides the clock for

a fast internal reset after power-on.

The watchdog timer in the C517A is a 15-bit timer, which is incremented by a count rate of f_OSC/24

up to f_OSC/384. The system clock of the C517A is divided by two prescalers, a divide-by-two and a

divide-by-16 prescaler. For programming of the watchdog timer overflow rate, the upper 7 bit of the

watchdog timer can be written. Figure 24 shows the block diagram of the watchdog timer unit.

0

7

8

f

/12

OSC

2

16

WDTL

14

WDT Reset-Request

WDTH

IP0 (A9

)

H

WDTPSEL

-

WDTS

External HW Reset

External HW Power-Down

PE/SWD

7

6

0

WDTREL (86

)

H

Control Logic

-

IEN0 (A8 )

WDT

H

IEN1 (B8 )

SWDT

MCB03250

Figure 24

Block Diagram of the Watchdog Timer

The watchdog timer can be started by software (bit SWDT) or by hardware through pin PE/SWD,

but it cannot be stopped during active mode of the C517A. If the software fails to refresh the running

watchdog timer an internal reset will be initiated on watchdog timer overflow. For refreshing of the

watchdog timer the content of the SFR WDTREL is transfered to the upper 7-bit of the watchdog

timer. The refresh sequence consists of two consequtive instructions which set the bits WDT and

SWDT each. The reset cause (external reset or reset caused by the watchdog) can be examined

by software (flag WDTS). It must be noted, however, that the watchdog timer is halted during the

idle mode and power down mode of the processor.

Semiconductor Group

48

C517A

Oscillator Watchdog

The oscillator watchdog unit serves for four functions:

– Monitoring of the on-chip oscillator’s function

The watchdog supervises the on-chip oscillator's frequency; if it is lower than the frequency of

the auxiliary RC oscillator in the watchdog unit, the internal clock is supplied by the RC

oscillator and the device is brought into reset; if the failure condition disappears (i.e. the on-

chip oscillator has a higher frequency than the RC oscillator), the part executes a final reset

phase of typ. 1 ms in order to allow the oscillator to stabilize; then the oscillator watchdog reset

is released and the part starts program execution again.

– Fast internal reset after power-on

The oscillator watchdog unit provides a clock supply for the reset before the on-chip oscillator

has started. The oscillator watchdog unit also works identically to the monitoring function.

– Restart from the hardware power down mode.

If the hardware power down mode is terminated the oscillator watchdog has to control the

correct start-up of the on-chip oscillator and to restart the program. The oscillator watchdog

function is only part of the complete hardware power down sequence; however, the watchdog

works identically to the monitoring function.

RC

Oscillator

f _RC

f ₁

÷ 5

3MHz

f ₂< f ₁

Frequency

Comparator

Delay

_

Internal Reset

<

1

f ₂

XTAL1

XTAL2

IP0 (A9

)

H

On-Chip

Oscillator

OWDS

÷ 2

Internal Clock

MCB03337

Figure 25

Block Diagram of the Oscillator Watchdog

Semiconductor Group

49

C517A

Power Saving Modes

The C517A provides two basic power saving modes, the idle mode and the power down mode.

Additionally, a slow down mode is available. This power saving mode reduces the internal clock

rate in normal operating mode and it can be also used for further power reduction in idle mode.

– Idle mode

The CPU is gated off from the oscillator. All peripherals are still provided with the clock and

are able to work. Idle mode is entered by software and can be left by an interrupt or reset.

– Slow down mode

The controller keeps up the full operating functionality, but its normal clock frequency is

internally divided by 8. This slows down all parts of the controller, the CPU and all peripherals,

to 1/8th of their normal operating frequency and also reduces power consumption.

– Software power down mode

The operation of the C517A is completely stopped and the oscillator is turned off. This mode

is used to save the contents of the internal RAM with a very low standby current. This power

down mode is entered by software and can be left by reset.

– Hardware Power down mode

If pin HWPD gets active (low level) the part enters the hardware power down mode and starts

a complete internal reset sequence. Thereafter, both oscillators of the chip are stopped and

the port pins and several control lines enter a floating state.

In the power down mode of operation, V_DDcan be reduced to minimize power consumption. It must

be ensured, however, that V_DDis not reduced before the power down mode is invoked, and that V_DD

is restored to its normal operating level, before the power down mode is terminated. Table 12 gives

a general overview of the entry and exit procedures of the power saving modes.

Semiconductor Group

50

C517A

Table 12

Power Saving Modes Overview

Mode

Entering

Leaving by

Remarks

2-Instruction

Example

Idle mode

ORL PCON, #01H Ocurrence of an

ORL PCON, #20H interrupt from a

peripheral unit

CPU clock is stopped;

CPU maintains their data;

peripheral units are active (if

enabled) and provided with

clock

Hardware Reset

Slow Down Mode

In normal mode :

ORL PCON,#10H

ANL PCON,#0EFH

or

Internal clock rate is reduced

to 1/8 of its nominal frequency

Hardware Reset

With idle mode :

ORL PCON,#01H

ORL PCON, #30H peripheral unit

Ocurrence of an

interrupt from a

CPU clock is stopped;

CPU maintains their data;

peripheral units are active (if

enabled) and provided with 1/8

of its nominal frequency

Hardware reset

Software

ORL PCON, #02H Hardware Reset

Oscillator is stopped;

Power Down Mode ORL PCON, #40H

contents of on-chip RAM and

SFR’s are maintained;

Rising edge at

PE/SWD

Hardware

Power Down Mode

HWPD = 0

HWPD = 1

Oscillator is stopped; internal

reset is executed;

Semiconductor Group

51

C517A

Absolute Maximum Ratings

Parameter

Symbol

Limit Values

max.

Unit Notes

min.

– 65

–0.5

Storage temperature

T_ST

150

°C

V

–

Voltage on V_DDpins with respect V_DD

to ground (V_SS)

6.5

Voltage on any pin with respect V_IN

to ground (V_SS)

–0.5

–10

–

V

–

V

_DD+ 0.5

Input current on any pin during

overload condition

mA

10

Absolute sum of all input

currents during overload

condition

| 100 |

Power dissipation

–

TBD

W

–

P_DISS

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent

damage of the device. This is a stress rating only and functional operation of the device at

these or any other conditions above those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for longer

periods may affect device reliability. During absolute maximum rating overload conditions

(V_IN> V_DDor V_IN< V_SS) the voltage on V_DDpins with respect to ground (V_SS) must not exceed

the values defined by the absolute maximum ratings.

Operating Conditions

Parameter

Symbol

Limit Values

Unit Notes

min.

max.

5.5

Supply voltage

Ground voltage

V_DD

V_SS

4.25

V

–

0

Ambient temperature

SAB-C517A

0

–40

70

85

110

°C

18 and 24 MHz

18 MHz

T_A

SAF-C517A

SAH-C517A

Analog reference voltage

Analog ground voltage

Analog input voltage

CPU clock

4

V

_DD+ 0.1

V

–

V_AREF

V_AGND

V_AIN

V_SS- 0.1

V_AGND

3.5

V_SS+ 0.2

V_AREF

24

MHz –

f_CPU

Semiconductor Group

52

C517A

DC Characteristics

(Operating Conditions apply)

Parameter

Symbol

Limit Values

max.

Unit Test Condition

min.

Input low voltage

Pins except EA,RESET,HWPD V_IL

– 0.5

0.2 V_DD– 0.1 V

0.2 V_DD– 0.3 V

0.2 V_DD+ 0.1 V

–

EA pin

V_IL1

V_IL2

HWPD and RESET pins

Input high voltage

pins except RESET, XTAL2 and

HWPD

XTAL2 pin

RESET and HWPD pin

V_IH

V_IH1

V_IH2

0.2 V_DD+ 0.9 V_DD+ 0.5

V

–

0.7 V_DD

0.6 V_DD

V

_DD+ 0.5

Output low voltage

Ports 1, 2, 3, 4, 5, 6

Port 0, ALE, PSEN, RO

V_OL

V_OL1

–

0.45

V

I _OL= 1.6 mA ¹⁾

I _OL= 3.2 mA ¹⁾

Output high voltage

Ports 1, 2, 3, 4, 5, 6

V_OH

2.4

0.9 V_DD

2.4

–

V

I_OH= – 80 µA

I_OH= – 10 µA

I_OH= – 800 µA²⁾

I_OH= – 80 µA ²⁾

Port 0 in external bus mode,

ALE, PSEN, RO

V_OH1

0.9 V_DD

Logic 0 input current

Ports 1, 2, 3, 4, 5, 6

I _LI

I _TL

I _LI

– 10

– 65

–

– 70

– 650

± 1

µA

V_{I N}= 2 V

Logical 0-to-1 transition current,

Ports 1, 2, 3, 4, 5, 6

V_{I N}= 2 V

Input leakage current

Port 0, 7 and 8, EA, HWPD

0.45 < V_{I N}< V_DD

Input low current

to RESET for reset

XTAL2

I _IL2

I _IL3

I _IL4

– 10

–

– 100

– 15

– 20

µA

V_IN= 0.45 V

V_{I N}= 0.45 V

PE/SWD, OWE

Pin capacitance

C _IO

–

10

pF

f_C= 1 MHz,

T_A= 25°C

7) 8)

Overload current

Notes see next page

I_OV

± 5

mA

Semiconductor Group

53

C517A

Power Supply Current

Parameter

Symbol

Limit Values

typ. ⁹⁾max. ¹⁰⁾

Unit Test Condition

4)

5)

6)

Active mode

Idle mode

18 MHz

24 MHz

I_DD

21.3

27.3

29.2

37.6

mA

18 MHz

24 MHz

I_DD

11.6

14.6

16.2

20.4

mA

Active mode with

18 MHz

24 MHz

I_DD

9.5

10.7

13.1

14.9

mA

slow-down enabled

Power-down mode

I_PD

15

50

µA

V

_DD= 2…5.5 V ³⁾

Notes:

1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the V_OLof ALE

and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these

pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise

pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger,

or use an address latch with a schmitt-trigger strobe input.

2) Capacitive loading on ports 0 and 2 may cause the V_OHon ALE and PSEN to momentarily fall below the 0.9 V_DD

specification when the address lines are stabilizing.

3) I_PD(power-down mode) is measured under following conditions:

EA = RESET = Port 0 = Port 7 = Port 8 = V_DD; XTAL1 = N.C.; XTAL2 = V_SS; PE/SWD = OWE = V_SS

HWPD = V_DDfor software power-down mode; V_AGND= V_SS; V_AREF= V_DD; all other pins are disconnected.

;

I

_PD(hardware power-down mode) is independent of any particular pin connection.

4) I_DD(active mode) is measured with:

XTAL2 driven with t_CLCH, t_CHCL= 5 ns , V_IL= V_SS+ 0.5 V, V_IH= V_DD– 0.5 V; XTAL1 = N.C.;

EA = PE/SWD == V_SS; Port 0 = Port 7 = Port 8 = V_DD; HWPD = V_DD; RESET = V_DD; all other pins are

disconnected.

5) I_DD(idle mode) is measured with all output pins disconnected and with all peripherals disabled;

XTAL2 driven with t_CLCH, t_CHCL= 5 ns, V_IL= V_SS+ 0.5 V, V_IH= V_DD– 0.5 V; XTAL1 = N.C.;

RESET = V_DD; HWPD = Port 0 = Port 7 = Port 8 = V_DD; EA = PE/SWD = V_SS

;

all other pins are disconnected;

6) I_DD(active mode with slow-down mode) is measured with all output pins disconnected and with all peripherals

disabled; XTAL2 driven with t_CLCH, t_CHCL= 5 ns , V_IL= V_SS+ 0.5 V, V_IH= V_DD– 0.5 V; XTAL1 = N.C.;

HWPD = V_DD; RESET = V_DD; Port 7 = Port 8 = V_DD;; EA = PE/SWD == V_SS; all other pins are disconnected.

7) Overload conditions under operating conditions occur if the voltage on the respective pin exceeds the specified

operating range (i.e. V_OV> V_DD+ 0.5 V or V_OV< V_SS- 0.5 V). The absolute sum of input currents on all port

pins may not exceed 50 mA. The supply voltage V_DDand V_SSmust remain within the specified limits.

8) Not 100% tested, guaranteed by design characterization

9) The typical I_DDvalues are periodically measured at T_A= +25 °C and V_DD= 5 V but not 100% tested.

10)The maximum I_DDvalues are measured under worst case conditions (T_A= 0 °C or -40 °C and V_DD= 5.5 V)

Semiconductor Group

54

C517A

MCD03338

40

I

Ι

DD

CC max

I

Ι

mA

DD

CC typ

I

Ι

DD

CC

30

20

10

0

Active + Slow Down Mode

0

3.5

8

12

16

20

MHz

24

f_OSC

Figure 26

IDD Diagram

Table 13

Power Supply Current Calculation Formulas

Parameter

Symbol

Formula

1 f_OSC+ 3.3

Active mode

I_{DD typ}

*

I_{DD max}

1.4 f_OSC+ 4.0

*

Idle mode

I_{DD typ}

0.5 f_OSC+ 2.6

*

I_{DD max}

0.7 f_OSC+ 3.6

*

Active mode with

I_{DD typ}

0.25 f_OSC+ 4.95

*

slow-down enabled

I_{DD max}

0.3 f_OSC+ 7.7

*

Note : f_oscis the oscillator frequency in MHz. I_DDvalues are given in mA.

Semiconductor Group

55

C517A

A/D Converter Characteristics

(Operating Conditions apply)

Parameter

Symbol

Limit Values

Unit Test Condition

min.

max.

1)

Analog input voltage

Sample time

V_AIN

t_S

V_AGND

V_AREF

V

–

16 x t_IN

8 x t_IN

ns

Prescaler ÷ 8

Prescaler ÷ 4

2)

3)

Conversion cycle time

Total unadjusted error

t_ADCC

–

96 x t_IN

48 x t_IN

ns

Prescaler ÷ 8

Prescaler ÷ 4

T_UE

–

± 2

LSB V_SS+0.5V ≤ V_IN≤ V_DD-0.5V ⁴⁾

5) 6)

t_ADCin [ns]

Internal resistance of

R_AREF

t_ADC/ 250 kΩ

reference voltage source

- 0.25

2) 6)

t_Sin [ns]

Internal resistance of

analog source

R_ASRC

C_AIN

–

t_S/ 500

- 0.25

kΩ

6)

ADC input capacitance

50

pF

Notes see next page.

Clock calculation table :

ClockPrescaler ADCL

Ratio

t

ADC

S

ADCC

÷ 8

÷ 4

1

0

8 x t

4 x t

16 x t

8 x t

96 x t

48 x t

IN

Further timing conditions : t

t

min = 500 ns

ADC

IN

= 2 / f

= 2 t

OSC

CLCL

Semiconductor Group

56

C517A

Notes:

1) V

may exeed V

or V up to the absolute maximum ratings. However, the conversion result in

AREF

AIN

AGND

these cases will be X000 or X3FF , respectively.

H

2) During the sample time the input capacitance C

can be charged/discharged by the external source. The

AIN

internal resistance of the analog source must allow the capacitance to reach their final voltage level within t .

After the end of the sample time t , changes of the analog input voltage have no effect on the conversion result.

S

3) This parameter includes the sample time t , the time for determining the digital result and the time for the

S

calibration. Values for the conversion clock t

the previous page.

depend on programming and can be taken from the table on

ADC

4) T

is tested at V

= 5.0 V, V

= 0 V, V

= 4.9 V. It is guaranteed by design characterization for all

DD

UE

AREF

AGND

other voltages within the defined voltage range.

If an overload condition occurs on maximum 2 not selected analog input pins and the absolute sum of input

overload currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB

is permissible.

5) During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal

resistance of the reference source must allow the capacitance to reach their final voltage level within the

indicated time. The maximum internal resistance results from the programmed conversion timing.

6) Not 100% tested, but guaranteed by design characterization.

Semiconductor Group

57

C517A

AC Characteristics (18 MHz)

(Operating Conditions apply)

(C_Lfor port 0, ALE and PSEN outputs = 100 pF; C_Lfor all other outputs = 80 pF)

Program Memory Characteristics

Parameter

Symbol

Limit Values

Variable Clock

1/t_CLCL= 3.5 MHz to 18 MHz

Unit

18 MHz

Clock

min. max. min.

max.

ALE pulse width

t_LHLL

t_AVLL

t_LLAX

t_LLIV

71

26

–

2 t_CLCL– 40

–

ns

Address setup to ALE

Address hold after ALE

ALE low to valid instruction in

ALE to PSEN

–

t

_CLCL– 30

–

122

–

4 t_CLCL– 100 ns

t_LLPL

t_PLPH

t_PLIV

31

132

–

t

_CLCL– 25

–

ns

PSEN pulse width

–

3 t_CLCL– 35

–

PSEN to valid instruction in

92

–

0

–

3 t_CLCL– 75

Input instruction hold after PSEN t_PXIX

0

–

*)

Input instruction float after PSEN t_PXIZ

–

46

–

t_CLCL– 10

*)

Address valid after PSEN

Address to valid instr in

Address float to PSEN

t_PXAV

t_AVIV

t_AZPL

48

–

t

_CLCL– 8

–

180

–

0

5 t_CLCL– 98

0

–

*)

Interfacing the C517A to devices with float times up to 45 ns is permissible. This limited bus contention will not

cause any damage to port 0 drivers.

CLKOUT Characteristics

Parameter

Symbol

Limit Values

Variable Clock

1/t_CLCL= 3.5 MHz to 18 MHz

Unit

18 MHz

Clock

min. max. min.

max.

ALE to CLKOUT

t_LLSH

t_SHSL

t_SLSH

t_SLLH

349

71

–

7 t_CLCL– 40

2 t_CLCL– 40

10 t_CLCL– 40

–

ns

CLKOUT high time

CLKOUT low time

CLKOUT low to ALE high

–

516

16

–

96

t

_CLCL– 40

t_CLCL+ 40

Semiconductor Group

58

C517A

AC Characteristics (18 MHz, cont’d)

External Data Memory Characteristics

Parameter

Symbol

Limit Values

Variable Clock

1/t_CLCL= 3.5 MHz to 18 MHz

Unit

18 MHz

Clock

min. max. min.

max.

RD pulse width

t_RLRH

t_WLWH

t_LLAX2

t_RLDV

t_RHDX

t_RHDZ

t_LLDV

233

81

–

6 t_CLCL– 100

–

ns

WR pulse width

–

6 t_CLCL– 100

Address hold after ALE

RD to valid data in

–

2 t_CLCL– 30

128

–

5 t_CLCL– 150 ns

Data hold after RD

0

–

ns

Data float after RD

–

51

294

335

217

–

2 t_CLCL– 60

ALE to valid data in

Address to valid data in

ALE to WR or RD

–

8 t_CLCL– 150 ns

9 t_CLCL– 165 ns

t_AVDV

t_LLWL

t_AVWL

t_WHLH

t_QVWX

t_QVWH

t_WHQX

t_RLAZ

–

117

92

16

11

239

16

–

3 t_CLCL– 50

4 t_CLCL– 130

3 t_CLCL+ 50

ns

Address valid to WR or RD

WR or RD high to ALE high

Data valid to WR transition

Data setup before WR

Data hold after WR

Address float after RD

–

96

–

t

_CLCL– 40

_CLCL– 45

t_CLCL+ 40

–

0

–

7 t_CLCL– 150

_CLCL– 40

–

t

0

–

External Clock Drive Characteristics

Parameter

Symbol

Limit Values

Variable Clock

Unit

Freq. = 3.5 MHz to 18 MHz

min.

55.6

15

–

max.

Oscillator period

High time

t_CLCL

t_CHCX

t_CLCX

t_CLCH

t_CHCL

285.7

ns

t

_CLCL– t_CLCX

_CLCL– t_CHCX

Low time

Rise time

15

Fall time

–

Semiconductor Group

59

C517A

AC Characteristics (24 MHz)

(Operating Conditions apply)

(C_Lfor port 0, ALE and PSEN outputs = 100 pF; C_Lfor all other outputs = 80 pF)

Program Memory Characteristics

Parameter

Symbol

Limit Values

Variable Clock

1/t_CLCL= 3.5 MHz to 24 MHz

Unit

24 MHz

Clock

min. max. min.

max.

ALE pulse width

t_LHLL

t_AVLL

t_LLAX

t_LLIV

43

17

–

2 t_CLCL– 40

–

ns

Address setup to ALE

Address hold after ALE

ALE low to valid instruction in

ALE to PSEN

–

t

_CLCL– 25

–

80

–

4 t_CLCL– 87

t_LLPL

t_PLPH

t_PLIV

22

95

–

t

_CLCL– 20

–

PSEN pulse width

–

3t_CLCL– 30

–

PSEN to valid instruction in

60

–

0

–

3 t_CLCL– 65

Input instruction hold after PSEN t_PXIX

0

–

*)

Input instruction float after PSEN t_PXIZ

–

32

–

t_CLCL– 10

*)

Address valid after PSEN

Address to valid instr in

Address float to PSEN

t_PXAV

t_AVIV

t_AZPL

37

–

t

_CLCL– 5

–

148

–

0

5 t_CLCL– 60

0

–

*)

Interfacing the C517A to devices with float times up to 37 ns is permissible. This limited bus contention will not

cause any damage to port 0 drivers.

CLKOUT Characteristics

Parameter

Symbol

Limit Values

Variable Clock

1/t_CLCL= 3.5 MHz to 24 MHz

Unit

24 MHz

Clock

min. max. min.

max.

ALE to CLKOUT

t_LLSH

t_SHSL

t_SLSH

t_SLLH

252

43

–

7 t_CLCL– 40

2 t_CLCL– 40

10 t_CLCL– 40

–

ns

CLKOUT high time

CLKOUT low time

CLKOUT low to ALE high

–

377

2

–

82

t

_CLCL– 40

t_CLCL+ 40

Semiconductor Group

60

C517A

AC Characteristics (24 MHz, cont’d)

External Data Memory Characteristics

Parameter

Symbol

Limit Values

Variable Clock

1/t_CLCL= 3.5 MHz to 24 MHz

Unit

24 MHz

Clock

min. max. min.

max.

RD pulse width

t_RLRH

t_WLWH

t_LLAX2

t_RLDV

t_RHDX

t_RHDZ

t_LLDV

180

53

–

6 t_CLCL– 70

–

ns

WR pulse width

–

6 t_CLCL– 70

–

Address hold after ALE

RD to valid data in

–

2 t_CLCL– 30

–

118

–

5 t_CLCL– 90

–

Data hold after RD

0

Data float after RD

–

63

200

220

175

–

2 t_CLCL– 20

ALE to valid data in

Address to valid data in

ALE to WR or RD

–

8 t_CLCL– 133 ns

9 t_CLCL– 155 ns

t_AVDV

t_LLWL

t_AVWL

t_WHLH

t_QVWX

t_QVWH

t_WHQX

t_RLAZ

–

75

67

17

5

3 t_CLCL– 50

4 t_CLCL– 97

3 t_CLCL+ 50

ns

Address valid to WR or RD

WR or RD high to ALE high

Data valid to WR transition

Data setup before WR

Data hold after WR

Address float after RD

–

67

–

t

_CLCL– 25

_CLCL– 37

t_CLCL+ 25

–

0

170

15

–

7 t_CLCL– 122

_CLCL– 27

–

t

0

–

External Clock Drive Characteristics

Parameter

Symbol

Limit Values

Variable Clock

Unit

Freq. = 3.5 MHz to 24 MHz

min.

41.7

12

–

max.

Oscillator period

High time

t_CLCL

t_CHCX

t_CLCX

t_CLCH

t_CHCL

285.7

ns

t

_CLCL– t_CLCX

_CLCL– t_CHCX

Low time

Rise time

12

Fall time

–

Semiconductor Group

61

C517A

t _LHLL

ALE

PSEN

Port 0

t _AVLL

t _PLPH

t _LLPL

t

LLIV

t

PLIV

t _AZPL

t _LLAX

t

PXAV

PXIZ

t

t _PXIX

A0 - A7

Instr.IN

A0 - A7

t

AVIV

Port 2

A8 - A15

MCT00096

Figure 27

Program Memory Read Cycle

Semiconductor Group

62

C517A

t_WHLH

ALE

PSEN

RD

t _LLDV

t _LLWL

t _RLRH

t _RLDV

t _AVLL

t_RHDZ

t _LLAX2

t _RLAZ

t_RHDX

A0 - A7 from

Ri or DPL

A0 - A7

from PCL

Instr.

IN

Port 0

Data IN

t_AVWL

t _AVDV

Port 2

P2.0 - P2.7 or A8 - A15 from DPH

A8 - A15 from PCH

MCT00097

Figure 28

Data Memory Read Cycle

Figure 29

CLKOUT Timing

Semiconductor Group

63

C517A

t_WHLH

ALE

PSEN

WR

t _LLWL

t _WLWH

t_QVWX

t _AVLL

t_WHQX

t _LLAX2

t_QVWH

A0 - A7 from

Ri or DPL

A0 - A7

from PCL

Instr.IN

Port 0

Port 2

Data OUT

t_AVWL

P2.0 - P2.7 or A8 - A15 from DPH

A8 - A15 from PCH

MCT00098

Figure 30

Data Memory Write Cycle

t_CLCL

V

- 0.5V

DD

CC

0.7 V_CC

0.2 V_CC- 0.1

0.45V

t_CLCX

t_CHCX

MCT00033

t_CHCL

t_CLCH

Figure 31

External Clock Drive on XTAL2

Semiconductor Group

64

C517A

ROM Verification Characteristics for the C517A-4RM/4RN

ROM Verification Mode 1

Parameter

Symbol

Limit Values

max.

Unit

min.

t_AVQV

Address to valid data

–

10 t_CLCL

ns

P1.0-P1.7

P2.0-P2.6

Address

Data Out

New Address

t

AVQV

Port 0

New Data Out

Data:

Addresses:

P0.0-P0.7 = D0-D7

P1.0-P1.7 = A0-A7

P2.0-P2.6 = A8-A14

Inputs:

PSEN

ALE, EA = V

RESET = V

= V

SS

IH

IL2

MCS03253

Figure 32

ROM Verification Mode 1

Semiconductor Group

65

C517A

ROM Verification Mode 2

Parameter

Symbol

Limit Values

Unit

min.

typ

2 t_CLCL

12 t_CLCL

–

max.

t_AWD

t_ACY

ALE pulse width

–

ns

ALE period

–

ns

t_DVA

Data valid after ALE

Data stable after ALE

P3.5 setup to ALE low

Oscillator frequency

–

4 t_CLCL

ns

t_DSA

8 t_CLCL

–

ns

t_AS

t_CLCL

–

ns

1/ t_CLCL

3.5

–

24

MHz

t _ACY

t _AWD

ALE

t _DSA

t _DVA

Port 0

P3.5

Data Valid

t _AS

MCT02613

Figure 33

ROM Verification Mode 2

Semiconductor Group

66

C517A

0.2 V_CC+0.9

0.2 V_CC-0.1

V_DD

Test Points

V

DD

0.45 V

MCT00039

V

DD

AC Inputs during testing are driven at V_DD- 0.5 V for a logic ’1’ and 0.45 V for a logic ’0’.

Timing measurements are made at V_IHminfor a logic ’1’ and V_ILmaxfor a logic ’0’.

Figure 34

AC Testing: Input, Output Waveforms

Timing Reference

Points

V_Load

-0.1 V

V_Load

V_OL+0.1 V

MCT00038

For timing purposes a port pin is no longer floating when a 100 mV change from load voltage

occurs and begins to float when a 100 mV change from the loaded V_OH/V_OLlevel occurs.

I_OL/I_OH≥ ± 20 mA

Figure 35

AC Testing : Float Waveforms

Crystal Oscillator Mode

Driving from External Source

C

N.C.

XTAL1

XTAL2

3.5-24 MHz

C

External Oscillator

Signal

XTAL2

±

Crystal Mode : C = 20 pF 10 pF

(incl. stray capacitance)

MCS03339

Figure 36

Recommended Oscillator Circuits for Crystal Oscillator

Semiconductor Group

67

C517A

Plastic Package, P-MQFP-100-2 (SMD)

(Plastic Metric Quad Flat Package)

Figure 37

P-LCC-100-2 Package Outlines

Semiconductor Group

68

C517A

Plastic Package, P-LCC-84-2 (SMD)

(Plastic Leaded Chip-Carrier)

1.27 x 45˚

1.27

2)

±0.5

28.2

±0.1

0.43

0.1

M

0.18

84x

25.4

Index Marking

84

1

1.14 x 45˚

1)

±0.076

±0.13

29.31

30.23

1) Does not include plastic or metal protrusions of 0.25 max. per side

2) Dimension from center to center

Figure 38

P-LCC-84-2 Package Outline

Sorts of Packing

Package outlines for tubes, trays etc. are contained in our

Data Book “Package Information”

Dimensions in mm

SMD = Surface Mounted Device

Semiconductor Group

69

C517A

Semiconductor Group

70


型号：	C517
厂家：	Infineon
描述：	8-bit CMOS MICROCONTROLLER 8位CMOS微控制器微控制器
文件：	总72页 (文件大小：803K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

C517 [INFINEON]

相关型号：

C517-3A

C5174G

C5174K

C5174V

C5175G

C5175K

C5175V

C5176G

C5176K

C5176V

C5177G

C5177GJ