6ED003L02-F2 [INFINEON]
Half Bridge Based MOSFET Driver, CMOS, PDSO28, GREEN, PLASTIC, TSSOP-28;
| 型号： | 6ED003L02-F2 |
| 厂家： | 
Infineon |
| 描述： | Half Bridge Based MOSFET Driver, CMOS, PDSO28, GREEN, PLASTIC, TSSOP-28 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总21页 (文件大小：1193K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EiceDRIVER™
High voltage gate driver IC
6ED family - 2nd generation
3 phase 600 V gate drive IC
6ED003L06-F2
6ED003L02-F2
EiceDRIVER™
datasheet
<Revision 2.5>, 21.01.2013
Industrial Power & Control
Edition 21.01.2013
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2013 Infineon Technologies AG
All Rights Reserved.
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For further information on technology, delivery terms and conditions and prices, please contact the nearest
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persons may be endangered.
EiceDRIVER(TM)
6ED003L06-F2, 6ED003L02-F2
Revision History
Page or Item
Subjects (major changes since previous revision)
<Revision 2.5>, 21.01.2013
p. 8
revised Figure 1
p. 20
revised Figure 8
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TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company
Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas Instruments
Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex
Limited.
Last Trademarks Update 2010-10-26
datasheet
3
<Revision 2.5>, 21.01.2013
EiceDRIVER(TM)
6ED003L06-F2, 6ED003L02-F2
Table of Contents
1
Overview .............................................................................................................................................7
2
Blockdiagram......................................................................................................................................8
3
Pin configuration, description, and functionality ...........................................................................9
Low Side and High Side Control Pins (Pin 2, 3, 4, 5, 6, 7) ..................................................................9
EN (Gate Driver Enable, Pin 10)........................................................................................................10
FAULT (Fault Feedback, Pin 8) .........................................................................................................10
ITRIP and RCIN (Over-Current Detection Function, Pin 9, 11) .........................................................11
VCC, VSS and COM (Low Side Supply, Pin 1, 12,13) ......................................................................11
VB1,2,3 and VS1,2,3 (High Side Supplies, Pin 18, 20, 22, 24, 26, 28) .............................................11
LO1,2,3 and HO1,2,3 (Low and High Side Outputs, Pin 14, 15, 16, 19, 23, 27) ...............................11
3.1
3.2
3.3
3.4
3.5
3.6
3.7
4
Electrical Parameters.......................................................................................................................12
Absolute Maximum Ratings ...............................................................................................................12
Required operation conditions ...........................................................................................................13
Operating Range................................................................................................................................13
Static logic function table ...................................................................................................................14
Static parameters ...............................................................................................................................14
Dynamic parameters..........................................................................................................................16
4.1
4.2
4.3
4.4
4.5
4.6
5
Timing diagrams...............................................................................................................................17
6
6.1
6.2
Package.............................................................................................................................................19
PG-DSO-28........................................................................................................................................19
PG-TSSOP-28....................................................................................................................................20
datasheet
4
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EiceDRIVER(TM)
6ED003L06-F2, 6ED003L02-F2
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Typical Application ...............................................................................................................................8
Block diagram for 6ED003L06-F2 / 6ED003L02-F2 ............................................................................8
Pin Configuration of 6ED003L06-F2 and 6ED003L02-F2 ...................................................................9
Input pin structure...............................................................................................................................10
Input filter timing diagram...................................................................................................................10
EN pin structures................................................................................................................................10
FAULT pin structures .........................................................................................................................11
Timing of short pulse suppression .....................................................................................................17
Timing of internal deadtime................................................................................................................17
Figure 10 Enable delay time definition ...............................................................................................................17
Figure 11 Input to output propagation delay times and switching times definition.............................................18
Figure 12 Operating areas..................................................................................................................................18
Figure 13 ITRIP-Timing ......................................................................................................................................18
Figure 14 Package drawing................................................................................................................................19
Figure 15 PCB reference layout .........................................................................................................................19
Figure 16 Package drawing................................................................................................................................20
Figure 17 PCB reference layout (according to JEDEC 1s0P) left: Reference layout right: detail of footprint20
datasheet
5
<Revision 2.5>, 21.01.2013
EiceDRIVER(TM)
6ED003L06-F2, 6ED003L02-F2
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Members of 6ED family – 2nd generation .............................................................................................7
Pin Description .....................................................................................................................................9
Abs. maximum ratings........................................................................................................................12
Required Operation Conditions..........................................................................................................13
Operating range .................................................................................................................................13
Static parameters ...............................................................................................................................14
Dynamic parameters..........................................................................................................................16
Data of reference layout.....................................................................................................................20
datasheet
6
<Revision 2.5>, 21.01.2013
EiceDRIVER(TM)
6ED003L06-F2, 6ED003L02-F2
EiceDRIVER™
3 phase 600 V gate drive IC
1
Overview
Main features
Thin-film-SOI-technology
PG-DSO28
Maximum blocking voltage +600V
Separate control circuits for all six drivers
CMOS and LSTTL compatible input (negative logic)
Signal interlocking of every phase to prevent cross-conduction
Detection of over current and under voltage supply
externally programmable delay for fault clear after over current
detection
PG-TSSOP28
Product highlights
Insensitivity of the bridge output to negative transient voltages up to -50V given by SOI-technology
'shut down' of all switches during error conditions
Typical applications
Home appliances
Fans, pumps
General purpose drives
Product family
Table 1
Members of 6ED family – 2nd generation
high side control input typ. UVLO-
HIN1,2,3 and LIN1,2,3 Thresholds
Sales Name
Bootstrap Package
diode
6ED003L06-F2 / 6ED003L02-F2 negative logic
11.7 V / 9.8 V No
DSO28 / TSSOP28
Description
The devices are full bridge drivers to control power devices like MOS-transistors or IGBTs in 3-phase systems
with a maximum blocking voltage of +600 V. Based on the used SOI-technology there is an excellent
ruggedness on transient voltages. No parasitic thyristor structures are present in the device. Hence, no parasitic
latch-up may occur at all temperatures and voltage conditions.
The six independent drivers are controlled at the low-side using CMOS resp. LSTTL compatible signals, down
to 3.3 V logic. The device includes an under-voltage detection unit with hysteresis characteristic and an over-
current detection. The over-current level is adjusted by choosing the resistor value and the threshold level at pin
ITRIP. Both error conditions (under-voltage and over-current) lead to a definite shut down of all six switches. An
error signal is provided at the FAULT open drain output pin. The blocking time after over-current can be
adjusted with an RC-network at pin RCIN. The input RCIN owns an internal current source of 2.8 µA. Therefore,
the resistor RRCIN is optional. The typical output current can be given with 165 mA for pull-up and 375 mA for pull
down. Because of system safety reasons a 310 ns interlocking time has been realised. The function of input EN
can optionally be extended with an over-temperature detection, using an external NTC-resistor (see Fig.1).
datasheet
7
<Revision 2.5>, 21.01.2013
EiceDRIVER(TM)
6ED003L06-F2, 6ED003L02-F2
DC-Bus
VCC
HIN1,2,3
LIN1,2,3
EN
VCC
VB1,2,3
HO1,2,3
HIN1,2,3
LIN1,2,3
EN
To Load
VS1,2,3
5V
FAULT
RCIN
FAULT
LO1,2,3
COM
RRCIN
CRCIN
ITRIP
VSS
RSh
VSS
Figure 1
Typical Application
2
Blockdiagram
BIAS NETWORK / VDD2
VB
INPUT NOISE
FILTER
BIAS NETWORK - VB1
HIN1
LIN1
DEADTIME &
SHOOT-THROUGH
PREVENTION
LATCH
Gate-
Drive
HV LEVEL-SHIFTER
+ REVERSE-DIODE
COMPAR
ATOR
z
HO
VS
UV-
DETECT
INPUT NOISE
FILTER
VB
INPUT NOISE
FILTER
BIAS NETWORK - VB2
HIN2
LIN2
HIN3
LIN3
EN
DEADTIME &
SHOOT-THROUGH
PREVENTION
LATCH
Gate-
Drive
HV LEVEL-SHIFTER
+ REVERSE-DIODE
COMPAR
ATOR
HO
VS
UV-
DETECT
INPUT NOISE
FILTER
INPUT NOISE
FILTER
VB
HO
VS
BIAS NETWORK / VB3
DEADTIME &
SHOOT-THROUGH
PREVENTION
LATCH
Gate-
Drive
HV LEVEL-SHIFTER
+ REVERSE-DIODE
COMPAR
ATOR
UV-
DETECT
INPUT NOISE
FILTER
>1
INPUT NOISE
FILTER
VC
LO
UV-
DETECT
VSS / COM
LEVEL-
SHIFTER
Gate-
Drive
DELAY
INPUT NOISE
FILTER
ITRIP
VSS / COM
LEVEL-
SHIFTER
Gate-
Drive
DELAY
DELAY
LO
S
Q
VDD2
SET
DOMINANT
LATCH
R
IRCIN
VSS / COM
LEVEL-
SHIFTER
Gate-
Drive
LO
RCIN
CO
FAULT
VS
>1
Figure 2
Block diagram for 6ED003L06-F2 / 6ED003L02-F2
datasheet
8
<Revision 2.5>, 21.01.2013
EiceDRIVER(TM)
6ED003L06-F2, 6ED003L02-F2
Pin configuration, description, and functionality
1
2
3
4
5
6
7
8
9
VCC
VB1 28
HO1 27
VS1 26
HIN1
HIN2
HIN3
LIN1
nc
25
VB2 24
HO2 23
VS2 22
LIN2
LIN3
nc
FAULT
ITRIP
21
VB3 20
HO3 19
VS3 18
10 EN
11 RCIN
12 VSS
13 COM
14 LO3
17
nc
LO1 16
LO2 15
Figure 3
Pin Configuration of 6ED003L06-F2 and 6ED003L02-F2
Table 2
Symbol
VCC
Pin Description
Description
Low side power supply
Logic ground
VSS
/HIN1,2,3
/LIN1,2,3
/FAULT
EN
High side logic input
Low side logic input
Indicates over-current and under-voltage (negative logic, open-drain output)
Enable I/O functionality (positive logic)
ITRIP
Analog input for over-current shut down, activates FAULT and RCIN to VSS
External RC-network to define FAULT clear delay after FAULT-Signal (TFLTCLR
Low side gate driver reference
RCIN
)
COM
VB1,2,3
HO1,2,3
VS1,2,3
LO1,2,3
nc
High side positive power supply
High side gate driver output
High side negative power supply
Low side gate driver output
Not connected
2.1
Low Side and High Side Control Pins (Pin 2, 3, 4, 5, 6, 7)
The Schmitt trigger input threshold of them are such to guarantee LSTTL and CMOS compatibility down to 3.3 V
controller outputs. Input Schmitt trigger and noise filter provide beneficial noise rejection to short input pulses
according to Figure 4 and Figure 5.
Vcc
Schmitt-Trigger
INPUT NOISE
FILTER
HINx
LINx
UZ=10.5V
SWITCH LEVEL
VIH; VIL
datasheet
9
<Revision 2.5>, 21.01.2013
EiceDRIVER(TM)
6ED003L06-F2, 6ED003L02-F2
Figure 4
Input pin structure
An internal pull-up of about 75 k (negative logic) pre-biases the input during supply start-up and a ESD zener
clamp is provided for pin protection purposes. The zener diodes are therefore designed for single pulse stress
only and not for continuous voltage stress over 10V.
tFILIN
tFILIN
HIN
LIN
LIN
HIN
on
off
on
off
on
off
high
HO
LO
LO
HO
low
Figure 5
Input filter timing diagram
It is anyway recommended for proper work of the driver not to provide input pulse-width lower than 1 µs.
The 6ED-F2 driver IC provide additionally a shoot through prevention capability which avoids the simultaneous
on-state of two channels of the same leg (i.e. HO1 and LO1, HO2 and LO2, HO3 and LO3). When two inputs of
a same leg are activated, only one leg output is activated, so that the leg is kept steadily in a safe state. Please
refer to the application note AN-Gatedrive-6ED2-1 for a detailed description.
A minimum dead time insertion of typ. 310 ns is also provided, in order to reduce cross-conduction of the
external power switches.
2.2
EN (Gate Driver Enable, Pin 10)
The signal applied to pin EN controls directly the output stages. All outputs are set to LOW, if EN is at LOW
logic level. The internal structure of the pin is given in Figure 6. The switching levels of the Schmitt-Trigger are
here VEN,TH+ = 2.1 V and VEN,TH- = 1.3 V. The typical propagation delay time is tEN = 780 ns. There is an internal
pull down resistor (75 k), which keeps the gate outputs off in case of broken PCB connection.
IEN+, IEN-
EN
INPUT NOISE
FILTER
VEN,TH+
VEN,TH-
,
VZ= 10.5 V
6ED family – 2nd generation
Figure 6
EN pin structures
2.3
/FAULT (Fault Feedback, Pin 8)
/Fault pin is an active low open-drain output indicating the status of the gate driver (see Figure 7). The pin is
active (i.e. forces LOW voltage level) when one of the following conditions occur:
Under-voltage condition of VCC supply: In this case the fault condition is released as soon as the
supply voltage condition returns in the normal operation range (please refer to VCC pin description for
more details).
Over-current detection (ITRIP): The fault condition is latched until current trip condition is finished and
RCIN input is released (please refer to ITRIP pin).
6ED family –
2nd generation
VDD
VCC
RON,FLT
from ITRIP-Latch
from uv-detection
FAULT
>1
datasheet
10
<Revision 2.5>, 21.01.2013
EiceDRIVER(TM)
6ED003L06-F2, 6ED003L02-F2
Figure 7
/FAULT pin structures
2.4
ITRIP and RCIN (Over-Current Detection Function, Pin 9, 11)
The 6ED family – 2nd generation provides an over-current detection function by connecting the ITRIP input with
the motor current feedback. The ITRIP comparator threshold (typ 0.44 V) is referenced to VSS ground. A input
noise filter (typ. tITRIPMIN = 230 ns) prevents the driver to detect false over-current events.
Over-current detection generates a hard shut down of all outputs of the gate driver and provides a latched fault
feedback at /FAULT pin. RCIN input/output pin is used to determine the reset time of the fault condition. As
soon as ITRIP threshold is exceeded the external capacitor connected to RCIN is fully discharged. The
capacitor is then recharged by the RCIN current generator when the over-current condition is finished. As soon
as RCIN voltage exceeds the rising threshold of typ VRCIN,TH = 5.2 V, the fault condition releases and the driver
returns operational following the ontrol input pins according to section 2.1. Please refer to AN-Gatedrive-6ED2-1
for details on setting RCIN time constant.
2.5
VCC, VSS and COM (Low Side Supply, Pin 1, 12,13)
VCC is the low side supply and it provides power both to input logic and to low side output power stage. Input
logic is referenced to VSS ground as well as the under-voltage detection circuit. Output power stage is
referenced to COM ground. COM ground is floating respect to VSS ground with a maximum range of operation
of +/-5.7 V. A back-to-back zener structure protects grounds from noise spikes.
The under-voltage circuit enables the device to operate at power on when a typical supply voltage higher than
VCCUV+ is present.
The IC shuts down all the gate drivers power outputs, when the VCC supply voltage is below VCCUV- = 9.8 V.
This prevents the external power switches from critically low gate voltage levels during on-state and therefore
from excessive power dissipation. Please consult the individual output characteristic of the driven transistor.
2.6
VB1,2,3 and VS1,2,3 (High Side Supplies, Pin 18, 20, 22, 24, 26, 28)
VB to VS is the high side supply voltage. The high side circuit can float with respect to VSS following the
external high side power device emitter/source voltage. Due to the low power consumption, the floating driver
stage can be supplied by bootstrap topology connected to VCC.
The device operating area as a function of the supply voltage is given in Figure 12. Details on bootstrap supply
section and transient immunity can be found in application note AN-Gatedrive-6ED2-1.
2.7
LO1,2,3 and HO1,2,3 (Low and High Side Outputs, Pin 14, 15, 16, 19, 23, 27)
Low side and high side power outputs are specifically designed for pulse operation such as gate drive of IGBT
and MOSFET devices. Low side outputs (i.e. LO1,2,3) are state triggered by the respective inputs, while high
side outputs (i.e. HO1,2,3) are edge triggered by the respective inputs. In particular, after an under voltage
condition of the VBS supply, a new turn-on signal (edge) is necessary to activate the respective high side
output, while after a under voltage condition of the VCC supply, the low side outputs switch to the state of their
respective inputs.
datasheet
11
<Revision 2.5>, 21.01.2013
EiceDRIVER(TM)
6ED003L06-F2, 6ED003L02-F2
3
Electrical Parameters
3.1
Absolute Maximum Ratings
All voltages are absolute voltages referenced to VSS -potential unless otherwise specified. (Ta=25°C)
Table 3
Abs. maximum ratings
Parameter
Symbol Min.
Max.
Unit
VS
High side offset voltage(Note 1)
DSO28
TSSOP28
V
VCC-VBS-6
600
180
High side offset voltage (tp<500ns, Note 1)
VCC -VBS – 50 –
VB
High side offset voltage(Note 1)
DSO28
TSSOP28
VCC – 6
620
200
High side offset voltage (tp<500ns, Note 1)
VCC – 50
-1
–
High side floating supply voltage (VB vs. VS) (internally clamped) VBS
20
High side output voltage (VHO vs. VS)
VHO
-0.5
-1
VB + 0.5
20
VCC
Low side supply voltage (internally clamped)
Low side supply voltage (VCC vs. VCOM
)
VCCOM
VCOM
VLO
-0.5
-5.7
-0.5
-1
25
Gate driver ground
5.7
Low side output voltage (VLO vs. VCOM
Input voltage /LIN, /HIN, EN, ITRIP
FAULT output voltage
)
VCCOM + 0.5
10
VIN
VFLT
VRCIN
PD
VCC + 0.5
VCC + 0.5
-0.5
-0.5
RCIN output voltage
–
–
Power dissipation (to package) Note 2
DSO28
TSSOP28
1.3
0.6
W
Rth(j-a)
–
–
Thermal resistance
(junction to ambient, see section 5)
DSO28
TSSOP28
75
165
K/W
°C
TJ
–
Junction temperature
125
150
50
TS
Storage temperature
- 40
dVS/dt
offset voltage slew rate (Note 3)
V/ns
Note :The value for ESD immunity is 1.0kV (Human Body Model). ESD immunity for pins inside the low side (i.e. VCC, /HINx, /LINx, FAULT,
EN, RCIN, ITRIP, VSS, COM, LOx) and ESD immunity for pins inside each high side itself (i.e. VBx, HOx, VSx) is guaranteed up to 1.5kV
(Human Body Model).
Note 1 : Insensitivity of bridge output to negative transient voltage up to –50V is not subject to production test – verified by design /
characterization. External bootstrap diode is mandatory. Refer to application note.
Note 2: Consistent power dissipation of all outputs. All parameters inside operating range.
Note 3: Not subject of production test, verified by characterisation
datasheet
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<Revision 2.5>, 21.01.2013
EiceDRIVER(TM)
6ED003L06-F2, 6ED003L02-F2
3.2
Required operation conditions
All voltages are absolute voltages referenced to VSS -potential unless otherwise specified. (Ta = 25°C)
Table 4
Required Operation Conditions
Parameter
Symbol Min.
Max. Unit
VB
High side offset voltage (Note 1)
DSO28
TSSOP28
V
7
620
200
Low side supply voltage (VCC vs. VCOM
)
DSO28
TSSOP28
VCCOM
10
25
3.3
Operating Range
All voltages are absolute voltages referenced to VSS -potential unless otherwise specified. (Ta = 25°C)
Table 5
Operating range
Parameter
Symbol Min.
Max. Unit
VS
VCC -
High side floating supply offset voltage
V
VBS -1
-1.0
13
10
0
500
High side floating supply offset voltage (VB vs. VCC, statically)
High side floating supply voltage (VB vs. VS, Note 1)
High side output voltage (VHO vs. VS)
VBCC
VBS
VHO
VLO
VCC
VCOM
VIN
500
17.5
VBS
VCC
17.5
2.5
5
Low side output voltage (VLO vs. VCOM
Low side supply voltage
)
13
-2.5
0
Low side ground voltage
Logic input voltages /LIN, /HIN, EN, ITRIP (Note 2)
FAULT output voltage
VFLT
VRCIN
tIN
VCC
VCC
0
RCIN input voltage
0
Pulse width for ON or OFF (Note 3)
Ambient temperature
1
–
µs
°C
Ta
-40
95
Note 1 : Logic operational for VB (VB vs. VSS) > 7,0V
Note 2 : All input pins (/HINx, /LINx) and EN, ITRIP pin are internally clamped (see abs. maximum ratings)
Note 3 : In case of input pulse width at /LINx and /HINx below 1µs the input pulse may not be transmitted properly
datasheet
13
<Revision 2.5>, 21.01.2013
EiceDRIVER(TM)
6ED003L06-F2, 6ED003L02-F2
3.4
Static logic function table
VCC
VBS
X
RCIN
X
ITRIP
ENABLE
X
FAULT
LO1,2,3
HO1,2,3
<VCCUV–
15V
X
0
0
0
<VBSUV–
15V
X
0
3.3 V
3.3 V
3.3 V
3.3 V
0
High imp
0
/LIN1,2,3
0
15V
0
0
0
<3.2 V
X
> VIT,TH+
15V
15V
0
0
/LIN1,2,3
0
0
/HIN1,2,3
0
> VRCIN,TH
> VRCIN,TH
15V
15V
0
0
High imp
High imp
15V
15V
3.5
Static parameters
VCC = VBS = 15V unless otherwise specified. (Ta=25°C)
Table 6
Static parameters
Parameter
Symbol
Values
Unit Test condition
Min.
1.7
0.7
1.9
1.1
380
45
-
Typ.
2.1
0.9
2.1
1.3
445
70
Max.
2.4
VIH
High level input voltage
Low level input voltage
EN positive going threshold
EN negative going threshold
ITRIP positive going threshold
ITRIP input hysteresis
V
VIL
1.1
VEN,TH+
VEN,TH-
VIT,TH+
VIT,HYS
VRCIN,TH
VRCIN,HYS
VIN,CLMAP
2.3
1.5
510
mV
RCIN positive going threshold
RCIN input hysteresis
5.2
2.0
10.3
6.4
-
V
-
Input clamp voltage
9
12
IIN = 4mA
(/HIN, /LIN, EN, ITRIP)
Input clamp voltage at high impedance
(/HIN, /LIN)
VIN,FLOAT
VOH
-
5.3
5.8
controller output
pin floating
High level output voltage
LO1,2,3
-
-
VCC -0.7 VCC -1.4
VB -0.7 VB -1.4
IO = 20mA
HO1,2,3
LO1,2,3
VOL
VCOM
+
VCOM+
IO = -20mA
Low level output voltage
-
0.2
0.6
VS+ 0.2 VS + 0.6
HO1,2,3
-
VCC and VBS supply undervoltage positive
going threshold
VCCUV+
VBSUV+
11
11.7
12.5
VCC and VBS supply undervoltage negative
going threshold
VCCUV–
VBSUV–
9.5
1.2
9.8
10.8
V
VCC and VBS supply undervoltage lockout
hysteresis
VCCUVH
VBSUVH
1.9
-
datasheet
14
<Revision 2.5>, 21.01.2013
EiceDRIVER(TM)
6ED003L06-F2, 6ED003L02-F2
Table 6
Static parameters
Parameter
Symbol
Values
Unit Test condition
Min.
Typ.
1
Max.
12.5
-
ILVS+
VS = 600V
High side leakage current betw. VS and VSS
-
-
µA
1
TJ = 125°C,
VS = 600V
High side leakage current betw. VS and VSS ILVS+
10
1
TJ = 125°C
High side leakage current between VSx and ILVS–
-
10
-
VSy (x=1,2,3 and y=1,2,3)
VSx - VSy = 600V
Quiescent current VBS supply (VB only)
Quiescent current VBS supply (VB only)
Quiescent current VCC supply (VCC only)
Quiescent current VCC supply (VCC only)
Input bias current
IQBS1
IQBS2
IQCC1
IQCC2
ILIN+
-
-
-
-
-
210
210
1.1
1.3
70
400
400
1.8
2
µA
HO=low
HO=high
mA VLIN=float.
VLIN=0, VHIN=3.3 V
100
µA
µA
VLIN=3.3 V
ILIN-
IHIN+
IHIN-
VLIN=0
Input bias current
Input bias current
Input bias current
-
-
-
110
70
200
100
200
VHIN=3.3 V
VHIN=0
110
IITRIP+
IEN+
VITRIP=3.3 V
VENABLE=3.3 V
VRCIN = 2 V
Input bias current (ITRIP=high)
Input bias current (EN=high)
45
45
2.8
120
120
-
IRCIN
Input bias current RCIN (internal current
source)
IO+
Mean output current for load capacity
charging in range from 3 V (20%) to 6 V
(40%)
120
165
-
-
mA CL=10 nF
1
IOpk+
Peak output current turn on (single pulse)
240
375
RL = 0 , tp <10 µs
IO-
Mean output current for load capacity
discharging in range from 12 V (80%) to 9 V
(60%)
250
CL=10 nF
1
IOpk-
Peak output current turn off (single pulse)
420
40
RL = 0 , tp <10 µs
VRCIN=0.5 V
Ron,RCIN
RCIN low on resistance of the pull down
transistor
-
-
100
100
Ron,FLT
VFAULT=0.5 V
FAULT low on resistance of the pull down
transistor
45
1 Not subject of production test, verified by characterisation
datasheet
15
<Revision 2.5>, 21.01.2013
EiceDRIVER(TM)
6ED003L06-F2, 6ED003L02-F2
3.6
Dynamic parameters
VCC = VBS = 15 V, VS = VSS = VCOM unless otherwise specified. (TA=25°C)
Table 7
Dynamic parameters
Parameter
Symbol
Values
Unit Test condition
Min.
400
360
-
Typ.
530
490
60
Max.
800
760
100
45
ton
Turn-on propagation delay
Turn-off propagation delay
Turn-on rise time
ns
VLIN/HIN = 0 or 3.3 V
toff
tr
VLIN/HIN = 0 or 3.3 V
CL = 1 nF
tf
Turn-off fall time
-
26
tEN
VEN=0
Shutdown propagation delay ENABLE
Shutdown propagation delay ITRIP
Input filter time ITRIP
-
780
670
230
420
300
600
1.9
1100
1000
380
700
-
tITRIP
tITRIPMIN
tFLT
VITRIP=1 V
400
155
-
Propagation delay ITRIP to FAULT
Input filter time at LIN/HIN for turn on and off
Input filter time EN
tFILIN
tFILEN
tFLTCLR
VLIN/HIN = 0 & 3.3 V
120
300
1.0
-
VLIN/HIN = 0 & 3.3 V
VITRIP = 0
Fault clear time at RCIN after ITRIP-fault,
(CRCin=1nF)
3.0
ms
ns
Dead time
DT
150
-
310
20
-
VLIN/HIN = 0 & 3.3 V
Matching delay ON, max(ton)-min(ton), ton MTON
are applicable to all 6 driver outputs
100
external dead time
> 500 ns
Matching delay OFF, max(toff)-min(toff), toff MTOFF
are applicable to all 6 driver outputs
-
40
40
100
100
external dead time
>500 ns
Output pulse width matching. Pwin-PWout
PM
PWin > 1 µs
datasheet
16
<Revision 2.5>, 21.01.2013
EiceDRIVER(TM)
6ED003L06-F2, 6ED003L02-F2
4
Timing diagrams
tFILIN
tIN
tFILIN
tIN
HIN/LIN
HIN/LIN
HO/LO
HIN/LIN
HO/LO
tIN < tFILIN
tIN < tFILIN
high
HO/LO
HIN/LIN
HO/LO
low
tIN
tIN
tIN > tFILIN
tIN > tFILIN
Figure 8
Timing of short pulse suppression
LIN1,2,3
2.5V
2.5V
HIN1,2,3
HO1,2,3
DT
12V
3V
DT
3V
12 V
LO1,2,3
Figure 9
Timing of internal deadtime
EN
tEN
HO1,2,3
LO1,2,3
3V
Figure 10 Enable delay time definition
datasheet
17
<Revision 2.5>, 21.01.2013
EiceDRIVER(TM)
6ED003L06-F2, 6ED003L02-F2
PWIN
LIN1,2,3
HIN1,2,3
1.65V
1.65V
toff
ton
tr
tf
12V
12V
HO1,2,3
LO1,2,3
3V
3V
PWOUT
Figure 11 Input to output propagation delay times and switching times definition
VCCMAX , VBSMAX
20
V
17.5
vCC
vBS
13
VCCUV+, VBSUV+ 11.7
VCCUV-, VBSUV- 9.8
t
IC STATE
ON
Recommended
Area
ON
Recommended
Area
Forbidden
Area
OFF
ON
ON
ON
ON
OFF
Figure 12 Operating areas
VRCIN,TH
RCIN
ITRIP
0.1V
0.1V
FAULT
1V
0.5V
tFLT
tFLTCLR
Any
output
3V
tITRIP
Figure 13 ITRIP-Timing
datasheet
18
<Revision 2.5>, 21.01.2013
EiceDRIVER(TM)
6ED003L06-F2, 6ED003L02-F2
5
Package
5.1
PG-DSO-28
Figure 14 Package drawing
Dimensions
Material
80.0 80.0 1.5 mm³
therm [W/mK]
FR4
0.3
Metal (Copper) 70µm
388
Figure 15 PCB reference layout
datasheet
19
<Revision 2.5>, 21.01.2013
EiceDRIVER(TM)
6ED003L06-F2, 6ED003L02-F2
5.2
PG-TSSOP-28
Footprint for Reflow soldering
e = 0.65
A = 6.10
L = 1.30
B = 0.40
Figure 16 Package drawing
Figure 17 PCB reference layout (according to JEDEC 1s0P)
left: Reference layout
right: detail of footprint
Table 8
Data of reference layout
Dimensions
Material
Metal (Copper)
76.2 114.3 1.5 mm³
FR4 (therm = 0.3 W/mK)
70µm (therm = 388 W/mK)
datasheet
20
<Revision 2.5>, 21.01.2013
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
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