6ED003L06-F [INFINEON]
Integrated 3 Phase Gate Driver; 集成3相栅极驱动器
| 型号： | 6ED003L06-F |
| 厂家： | 
Infineon |
| 描述： | Integrated 3 Phase Gate Driver |
| 文件： | 总18页 (文件大小：288K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data sheet, Rev. 2.1, Dec 2008
6ED003L06-F
Integrated 3 Phase Gate Driver
Power Management & Drives
N e v e r
s t o p
t h i n k i n g
6ED003L06-F
Integrated 3 Phase Gate Driver
6ED003L06-F
Revision History:
2009-07
Rev. 2.1
Previous Version:
2.0
Page
11
Subjects (major changes since last revision)
VIT Hys changed
9
Corrected RthJA Fig3 Æ Fig13
Edition 2006-01
Published by
Infineon Technologies AG
81726 München, Germany
© Infineon Technologies AG 7/28/09.
All Rights Reserved.
Attention please!
The information given in this data sheet shall in no event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical
values stated herein and/or any information regarding the application of the device, Infineon Technologies
hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of
non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types
in question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express
written approval of Infineon Technologies, if a failure of such components can reasonably be expected to
cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or
system. Life support devices or systems are intended to be implanted in the human body, or to support
and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.
Datasheet
2
Rev. 2, Dec 2008
6ED003L06-F
Integrated 3 Phase Gate Driver
Table of Contents:
1
Overview ........................................................................................................................................4
1.1
Features ........................................................................................................................................ 4
1.2
Description ................................................................................................................................... 4
2
Pin Configuration and Description..............................................................................................5
2.1
Description ................................................................................................................................... 5
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
2.1.6
2.1.7
/HIN1,2,3 and /LIN1,2,3 (Low side and high side control pins, Pin 2, 3, 4, 5, 6, 7)................. 5
EN (Gate driver enable, Pin 10)................................................................................................... 6
/FAULT (Fault feedback, Pin 8)................................................................................................... 6
ITRIP and RCIN (Over-current detection function, Pin 9, 11) .................................................. 6
VCC, VSS and COM (Low side supply, Pin 1, 12,13) ................................................................ 6
VB1,2,3 and VS1,2,3 (High side supplies, Pin 18, 20, 22, 24, 26, 28)....................................... 7
LO1,2,3 and HO1,2,3 (Low and High side outputs, Pin 14, 15, 16, 19, 23, 27)........................ 7
3
Electrical parameters....................................................................................................................9
3.1
Absolute Maximum Ratings........................................................................................................ 9
3.2
3.3
3.4
3.5
3.6
Required Operation Conditions................................................................................................ 10
Operating Range ........................................................................................................................ 10
Static Logic function Table....................................................................................................... 11
Static Parameters....................................................................................................................... 11
Dynamic Parameters.................................................................................................................. 13
4
Timing Diagrams.........................................................................................................................14
5
Package........................................................................................................................................17
5.1
Package Drawing ....................................................................................................................... 17
5.2
Reference PCB for thermal resistance .................................................................................... 18
Datasheet
3
Rev. 2, Dec 2008
6ED003L06-F
Integrated 3 Phase Gate Driver
1
Overview
1.1 Features
• Thin-film-SOI-technology
• Insensitivity of the bridge output to negative transient voltages up to -50V
given by SOI-technology
• Maximum blocking voltage +600V
• Power supply of the high side drivers via boot strap
• Separate control circuits for all six drivers
• CMOS and LSTTL compatible input (negative logic)
• Signal interlocking of every phase to prevent cross-conduction
• Detection of over-current and under-voltage supply
• 'shut down' of all switches during error conditions
• externally programmable delay for fault clear after over current detection
PG-DSO28-17
1.2 Description
The device 6ED003L06-F is a full bridge driver to control power devices like MOS-transistors or IGBTs in 3-
phase systems with a maximum blocking voltage of +600V. Based on the used SOI-technology there is an
excellent ruggedness on transient voltages. No parasitic thyristor structures are present in the device.
Hence, no parasitic latch up may occur at all temperature and voltage conditions.
Figure 1: Typical Application
The six independent drivers are controlled at the low-side using CMOS resp. LSTTL compatible signals,
down to 3.3V logic. The device includes an under-voltage detection unit with hysterese characteristic and an
over-current detection. The over-current level is adjusted by choosing the resistor value and the threshold
DC-Bus
5V / 3.3V
VCC
HIN1,2,3
LIN1,2,3
FAULT
VCC
VB1,2,3
HO1,2,3
VS1,2,3
HIN1,2,3
LIN1,2,3
FAULT
EN
To Load
RRCIN
CRCIN
RCIN
ITRIP
VSS
LO1,2,3
COM
EN
RNTC
VSS
level at pin ITRIP. Both error conditions (under-voltage and over-current) lead to a definite shut-down off all
six switches. An error signal is provided at the FAULT open drain output pin. The blocking time after over-
current can be adjusted with an RC-network at pin RCIN. The input RCIN owns an internal current source of
2.8 µA. Therefore, the resistor RRCIN is optional. The minimum output current can be given with 120mA for
pull-up and 250mA for pull down. Because of system safety reasons a 380ns interlocking time has been
realised. The function of input EN can optionally be extended with an over-temperature detection, using an
external NTC-resistor (see Fig.1). There are parasitic diode structures between pins VCC and VBx due to
the monolithic setup of the IC, but external bootstrap diodes are still mandatory.
Datasheet
4
Rev. 2, Dec 2008
6ED003L06-F
Integrated 3 Phase Gate Driver
2
Pin Configuration and Description
Figure 2: Pin Configuration of 6ED003L06-F
Table 1: Pin Description
Symbol
VCC
Description
Low side power supply
Logic ground
VSS
/HIN1,2,3
/LIN1,2,3
/FAULT
EN
High side logic input (negative logic)
Low side logic input (negative logic)
Indicates over-current and under-voltage (negative logic, open-drain output)
Enable I/O functionality (positive logic)
ITRIP
Analog input for over-current shutdown, activates FAULT and RCIN to VSS
external RC-network to define FAULT clear delay after FAULT-Signal (TFLTCLR
Low side gate driver reference
RCIN
)
COM
VB1,2,3
HO1,2,3
VS1,2,3
LO1,2,3
nc
High side positive power supply
High side gate driver output
High side negative power supply
Low side gate driver output
Not Connected
2.1 Description
2.1.1 /HIN1,2,3 and /LIN1,2,3 (Low side and
high side control pins, Pin 2, 3, 4, 5, 6, 7)
These pins are active low and they are
responsible for HO1,2,3 and LO1,2,3 out-of-phase
Datasheet
5
Rev. 2, Dec 2008
6ED003L06-F
Integrated 3 Phase Gate Driver
commutation. The schmitt-trigger input threshold
of them are such to guarantee LSTTL and CMOS
compatibility down to 3.3V controller outputs.
• Under-voltage condition of VCC supply: In this
case the fault condition is released as soon as
the supply voltage condition returns in the
normal operation range (please refer to VCC
pin description for more details).
• Over-current detection (ITRIP): The fault
condition is latched until current trip condition
is finished and RCIN input is released (please
refer to ITRIP pin).
≈ 50Ω
Figure 3: Input pin structure
An internal pull-up resistor of about 75 kΩ is pre-
biases the input during supply start-up and a
zener clamp is provided for pin protection
purposes. Input schmitt-trigger and noise filter
provide beneficial noise rejection to short input
pulses according to Figure 4 and Figure 7.
Figure 5: /Fault pin structure
2.1.4 ITRIP
and
RCIN
(Over-current
detection function, Pin 9, 11)
6ED003L06-F provides an over-current detection
function by connecting the ITRIP input with the
motor current feedback. The ITRIP comparator
threshold (typ 0.46V) is referenced to VSS
ground. A input noise filter (typ: tITRIPMIN = 210 ns)
prevents the driver to detect false over-current
events.
Figure 4: Input filter timing diagram
Over-current detection generates a hard shut
down of all outputs of the gate driver and provides
a latched fault feedback at /FAULT pin.
It is anyway recommended for proper work of the
driver not to provide input pulse-width lower than
1us.
RCIN input/output pin is used to determine the
reset time of the fault condition. As soon as ITRIP
threshold is exceeded the external capacitor
connected to RCIN is fully discharged. The
capacitor is then recharged by the RCIN current
generator when the over-current condition is
finished. As soon as RCIN voltage exceeds the
rising threshold of typ VRCIN,TH = 6.0V, the fault
condition releases and the driver returns
operational following /HIN and /LIN inputs. Please
refer to AN-GateDriver-6ED003L06-1 for details
on setting RCIN time constant.
The 6ED003L06-F provides additionally an anti-
shoot through prevention capability which avoids
the simultaneous on-state of two gate drivers of
the same leg (i.e. HO1 and LO1, HO2 and LO2,
HO3 and LO3). When two inputs of a same leg
are activated, only one leg output is activated, so
that the leg is kept steadily in a safe state. Please
refer to the application note AN-Gatedrive-
6ED003L06-1 for a detailed description.
A minimum deadtime insertion of typ 380ns is also
provided, in order to reduce cross-conduction of
the external power switches.
2.1.5 VCC, VSS and COM (Low side supply,
2.1.2
EN (Gate driver enable, Pin 10)
Pin 1, 12,13)
The signal applied to pin EN controls directly the
output stages. All outputs are set to LOW, if EN is
at LOW logic level. The internal structure of the
pin is the same as Figure 3 made exception of the
switching levels of the Schmitt-Trigger, which are
here VEN,TH+ = 2.1 V and VEN,TH- = 1.3 V. The
typical propagation delay time is tEN = 780 ns.
VCC is the low side supply and it provides power
both to input logic and to low side output power
stage. Input logic is referenced to VSS ground as
well as the under-voltage detection circuit. Output
power stage is referenced to COM ground.COM
ground is floating respect to VSS ground with a
recommended range of operation of +/-2.5V. A
back-to-back zener structure protects grounds
from noise spikes.
2.1.3 /FAULT (Fault feedback, Pin 8)
/Fault pin is an active low open-drain output
indicating the status of the gate driver (see Figure
3). The pin is active (i.e. forces LOW voltage
level) when one of the following conditions occur:
The under-voltage circuit enables the device to
operate at power on when a typical supply voltage
VCCUV+ = 12 V is present.
Datasheet
6
Rev. 2, Dec 2008
6ED003L06-F
Integrated 3 Phase Gate Driver
The IC shuts down all the gate drivers power
outputs, when the VCC supply voltage is below
VCCUV- = 10.4 V. This prevents the external power
switches from critically low gate voltage levels
during on-state and therefore from excessive
power dissipation.
area as a function of the supply voltage. Details
on bootstrap supply section and transient
immunity can be found in application note AN-
GateDriver-6ED003L06-1.
2.1.7 LO1,2,3 and HO1,2,3 (Low and High
side outputs, Pin 14, 15, 16, 19, 23, 27)
2.1.6 VB1,2,3 and VS1,2,3 (High side
Low side and high side power outputs are
specifically designed for pulse operation such as
gate drive of IGBT and MOSFET devices. Low
side outputs (i.e. LO1,2,3) are state triggered by
the respective inputs (/LIN1,2,3), while high side
outputs (i.e. HO1,2,3) are edge triggered by the
respective inputs (/HIN1,2,3). In particular, after
an under-voltage condition of the VBS supply, a
falling /HIN edge is necessary to turn-on the
respective high side output, while after a under-
voltage condition of the VCC supply, the low side
outputs switch to the state of their respective
inputs.
supplies, Pin 18, 20, 22, 24, 26, 28)
VB to VS is the high side supply voltage. The high
side circuit can float with respect to VSS following
the
external
high
side
power
device
emitter/source voltage.
Due to the low power consumption, the floating
driver stage can be supplied by bootstrap
topology connected to VCC.
Under-voltage detection operates with a rising
supply threshold of typical VBSUV+ = 12 V and a
falling threshold of VCCUV- = 10.4 V. Please refer to
Figure 11 of the datasheet for device operating
Datasheet
7
Rev. 2, Dec 2008
6ED003L06-F
Integrated 3 Phase Gate Driver
BIAS NETWORK / VDD2
VB1
INPUT NOISE
FILTER
BIAS NETWORK - VB1
HIN1
LIN1
DEADTIME &
SHOOT-THROUGH
PREVENTION
LATCH
HV LEVEL-SHIFTER
+ REVERSE-DIODE
COMPA
RATOR
Gate-
Drive
HO1
VS1
UV-
DETECT
INPUT NOISE
FILTER
VB2
INPUT NOISE
FILTER
BIAS NETWORK - VB2
HIN2
LIN2
HIN3
LIN3
EN
DEADTIME &
SHOOT-THROUGH
PREVENTION
LATCH
Gate-
Drive
HV LEVEL-SHIFTER
+ REVERSE-DIODE
COMPA
RATOR
HO2
VS2
UV-
DETECT
INPUT NOISE
FILTER
INPUT NOISE
FILTER
VB3
HO3
VS3
DEADTIME &
SHOOT-THROUGH
PREVENTION
BIAS NETWORK / VB3
LATCH
HV LEVEL-SHIFTER
+ REVERSE-DIODE
COMPA
RATOR
Gate-
Drive
UV-
DETECT
INPUT NOISE
FILTER
>1
INPUT NOISE
FILTER
VCC
LO1
UV-
DETECT
VSS / COM
LEVEL-
SHIFTER
Gate-
Drive
DELAY
DELAY
DELAY
INPUT NOISE
FILTER
ITRIP
VSS / COM
LEVEL-
SHIFTER
Gate-
Drive
LO2
S
Q
VDD2
IRCIN
SET
DOMINANT
VSS / COM
LEVEL-
LATCH
Gate-
Drive
LO3
R
RCIN
SHIFTER
COM
FAULT
VSS
>1
Figure 6: Block diagram
Datasheet
8
Rev. 2, Dec 2008
6ED003L06-F
Integrated 3 Phase Gate Driver
3
Electrical parameters
3.1 Absolute Maximum Ratings
All voltages are absolute voltages referenced to VSS -potential unless otherwise specified. (TA=25°C)
Symbol
Definition
High side offset voltage(Note 1)
Min.
Max.
Unit
VS
VCC-VBS-
600
V
6
High side offset voltage (tp<500ns, Note 1)
VCC -VBS
-
-
50
VB
High side offset voltage(Note 1)
VCC - 6
VCC - 50
-1
620
-
High side offset voltage (tp<500ns, Note 1)
High side floating supply voltage (VB vs. VS)
High side output voltage (VHO vs. VS)
Low side supply voltage (internally clamped)
VBS
VHO
VCC
20
-0.5
VB + 0.5
20
-1
VCCOM Low side supply voltage (VCC vs. VCOM
)
-0.5
25
VCOM
VLO
Gate driver ground
-5.7
5.7
Low side output voltage (VLO vs. VCOM
)
-0.5
VCCOM
+0.5
VIN
Input voltage LIN,HIN,EN,ITRIP
tp <10µs
-1.0
10
15
VFLT
VRCIN
PD
FAULT output voltage
RCIN output voltage
-0.5
VCC + 0.5
VCC + 0.5
1.0
-0.5
Power dissipation (to package) Note 2
-
-
W
RthJA
Thermal resistance (junction to ambient, device mounted on PCB
see Fig.13)
70
K/W
°C
TJ
Junction temperature
Storage temperature
-
125
150
50
TS
-40
dVs/dt offset voltage slew rate
V/ns
Note :The minimal value for ESD immunity is 1.0kV (Human Body Model). ESD immunity inside pins connected to the low side (VCC,
HINx, LINx, FAULT, EN, RCIN, ITRIP, VSS, COM, LOx) and pins connected inside each high side itself (VBx, HOx, VSx) is guaranteed
up to 1.5kV (Human Body Model).
Note 1 : Insensitivity of bridge output to negative transient voltage up to –50V is not subject to production test – verified by design /
characterization. External bootstrap diode is mandatory. Refer to application note.
Note 2: Consistent power dissipation of all outputs
Datasheet
9
Rev. 2, Dec 2008
6ED003L06-F
Integrated 3 Phase Gate Driver
3.2 Required Operation Conditions
All voltages are absolute voltages referenced to VSS -potential unless otherwise specified. (TA=25°C)
Symbol
Definition
High side offset voltage (Note 1)
Min.
Max.
Unit
VB
11.1
10
620
25
V
VCCOM Low side supply voltage (VCC vs. VCOM
)
Note 1 : Logic operational for VB (VB vs. VSS) > 11,1V
3.3 Operating Range
All voltages are absolute voltages referenced to VSS -potential unless otherwise specified. (TA=25°C)
Symbol
Definition
Min.
Max.
Unit
VS
High side floating supply offset voltage
VCC -VBS-
550
V
0.5
VBCC
High side floating supply offset voltage (VB vs. VCC, statically, Note
-0.5
550
1, Note 2)
VBS
VHO
VLO
VCC
VCOM
VIN
High side floating supply voltage (VB vs. VS)
High side output voltage (VHO vs. VS)
13
0
17.5
VBS
20
Low side output voltage (VLO vs. VCOM
)
0
Low side supply voltage
13
-2.5
0
17.5
2.5
5
Low side ground voltage
Logic input voltages LIN,HIN,EN,ITRIP
FAULT output voltage
VFLT
VRCIN
tIN
0
VCC
VCC
-
RCIN input voltage
0
Pulse width for ON or OFF (Note 3)
Ambient temperature
1
µs
°C
TA
-40
95
Note 2 : All input pins (/HINx, /LINx) and EN, ITRIP pin are internally clamped with a 10.5V zener diode.
Note 3 : In case of input pulse width at /LINx and /HINx below 1µ the input pulse can not be transmitted properly
Datasheet
10
Rev. 2, Dec 2008
6ED003L06-F
Integrated 3 Phase Gate Driver
3.4 Static Logic function Table
VCC
<VCCUV-
15V
VBS
X
RCIN
X
ITRIP
X
ENABLE
FAULT
LO1,2,3
HO1,2,3
X
0
0
0
<VBSUV-
15V
15V
15V
15V
X
0V
5V
5V
5V
5V
0V
High imp
0
/LIN1,2,3
0
15V
0V
0
0
< 3.3V ↓
X
15V
> VIT,TH+
0V
0
0
/LIN1,2,3
0
0
/HIN1,2,3
0
15V
> 5.8V
> 5.8V
High imp
High imp
15V
0V
3.5 Static Parameters
VCC = VBS = 15V unless otherwise specified. (TA=25°C)
Symbol
VIH
Definition
Logic "0" input voltage (LIN,HIN)
Logic "1" input voltage (LIN,HIN)
EN positive going threshold
EN negative going threshold
ITRIP positive going threshold
ITRIP input hysteresis
Min.
1.7
0.7
1.9
1.1
360
45
-
Typ. Max. Unit
Test Conditions
2.1
0.9
2.1
1.3
460
70
2.4
1.1
2.3
1.5
540
V
VIL
VEN,TH+
VEN,TH-
VIT,TH+
VIT,HYS
mV
V
VRCIN,TH RCIN positive going threshold
VRCIN,HYS RCIN input hysteresis
6.0
2.5
0.8
7.5
-
-
VOH
Output voltage (high level, VCC-VO or VBS-
VO)
-
1.4
IO = 20mA
IO = -20mA
VOL
Output voltage (low level, VO-VCOM or VO-VS)
-
0.2
12
0.6
VCCUV+
VBSUV+
VCC and VBS supply undervoltage positive
going threshold
11.0
12.8
VCCUV-
VBSUV-
VCC and VBS supply undervoltage negative
going threshold
9.5
10.4
1.6
1
11.0
VCCUVH
VBSUVH
VCC and VBS supply undervoltage lockout
hysteresis
1.2
-
5
-
ILVS+
High side leakage current betw. VS and
VSS
-
-
-
µA
µA
VS = 600V
1
ILVS+
High side leakage current betw. VS and
VSS
30
30
Tj=125°C,
VS = 600V
1
ILVS-
High side leakage current between VSx and
VSy (x=1,2,3 and y=1,2,3)
-
Tj=125°C
VSx - VSy =600V
1 Not subject of production test, verified by characterisation
Datasheet 11
Rev. 2, Dec 2008
6ED003L06-F
Integrated 3 Phase Gate Driver
Symbol
IQBS1
Definition
Min.
Typ. Max. Unit
Test Conditions
HO=low
Quiescent VBS supply current (VB only)
Quiescent VBS supply current (VB only)
Quiescent VCC supply current (VCC only)
Quiescent VCC supply current (VCC only)
Quiescent VCC supply current (VCC only)
-
-
-
-
-
300
360
0.6
500
550
1
IQBS2
HO=high
IQCC1
mA
mA
mA
V
VLIN=float.
IQCC2
1.1
1.6
1.6
13
VLIN=0V, VHIN=5V,
VLIN=5V, VHIN=0V
IIN=4mA
IQCC3
0.9
VIN,CLAMP Input clamp voltage (/HIN, /LIN, EN, ITRIP) 9.0
10.6
(Note 1)
ILIN+
ILIN-
IHIN+
IHIN-
IITRIP+
IEN+
Input bias current
-
-
-
-
52
110
52
100
200
100
200
120
120
µA
VLIN=5V
VLIN=0V
Input bias current
Input bias current
VHIN=5V
Input bias current
110
70
VHIN=0V
Input bias current (ITRIP=high)
Input bias current (EN=high)
VITRIP=5V
VENABLE=5V
VRCIN = 2 V
-
69
IRCIN
Input bias current RCIN (internal current
source)
2.8
IO+
Mean output current for load capacity 120
charging in range from 3V(20%) to 6V(40%)
142
410
-
-
mA
CL=10nF
CL=10nF
Mean output current for load capacity
discharging in range from 12V(80%) to
9V(60%)
IO-
250
RCIN low on resistance of the pull down
transistors
RON,RCIN
RON,FLT
-
-
47
54
100
100
V
RCIN=0.5V
Ω
FAULT low on resistance of the pull down
transistors
VFAULT=0.5V
Note 1: There is an additional power dissipation for input voltages above the clamping voltage. In series to clamping diode there is a
limiting resistor of 55Ω (see also Fig.3)
Datasheet
12
Rev. 2, Dec 2008
6ED003L06-F
Integrated 3 Phase Gate Driver
3.6 Dynamic Parameters
CC = VBS =15V, VS = VSS = VCOM, unless otherwise specified. (TA=25°C)
V
Symbol
Definition
Min.
Typ. Max.
Unit
Test
Condition
ton
toff
Turn-on propagation delay
400
620
610
76
800
800
130
45
ns
VLIN/HIN=0V
VLIN/HIN=5V
VLIN/HIN=0V
VLIN/HIN=5V
VEN=0
Turn-off propagation delay
400
tr
Turn-on rise time (CL=1nF)
Turn-off fall time (CL=1nF)
-
tf
-
-
26
tEN
Shutdown propagation delay ENABLE
Shutdown propagation delay ITRIP
Input filter time ITRIP
780
765
210
450
270
1000
1000
380
700
-
tITRIP
tITRIPMIN
tFLT
tFILIN
400
155
-
VITRIP=1V
Propagation delay ITRIP to FAULT
Input filter time at LIN for turn on and off 120
and input filter time at HIN for turn on
only
VLIN/HIN=0V&
5V
tFILIN1
Input filter time at HIN for turn off (Note 100
1)
220
400
-
-
VHIN = 5V
VHIN = 5V
tFILIN2
Input filter time at HIN for turn off (Note
1)
-
tFILEN
Input filter time EN
300
485
2.3
-
tFLTCLR
Fault clear time at RCIN after ITRIP- 1.0
fault, (CRCin=1nF)
3.0
ms
ns
VLIN/HIN = 0 &
5V VITRIP=0V
DT
Dead time
150
380
70
-
VLIN/HIN = 0 &
5V
MTON
Matching delay ON, max(ton)-min(ton),
ton are applicable to all 6 driver outputs
-
150
external
dead time-
>500ns
MTOFF
PM
Matching
delay
OFF,
max(toff)-
-
90
12
150
100
external
dead time-
>500ns
min(toff), toff are applicable to all 6
driver outputs
Output pulse width matching. Pwin-
PWout
PWin>1µs
Note 1 : Because of internal signal processing and safety aspects the output HO at short turn off pulses shows the behaviour according
to figure 4. For proper work of the driver the input pulses must not fall below the recommended input width tIN of 1µs.
The short signal range is not subject to production test and is not guaranteed.
Datasheet
13
Rev. 2, Dec 2008
6ED003L06-F
Integrated 3 Phase Gate Driver
4
Timing Diagrams
tFILIN
tFILIN
HIN
LIN
on
off
on
off
LIN
LO
high
HO
LO
low
tFILIN2
tFILIN1
toff,HINx
a)
HIN
toff,HINx < tFILIN1
high
HO
b)
toff,HINx
HIN
toFILIN1 < toff,HINx < tFILIN2
HO
c)
HIN
toff,HINx
toff,HINx > tFILIN2
HO
Figure 7: Timing of short pulse suppression
Figure 8: Timing of internal deadtime
Datasheet
14
Rev. 2, Dec 2008
6ED003L06-F
Integrated 3 Phase Gate Driver
Figure 9: Enable delay time definition
Figure 10: Input to output propagation delay times and switng times definition
Figure 11: Operating Areas
Datasheet
15
Rev. 2, Dec 2008
6ED003L06-F
Integrated 3 Phase Gate Driver
Figure 12: ITRIP-timing
Datasheet
16
Rev. 2, Dec 2008
6ED003L06-F
Integrated 3 Phase Gate Driver
5
Package
5.1 Package Drawing
0.35 x 45˚
1)
7.6 -0.2
1.27
0.4 +0.8
0.1
0.35 +0.15
2)
±0.3
10.3
0.2 28x
28
15
14
1
1)
18.1-0.4
Index Marking
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Does not include dambar protrusion of 0.05 max. per side
Footprint for Reflow soldering
e = 1.27
A = 9.73
L = 1.67
B = 0.65
L
A
HLG05506
Datasheet
17
Rev. 2, Dec 2008
6ED003L06-F
Integrated 3 Phase Gate Driver
5.2 Reference PCB for thermal resistance
Figure 13: PCB Reference layout
Dimensions
Material
80.0 × 80.0 × 1.5 mm³
λtherm [W/m⋅K]
FR4
0.3
Metal (Copper)
70µm
388
Datasheet
18
Rev. 2, Dec 2008
相关型号：
©2020 ICPDF网 联系我们和版权申明