XFL215800.000000K [IDT]
LVDS Output Clock Oscillator;
| 型号： | XFL215800.000000K |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | LVDS Output Clock Oscillator 振荡器 |
| 文件： | 总17页 (文件大小：390K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
XF Family of Low Phase Noise
Quartz-based PLL Oscillators
XF
Datasheet
Description
Features
▪ Output types: LVDS, LVPECL, CML
• Frequency range: 15MHz to 2100MHz
▪ Output type: HCSL
• Frequency range: 15MHz to 725MHz
▪ Supply voltage options: 1.8V, 2.5V, or 3.3V
▪ Phase jitter (12kHz to 20MHz): 120fs typical
▪ Package: 2.5 × 2.0 mm, 0.4mm pitch DFN
The XF devices are ultra-low phase noise quartz-based PLL
oscillators supporting a large range of frequencies and output
interface types. These devices are designed to operate at three
different power supplies with several pinout configurations, as well
as two operational temperature ranges.
The XF devices can be programmed to generate an output
frequency from 15MHz to 2100MHz with a resolution as low as
1Hz accuracy. The configuration capability of this family of devices
allows for fast delivery times for both sample and large production
orders.
▪ Operating temperatures and frequency stability:
• -40°C to +85°C, ±25ppm
• -40°C to +105°C, ±50ppm
Parts are for one time programming (OTP) at the factory for a
fixed frequency application, or can be field programmable using
I2C, based on system needs (see notes under Pin Descriptions).
Typical Applications
▪ FOM Gear Box
▪ Data centers
Pin Assignments
1
2
3
4
5
6
12
11
10
9
NC
Ground Core
DD Core
▪ 10G / 40G / 100G / 400G Ethernet
V
NC
Voltage Control
SDA
Ground Output
Output 0b
8
Output 0
OE
7
SCL
VDD Output
Table 1. Pin Descriptions
Pin Number
Pin Name
Description
1
2
NC
NC
No connect.
No connect.
3
Voltage Control 2
Voltage control for VCXO option.
Serial data.
4
SDA 1
5
OE
Output enable.
6
SCL 1
Serial clock.
7
V
DD Output
Supply voltage.
Output 0.
8
Output 0
9
Output 0b
Complementary output 0.
Connect to ground.
Supply voltage.
Connect to ground.
10
11
12
13
Ground Output
V
DD Core
Ground Core
EPAD (dotted area shown in Pin Assignments diagram)
Connect to ground (required for heat dissipation).
1 Pins 4 and 6 are no connect for I2C applications.
2 Pin 3 is no connect for analog VCXO applications.
See Ordering Information for more details.
©2019 Integrated Device Technology, Inc.
1
July 22, 2019
XF Datasheet
Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
ESD Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Mechanical Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Solder Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Termination for 3.3V LVPECL Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Termination for 2.5V LVPECL Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
LVDS Driver Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Recommended Termination for HCSL Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
CML Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Package Outline Drawings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Marking Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
©2019 Integrated Device Technology, Inc.
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July 22, 2019
XF Datasheet
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the device. These ratings, which are standard values for IDT
commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those
indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Thermal characteristics, in actual applications, should be assessed case by case to guarantee junction temperature does not exceed
125°C.
Table 2. Absolute Maximum Ratings
Item
Rating
V
-0.5V to +3.8V
-0.5V to +3.8V
-55°C to 125°C
125°C
DD
E/D
Storage Temperature
Maximum Junction Temperature
1
Theta J (Still air, 2s2p board)
97.0 C/W
A
1
Theta J (Still air, 2s2p board)
62.2 C/W
B
1 Thermal characteristics are based on simulation in standard condition.
ESD Compliance
Table 3. ESD Compliance
Human Body Model (HBM)
2000V
Mechanical Testing
Table 4. Mechanical Testing *
Parameter
Test Method
Mechanical Shock
Half-sine wave with 0.3ms 3000G. X, Y, Z each direction 1 time.
Frequency: 10 to 55MHz amplitude: 1.5mm.
Frequency: 55–2000Hz peak value: 20G.
Mechanical Vibration
Duration time: 4H for each X,Y,Z axis; total 12hours.
High Temp Operating Life (HTOL)
Hermetic Seal
1000 hours at 125°C (under power).
Gross leak (air leak test). Fine leak (Helium leak test) He-pressure: 6kgf/cm² 2 hours.
* MSL level does not apply.
Solder Reflow Profile
tP
10 seconds Max within5°C of
260°C peak
260°C
Ramp up 3°C/s Max
225°C
180°C
Ramp down not to
exceed 6°C/s
50 ±10 seconds
above 225°C
reflow area
160°C
120 ±20 seconds in
pre-heating area
25°C
400 seconds Max from+25°C to 260°C peak
©2019 Integrated Device Technology, Inc.
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July 22, 2019
XF Datasheet
DC Electrical Characteristics
Note for all DC Electrical Characteristics tables: A pull-up resistor from VDD to OE enables output when pin 5 is left open.
Table 5. 3.3V IDD DC Electrical Characteristics
VDD = 3.3V ±5%, TA = -40°C to +85°C, -40°C to +105°C, typical at 156.25MHz.
Symbol
Parameter
Output Type
Conditions
Minimum
Typical
Maximum
Units
15MHz to 400MHz.
400MHz to 2.1GHz.
15MHz to 212.5MHz.
212MHz to 400MHz.
400MHz to 2.1GHz.
15MHz to 725MHz.
15MHz to 2.1GHz.
—
—
—
—
—
—
—
59
—
84
—
—
74
45
67
85
LVDS
94
I
Current Consumption
LVPECL
110
110
83
mA
DD
HCSL
CML
61
Table 6. 2.5V IDD DC Electrical Characteristics
VDD = 2.5V ±5%, TA = -40°C to +85°C, -40°C to +105°C, typical at 156.25MHz.
Symbol
Parameter
Output Type
Conditions
Minimum
Typical
Maximum
Units
15MHz to 400MHz.
400MHz to 2.1GHz.
15MHz to 156.25MHz.
156.25MHz to 400MHz.
400MHz to 2.1GHz.
15MHz to 400MHz.
400MHz to 725MHz.
15MHz to 2.1GHz.
—
—
—
—
—
—
—
—
59
—
84
—
—
—
74
54
66
85
LVDS
94
LVPECL
110
110
95
I
Current Consumption
mA
DD
HCSL
CML
82
61
Table 7. 1.8V IDD DC Electrical Characteristics
VDD = 1.8V ±5%, TA = -40°C to +85°C, -40°C to +105°C, typical at 156.25MHz.
Symbol
Parameter
Output Type
Conditions
Minimum
Typical
Maximum
Units
15MHz to 400MHz.
400MHz to 2.1GHz.
15MHz to 250MHz.
250MHz to 2.1GHz.
15MHz to 400MHz.
400MHz to 725MHz.
15MHz to 2.1GHz.
—
—
—
—
—
—
—
59
—
84
—
—
74
54
66
85
LVDS
93
LVPECL
I
Current Consumption
110
95
mA
DD
HCSL
CML
81
61
©2019 Integrated Device Technology, Inc.
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July 22, 2019
XF Datasheet
Table 8. LVCMOS DC Electrical Characteristics
VDD = 3.3V, 2.5V, 1.8V ±5%, TA = -40°C to +85°C, -40°C to +105°C, typical at 156.25MHz.
Symbol
Parameter
Conditions
Minimum
0.7 × V
Typical
Maximum
+ 0.3
Units
V
Input High Voltage (OE pin only)
Input Low Voltage (OE pin only)
V
V
= 3.3V, 2.5V, 1.8V ±5%
= 3.3V, 2.5V, 1.8V ±5%
—
—
V
DD
V
V
IH
DD
DD
DD
V
GND - 0.3
0.3 × V
DD
IL
Table 9. LVDS DC Electrical Characteristics
VDD = 3.3V, 2.5V, 1.8V ±5%, TA = -40°C to +85°C, -40°C to +105°C, typical at 156.25MHz.
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Units
V
Differential Output Voltage
V
= 3.3V, 2.5V, 1.8V ±5%
DD
0.30
1.11
1.08
0.75
0.44
1.26
1.25
0.88
0.60
1.41
1.41
1.01
OD
V
V
V
= 3.3V ±5%
= 2.5V ±5%
= 1.8V ±5%
DD
DD
DD
V
V
Output Offset Voltage
OS
Table 10. LVPECL DC Electrical Characteristics
VDD = 3.3V, 2.5V, 1.8V ±5%, TA = -40°C to +85°C, -40°C to +105°C, typical at 156.25MHz.
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Units
V
V
V
V
V
V
= 3.3V ±5%.
= 2.5V ±5%.
= 1.8V ±5%.
= 3.3V ±5%.
= 2.5V ±5%.
= 1.8V ±5%.
2.28
1.52
0.83
1.68
0.92
0.19
2.49
1.69
0.96
1.84
1.04
0.30
2.72
1.87
1.11
2.01
1.17
0.42
DD
DD
DD
DD
DD
DD
V
Output High Voltage
OH
V
V
Output Low Voltage
OL
Table 11. HCSL DC Electrical Characteristics
VDD = 3.3V, 2.5V, 1.8V ±5%, TA = -40°C to +85°C, -40°C to +105°C, typical at 156.25MHz.
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Units
V
V
V
= 3.3V ±5%.
= 2.5V ±5%.
= 1.8V ±5%.
—
0.78
0.74
0.67
-0.06
0.92
0.88
0.81
0.07
1.07
1.03
0.95
0.20
DD
DD
DD
V
Output High Voltage
OH
V
V
Output Low Voltage
OL
©2019 Integrated Device Technology, Inc.
5
July 22, 2019
XF Datasheet
Table 12. CML DC Electrical Characteristics
VDD = 3.3V, 2.5V, 1.8V ±5%, TA = -40°C to +85°C, -40°C to +105°C, typical at 156.25MHz.
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Units
V
V
V
V
V
V
= 3.3V ±5%.
= 2.5V ±5%.
= 1.8V ±5%.
= 3.3V ±5%.
= 2.5V ±5%.
= 1.8V ±5%.
3.09
2.33
1.66
2.70
1.95
1.30
3.26
2.46
1.76
2.85
2.06
1.37
3.43
2.59
1.85
3.00
2.17
1.45
DD
DD
DD
DD
DD
DD
V
Output High Voltage
V
OH
V
Output Low Voltage
V
OL
Table 13. DC Electrical Characteristics – Leakage Current
VDD = 3.3V, 2.5V, 1.8V ±5%, TA = -40°C to +85°C, -40°C to +105°C, typical at 156.25MHz.
Symbol
Parameter
Input
Conditions
Minimum
Typical
Maximum
Units
OE
SCLK
SDATA
OE
-5
-5
0.81
1.36
5
5
I
Input Leakage High
V
V
= 3.3V ±5%.
= 3.3V ±5%.
µA
IH
DD
DD
-5
1.44
5
-20
-37
-20
-17.44
-33.49
-17.02
-14
-30
-14
I
Input Leakage Low
SCLK
SDATA
µA
IL
AC Electrical Characteristics
Notes for all AC Electrical Characteristics tables:
1. A pull-up resistor from VDD to OE enables output when pin 5 is left open.
2. Installation should include a 0.01μF bypass capacitor placed between VDD and GND to minimize power supply line noise.
Table 14. 3.3V AC Electrical Characteristics
VDD = 3.3V ±5%, TA = -40°C to +85°C, -40°C to +105°C.
Symbol
Parameter
Test Condition
LVDS, LVPECL, CML.
Minimum
Typical
Maximum Units
15
15
—
—
—
2100
MHz
725
F
Output Frequency Range
HCSL.
Temperature = -40°C to +85°C.
Temperature = -40°C to +105°C.
Temperature = 25°C.
—
±25
±50
-15
ppm
ppm
ppm
ppm
ppm
Frequency Stability
—
—
Frequency Tolerance (25°C)
Aging (1st year)
-15
—
±10
—
T = 25°C.
±3
A
Aging (10 years)
T = 25°C.
—
—
±10
A
©2019 Integrated Device Technology, Inc.
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July 22, 2019
XF Datasheet
Table 14. 3.3V AC Electrical Characteristics (Cont.)
VDD = 3.3V ±5%, TA = -40°C to +85°C, -40°C to +105°C.
Symbol
Parameter
Test Condition
Differential.
- 2.0V.
Minimum
Typical
Maximum Units
LVDS.
—
—
—
100
50
—
Output Load
LVPECL.
HCSL.
V
—
—
Ω
DD
To GND.
50
Output valid time after V meets minimum
specified level.
DD
T
Start-up Time
—
5
—
ms
ST
LVDS.
—
—
—
—
—
—
—
—
45
45
45
45
—
299
287
306
301
279
274
284
279
—
400
400
400
400
400
400
400
400
55
LVPECL.
HCSL.
CML
20% – 80%,
156.25MHz
t
Output Rise Time
ps
ps
R
LVDS.
LVPECL.
HCSL.
CML
80% – 20%,
156.25MHz
t
Output Fall Time
F
LVDS.
LVPECL.
HCSL.
CML
156.25MHz
156.25MHz
156.25MHz
156.25MHz
—
—
55
O
Output Clock Duty Cycle
%
DC
—
55
—
55
T
Output Enable/Disable Time
—
1
—
ms
OE
©2019 Integrated Device Technology, Inc.
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July 22, 2019
XF Datasheet
Table 15. 2.5V AC Electrical Characteristics
VDD = 2.5V ±5%, TA = -40°C to +85°C, -40°C to +105°C.
Symbol
Parameter
Test Condition
LVDS, LVPECL, CML.
Minimum
Typical
Maximum Units
15
15
—
—
-15
—
—
—
—
—
—
—
2100
MHz
725
F
Output Frequency Range
HCSL.
Temperature = -40°C to +85°C.
Temperature = -40°C to +105°C.
Temperature = 25°C.
—
±25
±50
+15
±3
ppm
ppm
ppm
Frequency Stability
—
Frequency Tolerance (25°C)
Aging (1st year)
±10
—
T = 25°C.
A
Aging (10 years)
T = 25°C.
—
±10
—
A
LVDS.
Differential.
- 2.0V.
100
50
50
Output Load
LVPECL.
HCSL.
V
—
Ω
DD
To GND.
—
Output valid time after V meets minimum
specified level.
DD
T
Start-up Time
—
5
—
ms
ST
LVDS.
—
—
—
—
—
—
—
—
45
45
45
45
—
303
292
310
304
282
278
288
281
—
400
400
400
400
400
400
400
400
55
LVPECL.
HCSL.
CML
20% – 80%,
156.25MHz
t
Output Rise Time
Output Fall Time
ps
ps
R
LVDS.
LVPECL.
HCSL.
CML
80% – 20%,
156.25MHz
t
F
LVDS.
LVPECL.
HCSL.
CML
156.25MHz
156.25MHz
156.25MHz
156.25MHz
—
—
55
O
Output Clock Duty Cycle
%
DC
—
55
—
55
T
Output Enable/Disable Time
—
1
—
ms
OE
©2019 Integrated Device Technology, Inc.
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July 22, 2019
XF Datasheet
Table 16. 1.8V AC Electrical Characteristics
VDD = 1.8V ±5%, TA = -40°C to +85°C, -40°C to +105°C.
Symbol
Parameter
Test Condition
LVDS, LVPECL, CML.
Minimum
Typical
Maximum Units
15
15
—
—
—
2100
MHz
725
F
Output Frequency Range
HCSL.
Temperature = -40°C to +85°C.
Temperature = -40°C to +105°C.
Temperature = 25°C.
—
±25
±50
+15
±3
ppm
ppm
ppm
Frequency Stability
—
—
Frequency Tolerance (25°C)
Aging (1st year)
-15
—
±10
—
T = 25°C.
A
Aging (10 years)
T = 25°C.
—
—
±10
—
A
LVDS.
Differential.
To GND.
—
100
50
Output Load
Ω
LVPECL, HCSL.
—
—
Output valid time after V meets minimum
specified level.
DD
T
Start-up Time
—
5
—
ms
ST
LVDS.
—
—
—
—
—
—
—
—
45
45
45
45
—
311
312
316
313
290
297
294
289
—
450
450
450
450
450
450
450
450
55
LVPECL.
HCSL.
CML
20% – 80%,
156.25MHz
t
Output Rise Time
Output Fall Time
ps
ps
R
LVDS.
LVPECL.
HCSL.
CML
80% – 20%,
156.25MHz
t
F
LVDS.
LVPECL.
HCSL.
CML
156.25MHz
156.25MHz
156.25MHz
156.25MHz
—
—
55
O
Output Clock Duty Cycle
%
DC
—
55
—
55
T
Output Enable/Disable Time
—
1
—
ms
OE
Table 17. Phase Jitter Characteristics
VDD = 3.3V, 2.5V, 1.8V ±5%, TA = -40°C to +85°C, -40°C to +105°C.
Symbol
Parameter
Conditions
250.00MHz
Minimum
Typical
Maximum
Units
—
—
—
—
115
125
123
120
—
—
—
—
fsec
fsec
fsec
fsec
312.50MHz
625.00MHz
644.53MHz
f
Phase Jitter (12kHz – 20MHz)
JITTER
©2019 Integrated Device Technology, Inc.
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XF Datasheet
Output Waveforms
Figure 1. LVDS Output Waveforms
Output Levels /Rise Time/Fall Time Measurements
TF
TR
OUT0b
20% to 80%
OUT0
VOS
VOD
Oscillator Symmetry
VOH
OUT0b
OUT0
VOL
½ Period
Period
Figure 2. LVPECL Output Waveforms
Rise Time/Fall Time Measurements
TF
TR
VOH
OUT0b
20% to 80%
OUT0
VOL
Oscillator Symmetry
VOH
OUT0b
OUT0
VOL
½ Period
Period
©2019 Integrated Device Technology, Inc.
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XF Datasheet
Figure 3. HCSL Output Waveforms
Rise Time/Fall Time Measurements
TF
TR
VOH
OUT0b
20% to 80%
OUT0
VOL
Oscillator Symmetry
VOH
OUT0b
OUT0
VOL
½ Period
Period
Figure 4. CML Output Waveforms
Rise Time/Fall Time Measurements
TF
TR
VOH
OUT0b
20% to 80%
OUT0
VOL
Oscillator Symmetry
VOH
OUT0b
OUT0
VOL
½ Period
Period
©2019 Integrated Device Technology, Inc.
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XF Datasheet
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential output is a low impedance follower output that generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω
transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion.
Figure 5 and Figure 6 show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and
it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component
process variations.
Figure 5. 3.3V LVPECL Output Termination
Figure 6. 3.3V LVPECL Output Termination
3.3V
R3
R4
125Ω
125Ω
3.3V
3.3V
Zo = 50Ω
Zo = 50Ω
+
_
Input
R1
84Ω
R2
84Ω
©2019 Integrated Device Technology, Inc.
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XF Datasheet
Termination for 2.5V LVPECL Outputs
Figure 7 and Figure 8 show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to
V
CCO – 2V. For VCCO = 2.5V, the VCCO – 2V is very close to ground level. The R3 in Figure 8 can be eliminated and the termination is
shown in Figure 9.
Figure 7. 2.5V LVPECL Driver Termination Example
2.5V
2.5V
VCCO = 2.5V
R1
R3
250
250
50Ω
50Ω
+
–
2.5V LVPECL Driver
R2
62.5
R4
62.5
Figure 8. 2.5V LVPECL Driver Termination Example
2.5V
VCCO = 2.5V
50Ω
+
50Ω
–
2.5V LVPECL Driver
R1
50
R2
50
Figure 9. 2.5V LVPECL Driver Termination Example
2.5V
VCCO = 2.5V
50Ω
+
50Ω
–
2.5V LVPECL Driver
R1
50
R2
50
R3
18
©2019 Integrated Device Technology, Inc.
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XF Datasheet
LVDS Driver Termination
For a general LVDS interface, the recommended value for the termination impedance (ZT) is between 90Ω and 132Ω. The actual value
should be selected to match the differential impedance (Z0) of your transmission line. A typical point-to-point LVDS design uses a 100Ω
parallel resistor at the receiver and a 100Ω differential transmission-line environment. In order to avoid any transmission-line reflection
issues, the components should be surface mounted and must be placed as close to the receiver as possible. IDT offers a full line of LVDS
compliant devices with two types of output structures: current source and voltage source.
The standard termination schematic as shown in Figure 10 can be used with either type of output structure. Figure 11, which can also be
used with both output types, is an optional termination with center tap capacitance to help filter common mode noise. The capacitor value
should be approximately 50pF. If using a non-standard termination, it is recommended to contact IDT and confirm if the output structure is
current source or voltage source type. In addition, since these outputs are LVDS compatible, the input receiver’s amplitude and
common-mode input range should be verified for compatibility with the output.
Figure 10. Standard LVDS Termination
Figure 11. Optional LVDS Termination
©2019 Integrated Device Technology, Inc.
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XF Datasheet
Recommended Termination for HCSL Outputs
Figure 12 is the recommended source termination for applications where the driver and receiver will be on a separate PCBs. This
termination is the standard for PCI Express™ and HCSL output types. All traces should be 50Ω impedance single-ended or 100Ω
differential. Figure 13 is the recommended termination for applications where a point-to-point connection can be used. A point-to-point
connection contains both the driver and the receiver on the same PCB. With a matched termination at the receiver, transmission-line
reflections will be minimized. In addition, a series resistor (Rs) at the driver offers flexibility and can help dampen unwanted reflections.
The optional resistor can range from 0Ω to 33Ω. All traces should be 50Ω impedance single-ended or 100Ω differential.
Figure 12. Recommended Source Termination (where the driver and receiver will be on separate PCBs)
Rs
0.5" Max
L1
0-0.2"
L2
1-14"
L4
0.5 - 3.5"
L5
22 to 33 +/-5%
L1
L2
L4
L5
PCI Express
Connector
PCI Express
Driver
PCI Express
Add-in Card
0-0.2" L3
L3
49.9 +/- 5%
Rt
Figure 13. Recommended Termination (where a point-to-point connection can be used)
Rs
0.5" Max
L1
0-18"
L2
0-0.2"
L3
0 to 33
0 to 33
L1
L2
L3
PCI Express
Driver
49.9 +/- 5%
Rt
CML Termination
Figure 14 shows an example of the termination for a CML driver. In this example, the transmission line characteristic impedance is 50Ω.
The R1 and R2 50Ω matched load terminations are pulled up to VDDO. The matched loads are located close to the receiver.
Figure 14. CML Termination Example
VDDO
VDDO
R1
50
R2
50
Zo = 50
Zo = 50
CML Driver
©2019 Integrated Device Technology, Inc.
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XF Datasheet
Package Outline Drawings
The package outline drawings are appended at the end of this document and are accessible from the link below. The package information
is the most current data available.
www.idt.com/document/psc/njg12-package-outline-drawing-200-x-250-x-100-mm-body-epad-080-x-190-mm-040mm-pitch-dfn
Marking Diagram
▪ Lines 1 indicates the following:
• “ABC” denotes the truncated first three digits of the frequency code (e.g., 156).
• “-YW” denotes the last digit of the year and week when the part was assembled.
▪ Line 2 indicates the following:
ABC-YW
$PF**
• “$” denotes the mark location code.
• “PF” denotes the package and frequency codes, where “P” = package code and “F” = frequency code.
• “**” denotes the sequential lot number.
Ordering Information
XF
L
2
3
5
125.000000
I
Family and ASIC
Output Type
Package
Voltage
Precision
Frequency
Temperature Range
I: Industrial range– 40to +85°C
K: Extended industrial range– 40to +105°C
1: 1.8 VDC ±5%
2: 2.5 VDC ±5%
3: 3.3 VDC ±5%
2: 2.5 x 2.0 mm
C: CML
L: LVDS
P: LVPECL
N: HCSL
125.000000 Listed in MHz to 6 digits
015.000000MHz to 999.999999MHz
F00.000000 to F99.999999 1500MHz to 1599.999MHz
G00.000000 to G99.999999 1600MHz to 1699.999MHz
H00.000000 to H99.999999 1700MHz to 1799.999MHz
I00.000000 to I99.999999 1800MHz to 1899.999MHz
J00.000000 to J99.999999 1900MHz to 1999.999MHz
K00.000000 to K99.999999 2000MHz to 2099.999MHz
XF: 150fs jitter
5: ±50 ppm (K only)
6: ±25 ppm (I only)
©2019 Integrated Device Technology, Inc.
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XF Datasheet
Revision History
Revision Date
Description of Change
July 22, 2019
May 22, 2019
April 3, 2019
Updated LVDS Differential Output Voltage minimum value from 0.28V to 0.30V.
Changed 3.3V, 2.5V, and 1.8V LVPECL current consumption conditions value from 670MHz to 2.1GHz.
Initial release
Corporate Headquarters
Sales
Tech Support
6024 Silver Creek Valley Road
San Jose, CA 95138 USA
www.IDT.com
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com/go/sales
www.IDT.com/go/support
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time,
without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same
way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability
of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not
convey any license under intellectual property rights of IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be rea-
sonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property
of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc. All rights reserved.
©2019 Integrated Device Technology, Inc.
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July 22, 2019
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