IDTQS34XST253Q38 [IDT]
Multiplexer And Demux/Decoder, 8-Func, 1 Line Input, 4 Line Output, True Output, CMOS, PDSO80, 0.150 INCH, MILLIPAK, DIP-80;
| 型号： | IDTQS34XST253Q38 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Multiplexer And Demux/Decoder, 8-Func, 1 Line Input, 4 Line Output, True Output, CMOS, PDSO80, 0.150 INCH, MILLIPAK, DIP-80 光电二极管 逻辑集成电路 |
| 文件： | 总10页 (文件大小：128K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
QUICKSWITCH® PRODUCTS
HIGH-SPEED CMOS
IDTQS34XST253
SYNCHROSWITCH™ 32:8 MUX/DEMUX
WITH ACTIVE TERMINATORS
DESCRIPTION:
FEATURES :
−
−
−
−
−
−
−
−
−
−
−
−
−
Enhanced N channel FET with no inherent diode to Vcc
Bidirectional signal flow
Flow-through pinout
Zero propagation delay, zero ground bounce
8 banks of 4:1 Mux/Demux
Port select synchronous to the clock
Clock enable and asynchronous enable
“Bus-hold” terminators on the Demux side
Undershoot clamp diodes on all switch and control pins
Asynchronous SEL option
TheQS34XST253isahigh-speedCMOS 32:8 multiplexer/demultiplexer
withactiveterminators(bus-holdcircuits)onthedemuxside. Itisorganized
as four independent dual 4:1 mux/demux blocks. Port selection and
connection, controlled by SEL signals, can be either asynchronous or
synchronous. In the synchronous mode, the A, B, C, or D port to Y port
connectionis updatedonthe risingedge ofthe inputclockCLK. Once the
port-to-portconnectionismade,dataflowcanbebi-directionalwithatypical
250ps propagation delay through the switch. Clock Enable, overriding
Asynchronous Enable, and Asynchronous Select controls provide addi-
tionaldesignflexibility.
Break-before-make feature
The bus-hold circuits latch the last data driven on the demux side,
providinginfiniteholdtimeandglitch-freesignaltransitions. Synchronous
controlsandbus-holdeasetimingconstraintsinmanyhighspeeddatamux/
demux applications, such as bank interleaving. The QS34XST253 is
available inthe space-saving,80-pindual-in-line MillipaQpackage.
Available in 80-pin MillipaQ (Q3)
Bus-hold eliminates floating bus lines and reduces static power
consumption
AP P LICATIONS
The QS34XST253 is characterized for operation at -40°C to +85°C.
−
Video, audio, graphics switching, muxing
FUNCTIONAL BLOCK DIAGRAM
R
=
T
OEn0
OEn1
SELn0
SELn1
CLKn
CONTROL
LOGIC
CLKENn
SYNCn
An0
Bn0
Cn0
Dn0
An1
Bn1
Cn1
Dn1
T
T
T
T
T
T
T
T
Yn0
Yn1
NOTE: One of four blocks shown.
INDUS TRIAL TEMP ERATURE RANGE
NOVEMBER 1 9 9 9
1
c
1999 Integrated Device Technology, Inc.
DSC-5531/-
IDTQS34XST253
HIGH-SPEEDCMOSSYNCHROSWITCH32:8MUX/DEMUX
INDUSTRIALTEMPERATURERANGE
(1 )
P IN CONFIGURATION
ABS OLUTE MAXIMUM RATINGS
Symbol
Description
Supply Voltage to Ground
DC Switch Voltage VS
Max.
– 0.5 to +7
– 0.5 to +7
– 0.5 to +7
-3
Unit
V
(2)
VTERM
1
2
3
80
79
78
77
NC
A00
Vcc
(3)
V
VTERM
OE00
OE01
SEL00
SEL01
Y00
(3)
DC Input Voltage VIN
V
VTERM
A01
B00
B01
VAC
AC Input Voltage (pulse width ≤20ns)
DC Output Current
V
4
5
IOUT
PMAX
TSTG
120
mA
W
76
Maximum Power Dissipation (TA = 85°C)
Storage Temperature
1.16
6
C00
C01
D00
75
74
73
– 65 to +150 °C
7
Y01
NOTES:
8
CLKEN0
CLK0
SYNC0
Vcc
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. Vcc Terminals.
9
72
71
70
69
68
D01
GND
NC
10
11
12
13
14
15
16
17
18
A10
OE10
OE11
SEL10
SEL11
Y10
A11
3. All terminals except Vcc.
B10
67
66
65
B11
CAP ACITANCE
C10
C11
(TA = +25OC, f = 1.0MHz, VIN = 0V, VOUT = 0V)
64
Y11
Pins
Typ.
Max. (1)
Unit
D10
63
62
CLKEN1
CLK1
SYNC1
Vcc
Control Inputs
4
5
pF
19
20
21
22
23
D11
Quickswitch Channels
(Switch OFF)
Demux
Mux
6
7
pF
pF
61
60
59
58
57
56
GND
13
15
NC
A20
NOTE:
OE20
OE21
SEL20
SEL21
Y20
1. This parameter is guaranteed at characterization but not production
tested.
A21
B20
B21
24
25
26
P IN DES CRIP TION
C20
C21
55
54
53
52
Pin Names
I/O
Description
27
28
29
An0 - Dn0
I/O
Demux Ports
Demux Ports
Mux Ports
Y21
D20
An1 - Dn1
Yn0, Yn1
I/O
CLKEN2
CLK2
SYNC2
Vcc
D21
I/O
SELn0, SELn1
CLKn
I
I
I
I
I
Select Inputs
Clock
GND
NC
30
31
32
51
50
49
CLKENn
Clock Enable
A30
A31
B30
B31
OE30
OE31
SEL30
SEL31
Y30
33
OEn0, OEn1
SYNCn
Output Enable
48
47
46
Synchronous Selection Enable
34
35
36
37
38
39
40
45
44
43
42
41
C30
C31
Y31
D30
D31
CLKEN3
CLK3
SYNC3
GND
MILLIPAQ
TOP VIEW
2
IDTQS34XST253
HIGH-SPEEDCMOSSYNCHROSWITCH32:8MUX/DEMUX
INDUSTRIALTEMPERATURERANGE
FUNCTION TABLE(1 )
Control Inputs
MUX Ports
Yn1
SYNCn
OEn0
L
OEn1
L
CLKn CLKENn
SELn0
SELn1
Yn0
An0
Bn0
Cn0
Dn0
L
L
L
L
L
L
↑
↑
↑
↑
↑
↑
L
L
L
L
L
H
L
H
L
L
L
An1
L
L
Bn1
L
L
H
H
X
X
Cn1
L
L
H
X
X
Dn1
H
H
Hold Previous Data (2) (Switch OFF)
Hold Previous Data (2) (Switch OFF)
L
L
Hold Previous Mux connection (3)
Hold Previous Mux connection (3)
(Switch ON)
(Switch ON)
L
H
H
H
H
H
L
L
L
L
H
H
L
L
L
L
H
↑
H
X
X
X
X
X
X
L
X
L
Hold Previous Data (4) (Switch OFF)
Hold Previous Data (4) (Switch OFF)
X
X
X
X
X
An0
An1
H
L
L
Bn0
Bn1
H
H
X
Cn0
Cn1
H
X
Dn0
Dn1
H
Hold Previous Data (Switch OFF)
Hold Previous Data (Switch OFF)
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
↑
= Low-to-High Transition
2. Mux switches are turned off and the terminators (last value latches) hold the previous data state. The port connections can be changed by the SEL
input.
3. The contents of the “Mux select register” are unchanged and the previous Mux connection is unchanged. The output (Mux port) data state will
depend on the present data state of the input (Demux port).
4. The contents of the “Mux select register” are unchanged and the last value latch holds the previous data state.
(1 )
CONTROL LOGIC
OEn0
2:1
D
Q
MUX
S0
2:1
SELn0
To Bank n0 Switches
MUX
DECODE
LOGIC
AND
CLKENn
CLKn
SWITCH
CONTROL
SYNCn
2:1
S1
To Bank n1 Switches
SELn
1
MUX
2:1
D
Q
MUX
OEn1
NOTE:
1. One of four blocks.
3
IDTQS34XST253
HIGH-SPEEDCMOSSYNCHROSWITCH32:8MUX/DEMUX
INDUSTRIALTEMPERATURERANGE
DC ELECTRICAL CHARACTERIS TICS OVER OP ERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: TA = -40°C to +85°C, VCC = 5.0V ± 10%
Symbol
Parameter
Input HIGH Voltage
Test Conditions
Min. Typ.(1) Max.
Unit
VIH
Guaranteed Logic HIGH for Control Pins
2
—
—
—
7
—
0.8
V
VIL
IIN
Input LOW Voltage
Guaranteed Logic LOW for Control Pins
0V ≤ VIN ≤ Vcc
—
—
—
—
60
V
µA
Ω
Input Leakage Current (Control Inputs)
Switch On Resistance (2,3)
±1
RON
Vcc = Min., VIN = 0V, ION = 30mA
Vcc = Min., VIN = 2.4V, ION = 15mA
9
10
—
—
—
—
13
IBHL
IBHH
IBH
Input Hold Current (4,5)
(A, B, C, D)
Input Current (7)
Vcc = 4.5V
Switch OFF
Vcc = Max.
VIN = 0.8V
—
µA
µA
VIN = 2V
—
60
–
VIN = 0V or Vcc
0.8 < VIN < 2V
—
±20
±500(6)
(A, B, C, D)
—
NOTES:
1. Typical values are at VCC = 5.0V, TA = 25°C.
2. Measured by voltage drop between A/B and Y pin at indicated current through the switch.
3. RON guaranteed but not production tested.
4. IBHL is the minimum sustaining “sink” current at the input for VIN = 0.8V. This parameter signifies the latching capability of the bus-hold circuit in
logic LOW state.
5. IBHH is the minimum sustaining “source” current at the input for VIN = 2V. This parameter signifies the latching capability of the bus-hold circuit in
logic HIGH state.
6. An external driver must provide at least IBH during transition to guarantee that the bus-hold input will change states.
7. IBH is the magnitude of the input current specified under two conditions:
a) Input voltage at GND or Vcc. This indicates the input current under steady-state condition.
b) Input voltage between 0.8V and 2V (TTL input threshold range). This indicates the maximum input current during transient condition. The
driver connected to the input must overcome this current requirement in order to switch the logic state of the bus-hold circuit.
TYP ICAL ON RES IS TANCE vs VIN AT VCC = 5 V
16
14
RON
(ohms)
12
10
8
6
4
2
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VIN
(Volts)
4
IDTQS34XST253
HIGH-SPEEDCMOSSYNCHROSWITCH32:8MUX/DEMUX
INDUSTRIALTEMPERATURERANGE
P OWER S UP P LY CHARACTERIS TICS
Symbol
Parameter
Test Conditions(1)
Max.
Unit
ICCQ
Quiescent Power Supply Current
VCC = Max., VIN = GND or Vcc, f = 0
12
µA
∆ICC
Power Supply Current per Control Input HIGH (2)
Dynamic Power Supply Current per MHz(3)
VCC = Max., VIN = 3.4V, f = 0
1.5
mA
ICCD
VCC = Max., A/B/C/D and Y pins open
Control Input Toggling at 50% Duty Cycle
0.25
mA/MHz
NOTES:
1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics.
2. Per TLL driven control input. (VIN = 3.4V, Control Pins only.) A/B/C/D and Y pins do not contribute to ∆Icc
.
3. This current applies to the control inputs only and represents the current required to switch internal capacitance at the specified frequency. The
A/B/C/D and Y inputs generate no significant AC or DC currents as they transition. This parameter is guaranteed but not production tested.
S WITCHING CHARACTERIS TICS OVER OP ERATING RANGE
TA = -40°C to +85°C, VCC = 5.0V ± 10%
Ω
CLOAD = 50pF, RLOAD = 500 unless otherwise noted.
Min.
Typ.
0.25
—
Max.
Symbol
tPLH
Parameter
Unit
Data Propagation Delay (1,2)
A/B/C/D to Y, Y to A/B/C/D
—
—
ns
tPHL
tSEC
Clock Enable to Clock Setup Time
Clock Enable to Clock Hold Time
Clock to Switch Turn-On Delay (3)
Asynchronous Select to Switch Turn-On Delay (3)
Clock Pulse Width (High)
—
—
3
0
ns
ns
ns
ns
ns
ns
ns
ns
tHEC
tCSO
tASO
tW
—
—
0.5
0.5
3
7
—
7
—
—
tSCS
tHCS
SEL to Clock Setup Time
—
—
—
3
SEL to Clock Hold Time
—
0
tPZL
tPZH
tPLZ
Asynchronous Enable to Switch Turn-On Delay (3)
—
1.5
5.2
4.8
Asynchronous Enable to Switch Turn-Off Delay (1,3)
—
1.5
ns
tPHZ
NOTES:
1. This parameter is guaranteed but not production tested.
2. The bus switch contributes no propagation delay other than the RC delay of the ON resistance of the switch and the load capacitance. The time
constant for the switch alone is of the order of 0.25ns for CL = 50pF. Since this time constant is much smaller than the rise and fall times of typical
driving signals, it adds very little propagation delay to the system. Propagation delay of the bus switch, when used in a system, is determined by the
driving circuit on the driving side of the switch and its interaction with the load on the driven side.
3. Minimums guaranteed but not production tested.
5
IDTQS34XST253
HIGH-SPEEDCMOSSYNCHROSWITCH32:8MUX/DEMUX
INDUSTRIALTEMPERATURERANGE
TIMING WAVEFORMS - S YNCHRONOUS MODE, DEMUX FUNCTION
SYNC
tSEC tHEC
CLKEN
CLK
SEL
tSCS tHCS
tSCS tHCS
OE
Port Y
DATA 0
DATA 2
DATA 1
tPLH, tPHL
tCSO
DATA
1
Port A
Port D
DATA 0
HOLD PREVIOUS DATA, DATA 1
tPLH, tPHL
INVALID DATA
tCSO
HOLD PREVIOUS DATA, DATA 2
INVALID DATA
DATA 1 DATA 2
EXAMPLE:PORTYTOPORTA/PORTD
6
IDTQS34XST253
HIGH-SPEEDCMOSSYNCHROSWITCH32:8MUX/DEMUX
INDUSTRIALTEMPERATURERANGE
TIMING WAVEFORMS - S YNCHRONOUS MODE, MUX FUNCTION
SYNC
SEC HEC
t
t
CLKEN
CLK
tSCS tHCS
SCS HCS
t
t
SEL0, SEL1
Port A
DATA1
DATA2
Port B
INVALID DATA
tCSO
DATA3
DATA4
CSO
t
tPLH,
PLH,
t
tPHL
PHL
t
DATA1
INVALID DATA
DATA2
DATA3
DATA4
Port Y
EXAMPLE:PORTA/PORTDTOPORTY
7
IDTQS34XST253
HIGH-SPEEDCMOSSYNCHROSWITCH32:8MUX/DEMUX
INDUSTRIALTEMPERATURERANGE
TIMING WAVEFORMS - AS YNCHRONOUS MODE, MUX FUNCTION
SYNC
SEL
OE
INVALID
DATA
Port A
DATA1
DATA2
tPLH, tPHL
tPLH, tPHL
Port D
Port Y
INVALID DATA
INVALID DATA
DATA3
tASO
tPZL, tPZH
tPLZ, tPHZ
DATA1
DATA2
DATA3
DATA3
EXAMPLE:PORTA/PORTDTOPORTY
8
IDTQS34XST253
HIGH-SPEEDCMOSSYNCHROSWITCH32:8MUX/DEMUX
INDUSTRIALTEMPERATURERANGE
ACTIVE TERMINATOR OR BUS -HOLD CIRCUIT
The Active Terminator circuit, also known as the bus-hold circuit, is configured as a “weak latch” with positive feedback. When connected to a
TTL or CMOS input port, the bus-hold circuit holds the last logic state at the input when the input is “disconnected” from the driver. When the output
of a device connected to such an input attempts a logic level transition, it will overdrive the bus-hold circuit. The primary benefit of a bus-hold circuit
is that it prevents CMOS inputs from floating, a situation which should be avoided to prevent spurious switching of inputs and unnecessary power
dissipation. Bus-hold is a better solution than the traditional approach of using resistive termination to Vcc or GND to prevent bus floating, because
the bus-hold circuit does not consume any static power.
V-I CHARACTERIS TICS OF BUS -HOLD CIRCUIT
IBH
+500
Sinking
Current
( + )
Voltage
+20 IBH
IBHL
IBH
+60
+20
+60 IBHL
VT
– 20 IBH
– 20
– 60
Vcc
IBHH
– 60 IBHL
VIH
VIL
Sourcing
Current
( – )
IBH
– 500
0.8V
2V
VT ≡ Threshold Voltage ≈ 1.5V
VIL ≈ .8 VIH ≈ 2V
This figure shows the input V-I characteristics of a typical bus-hold implementation. The input characteristics resemble a resistor. As the input
voltage is increased from 0 volts, the input “sink” current increases linearly. When the TTL threshold of the circuit is reached (typically 1.5 volts), the
latch changes the logic state due to positive feedback and the direction of the current is reversed. As the input voltage is further increased towards
Vcc, the input “source” current begins to decrease, reaching the lowest level at VIN = Vcc.
9
IDTQS34XST253
HIGH-SPEEDCMOSSYNCHROSWITCH32:8MUX/DEMUX
INDUSTRIALTEMPERATURERANGE
ORDERING INFORMATION
XX
IDTQS
XXXXX
X
Package
Process
Device Type
Blank
Industrial (-40°C to +85°C)
Q3
150 mil MillipaQ
High Speed CMOS SynchroSwitch 32:8
Mux/Demux with Active Terminators
34XST253
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
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www.idt.com*
*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.
The IDT logo, QuickSwitch, and SynchroSwitch are registered trademarks of Integrated Device Technology, Inc.
10
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