IDTQS34XST257Q3 [IDT]
Multiplexer And Demux/Decoder, 4-Func, 8 Line Input, 4 Line Output, True Output, CMOS, PDSO80, 0.150 INCH, MILLIPAK, DIP-80;
| 型号： | IDTQS34XST257Q3 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Multiplexer And Demux/Decoder, 4-Func, 8 Line Input, 4 Line Output, True Output, CMOS, PDSO80, 0.150 INCH, MILLIPAK, DIP-80 光电二极管 逻辑集成电路 |
| 文件： | 总10页 (文件大小：123K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
QUICKSWITCH® PRODUCTS
IDTQS34XST257
HIGH-SPEED CMOS
SYNCHROSWITCH™ 32:16 MUX/
DEMUX WITH ACTIVE TERMINATORS
FEATURES:
DESCRIPTION:
−
−
−
−
−
−
−
−
−
−
−
−
−
Enhanced N channel FET with no inherent diode to Vcc
Bidirectional signal flow
Flow-through pinout
Zero propagation delay, zero ground bounce
16 banks of 2:1 Mux/Demux
Port select synchronous to the clock
Clock enable and Asynchronous enable
“Bus-hold” terminators on the Demux side
Undershoot clamp diodes on all switch and control pins
Asynchronous SEL option
The QS34XST257 is a high-speed CMOS quad 32:16 multiplexer/
demultiplexerwithactiveterminators(bus-holdcircuits)onthedemuxside.
It is organized as four independent quad 2:1 mux/demux blocks. Port
selectionandconnection, controlledbySELsignals, canbe eitherasyn-
chronous orsynchronous. Inthe synchronous mode, the AorBporttoY
portconnectionis updatedontherisingedgeoftheinputclockCLK. Once
the port-to-portconnectionis made,data flowcanbe bi-directionalwitha
typical 250ps propagation delay through the switch. Clock Enable,
overriding Asynchronous Enable, and Asynchronous Select controls
provide additionaldesignflexibility.
Break-before-make feature
The bus-hold circuits latch the last data driven on the demux side,
providinginfiniteholdtimeandglitch-freesignaltransitions. Synchronous
controlsandbus-holdeasetimingconstraintsinmanyhighspeeddatamux/
demux applications, such as bank interleaving. The QS34XST257 is
available inthe space-saving,80-pindual-in-line MillipaQpackage.
Available in 80-pin MillipaQ (Q3)
Bus-hold eliminates floating bus lines and reduces static power
consumption
APPLICATIONS:
The QS34XST257 is characterized for operation at -40°C to +85°C.
−
Memory Interleaving
FUNCTIONALBLOCKDIAGRAM
R
=
T
SELn
CLKn
CONTROL
CLKENn
LOGIC
OEn
SYNCn
An0
Bn0
An1
Bn1
An2
Bn2
An3
Bn3
T
T
T
T
T
T
T
T
Yn0
Yn1
Yn2
Yn3
NOTE: One of four blocks shown.
INDUSTRIAL TEMPERATURE RANGE
NOVEMBER 1999
1
c
1999 Integrated Device Technology, Inc.
DSC-5532/-
IDTQS34XST257
HIGH-SPEEDCMOSSYNCHROSWITCH32:16MUX/DEMUX
INDUSTRIALTEMPERATURERANGE
ABSOLUTE MAXIMUM RATINGS (1)
PINCONFIGURATION
Symbol
Description
Supply Voltage to Ground
DC Switch Voltage VS
Max.
– 0.5 to +7
– 0.5 to +7
– 0.5 to +7
-3
Unit
V
1
2
80
79
78
77
NC
A00
A01
A02
A03
B00
B01
B02
B03
GND
NC
Vcc
(2)
VTERM
OE0
(3)
V
VTERM
3
SEL0
Y00
(3)
DC Input Voltage VIN
V
VTERM
4
5
VAC
AC Input Voltage (pulse width ≤20ns)
DC Output Current
V
76
Y01
IOUT
PMAX
TSTG
120
mA
W
6
75
74
73
Y02
Maximum Power Dissipation (TA = 85°C)
Storage Temperature
1.16
7
Y03
– 65 to +150 °C
8
CLKEN0
CLK0
SYNC0
Vcc
NOTES:
9
72
71
70
69
68
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. Vcc Terminals.
10
11
12
13
14
15
16
17
18
A10
A11
A12
A13
B10
B11
B12
B13
GND
NC
OE1
SEL1
Y10
67
66
65
3. All terminals except Vcc.
Y11
Y12
CAPACITANCE
64
Y13
(TA = +25OC, f = 1.0MHz, VIN = 0V, VOUT = 0V)
63
62
CLKEN1
CLK1
SYNC1
Vcc
Pins
Typ.
Max. (1)
Unit
19
20
Control Inputs
4
5
pF
61
Quickswitch Channels
(Switch OFF)
Demux
Mux
5
7
7
9
pF
pF
21
22
23
60
59
58
57
A20
A21
A22
A23
B20
B21
B22
B23
GND
NC
NOTE:
OE2
1. This parameter is guaranteed at characterization but not tested.
SEL2
Y20
24
25
26
56
55
54
53
52
PIN DESCRIPTION
Y21
Pin Names
I/O
Description
Demux Port A
Y22
27
28
29
An0 - An3
I/O
Y23
Bn0 - Bn3
Yn0 - Yn3
SELn
I/O
Demux Port B
Mux Port Y
CLKEN2
CLK2
SYNC2
Vcc
I/O
I
I
I
I
I
Select Input
30
31
32
51
50
CLKn
Clock
49
CLKENn
OEn
Clock Enable
A30
A31
A32
A33
B30
B31
B32
B33
GND
OE3
Output Enable
Synchronous Selection Enable
33
48
47
46
SEL3
Y30
SYNCn
34
35
Y31
36
37
38
39
40
45
44
43
42
41
Y32
Y33
CLKEN3
CLK3
SYNC3
MILLIPAQ
TOP VIEW
2
IDTQS34XST257
HIGH-SPEEDCMOSSYNCHROSWITCH32:16MUX/DEMUX
INDUSTRIALTEMPERATURERANGE
FUNCTION TABLE(1)
Control Inputs
Port Status
Yn2
Function
SYNC
OEn
L
CLKn CLKENn SELn
Yn0
An0
Bn0
Yn1
An1
Bn1
Yn3
An3
Bn3
L
L
L
L
L
H
H
↑
L
L
L
H
X
X
X
L
An2
Bn2
Select Port A
L
↑
Select Port B
H
L
↑
L
No change in Mux connection
No change in Mux connection
No change in Mux connection
Hold Previous Data (2) (Switch OFF)
Hold Previous Mux connection (3) (Switch ON)
Hold Previous Data (4) (Switch OFF)
Select Port A
↑
H
H
X
X
X
H
L
↑
X
X
X
An0
Bn0
An1
Bn1
An2
Bn2
An3
Bn3
L
H
X
Select Port B
H
H
No change in Mux connection
Hold Previous Data (Switch OFF)
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
↑
= Low-to-High Transition
2. Mux switches are turned off and the terminators (last value latches) hold the previous data state. The port connection can be changed by the SEL
input.
3. The contents of the “Mux select register” are unchanged and the previous Mux connection is unchanged. The output (Mux port) data state will
depend on the present data state of the input (Demux port).
4. The contents of the “Mux select register” are unchanged and the last value latches hold the previous data state.
CONTROL LOGIC (1)
1
2:1
D
Q
0
MUX
2:1
MUX
0
SELn
To Port B Switches
1
CLKENn
CLKn
SYNCn
OEn
To Port A Switches
NOTE:
1. One of four blocks.
3
IDTQS34XST257
HIGH-SPEEDCMOSSYNCHROSWITCH32:16MUX/DEMUX
INDUSTRIALTEMPERATURERANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: TA = -40°C to +85°C, VCC = 5.0V ± 10%
Symbol
Parameter
Input HIGH Voltage
Test Conditions
Min. Typ.(1) Max.
Unit
VIH
Guaranteed Logic HIGH for Control Pins
2
—
—
0.01
7
—
0.8
V
VIL
IIN
Input LOW Voltage
Guaranteed Logic LOW for Control Pins
0V ≤ VIN ≤ Vcc
—
—
—
—
60
V
µA
Ω
Input Leakage Current (Control Inputs)
Switch On Resistance (2,3)
±1
RON
Vcc = Min., VIN = 0V, ION = 30mA
Vcc = Min., VIN = 2.4V, ION = 15mA
9
10
13
IBHL
IBHH
IBH
Input Hold Current (4,5)
(A or B port)
Input Current (7)
Vcc = Min.
Switch OFF
Vcc = Max.
VIN = 0.8V
—
—
—
—
—
µA
µA
VIN = 2V
—
60
–
VIN = 0V or Vcc
0.8 < VIN < 2V
—
±20
±500(6)
A and B port
—
NOTES:
1. Typical values are at VCC = 5.0V, TA = 25°C.
2. Measured by voltage drop between A/B and Y pin at indicated current through the switch.
3. RON guaranteed but not production tested.
4. IBHL is the minimum sustaining “sink” current at the input for VIN = 0.8V. This parameter signifies the latching capability of the bus-hold circuit in
logic LOW state.
5. IBHH is the minimum sustaining “source” current at the input for VIN = 2V. This parameter signifies the latching capability of the bus-hold circuit in
logic HIGH state.
6. An external driver must provide at least IBH during transition to guarantee that the bus-hold input will change states.
7. IBH is the magnitude of the input current specified under two conditions:
a) Input voltage at GND or Vcc. This indicates the input current under steady-state condition.
b) Input voltage between 0.8V and 2V (TTL input threshold range). This indicates the maximum input current during transient condition. The
driver connected to the input must overcome this current requirement in order to switch the logic state of the bus-hold circuit.
TYPICAL ON RESISTANCE vs VIN AT VCC = 5V
16
14
RON
(ohms)
12
10
8
6
4
2
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VIN
(Volts)
4
IDTQS34XST257
HIGH-SPEEDCMOSSYNCHROSWITCH32:16MUX/DEMUX
INDUSTRIALTEMPERATURERANGE
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
Max.
Unit
ICCQ
Quiescent Power Supply Current
VCC = Max., VCTRL = GND or Vcc, f = 0
12
mA
∆ICC
Power Supply Current per Control Input HIGH (2)
Dynamic Power Supply Current per MHz(3)
VCC = Max., VIN = 3.4V, f = 0
1.5
mA
ICCD
VCC = Max., A/B and Y pins open
0.25
mA/MHz
Control Input Toggling at 50% Duty Cycle
NOTES:
1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics.
2. Per TLL driven control inputs. A/B and Y pins do not contribute to ∆Icc
.
3. This current applies to the control inputs only and represents the current required to switch internal capacitance at the specified frequency. The A/B
and Y inputs generate no significant AC or DC currents as they transition. This parameter is guaranteed but not production tested.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
TA = -40°C to +85°C, VCC = 5.0V ± 10%
Ω
CLOAD = 50pF, RLOAD = 500 unless otherwise noted.
Min.
Typ.
0.25
—
Max.
Symbol
tPLH
Parameter
Unit
Data Propagation Delay (1,2)
A/B to Y, Y to A/B
—
—
ns
tPHL
tSEC
Clock Enable to Clock Setup Time
Clock Enable to Clock Hold Time
Clock to A, B Switch Turn-On Delay (3)
Asynchronous Select to A, B Switch Turn-On Delay (3)
Clock Pulse Width HIGH
—
—
3
0
ns
ns
ns
ns
ns
ns
ns
ns
tHEC
tCSO
tASO
tW
—
—
0.5
0.5
3
7
—
7
—
—
tSCS
tHCS
Clock to SEL Setup Time
—
—
—
3
Clock to SEL Hold Time
—
0
tPZL
tPZH
tPLZ
tPHZ
Asynchronous Enable to Switch Turn-On Delay (3)
—
1.5
5.2
4.8
Asynchronous Enable to Switch Turn-Off Delay (1,3)
—
1.5
ns
NOTES:
1. This parameter is guaranteed but not tested.
2. The bus switch contributes no propagation delay other than the RC delay of the ON resistance of the switch and the load capacitance. The time
constraint for the switch alone is of the order of 0.25ns for CL = 50pF. Since this time constant is much smaller than the rise and fall times of typical
driving signals, it adds very little propagation delay to the system. Propagation delay of the bus switch, when used in a system, is determined by the
driving circuit on the driving side of the switch and its interaction with the load on the driven side.
3. Minimums guaranteed but not tested.
5
IDTQS34XST257
HIGH-SPEEDCMOSSYNCHROSWITCH32:16MUX/DEMUX
INDUSTRIALTEMPERATURERANGE
TIMING WAVEFORMS - SYNCHRONOUS MODE, DEMUX FUNCTION
SYNC
tSEC tHEC
CLKEN
CLK
SEL
tSCS tHCS
tSCS tHCS
OE
Port Y
DATA 0
DATA 2
DATA 1
tPLH, tPHL
tCSO
DATA
1
Port A
Port B
DATA 0
HOLD PREVIOUS DATA, DATA 1
tPLH, tPHL
INVALID DATA
tCSO
HOLD PREVIOUS DATA, DATA 2
INVALID DATA
DATA 1 DATA 2
6
IDTQS34XST257
HIGH-SPEEDCMOSSYNCHROSWITCH32:16MUX/DEMUX
INDUSTRIALTEMPERATURERANGE
TIMING WAVEFORMS - SYNCHRONOUS MODE, MUX FUNCTION
SYNC
SEC HEC
t
t
CLKEN
CLK
tSCS tHCS
tSCS tHCS
SEL0, SEL1
Port A
DATA1
DATA2
Port D
INVALID DATA
DATA3
DATA4
CSO
t
CSO
t
PLH,
t
tPLH,
tPHL
PHL
t
DATA1
INVALID DATA
DATA2
DATA3
DATA4
Port Y
7
IDTQS34XST257
HIGH-SPEEDCMOSSYNCHROSWITCH32:16MUX/DEMUX
INDUSTRIALTEMPERATURERANGE
TIMING WAVEFORMS - ASYNCHRONOUS MODE, MUX FUNCTION
S Y N C
S E L
O E
IN V A L ID
D A T A
P o rt A
D A T A 1
D A T A 2
tP L H , tP H L
tP L H , tP H L
P o rt B
IN V A L ID D A T A
IN V A L ID D A T A
D A T A 3
tA S O
tP Z L , tP Z H
tP L Z , tP H Z
P o rt Y
D A T A 1
D A T A 2
D A T A 3
D A T A 3
8
IDTQS34XST257
HIGH-SPEEDCMOSSYNCHROSWITCH32:16MUX/DEMUX
INDUSTRIALTEMPERATURERANGE
ACTIVE TERMINATOR OR BUS-HOLD CIRCUIT
The Active Terminator circuit, also known as the bus-hold circuit, is configured as a “weak latch” with positive feedback. When connected to a
TTL or CMOS input port, the bus-hold circuit holds the last logic state at the input when the input is “disconnected” from the driver. When the output
of a device connected to such an input attempts a logic level transition, it will overdrive the bus-hold circuit. The primary benefit of a bus-hold circuit
is that it prevents CMOS inputs from floating, a situation which should be avoided to prevent spurious switching of inputs and unnecessary power
dissipation. Bus-hold is a better solution than the traditional approach of using resistive termination to Vcc or GND to prevent bus floating, because
the bus-hold circuit does not consume any static power.
V-ICHARACTERISTICSOFBUS-HOLDCIRCUIT
IBH
+500
Sinking
Current
( + )
Voltage
+20 IBH
IBHL
IBH
+60
+20
+60 IBHL
VT
– 20 IBH
– 20
– 60
Vcc
IBHH
– 60 IBHL
VIH
VIL
Sourcing
Current
( – )
IBH
– 500
0.8V
2V
VT ≡ Threshold Voltage ≈ 1.5V
VIL ≈ .8 VIH ≈ 2V
This figure shows the input V-I characteristics of a typical bus-hold implementation. The input characteristics resemble a resistor. As the input
voltage is increased from 0 volts, the input “sink” current increases linearly. When the TTL threshold of the circuit is reached (typically 1.5 volts), the
latch changes the logic state due to positive feedback and the direction of the current is reversed. As the input voltage is further increased towards
Vcc, the input “source” current begins to decrease, reaching the lowest level at VIN = Vcc.
9
IDTQS34XST257
HIGH-SPEEDCMOSSYNCHROSWITCH32:16MUX/DEMUX
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
XX
IDTQS
XXXXX
X
Package
Process
Device Type
Extended Commercial (-40°C to +85°C)
Blank
Q3
150 mil MillipaQ
34XST257
High Speed CMOS SynchroSwitch 32:16
Mux/Demux with Active Terminators
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com*
*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.
The IDT logo, QuickSwitch, and SynchroSwitch are registered trademarks of Integrated Device Technology, Inc.
10
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