IDTAMB0480RH8 [IDT]
Memory IC;
| 型号： | IDTAMB0480RH8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Memory IC |
| 文件： | 总15页 (文件大小：252K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDTAMB0480
PRODUCT
BRIEF
ADVANCED MEMORY BUFFER
FOR FULLY BUFFERED DIMM
MODULES
FEATURES:
DESCRIPTION:
• Advanced Memory Buffer for Fully buffered DIMMs
• 3.2 and 4 Gbit/s serial speeds (DDR2-533 and 667 DRAM)
• Support for up to eight DIMMs per channel
• Repeater Mode for extending FB-DIMM links
The fully buffered dual in-line memory module (FB-DIMM) is the next
generationmemoryarchitecturetomeetthegrowingmemoryrequirementof
serversandworkstations.TheIDTAdvancedMemoryBuffer(AMB)chipisthe
essential building block located on each FB-DIMM. The IDT AMB receives
• Northbound and Southbound single lane fail over and channel commandsanddatafromthehostcontrollertocontrolandwrite/readdatato/
error detection
fromtheDRAMsontheDIMM.Commandsandwritedataaresentsouthbound
fromthehostcontrollertoAMBsinadaisychainfashionandinterpretedbythe
targetAMB.StatusandreaddataaresentnorthboundfromAMBstothehost
controlleralsoinadaisychainfashion,passingthroughnon-targetAMBs.This
uniquechannelstructurealleviatesbufferloadingissuescommoninregistered
DIMMtechnology,enablingdesignerstousealargenumberofDIMMswithin
asinglesystem.
IDTAMB0480complieswiththelatest JEDECdefinedFB-DIMMArchitecture
andProtocolSpecificationand supportsDDR2-533andDDR2-667DRAM.
It also enables serial data transfer at 3.2 and 4.0Gbps. The IDTAMB0480
supportsservers,workstations,storagedevicesandcommunicationapplications
thatsupportthenextgenerationFB-DIMMarchitecture.
• Voltage and Timing margin high-speed I/O test capability
• Fully Supports the FB-DIMM configuration register set
• Test features supported include:
- Integrated thermal sensor and status indicator
- Supports MEMBIST, IBIST and Virtual Host mode
- Transparent mode and direct access mode for DRAM testing
• Complies with JEDEC Architecture and Protocol Specification
• Available in 655 ball FCBGA package
EXPANDEDFEATURES:
• Wide range DDR Timing Control
• Superfine adjustment for DDR timing
• Wide range of DDR slew rate control
• Slew rate controllable independent of output impedance
• High speed SMBus in test mode
• IBIST IDT PRBS Generator
FDBMEMORYCHANNEL
Up to 8 modules
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
14
Host
IDT
AMB
IDT
AMB
IDT
AMB
IDT
AMB
Memory
Controller
10
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIAL TEMPERATURE RANGE
APRIL 2006
1
c
2006 Integrated Device Technology, Inc.
DSC - 7042/2
IDTAMB0480
ADVANCEDMEMORYBUFFERFORFULLYBUFFEREDDIMM
COMMERCIALTEMPERATURERANGE
FUNCTIONALBLOCKDIAGRAM
10 x 2
10 x 2
PS[9:0]/PS[9:0]
SS[9:0]/SS[9:0]
Southbound Lanes
Re-sync
FIFO
SIPO
10 x 12b
PISO
10 x 12b
De-skew
FIFO
Re-skew
FIFO
3
Link Init FSM
and Control
SA[2:0]
SCL
SDA
SMBus
SB Link
CSRs
4
Controller
CLK[3:0]
Thermal
Sensor
DDR Link
CSRs
IBIST Rx
IBIST Tx
CLK[3:0]
19
DDR State
Controller
A[15:0]A/BA[2:0]A
Failover
Termination
FSM
A[15:0]B/BA[2:0]B
FBDRES
3
Cmnd Decode
& CRC Check
RASA/CASA/WEA
Core Control
and CSRs
RASB/CASB/WEB
BFUNC
RESET
External MemBIST,
4
SB clock
CS[1:0]A/CKE[1:0]A
DDR Calibration and
DDR IOBIST
CS[1:0]B/CKE[1:0]B
Reset
Control
ODTA
ODTB
32 x 144b
REF clock
Phase-locked
Loop
Write Data
FIFO
SCK
SCK
18
DQS[17:0]
DQS[17:0]
Clock
PLLTSTO
DDR clocks
DLL
Generator
144b
72
CB[7:0]/DQ[63:0]
NB clock
168b
144b
CRC Gen
& Read FIFO
Vref
Sync and Idle
DDRC_B18
DDRC_C18
IBIST Tx
IBIST Rx
Pattern Gen
Impedance
Control
FSM
DDRC_B12
DDRC_C12
DDRC_C14
NB Link
CSRs
Link Init FSM
and Control
Failover
Re-skew
FIFO
De-skew
FIFO
14 x 12b
PISO
14 x 12b
SIPO
Re-sync
FIFO
Northbound Lanes
PN[13:0]/PN[13:0]
SN[13:0]/SN[13:0]
14 x 2
14 x 2
2
IDTAMB0480
ADVANCEDMEMORYBUFFERFORFULLYBUFFEREDDIMM
COMMERCIALTEMPERATURERANGE
PINCONFIGURATIONS
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
TEST
LO
DQS
10
VDD
A
B
VDD
VDD
VDD
VDD
DQS1 DQ10
VDD
DQ26 DQ12
DQ13
VSS
DQS
10
TEST
LO
DDRC
_B12
VDD
DQS3 DQS3
DQ14
DQ11 DQS1
VSS
VSS
VSS
DQ8
VSS
DDRC
_C12
DDRC
_C14
DQS
17
DQS2 DQ18
DQ4 DQS9
DQ15 DQ9
VSS VSS
C
VSS
VSS
VSS
DQ19 DQS2
DQ16 DQ24
DQS9 DQ7
DQ3 DQS0
DQS8 DQS8
VSS
VSS
DQ17 DQ29
VSS
VSS
VDD
CB2
D
E
DQ21
VSS
DQ25 DQ6
DQ5 DQ1
DQ0 CB1
VSS
VSS
DQ20 DQ23
VSS
DQ31 DQ27
VSS
VSS
TEST
LO
F
TEST
DQS0 DQ2
CB0 CB3
VSS
VSS
VSS
VDD
DQS DQS
DQS DQS
G
H
NC NC NC
NC NC NC
NC NC NC
NC NC NC
NC NC NC
NC NC NC
NC NC NC
BFUNC
VSS
VDD
RFU RFU RFU
VSS
11
11
12
12
DQ22
DQ28 DQ30
VSS
VSS
VSS
VDD
VDD
VSS
VCC
VDD
VSS
VCC
CKE
1A
J
CLK2 NC NC NC BA1A
VSS
VSS
K
NC NC NC
NC NC NC
CLK2 CLK0
WEA RASA
VSS
A0A
VSS
VCC
VSS
VCC
CKE
L
CLK0
VSS
VSS
0A
VSS
VCC
VSS
VCC
ODT
0A
M
N
RFU NC NC NC CASA
BA2A NC NC NC
VSS
VSS
VCC
VSS
VCC
CS1A CS0A
A6A VSS
BA0A A10A
NC NC NC
NC NC NC
VSS
VSS
VCC
VSS
VSS
VCC
VSS
P
NC NC NC A2A A1A A3A NC NC NC
VSS
VCC
VSS
VCC
A8A
VSS
A11A
VSS
A5A
A9A A7A
R
NC NC NC
NC NC NC
NC NC NC
VSS
NC NC NC
NC NC NC
NC NC NC
T
A4A A13A
PN0 PN0
VCC
VCC
VSS
RFU
VSS
VCC
FBD
A15A A14A A12A
U
VSS VSS
VCC
FBD
VCC
FBD
VCC
FBD
RFU(1) RFU(1)
VSS
VSS
SN0
V
PN1 PN1
PN2 PN2
PN3 PN3
SN0
VSS
VSS
VSS VSS VSS
W
Y
SN1 SN1 SN3 SN4 SN5 SN13 SN12 SN6 SN7 SN8 SN9 SN10
SN2 SN2 SN3 SN4 SN5 SN13 SN12 SN6 SN7 SN8 SN9 SN10
VSS
AA
AB
AC
PN4 PN4
VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
(1)
VSS
VCC
RESET PN5 PN13 RFU PN12 PN6 PN7 PN8 PN9
PN10 PN11
PN10 PN11
VSS
APLL
APLL
FBD
RES TSTO
PLL
RFU(1)
PN5 PN13
PN12 PN6 PN7 PN8 PN9
VSS
FCBGA
TOP VIEW, LEFT SIDE
NOTE:
1. These pin positions are reserved for forward clocks to be used in future implementations.
3
IDTAMB0480
ADVANCEDMEMORYBUFFERFORFULLYBUFFEREDDIMM
COMMERCIALTEMPERATURERANGE
16 17 18 19 20 21 22 23 24 25 26 27 28 29
DQS15
VDD
VDD
VDD
VDD
DQ52
VSS
VDD DQ49
DQ48 DQ38
VSS DQS13
DQS6
DQS6
A
B
C
D
E
F
VDD
TEST
DDRC
_B18
TEST
LO
VSS
DQS13
DQS15
DQ53
VSS
DQ50
DDRC
_C18
DQS17
CB6
DQ46
DQ54
DQS16
VSS DQ55
DQ63
VSS
DQS14 VDD
VSS
VSS DQS7
VSS
DQ51
DQ56
DQ47
VSS
VSS DQ59 DQS7
DQ36 DQ44
VSS
DQS14
CB7
CB5
VDD
VSS DQ58
DQ57
VSS
DQS16
DQ33
VSS
DQ41
VSS
DQ61
VSS
DQ39
DQ37
DQ45
VSS
VSS
CB4
VSS
TEST TEST
DQS4
DQ35
DQ43
DQS5
VSS DQS5
DQ62 DQ60
TEST
LO
DQS4
RFU RFU
VSS NC NC NC
NC NC NC
NC NC NC VSS
RASB
DQ40
DQ42
G
H
J
VSS VDD VSS
DQ34 DQ32
CLK3
VSS
RFU NC NC NC
NC NC NC
VSS
VDD
VSS
VCC
VDD NC NC NC
VSS
ODT
0B
CLK3
CS1B
CLK1
NC NC NC
NC NC NC
NC NC NC
NC NC NC
VSS
K
L
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
CLK1
VSS CASB WEB
VSS
VCC
VSS
CKE0B
BA0B
VSS
NC NC NC CS0B VSS BA1B NC NC NC
M
N
P
R
T
VSS
BA2B
VSS
VCC
VSS
VCC
NC NC NC
NC NC NC
VSS
A2B
A0B
CKE1B
VSS
VCC
VSS NC NC NC
A1B NC NC NC
A4B
VSS
A9B
VSS
A6B
A3B VSS
A5B
PS8 PS8
NC NC NC
NC NC NC
A10B
VCC
A7B
NC NC NC A11B
NC NC NC
VSS
VSS
VSS
VSS
RFU
Vcc
FBD
SDA
NC NC NC A8B
Vcc
U
V
W
Y
A15B A14B SA0 SCL
RFU(1) RFU(1) VSS
Vcc
FBD
Vcc
FBD
A13B A12B SA2 SA1 PS7 PS7
VSS
VSS
FBD
SS0 SS1 SS2 SS3 SS4 SS9 SS5 SS6 SS7 SS8 VSS PS6 PS6
VSS
VSS
SS0 SS1 SS2 SS3 SS4
PS5 PS5
SS9 SS5 SS6 SS7 SS8
VSS
PS9 PS9
AA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS
(1)
RFU
TESTLO_
AB20
VDD
SPD
SCK
VSS
SN11
VSS
VSS
RFU SN11
AB
AC
PS0
PS1 PS2 PS3 PS4
PS1 PS2 PS3 PS4
TESTLO_
AC20 PS0
RFU(1)
VSS SCK
VSS
FCBGA
TOP VIEW, RIGHT SIDE
NOTE:
1. These pin positions are reserved for forward clocks to be used in future implementations.
4
IDTAMB0480
ADVANCEDMEMORYBUFFERFORFULLYBUFFEREDDIMM
COMMERCIALTEMPERATURERANGE
655 BALL BGA PACKAGE ATTRIBUTES
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
16 17 18 19 20 21 22 23 24 25 26 27 28 29
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
5
IDTAMB0480
ADVANCEDMEMORYBUFFERFORFULLYBUFFEREDDIMM
COMMERCIALTEMPERATURERANGE
ADVANCEDMEMORYBUFFERSIGNALSBYBALLNUMBER
Ball No.
F9
Signal
TEST
VSS
Ball No.
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
E1
Signal
Ball No.
B26
B27
B28
C1
Signal
DQS13
DQS13
VSS
Ball No.
A3
Signal
VSS
VSS
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
F27
F28
F29
G1
DQS16
DQ63
VSS
A4
DQ26
DQ12
VDD
DQS0
DQ2
VDD
A5
A6
VSS
DQ59
DQS7
VSS
C2
DQS2
DQ18
VSS
A7
DQS10
DQ13
VDD
CB0
CB3
CB4
VDD
C3
A8
C4
A9
DQ36
DQ44
VSS
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
B2
DQS1
DQ10
VDD
C5
DQ4
C6
DQS9
VSS
DQ62
DQ60
VSS
C7
DQS14
DQ47
DQ21
VSS
C8
DQ15
DQ9
TESTLO
VDD
C9
TEST
TEST
VSS
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
D1
VSS
VDD
E2
VDD
DQ8
E3
DQ17
DQ29
VSS
TEST
VDD
DDRC_C12
VSS
DQ37
DQ35
VSS
E4
E5
DDRC_C14
DQS17
DQS17
VSS
DQ52
DQS15
VDD
E6
DQ25
DQ6
VSS
DQS5
DQ43
VSS
E7
E8
DQ49
DQS6
VDD
E9
DQ5
DQ1
VSS
DDRC_C18
DQ54
VSS
DQS11
DQS11
N C
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
E27
E28
E29
F1
G2
DQ48
DQ38
VDD
G3
DQ0
CB1
VSS
DQ55
DQ51
VSS
G4
N C
G5
N C
VDD
G6
VSS
CB2
VSS
B3
DQS3
DQS3
VSS
DQS7
DQ56
VSS
G7
DQS12
DQS12
N C
B4
G8
CB5
DQS16
VSS
B5
G9
DQ46
DQS14
VDD
B6
DQ14
DQS10
VSS
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
G24
G25
G26
G27
G28
N C
B7
N C
DQ61
DQ57
VSS
B8
BFUNC
RFU
RFU
RFU
TESTLO
RFU
RFU
N C
B9
DQ11
DQS1
VSS
DQ19
DQS2
VSS
D2
B10
B11
B12
B13
B14
B15
B16
B17
B 18
B19
B20
B21
B22
B23
B24
B25
DQ58
DQ39
VSS
D3
D4
DQ16
DQ24
VSS
DDRC_B12
TESTLO
VDD
D5
DQ33
DQ45
VSS
D6
VSS
D7
DQS9
DQ7
D8
VDD
N C
DQ41
VSS
D9
VSS
TESTLO
DDRC_B18
VSS
N C
D10
D11
D12
D13
D14
D15
D16
D17
DQ3
DQS4
DQS4
VSS
F2
DQ20
DQ23
VSS
DQS0
VSS
F3
DQS15
DQ53
VSS
F4
DQS8
DQS8
VDD
N C
F5
DQ31
DQ27
VSS
N C
F6
DQS6
DQ50
VSS
N C
F7
CB6
DQS5
F8
TESTLO
CB7
6
IDTAMB0480
ADVANCEDMEMORYBUFFERFORFULLYBUFFEREDDIMM
COMMERCIALTEMPERATURERANGE
ADVANCEDMEMORYBUFFERSIGNALSBYBALLNUMBER(CONT.)
Ball No.
G29
H1
Signal
DQ40
DQ22
VSS
Ball No.
J20
J21
J22
J23
J24
J25
J26
J27
J28
J29
K1
Signal
N C
Ball No.
Signal
Ball No.
Signal
CS0A
NC
NC
NC
VSS
L11
N C
N2
N C
L12
VCC
VSS
N3
H2
RASB
VSS
L13
N4
H3
NC
L14
VCC
VSS
N5
H4
NC
RFU
N C
L15
N6
H5
NC
L16
VCC
VSS
N7
BA0A
A10A
NC
N C
N C
VCC
VSS
H6
DQ28
DQ30
VSS
N C
L17
N8
H7
N C
L18
VCC
N C
N9
H8
CLK3
VSS
L19
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
N23
N24
N25
N26
N27
N28
N29
P1
H9
NC
L20
N C
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
H29
J1
N C
CLK2
CLK0
N C
L21
N C
N C
K2
L22
VSS
VSS
K3
L23
CASB
WEB
N C
VCC
VSS
VDD
VSS
K4
N C
L24
K5
N C
L25
VCC
VSS
VDD
VSS
K6
VSS
L26
N C
K7
WEA
RASA
N C
L27
N C
VCC
N C
N C
N C
A0B
A2B
VSS
VDD
VSS
K8
L28
VSS
K9
L29
CLK1
ODT0A
RFU
NC
N C
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
K23
K24
K25
K26
K27
K28
K29
L1
N C
M1
N C
N C
M2
N C
VSS
M3
VSS
VCC
M4
NC
DQ34
DQ32
N C
VSS
M5
NC
N C
N C
N C
BA0B
BA2B
A6A
VSS
VCC
M6
CASA
VSS
VSS
M7
N C
VCC
M8
BA2A
NC
N C
VSS
M9
VSS
N C
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
M23
M24
M25
M26
M27
M28
M29
N1
N C
DQ42
VSS
N C
N C
P2
N C
VSS
P3
N C
N C
N C
A2A
A1A
A3A
N C
N C
N C
VSS
J2
CLK2
N C
ODT0B
CS1B
VSS
VCC
VSS
P4
J3
P5
J4
N C
VCC
VSS
P6
J5
N C
N C
P7
J6
BA1A
VSS
N C
VCC
VSS
P8
J7
N C
P9
J8
CKE1A
N C
CLK1
CLK3
CLK0
VSS
N C
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
J9
N C
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
N C
N C
N C
L2
CS0B
VSS
VCC
VSS
VDD
VSS
L3
N C
L4
N C
BA1B
N C
VCC
VSS
VDD
VSS
L5
N C
L6
A0A
CKE0A
VSS
N C
VCC
VSS
VDD
VSS
L7
N C
L8
CKE0B
VSS
N C
N C
N C
VDD
N C
L9
N C
L10
N C
CS1A
7
IDTAMB0480
ADVANCEDMEMORYBUFFERFORFULLYBUFFEREDDIMM
COMMERCIALTEMPERATURERANGE
ADVANCEDMEMORYBUFFERSIGNALSBYBALLNUMBER(CONT.)
Ball No.
V2
Signal
PN1
Ball No.
W21
W22
W23
W24
W25
W26
W27
W28
W29
Y1
Signal
SS4
SS9
SS5
SS6
SS7
SS8
VSS
Ball No.
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
T26
T27
T28
T29
U1
Signal
VSS
Ball No.
P22
P23
P24
P25
P26
P27
P28
P29
R1
Signal
VSS
V3
VSS
VCC
A4B
A1B
N C
N C
N C
VSS
V4
SN0
VSS
V5
SN0
VCCFBD
VCC
V6
VSS
V7
VSS
VCC
V8
VCCFBD
VSS
VSS
V9
PS6
PS6
PN3
PN3
VSS
N C
CKE1B
VSS
(1)
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
V23
V24
V25
V26
V27
V28
V29
W1
RFU
N C
(1)
RFU
N C
R2
A8A
N C
N C
N C
A11A
VSS
VCCFBD
VSS
Y2
A11B
A9B
VSS
R3
Y3
R4
VSS
Y4
SN2
SN2
SN3
SN4
SN5
SN13
SN12
SN6
SN7
SN8
SN9
SN10
VSS
R5
VSS
Y5
N C
R6
VCCFBD
VSS
Y6
N C
R7
Y7
N C
R8
A5A
N C
N C
N C
VCC
VSS
VCCFBD
VSS
Y8
A7B
A5B
PN0
PN0
NC
R9
Y9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
T1
VCCFBD
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
Y25
Y26
Y27
Y28
Y29
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
(1)
RFU
U2
(1)
RFU
U3
VSS
A13B
A12B
SA2
SA1
PS7
PS7
PN2
PS2
VSS
U4
NC
VCC
VSS
U5
NC
U6
A15A
A14A
A12A
NC
VCC
VSS
U7
SS0
SS1
SS2
SS3
SS4
SS9
SS5
SS6
SS7
SS8
VSS
U8
VCC
N C
N C
N C
A6B
VSS
U9
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23
U24
U25
U26
U27
U28
U29
V1
N C
N C
W2
RFU
VCCFBD
VSS
W3
W4
SN1
SN1
SN3
SN4
SN5
SN13
SN12
SN6
SN7
SN8
SN9
SN10
VSS
A10B
N C
N C
N C
A3B
VSS
W5
VSS
W6
VSS
W7
VCCFBD
RFU
N C
W8
W9
PS5
PS5
VSS
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
N C
A4A
A13A
N C
N C
N C
VSS
N C
T2
PN4
PN4
VSS
A8B
A15B
A14B
SA0
SCL
SDA
PS8
PS8
PN1
T3
T4
T5
VSS
T6
VSS
T7
A9A
A7A
N C
N C
N C
SS0
SS1
SS2
SS3
VSS
T8
VSS
T9
VSS
T10
T11
VSS
NOTE:
1. These pin positions are reserved for forward clocks to be used in future implementations.
8
IDTAMB0480
ADVANCEDMEMORYBUFFERFORFULLYBUFFEREDDIMM
COMMERCIALTEMPERATURERANGE
ADVANCEDMEMORYBUFFERSIGNALSBYBALLNUMBER(CONT.)
Ball No.
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AB2
Signal
VSS
Ball No.
AC5
Signal
PN13
(1)
VSS
AC6
RFU
VSS
AC7
PN12
PN6
VSS
AC8
VSS
AC9
PN7
VSS
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AC26
AC27
PN8
VSS
PN9
VSS
FBDRES
PLLTSTO
PN10
PN11
RFU
VSS
VSS
VSS
VSS
VSS
SN11
VSS
VSS
VSS
SCK
TESTLO_AC20
VSS
PS9
PS9
VSS
PS0
PS1
PS2
VSS
PS3
AB3
RESET
PN5
PN13
PS4
(1)
AB4
RFU
AB5
VSS
(1)
AB6
RFU
AB7
PN12
PN6
AB8
AB9
PN7
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AB24
AB25
AB26
AB27
AB28
AC3
PN8
PN9
VSSAPLL
VCCAPLL
PN10
PN11
VSS
PN11
VSS
SCK
TESTLO_AB20
PS0
PS1
PS2
PS3
PS4
(1)
RFU
VDDSPD
VSS
VSS
AC4
PN5
NOTE:
1. These pin positions are reserved for forward clocks to be used in future implementations.
9
IDTAMB0480
ADVANCEDMEMORYBUFFERFORFULLYBUFFEREDDIMM
COMMERCIALTEMPERATURERANGE
PINDESCRIPTION
Signal
ChannelInterface
PN[13:0]
Type
Description
O
O
I
NorthboundOutputData:Highspeedserialsignal. ReadpathfromAMBtowardhostonprimaryside ofthe DIMMconnector.
NorthboundOutputDataComplement
PN[13:0]
SN[13:0]
Northbound Input Data: High speed serial signal. Read path from the previous AMB toward this AMB on secondary side of the DIMM
connector.
SN[13:0]
PS[9:0]
PS[9:0]
SS[9:0]
I
I
NorthboundInputDataComplement
SouthboundInputData:Highspeedserialsignal. Write pathfromhosttowardAMBonprimaryside ofthe DIMMconnector.
SouthboundInputDataComplement
I
O
SouthboundOutputData:Highspeedserialsignal.WritepathfromthisAMBtowardnextAMBonsecondarysideoftheDIMMconnector.
TheseoutputbuffersaredisabledforthelastAMBonthechannel.
SS[9:0]
FBDRES
O
A
SouthboundOutputDataComplement
External100ΩprecisionresistorconnectedtoVCC.On-dieterminationcalibratedagainstthisresistor.
DRAMInterface
CB[7:0]
I/O
I/O
I/O
I/O
O
Check bits
DQ[63:0]
Data
DQS[17:0]
DQS[17:0]
DataStrobe:DDR2dataandcheck-bitstrobe.
DataStrobeComplement:DDR2dataandcheck-bitstrobecomplements.
Address: Used for providing multiplexed row and column address to SDRAM.
A0A-A15A,
A0B-A15B
BA0A-BA2A,
BA0B-BA2B
RASA, RASB
CASA, CASB
WEA, WEB
O
Bank Active: Used to select the bank within a rank.
O
O
O
O
Row Address Strobe: Used with CS, CAS, and WE to specify the SDRAM command.
Column Address Strobe: Used with CS, RAS, and WE to specify the SDRAM command.
Write Enable: Used with CS, CAS, and RAS to specify the SDRAM command.
ChipSelect:UsedwithCAS,RAS, andWE tospecifythe SDRAMcommand. These signals are usedforselectingone oftwoSDRAM
ranks. CS0 is used to select the first rank and CS1 is used to select the second rank.
CS0A-CS1A,
CS0B-CS1B
CKE0A-CKE1A,
O
ClockEnable: DIMMcommandregisterenable.
CKE0B-CKE1B
ODT0A, ODT0B
CLK[3:0]
O
O
O
DIMMOn-Die-Termination:DynamicODTenables foreachDIMMonthe channel.
Clock:ClockstoDRAMs.CLK0andCLK1arealwaysused.CLK2andCLK3areusedwhentheAMBisconfiguredfordualrankDIMMs.
Clock Complement: Clocks to DRAMs.
CLK[3:0]
DDRCompensation
DDRC_C14
DDRC_B18
DDRC_C18
DDRC_B12
DDRC_C12
A
A
A
A
A
DDRCompensationCommon:Commonreturn(ground)pinforDDRC_B18andDDRC_C18
DDRCompensationBallResistor(825Ω)connectedtoCompensationCommonabove
DDRCompensationBallResistor(121Ω)connectedtoCompensationCommonabove
DDRCompensationBallResistor(82Ω)connectedtoVSS
DDRCompensationBallResistor(82Ω)connectedtoVDD
10
IDTAMB0480
ADVANCEDMEMORYBUFFERFORFULLYBUFFEREDDIMM
COMMERCIALTEMPERATURERANGE
PINDESCRIPTION(CONT.)
Signal
Clocking
Type
Description
SCK
I
I
AMBClock:ThisisoneofthetwodifferentialreferenceclockinputstothePhaseLockedLoopintheAMBcore.PhaseLockedLoopsin
the AMB will shift this to all frequencies required by the core, DDR channels, and FBD Channel.
SCK
AMBClockComplement:ThisistheotherdifferentialreferenceclockinputtothePhaseLockedLoopintheAMBcore.PhaseLockedLoops
in the AMB will shift this to all frequencies required by the core, DDR channels, and FBD Channel.
PLLTSTO
O
PLLClockObservabilityOutput:This pincanbe usedtoobserve VCO, reference clock, core clock, etc. Forsystemdebuganddesign
characterization.
VCCA PLL
VSSA PLL
A
A
VCC:PLLAnalogVoltage forthe core PLL
VSS:PLLAnalogVoltage forthe core PLL
SystemManagement
SCL
I/O
I/O
SMBus Clock
SDA
SMBus Address/Data
DIMM Select ID
SA[2:0]
Reset
RESET
PowerGoodReset
Miscellaneous Test
TEST(4pins)
TESTLO(5pins)
TESTLO_AB20
TESTLO_AC20
Power Supplies
VCC (24 pins)
VCCFBD (8 pins)
VDD (24 pins)
VSS (156 pins)
VDDSPD
NC
A
Pin for debug and test. Must be floated on DIMM.
Pin for debug and test. Must be tied to Ground on DIMM
A
Pinfordebugandtest.Connectedtotworesistors.Oneresistoris connectedtoVCCFBD,theotherresistoris connectedtoVSS.
Pinfordebugandtest.Connectedtotworesistors.One resistoris connectedtoVCCFBD,theotherresistoris connectedtoVSS.
A
A
A
A
A
A
1.5V nominal supply for core I/O
1.5V nominal supply for FBD high speed I/O
1.8V nominal supply for DDR I/O
Ground
3.3V nominal supply for SMB receivers and ESD diodes
Other Pins
BFUNC
I
BufferFunctionBit:WhenBFUNC=0,AMBisusedasaregularbufferonFBDIMM.WhenBFUNC=1,AMBisusedaseitherarepeater
or a buffer for LAI function. On FB-DIMM, BFUNC is tied to Ground
RFU (18 pins)
NC
Reserved for Future Use. Must be floated on DIMM. RFU pins denoted by “a” are reserved for forwarded clocks in future AMB
implementations.
Other No Connect Pins
NC (129 pins) NC
NoConnectpins
11
IDTAMB0480
ADVANCEDMEMORYBUFFERFORFULLYBUFFEREDDIMM
COMMERCIALTEMPERATURERANGE
ELECTRICAL,POWER,ANDTHERMAL
ABSOLUTEMAXIMUMRATINGS(1)
ADVANCEDMEMORYBUFFER
Symbol
Description
Min
-0.5
0.5
Max
+2.3
+2.3
Unit
V
NORMALMODEDCELECTRICAL
PARAMETERS
VDD
Supply voltage DRAM Interface
VIN (DDR2). Voltage on any DDR2 interface
VOUT (DDR2) pin relative to Vss(2)
V
Parameter
VCC link / core(1,2,3,4)
VDD
Min
1.425
1.7
Typ
1.5
1.8
3.3
Max
1.59
1.9
Unit
V
IINK
Input Clamp Current
(VIN < 0 or VIN > VDD)
+30
+30
mA
mA
mA
mA
V
V
VDDSPD
3.0
3.6
V
IOUTK
IOUT
N/A
VCC
Output Clamp Current
(VOUT < 0 or VOUT > VDD)
NOTES:
1. AMB 1.5V voltage regulation as measured at the package Balls.
2. DC defined as 0 KHz to 30 KHz.
3. DC + AC specified as 1.5V +6%, -5% 30KHz to 1 MHz.
4. There is also a +7%, -5% tolerance allowed for current load steps associated with
initialization/error-recovery state transitions, such as into and out of EI, IBIST, and
MEMBIST. For these transitions, a temporary voltage overshoot is expected and
acceptable as long as it is within +7% (step transition for 20μs and maximum duty cycle
of 10-6 %). Transitions between Active and Idle states are not included in this +7%,
-5% tolerance.
Continous Output Current
(VOUT = 0 to VDD)
+30
Continuous current through
each VDD or GND
+100
+1.75
Supply voltage for Core
and High Speed Interface
-0.3
–55
TJ
Junction Temperature
+125
+100
° C
° C
TSTG
Storage Temperature Range
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed. This value is limited to 2.3V maximum.
12
IDTAMB0480
ADVANCEDMEMORYBUFFERFORFULLYBUFFEREDDIMM
COMMERCIALTEMPERATURERANGE
DDR BIAS
RB18
DDRC_B18
DDRC_C14
DDRC_C18
RC12
DDRC_C12
VDD
AMB0480
RB12
DDRC_B12
VSS
RC18
PLL AND CHANNEL BIAS
L
R
VCCAPLL
VCC
PLLTSTO
VSS
AMB0480
C1
C2
RPLLTST
VSSAPLL
RFBDRES
FBDRES
VCCFBD
NOTES:
1. Refer to JEDEC PC2-4200/5300/6400 DDR2 FULLY BUFFERED DIMM DESIGN SPECIFICATIONS, rev 2.0.
2. The resistor R must be 0Ω and the inductor L needs to be replaced with a 0Ω resistor. The resistor RFBDRES = 100Ω and Resistor RPLLTST = 51Ω.
3. It is not recommended to use a serpentine copper trace in place of the resistor R. This resistor value needs to be AMB manufacturer defined and not set to a single fixed value.
Some raw cards have implemented the resistor with a serpentine copper trace on the DIMM PCB, while others use a discrete resistor. The limitation of using the copper trace
has been discussed in JEDEC, highlighting that the resistor implemented as a serpentine copper trace is not a generic solution. The raw card artwork now allows the option of
bypassing any serpentine trace with a 0Ω resistor to VCC.
13
IDTAMB0480
ADVANCEDMEMORYBUFFERFORFULLYBUFFEREDDIMM
COMMERCIALTEMPERATURERANGE
MISCELLANEOUSBIAS
TEST_F9
NC
NC
NC
NC
TEST_A17
TEST_F21
TEST_F22
TESTLO_F8
TESTLO_A13
TESTLO_B13
TESTLO_B17
TESTLO_G16
BFUNC
VDD
AMB0480
R2
R1
VSS
RSA0
SPD
SA0
SA0
HVM
TESTLO_AC20
TESTLO_AB20
R4
R3
Gold Finger
VSS
VSS
NOTES:
1. Refer to JEDEC PC2-4200/5300/6400 DDR2 FULLY BUFFERED DIMM DESIGN SPECIFICATIONS, rev 2.0.
2. Component values for the AMB0480 are summarized in the BIAS COMPONENT table.
BIASCOMPONENTS-RECOMMENDEDVALUESAMB0480
SchematicDiagram
Reference
Value
Description
RC12
82Ω
The impedance ofthe pullup(PRU)andpulldown(PRD)onthe AMBDDROutputs is relatedtoRB12
& RC12 as follows:
RC12 = RB12 = 5.3125 * Desired Output Impedance
DDR Bias
RB12
82Ω
Aresistorvalueof 82ΩresultsinanimpedanceataJEDECnominalvalueof15Ω. Theusercanadjust
thesevaluetooptimizetheDDRoutputimpedanceforaDIMMrawcardconfiguration.
RB18
825Ω
121Ω
0Ω
RC18
R
Resistor R must be 0Ω
L
C1
0Ω
InductorLneeds tobereplacedwitha0Ωresistor
PLLandChannel
Miscellaneous
10μF
10μF
51Ω
100Ω
Notloaded
Notloaded
0Ω
C2
RPLLTSTO
RFBDRES
R1
R2
R3
R4
0Ω
RSA0
825Ω
14
IDTAMB0480
ADVANCEDMEMORYBUFFERFORFULLYBUFFEREDDIMM
COMMERCIALTEMPERATURERANGE
ORDERINGINFORMATION
XXXX
XX
XX
X
X
IDTAMB
Revision
Device Type
Package
Temp. Range
Shipping
Carrier
Blank
8
Tray
Tape and Reel
Blank
Commercial (0°C to +70°C)
Ball Grid Array - RoHS Compliant
(1) BGA - Green
RJ
BJG
RH
Ball Grid Array with heat spreader - RoHS Compliant
(1) BGA with heat spreader- Green
HJG
XX
Device Revision
0480
Advanced Memory Buffer for Fully Buffered DIMM Modules
NOTE:
1. Contact factory for availability.
Device Revision
Status
A5
AMB revision A1.5
Active
Other Ordering Information
AMB0480xxRJ8
AMB0480xxRJ
AMB in bare die packaged in tape/reel
AMB in bare die packaged in tray
AMB0480xxRH8
AMB0480xxRH
AMBwithheatspreaderpackagedintape/reel
AMBwithheatspreaderpackagedintray
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
6024 Silver Creek Valley Road
San Jose, CA 95138
800-345-7015 or 408-284-8200
fax: 408-284-2775
logichelp@idt.com
www.idt.com
15
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