IDT79RC32V334-100BBI

IDT^TMInterprise^TMIntegrated

Communications Processor

79RC32334—Rev. Y

◆

Programmable I/O (PIO)

Features

◆

–

Input/Output/Interrupt source

Individually programmable

RC32300 32-bit Microprocessor

–

Up to 150 MHz operation

Enhanced MIPS-II Instruction Set Architecture (ISA)

Cache prefetch instruction

Conditional move instruction

DSP instructions

Supports big or little endian operation

MMU with 32 page TLB

8kB Instruction Cache, 2-way set associative

2kB Data Cache, 2-way set associative

Cache locking per line

Programmable on a page basis to implement a write-through

no write allocate, write-through write allocate, or write-back

algorithms for cache management

Compatible with a wide variety of operating systems

◆

SDRAM Controller (32-bit memory only)

–

4 banks, non-interleaved

Up to 512MB total SDRAM memory supported

Implements full, direct control of discrete, SODIMM, or DIMM

memories

–

Supports 16Mb through 512Mb SDRAM device depths

Automatic refresh generation

◆

Serial Peripheral Interface (SPI) master mode interface

UART Interface

–

Two 16550 compatible UARTs

Baud rate support up to 1.5 Mb/s

Modem control signals available on one channel

–

◆

Memory & Peripheral Controller

◆

Local Bus Interface

–

6 banks, up to 64MB per bank

Supports 8-,16-, and 32-bit interfaces

Supports Flash ROM, SRAM, dual-port memory, and

peripheral devices

–

Up to 75 MHz operation

26-bit address bus

32-bit data bus

Direct control of local memory and peripherals

Programmable system watch-dog timers

Big or little endian support

–

Supports external wait-state generation

8-bit boot PROM support

Flexible I/O timing protocols

◆

Interrupt Controller simplifies exception management

Four general purpose 32-bit timer/counters

Block Diagram

Interrupt Contro

l

EJTAG

Programmable I/O

SPI Control

In-Circuit Emulator Interface

RISCore32300

Enhanced MIPS-II ISA Compatible

32-bit Timers

RC5000

Integer CPU

CP0

DMA Control

Dual UART

Local

Memory/IO

Control

32-page

TLB

IPBus

Bridge

SDRAM

Control

IDT

Peripheral

Bus

8kB

2-set

2kB

2-set, Lockable

Lockable

Instr. Cache

Data Cache

PCI Bridge

Figure 1 RC32334 Block Diagram

Note: This data sheet does not apply to revision Z silicon. Contact your IDT sales representative for information on revision Z.

IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.

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DSC 5701

IDT 79RC32334—Rev. Y

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4 DMA Channels

CPU Execution Core

–

4 general purpose DMA, each with endianess swappers and

byte lane data alignment

The RC32334 integrates the RISCore32300, the same CPU core

found in the award-winning RC32364 microprocessor.

–

Supports scatter/gather, chaining via linked lists of records

Supports memory-to-memory, memory-to-I/O, memory-to-

PCI, PCI-to-PCI, and I/O-to-I/O transfers

Supports unaligned transfers

Supports burst transfers

Programmable DMA bus transactions burst size

(up to 16 bytes)

The RISCore32300 implements the Enhanced MIPS-II ISA. Thus, it

is upwardly compatible with applications written for a wide variety of

MIPS architecture processors, and it is kernel compatible with the

modern operating systems that support IDT’s 64-bit RISController

product family.

–

◆

The RISCore32300 was explicitly defined and designed for inte-

grated processor products such as the RC32334. Key attributes of the

execution core found within this product include:

PCI Bus Interface

–

32-bit PCI, up to 66 MHz

Revision 2.2 compatible

Target or master

Host or satellite

Three slot PCI arbiter

–

◆

High-speed, 5-stage scalar pipeline executes to 150MHz. This

high performance enables the RC32334 to perform a variety of

performance intensive tasks, such as routing, DSP algorithms,

etc.

Serial EEPROM support, for loading configuration registers

◆

Off-the-shelf development tools

◆

32-bit architecture with enhancements of key capabilities. Thus,

JTAG Interface (IEEE Std. 1149.1 compatible)

256-ball BGA (1.0mm spacing)

the RC32334 can execute existing 32-bit programs, while

enabling designers to take advantage of recent advances in

CPU architecture.

3.3V operation with 5V tolerant I/O

EJTAG in-circuit emulator interface

◆

Count leading-zeroes/ones. These instructions are common to a

wide variety of tasks, including modem emulation, voice over IP

compression and decompression, etc.

Device Overview

◆

Cache PREFetch instruction support, including a specialized

The IDT RC32334 device is an integrated processor based on the

RC32300 CPU core. This product incorporates a high-performance, low-

cost 32-bit CPU core with functionality common to a large number of

embedded applications. The RC32334 integrates these functions to

enable the use of low-cost PC commodity market memory and I/O

devices, allowing the aggressive price/performance characteristics of

the CPU to be realized quickly into low-cost systems.

form intended to help memory coherency. System programmers

can allocate and stage the use of memory bandwidth to achieve

maximum performance.

◆

8kB of 2-way set associative instruction cache

Serial

SDRAM

Local

Memory

I/O Bus

Channels

RC32334

Integrated

Programmable I/O

FLASH

Core

Controller

Serial

EEPROM

Local I/O

32-bit, 66MHz PCI

Figure 2 RC32334 Based System Diagram

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IDT 79RC32334—Rev. Y

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66 MHz operation

2KB of 2-way set associative data cache, capable of write-back

and write-through operation.

PCI revision 2.2 compliant

◆

Cache locking per line to speed real-time systems and critical

system functions

Programmable address mappings between CPU/Local memory

and PCI memory and I/O

◆

On-chip TLB to enable multi-tasking in modern operating

systems

On-chip PCI arbiter

Extensive buffering allows PCI to operate concurrently with local

memory transfers

◆

EJTAG interface to enable sophisticated low-cost in-circuit

◆

emulation.

Selectable byte-ordering swapper

5V tolerant I/O.

Synchronous-DRAM Interface

The RC32334 integrates a SDRAM controller which provides direct

control of system SyncDRAM running at speeds to 75MHz.

On-Chip DMA Controller

To minimize CPU exception handling and maximize the efficiency of

system bandwidth, the RC32334 integrates a very sophisticated 4-

channel DMA controller on chip.

Key capabilities of the SDRAM controller include:

◆

Direct control of 4 banks of SDRAM (up to 2 64-bit wide DIMMs)

◆

On-chip page comparators optimize access latency.

The RC32334 DMA controller is capable of:

◆

Speeds to 75MHz

Chaining and scatter/gather support through the use of a

flexible, linked list of DMA transaction descriptors

◆

Programmable address map.

◆

Capable of memory<->memory, memory<->I/O, and

PCI<->memory DMA

Supports 16, 64, 128, 256, or 512Mb SDRAM devices

◆

Automatic refresh generation driven by on-chip timer

◆

Unaligned transfer support

Support for discrete devices, SODIMM, or DIMM modules.

◆

Byte, halfword, word, quadword DMA support.

Thus, systems can take advantage of the full range of commodity

memory that is available, enabling system optimization for cost, real-

estate, or other attributes.

On-Chip Peripherals

The RC32334 also integrates peripherals that are common to a wide

variety of embedded systems.

Local Memory and I/O Controller

◆

Dual channel 16550 compatible UARTs, with modem control

interface on one channel.

The local memory and I/O controller implements direct control of

external memory devices, including the boot ROM as well as other

memory areas, and also implements direct control of external periph-

erals.

◆

SPI master mode interface for direct interface to EEPROM,

A/D, etc.

◆

Interrupt Controller to speed interrupt decode and management

The local memory controller is highly flexible, allowing a wide range

of devices to be directly controlled by the RC32334 processor. For

example, a system can be built using an 8-bit boot ROM, 16-bit FLASH

cards (possibly on PCMCIA), a 32-bit SRAM or dual-port memory, and a

variety of low-cost peripherals.

◆

Four 32-bit on-chip Timer/Counters

◆

Programmable I/O module

Debug Support

To facilitate rapid time to market, the RC32334 provides extensive

support for system debug.

Key capabilities include:

◆

Direct control of EPROM, FLASH, RAM, and dual-port memories

◆

6 chip-select outputs, supporting up to 64MB per memory space

First and foremost, this product integrates an EJTAG in-circuit emula-

tion module, allowing a low-cost emulator to interoperate with programs

executing on the controller. By using an augmented JTAG interface, the

RC32334 is able to reuse the same low-cost emulators developed

around the RC32364 CPU.

◆

Supports mixture of 8-, 16-, and 32-bit wide memory regions

◆

Flexible timing protocols allow direct control of a wide variety of

devices

◆

Programmable address map for 2 chip selects

◆

Secondly, the RC32334 implements additional reporting signals

intended to simplify the task of system debugging when using a logic

analyzer. This product allows the logic analyzer to differentiate transac-

tions initiated by DMA from those initiated by the CPU and further allows

CPU transactions to be sorted into instruction fetches vs. data fetches.

Automatic wait state generation.

PCI Bus Bridge

In order to leverage the wide availability of low-cost peripherals for

the PC market as well as to simplify the design of add-in functions, the

RC32334 integrates a full 32-bit PCI bus bridge. Key attributes of this

bridge include:

Finally, the RC32334 implements a full boundary scan capability,

allowing board manufacturing diagnostics and debug.

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IDT 79RC32334—Rev. Y

September 14, 2001: In the Reset category of Table 6: switched

mem_addr[19:17] from Tsu22 and Thld22 to Tsu10 and Thld10;

switched mem_addr[22:20] from Tsu10 and Thld10 to Tsu22 and

Thld22; moved ejtag_pcst[2:0] from Reset to Debug Interface category

under Tsu20 and Thld20.

Packaging

The RC32334 is packaged using a 256-lead PBGA package, with

1.0mm ball spacing.

Thermal Considerations

November 1, 2001: Added Input Voltage Undershoot parameter and

2 footnotes to Table 10.

The RC32334 consumes less than 2.1 W peak power. The device is

guaranteed in an ambient temperature range of 0° to +70° C for

commercial temperature devices; -40° to +85° for industrial temperature

devices.

March 20, 2002: In Local System Interface section of AC Timing

Characteristics table, changed values in Min column for last category of

signals (Tdoh3) from 2.5 to 1.5 for all speeds. In Table 8, PCI Drive

Output Pads, the Conditions for parameters V_OL, V_OH, V_IL, and V_IHwere

Revision History

changed to read Per PCI 2.2.

May 16, 2000: Initial version.

May 2, 2002: Changed upper ambient temperature for commercial

uses back from +85° C to +70° C (changed erroneously from 70 to 85

on March 13, 2001). Added Reset State Status column to Table 1.

Revised description of jtag_trst_n in Table 1 and changed this pin to a

pull-down instead of a pull-up.

June 8, 2000: In CPU Core Specific Signals section of Table 1,

changed cpu_dr_r_n pin from Input to Output. Updated document from

Advance to Preliminary Information.

June 15, 2000: In Table 1, switched assertion and de-assertion for

debug_cpu_dma_n signal. In the AC Timing Characteristics table,

added SPI section and adjusted parameters in the Reset section.

July 3, 2002: This data sheet now describes revision Y silicon and is

no longer applicable to revision Z.

July 12, 2000: Removed “Preliminary Information” statement. Added

information regarding external pull-ups and pull-downs to the Pin

Description Table. Made minor revisions in other parts of the data sheet.

July 12, 2002: In Table 6: PCI section, changed Thld Min values

from 1 to zero; DMA section, changed Thld9 Min values from 2 to 1; in

PIO section, changed Thld9 Min values from 2 to 1; in Timer section,

changed Thld10 Min values from 2 to 1. Revision Y data sheet changed

from Preliminary to Final.

August 3, 2000: Added Pin Layout diagram showing power and

ground pins. Revised Power Curves section to reflect support of only 2x,

3x, and 4x.

September 18, 2002: Added cpu_coldreset_n rise time to Table 5,

Clock Parameters. Added mem_addr[16] and sdram_addr[16] to Tables

1 and 12. Changed Logic Diagram to include sdram_addr[16].

August 30, 2000: Added Standby mode and values to Power

Consumption table. Extended Power Curve figure to 75 MHz.

September 25, 2000: Changed MIPS32 ISA to Enhanced MIPS-II. In

Local System Interface section of Table 6, changed Thld2 values for

mem_data[31:0] from 1.8 to 1.5 ns and changed Tdoh3 values for

mem_addr[25:2], etc. from 1.8 to 1.5 ns.

December 18, 2002: In the Reset section of Table 6, AC Timing

Characteristics, setup and hold time categories for cpu_coldreset_n

have been deleted.

July 30, 2003: In Table 8, added 3 new categories (Input Pads, PCI

December 12, 2000: Changed Max values for cpu_masterclock

period in Table 5 and added footnote. In Table 1, added 2nd alternate

function for spi_mosi, spi_miso, spi_sck. In Table 10, removed the “1”

from Alt column for cpu_masterclk and added “2” in Alt column for pins

G3, G4, H2. In RC32334 Alternate Signal Functions table: added pin T2;

added pin names in Alt #2 column for pins G3, G4, H2; added PIO[11] to

Alt #2 column for pin R3.

Input Pads, and All Pads) and added footnotes 2 and 3.

March 24, 2004: In Table 1, changed description in Satellite Mode

for pci_rst_n. Specified “cold” reset on pages 11 and 12. Changed the

maximum value for Vcc to 4.0 in Table 10, Absolute Maximum Ratings,

and changed footnote 1 to that table. Added Power Ramp-up section on

page 21.

August 31, 2004: Added ”Green” orderable parts on page 30.

January 4, 2001: In Table 6 under Interrupt Handling, moved the

values for Tsu9 from the Max to the Min columns.

March 13, 2001: Changed upper ambient temperature for industrial

and commercial uses from +70° C to +85° C.

June 7, 2001: In the Clock Parameters table, added footnote 3 to

output_clk category and added NA to Min and Max columns. In Figure 3

(Reset Specification), enhanced signal line for cpu_masterclk. In Local

System Interface section of AC Timing Characteristics table, changed

values in Min column for last category of signals (Tdoh3) from 1.5 to 2.5

for all speeds. In SDRAM Controller section of same table, changed

values in Min column for last category of signals (9 signals) from 1 to 2.5

for all speeds.

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IDT 79RC32334—Rev. Y

Pin Description Table

The following table lists the pins provided on the RC32334. Note that those pin names followed by ”_n” are active-low signals. All external pull-ups

and pull-downs require 10 kΩ resistor.

Reset

Type State

Status

Drive

Name

Strength

Capability

Description

Local System Interface

mem_data[31:0]

I/O

Z

High

Local System Data Bus

Primary data bus for memory. I/O and SDRAM.

mem_addr[25:2]

I/O

[25:10] Z [25:17] Low Memory Address Bus

These signals provide the Memory or DRAM address, during a Memory or DRAM bus transaction. During

each word data, the address increments either in linear or sub-block ordering, depending on the transac-

tion type. The table below indicates how the memory write enable signals are used to address discreet

memory port width types.

[9:2] L

[16:2] High

Port Width

Pin Signals

mem_we_n[3]

mem_we_n[2]

mem_we_n[1]

mem_we_n[0]

DMA (32-bit) mem_we_n[3]

mem_we_n[2] mem_we_n[1]

mem_we_n[0]

32-bit

16-bit

mem_we_n[3]

Byte High Write Enable mem_addr[1] Not Used (Driven

Low)

Byte Low Write

Enable

8-bit

Not Used (Driven High) mem_addr[1] mem_addr[0]

Byte Write Enable

mem_addr[22] Alternate function: reset_boot_mode[1].

mem_addr[21] Alternate function: reset_boot_mode[0].

mem_addr[20] Alternate function: reset_pci_host_mode.

mem_addr[19] Alternate function: modebit [9].

mem_addr[18] Alternate function: modebit [8].

mem_addr[17] Alternate function: modebit [7].

mem_addr[16] Alternate function: sdram_addr[16].

mem_addr[15] Alternate function: sdram_addr[15].

mem_addr[14] Alternate function: sdram_addr[14].

mem_addr[13] Alternate function: sdram_addr[13].

mem_addr[11] Alternate function: sdram_addr[11].

mem_addr[10] Alternate function: sdram_addr[10].

mem_addr[9] Alternate function: sdram_addr[9].

mem_addr[8] Alternate function: sdram_addr[8].

mem_addr[7] Alternate function: sdram_addr[7].

mem_addr[6] Alternate function: sdram_addr[6].

mem_addr[5] Alternate function: sdram_addr[5].

mem_addr[4] Alternate function: sdram_addr[4].

mem_addr[3] Alternate function: sdram_addr[3].

mem_addr[2] Alternate function: sdram_addr[2].

mem_cs_n[5:0]

mem_oe_n

Output

H

Low with Memory Chip Select Negated

internal Recommend external pull-up.

Signals that a Memory Bank is actively selected.

pull-up

High

Memory Output Enable Negated

Recommend external pull-up.

Signals that a Memory Bank can output its data lines onto the cpu_ad bus.

Table 1 Pin Description (Part 1 of 7)

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IDT 79RC32334—Rev. Y

Reset

Type State

Status

Drive

Name

Strength

Capability

Description

mem_we_n[3:0]

Output

H

High

—

Memory Write Enable Negated Bus

Signals which bytes are to be written during a memory transaction. Bits act as Byte Enable and

mem_addr[1:0] signals for 8-bit or 16-bit wide addressing.

mem_wait_n

Input

Memory Wait Negated

Requires external pull-up.

SRAM/IOI/IOM modes: Allows external wait-states to be injected during last cycle before data is sampled.

DPM (dual-port) mode: Allows dual-port busy signal to restart memory transaction.

Alternate function: sdram_wait_n.

mem_245_oe_n

mem_245_dt_r_n

output_clk

Output

H

Z

Low

High

Memory FCT245 Output Enable Negated

Controls output enable to optional FCT245 transceiver bank by asserting during both reads and writes to

a memory or I/O bank.

Memory FCT245 Direction Xmit/Rcv Negated

Recommend external pull-up.

Alternate function: cpu_dt_r_n. See CPU Core Specific Signals below.

Output cpu_mas

terclk

Output Clock

Optional clock output.

PCI Interface

pci_ad[31:0]

I/O

Z

PCI

PCI Multiplexed Address/Data Bus

Address driven by Bus Master during initial frame_n assertion, and then the Data is driven by the Bus

Master during writes; or the Data is driven by the Bus Slave during reads.

pci_cbe_n[3:0]

pci_par

PCI Multiplexed Command/Byte Enable Bus

Command (not negated) Bus driven by the Bus Master during the initial frame_n assertion. Byte Enable

Negated Bus driven by the Bus Master during the data phase(s).

PCI Parity

Even parity of the pci_ad[31:0] bus. Driven by Bus Master during Address and Write Data phases. Driven

by the Bus Slave during the Read Data phase.

pci_frame_n

PCI Frame Negated

Driven by the Bus Master. Assertion indicates the beginning of a bus transaction. De-assertion indicates

the last datum.

pci_trdy_n

pci_irdy_n

pci_stop_n

pci_idsel_n

pci_perr_n

pci_serr_n

I/O

Z

PCI

—

PCI Target Ready Negated

Driven by the Bus Slave to indicate the current datum can complete.

PCI Initiator Ready Negated

Driven by the Bus Master to indicate that the current datum can complete.

I/O

PCI Stop Negated

Driven by the Bus Slave to terminate the current bus transaction.

Input

I/O

PCI Initialization Device Select

Uses pci_req_n[2] pin. See the PCI subsection.

Z

PCI

PCI Parity Error Negated

Driven by the receiving Bus Agent 2 clocks after the data is received, if a parity error occurs.

I/O

System Error

Open-

collector

External pull-up resistor is required.

Driven by any agent to indicate an address parity error, data parity during a Special Cycle command, or

any other system error.

pci_clk

Input

—

PCI Clock

Clock for PCI Bus transactions. Uses the rising edge for all timing references.

Table 1 Pin Description (Part 2 of 7)

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IDT 79RC32334—Rev. Y

Reset

Type State

Status

Drive

Name

Strength

Capability

Description

pci_rst_n

Input

L

—

PCI Reset Negated

Host mode: Resets all PCI related logic.

Satellite mode: Resets all PCI related logic and also warm resets the 32334.

pci_devsel_n

pci_req_n[2]

I/O

Z

PCI

—

PCI Device Select Negated

Driven by the target to indicate that the target has decoded the present address as a target address.

Input

PCI Bus Request #2 Negated

Requires external pull-up.

Host mode: pci_req_n[2] is an input indicating a request from an external device.

Satellite mode: used as pci_idsel pin which selects this device during a configuration read or write.

Alternate function: pci_idsel (satellite).

pci_req_n[1]

pci_req_n[0]

pci_gnt_n[2]

Input

I/O

Z

—

PCI Bus Request #1 Negated

Requires external pull-up.

Host mode: pci_req_n[1] is an input indicating a request from an external device.

Alternate function: Unused (satellite).

High

PCI Bus Request #0 Negated

Requires external pull-up for burst mode.

Host mode: pci_req_n[0] is an input indicating a request from an external device.

Satellite mode: pci_req_n[0] is an output indicating a request from this device.

Output

Z¹

PCI Bus Grant #2 Negated

Recommend external pull-up.

Host mode: pci_gnt_n[2] is an output indicating a grant to an external device.

Satellite mode: pci_gnt_n[2] is used as the pci_inta_n output pin.

Alternate function: pci_inta_n (satellite).

pci_gnt_n[1] /

pci_eeprom_cs

I/O X for 1 pci

clock then

H²

High

PCI Bus Grant #1 Negated

Recommend external pull-up.

Host mode: pci_gnt_n[1] is an output indicating a grant to an external device.

Satellite mode: Used as pci_eprom_cs output pin for Serial Chip Select for loading PCI Configuration

Registers in the RC32334 Reset Initialization Vector PCI boot mode. Defaults to the output direction at

reset time.

1st Alternate function: pci_eeprom_cs (satellite).

2nd Alternate function: PIO[11].

pci_gnt_n[0]

I/O

Z

High

PCI Bus Grant #0 Negated

Host mode: pci_gnt_n[0] is an output indicating a grant to an external device. Recommend external pull-

up.

Satellite mode: pci_gnt_n[0] is an input indicating a grant to this device. Require external pull-up.

pci_inta_n

pci_lock_n

Output

Open-

collector

PCI

—

PCI Interrupt #A Negated

Uses pci_gnt_n[2]. See the PCI subsection.

Input

PCI Lock Negated

Driven by the Bus Master to indicate that an exclusive operation is occurring.

¹Z in host mode; L in satellite non-boot mode; Z in satellite boot mode.

²H in host mode; L in satellite non-boot and boot modes. X = unknown.

SDRAM Control Interface

sdram_addr_12

sdram_ras_n

Output

L

High

SDRAM Address Bit 12 and Precharge All

SDRAM mode: Provides SDRAM address bit 12 (10 on the SDRAM chip) during row address and "pre-

charge all" signal during refresh, read and write command.

H

SDRAM RAS Negated

SDRAM mode: Provides SDRAM RAS control signal to all SDRAM banks.

Table 1 Pin Description (Part 3 of 7)

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August 31, 2004

IDT 79RC32334—Rev. Y

Reset

Drive

Name

sdram_cas_n

sdram_we_n

sdram_cke

Type State

Status

Strength

Capability

Description

Output

H

High

SDRAM CAS Negated

SDRAM mode: Provides SDRAM CAS control signal to all SDRAM banks.

SDRAM WE Negated

SDRAM mode: Provides SDRAM WE control signal to all SDRAM banks.

SDRAM Clock Enable

SDRAM mode: Provides clock enable to all SDRAM banks.

sdram_cs_n[3:0]

SDRAM Chip Select Negated Bus

Recommend external pull-up.

SDRAM mode: Provides chip select to each SDRAM bank.

SODIMM mode: Provides upper select byte enables [7:4].

sdram_s_n[1:0]

Output

H

High

Low

SDRAM SODIMM Select Negated Bus

SDRAM mode: Not used.

SDRAM SODIMM mode: Upper and lower chip selects.

sdram_bemask_n

[3:0]

SDRAM Byte Enable Mask Negated Bus (DQM)

SDRAM mode: Provides byte enables for each byte lane of all DRAM banks.

SODIMM mode: Provides lower select byte enables [3:0].

sdram_245_oe_n

SDRAM FCT245 Output Enable Negated

Recommend external pull-up.

SDRAM mode: Controls output enable to optional FCT245 transceiver bank by asserting during both

reads and writes to any DRAM bank.

sdram_245_dt_r_n Output

Z

High

Low

SDRAM FCT245 Direction Transmit/Receive

Recommend external pull-up.

Uses cpu_dt_r_n. See CPU Core Specific Signals below.

On-Chip Peripherals

dma_ready_n[1:0] /

dma_done_n[1:0]

I/O

DMA Ready Negated Bus

Requires external pull-up.

Ready mode: Input pin for each general purpose DMA channel that can initiate the next datum in the cur-

rent DMA descriptor frame.

Done mode: Input pin for each general purpose DMA channel that can terminate the current DMA descrip-

tor frame.

dma_ready_n[0] 1st Alternate function PIO[1]; 2nd Alternate function: dma_done_n[0].

dma_ready_n[1] 1st Alternate function PIO[0]; 2nd Alternate function: dma_done_n[1].

pio[15:0]

See

Low

Programmable Input/Output

General purpose pins that can each be configured as a general purpose input or general purpose output.

These pins are multiplexed with other pin functions:

uart_cts_n[0], uart_dsr_n[0], uart_dtr_n[0], uart_rts_n[0], pci_gnt_n[1], spi_mosi, spi_miso, spi_sck,

spi_ss_n, uart_rx[0], uart_tx[0], uart_rx[1], uart_tx[1], timer_tc_n[0], dma_ready_n[0], dma_ready_n[1].

Note that pci_gnt_n[1], spi_mosi, spi_sck, and spi_ss_n default to outputs at reset time. The others

default to inputs.

timer_tc_n[0] /

timer_gate_n[0]

I/O

Z

Low

Timer Terminal Count Overflow Negated

Terminal count mode (timer_tc_n): Output indicating that the timer has reached its count compare value

and has overflowed back to 0.

Gate mode (timer_gate_n): input indicating that the timer may count one tick on the next clock edge.

1st Alternate function: PIO[2].

2nd Alternate function: timer_gate_n[0].

uart_rx[1:0]

UART Receive Data Bus

UART mode: Each UART channel receives data on their respective input pin.

uart_rx[0] Alternate function: PIO[6].

uart_rx[1] Alternate function: PIO[4].

Table 1 Pin Description (Part 4 of 7)

8 of 30

August 31, 2004

IDT 79RC32334—Rev. Y

Reset

Type State

Status

Drive

Name

Strength

Capability

Description

uart_tx[1:0]

I/O

Z

L

Low

UART Transmit Data Bus

UART mode: Each UART channel sends data on their respective output pin. Note that these pins default

to inputs at reset time and must be programmed via the PIO interface before being used as UART out-

puts.

uart_tx[0] Alternate function: PIO[5].

uart_tx[1] Alternate function: PIO[3].

uart_cts_n[0]

uart_dsr_n[0]

uart_dtr_n[0]

uart_rts_n[0]

UART Transmit Data Bus

UART mode: Data bus modem control signal pins for UART channel 0.

uart_cts_n[0] Alternate function: PIO[15].

uart_dsr_n[0] Alternate function: PIO[14].

uart_dtr_n[0] Alternate function: PIO[13].

uart_rts_n[0] Alternate function: PIO[12].

spi_mosi

SPI Data Output

Serial mode: Output pin from RC32334 as an Input to a Serial Chip for the Serial data input stream.

In PCI satellite mode, acts as an Output pin from RC32334 that connects as an Input to a Serial Chip for

the Serial data input stream for loading PCI Configuration Registers in the RC32334 Reset Initialization

Vector PCI boot mode.

1st Alternate function: PIO[10]. Defaults to the output direction at reset time.

2nd Alternate function: pci_eeprom_mdo.

spi_miso

I/O

Z

Low

SPI Data Input

Serial mode: Input pin to RC32334 from the Output of a Serial Chip for the Serial data output stream.

In PCI satellite mode, acts as an Input pin from RC32334 that connects as an output to a Serial Chip for

the Serial data output stream for loading PCI Configuration Registers in the RC32334 Reset Initialization

Vector PCI boot mode.

Defaults to input direction at reset time.

1st Alternate function: PIO[7].

2nd Alternate function: pci_eeprom_mdi.

spi_sck

I/O

L

SPI Clock

Serial mode: Output pin for Serial Clock.

In PCI satellite mode, acts as an Output pin for Serial Clock for loading PCI Configuration Registers in the

RC323334 Reset Initialization Vector PCI boot mode.

1st Alternate function: PIO[9]. Defaults to the output direction at reset time.

2nd Alternate function: pci_eeprom_sk.

spi_ss_n

H

Low

—

SPI Chip Select

Output pin selecting the serial protocol device as opposed to the PCI satellite mode EEPROM device.

Alternate function: PIO[8]. Defaults to the output direction at reset time.

CPU Core Specific Signals

cpu_nmi_n

Input

CPU Non-Maskable Interrupt

Requires external pull-up.

This interrupt input is active low to the CPU.

cpu_masterclk

Input

—

CPU Master System Clock

Provides the basic system clock.

cpu_int_n[5:4], [2:0] Input

CPU Interrupt

Requires external pull-up.

These interrupt inputs are active low to the CPU.

cpu_coldreset_n

Input

L

—

CPU Cold Reset

This active-low signal is asserted to the RC32334 after V_ccbecomes valid on the initial power-up. The

Reset initialization vectors for the RC32334 are latched by cold reset.

Table 1 Pin Description (Part 5 of 7)

9 of 30

August 31, 2004

IDT 79RC32334—Rev. Y

Reset

Type State

Status

Drive

Name

Strength

Capability

Description

cpu_dt_r_n

Output

Z

—

CPU Direction Transmit/Receive

This active-low signal controls the DT/R pin of an optional FCT245 transceiver bank. It is asserted during

read operations.

1st Alternate function: mem_245_dt_r_n.

2nd Alternate function: sdram_245_dt_r_n.

JTAG Interface Signals

jtag_tck

Input

—

JTAG Test Clock

Requires external pull-down.

An input test clock used to shift into or out of the Boundary-Scan register cells. jtag_tck is independent of

the system and the processor clock with nominal 50% duty cycle.

jtag_tdi,

Input

JTAG Test Data In

Requires an external pull-up on the board.

ejtag_dint_n

On the rising edge of jtag_tck, serial input data are shifted into either the Instruction or Data register,

depending on the TAP controller state. During Real Mode, this input is used as an interrupt line to stop the

debug unit from Real Time mode and return the debug unit back to Run Time Mode (standard JTAG).

This pin is also used as the ejtag_dint_n signal in the EJTAG mode.

jtag_tdo,

ejtag_tpc

Output

Input

Z

High

—

JTAG Test Data Out

The jtag_tdo is serial data shifted out from instruction or data register on the falling edge of jtag_tck. When

no data is shifted out, the jtag_tdo is tri-stated. During Real Time Mode, this signal provides a non-

sequential program counter at the processor clock or at a division of processor clock. This pin is also used

as the ejtag_tpc signal in the EJTAG mode.

jtag_tms

JTAG Test Mode Select

Requires external pull-up.

The logic signal received at the jtag_tms input is decoded by the TAP controller to control test operation.

jtag_tms is sampled on the rising edge of the jtag_tck.

jtag_trst_n

Input

Output

I/O

L

Z

—

JTAG Test Reset

When neither JTAG nor EJTAG are being used, jtag_trst_n must be driven low (pulled down) or the

jtag_tms/ejtag_tms signals must be pulled up and jtag_clk actively clocked.

ejtag_dclk

EJTAG Test Clock

Processor Clock. During Real Time Mode, this signal is used to capture address and data from the

ejtag_tpc signal at the processor clock speed or any division of the internal pipeline.

ejtag_pcst[2:0]

Low

EJTAG PC Trace Status Information

111 (STL) Pipe line Stall

110 (JMP) Branch/Jump forms with PC output

101 (BRT) Branch/Jump forms with no PC output

100 (EXP) Exception generated with an exception vector code output

011 (SEQ) Sequential performance

010 (TST) Trace is outputted at pipeline stall time

001 (TSQ) Trace trigger output at performance time

000 (DBM) Run Debug Mode

Alternate function: modebit[2:0].

ejtag_debugboot

ejtag_tms

Input

—

EJTAG DebugBoot

Requires The ejtag_debugboot input is used during reset and forces the CPU core to take a debug exception at the

external pull-

down

end of the reset sequence instead of a reset exception. This enables the CPU to boot from the ICE probe

without having the external memory working. This input signal is level sensitive and is not latched inter-

nally. This signal will also set the JtagBrk bit in the JTAG_Control_Register[12].

—

Requires

external pull-

up

EJTAG Test Mode Select

An external pull-up on the board is required.

The ejtag_tms is sampled on the rising edge of jtag_tck.

Table 1 Pin Description (Part 6 of 7)

10 of 30

August 31, 2004

IDT 79RC32334—Rev. Y

Reset

Type State

Status

Drive

Name

Strength

Capability

Description

Debug Signals

debug_cpu_dma_n

I/O

Z

Low

Debug CPU versus DMA Negated

De-assertion high during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transac-

tion was generated from the CPU.

Assertion low during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transaction

was generated from DMA.

Alternate function: modebit[6].

debug_cpu_ack_n

debug_cpu_ads_n

I/O

Z

Low

Debug CPU Acknowledge Negated

Indicates either a data acknowledge to the CPU or DMA.

Alternate function: modebit[4].

Debug CPU Address/Data Strobe Negated

Assertion indicates that either a CPU or a DMA transaction is beginning and that the mem_data[31:4] bus

has the current block address.

Alternate function: modebit[5].

debug_cpu_i_d_n

I/O

Z

Low

Debug CPU Instruction versus Data Negated

Assertion during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transaction is a

CPU or DMA data transaction.

De-assertion during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transaction is a

CPU instruction transaction.

Alternate function: modebit[3].

Table 1 Pin Description (Part 7 of 7)

Mode Bit Settings to Configure Controller on Reset

The following table lists the mode bit settings to configure the controller on cold reset.

Mode Bit

Description

Value

Mode Setting

ejtag_pcst[2:0]

2:0 MSB (2) Clock Multiplier

0

1

2

3

4

5

6

7

0

1

0

1

Multiply by 2

Multiply by 3

Multiply by 4

Reserved

MasterClock is multiplied internally to gener-

ate PClock

Reserved

debug_cpu_i_d_n

3

EndBit

Little-endian ordering

Big-endian ordering

debug_cpu_ack_n

debug_cpu_ads_n

debug_cpu_dma_n

4

5

6

Reserved

TmrIntEn

Enables timer interrupt

Disables timer interrupt

Enables/Disables the timer interrupt on Int*[5]

mem_addr[17]

7

Reserved for future use

Table 2 Boot-Mode Configuration Settings (Part 1 of 2)

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August 31, 2004

IDT 79RC32334—Rev. Y

Mode Bit

Description

Value

Mode Setting

8 bits

mem_addr[19:18] 9:8 MSB (9)

Boot-Prom Width specifies the memory port

width of the memory space which contains

the boot prom.

00

01

10

11

16 bits

32 bits

Reserved

Table 2 Boot-Mode Configuration Settings (Part 2 of 2)

reset_boot_mode Settings

By using the non-boot mode cold reset initialization mode the user can change the internal register addresses from base 1800_0000 to base

1900_0000, as required. The RC32334 cold reset-boot mode initialization setting values and mode descriptions are listed below.

Reset Boot Mode

Description

Value Mode Settings

mem_addr[22:21] 1:0 MSB (1)

Tri-state memory bus and EEPROM bus during cold reset_n

assertion

11

Tri-state_bus_mode

Reserved

10

01

PCI-boot mode (pci_host_mode must be in satellite mode)

RC32334 will reset either from a cold reset or from a PCI

reset. Boot code is provided via PCI.

PCI_boot_mode

Standard-boot mode

00

standard_boot_mode

Boot from the RC32334’s memory controller (typical system).

Table 3 RC32334 reset_boot_mode Initialization Settings

pci_host_mode Settings

During cold reset initialization, the RC32334’s PCI interface can be set to the Satellite or Host mode settings. When set to the Host mode, the CPU

must configure the RC32334’s PCI configuration registers, including the read-only registers. If the RC32334’s PCI is in the PCI-boot mode Satellite

mode, read-only configuration registers are loaded by the serial EEPROM.

Reset Boot Mode

Description

Value Mode Settings

mem_addr[20] PCI host mode

PCI is in satellite mode

1

0

PCI_satellite

PCI_host

PCI is in host mode (typical system)

Table 4 RC32334 pci_host_mode Initialization Settings

12 of 30

August 31, 2004

IDT 79RC32334—Rev. Y

Logic Diagram — RC32334

mem_addr[25:2]

cpu_masterclk

cpu_coldreset_n

cpu_nmi_n

mem_data[31:0]

mem_cs_n[5:0]

mem_oe_n

mem_we_n[3:0]

mem_wait_n

mem_245_oe_n

cpu_int_n[5:4],[2:0]

cpu_dt_r_n

mem_245_dt_r_n

output_clk

pci_cbe_n[3:0]

pci_ad[31:0]

pci_par

pci_frame_n

pci_trdy_n

spi_mosi

spi_miso

pci_irdy_n

spi_ss_n

spi_sck

pci_stop_n

pci_idsel

pci_perr_n

pci_serr_n

pci_clk

pci_rst_n

pci_devsel_n

pci_req_n[2:0]

sdram_addr[16:13]

sdram_addr[12]

sdram_addr[11:2]

sdram_ras_n

sdram_cas_n

sdram_we_n

RC32334

Logic

pci_gnt_n[2:0]

pci_inta_n

Symbol

sdram_cke

sdram_cs_n[3:0]

sdram_bemask_n[3:0]

sdram_245_oe_n

pci_lock_n

pci_eeprom_mdi

pci_eeprom_mdo

pci_eeprom_cs

pci_eeprom_sk

sdram_245_dt_r_n

sdram_s_n_[1:0]

dma_ready_n[1:0]

jtag_tck

jtag_tms

jtag_tdi

jtag_tdo

timer_tc_n[0]

uart_rx[1:0]

jtag_trst_n

uart_tx[1:0]

uart_cts_n[0]

debug_cpu_dma_n

debug_cpu_ack_n

debug_cpu_i_d_n

debug_cpu_ads_n

uart_rts_n[0]

uart_dtr_n[0]

uart_dsr_n[0]

ejtag_dclk

ejtag_pcst[2:0]

ejtag_tms

ejtag_debugboot

ejtag_tpc

V_ss

Gnd

V_ccI/O

V_cccore

V_ccto I/O

V_ccto core

V_ccP

V_ssP

pio[15:0]

13 of 30

August 31, 2004

IDT 79RC32334—Rev. Y

Clock Parameters — RC32334

(Ta = 0°C to +70°C Commercial, Ta = -40°C to +85°C Industrial, V_ccI/O = +3.3V 5%,V_ccCore = +3.3V 5%)

RC32334

100MHz

RC32334

133MHz

RC32334

150MHz

Parameter

Symbol

Test Conditions

Units

Min

8

Max

—

Min

6.75

15

Max

—

Min

6

Max

—

cpu_masterclock HIGH

cpu_masterclock LOW

cpu_masterclock period¹

t_MCHIGH

t_MCLOW

Transition ≤ 2ns

ns

ps

ns

Transition ≤ 2ns

8

—

6

—

20

—

15

—

10

100

4

66.6

3

66.6

3

13.33

—

66.6

3

tMCP

cpu_masterclock Rise & Fall Time²t_{MCRise, MCFall}

t

—

cpu_masterclock Jitter

pci_clk Rise & Fall Time

pci_clk Period¹

t_JITTER

t_{PCRise, PCFall}

t_PCP

t_{JCRise, JCFall}

t_{DCK, 11}

t_{TCK, 3}

t_{DCK High, 9}

—

+ 250

1.6

—

+ 250

1.6

—

+ 200

1.6

—

t

PCI 2.2

—

15

—

jtag_tck Rise & Fall Time

ejtag_dck period

t

—

5

—

5

t

—

10

—

10

100

4

—

jtag_tck clock period

ejtag_dclk High, Low Time

t

—

100

4

—

t

—

t_{DCK Low, 10}

t

ejtag_dclk Rise, Fall Time

output_clk³

t

_{DCK Rise,}t₉

—

1

—

1

—

1

ns

t_{DCK Fall, 10}

t

Tdo21

N/A

120

N/A

—

N/A

120

N/A

—

N/A

120

N/A

—

cpu_coldreset_n

power-on sequence

ms

Asserted during power-up

cpu_coldreset_n Rise Time

t_CRRise

—

5

—

5

—

5

ns

Table 5 Clock Parameters - RC32334

cpu_masterclock frequency should never be below pci_clk frequency if PCI interface is used.

1.

2.

3.

Rise and fall times are measured between 10% and 90%

Output_clk should not be used in a system. Only the cpu_masterclock or its derivative must be used to drive all the subsystems with designs based on the

RC32334 device. Refer to the RC3233x Device Errata for more information.

Reset Specification

VCC

cpu_masterclk

(MClk)

cpu_coldreset_n

modebit[9:0]

t_CRRise

>= 110 ms

120 ms

>= 10 ms

Figure 3 Mode Configuration Interface Cold Reset Sequence

14 of 30

August 31, 2004

IDT 79RC32334—Rev. Y

Power Ramp-up

There is no special requirement for how fast Vcc and VccP ramp up to 3.3V. However, all timing references are based on Vcc and VccP stabilized

at 3.3V -5%.

AC Timing Characteristics — RC32334

(Ta = 0°C to +70°C Commercial, Ta = -40°C to +85°C Industrial, V_ccI/O = +3.3V 5%,V_ccCore = +3.3V 5%)

RC32334¹RC32334¹RC32334¹

100MHz 133MHz 150MHz

User

Manual

Reference

Edge

Signal

Symbol

Unit

Timing

Diagram

Reference

Min

Max

Min

Max

Min

Max

Local System Interface

mem_data[31:0] (data phase)

cpu_dt_r_n

Tsu2

Thld2

Tdo3

Tdo4

Tdoh1

Tdz

cpu_masterclk rising

6

1.5

—

1

—

5

1.5

—

1

—

12

10

—

10²

—

9

4.8

1.5

—

1

—

10

9.3

—

9.3²

—

8

ns

15

12

—

12²

—

ns Chapter 9,

Figures 9.2

and 9.3

mem_data[31:0]

ns

mem_data[31:0] output hold time

mem_data[31:0] (tristate disable time)

mem_data[31:0] (tristate to data time)

mem_wait_n

—

9

—

7

—

6

Tzd

Tsu6

Thld8

Tdo5

Tdo6

Tdo7

Tdo7a

Tdo8

Tdoh3

mem_wait_n

1

—

1

ns Chapter 10,

Figures 10.6

mem_addr[25:2]

—

1.5

12

15

—

1.5

—

1.5

ns

through 10.8

ns

mem_cs_n[5:0]

9

8

mem_oe_n, mem_245_oe_n

mem_we_n[3:0]

9

8

ns

12

—

10

—

mem_245_dt_r_n

mem_addr[25:2]

mem_cs_n[5:0]

mem_oe_n, mem_we_n[3:0], mem_245_dt_r_n,

mem_245_oe_n

PCI

pci_ad[31:0], pci_cbe_n[3:0], pci_par, pci_frame_n, Tsu

pci_trdy_n, pci_irdy_n, pci_stop_n, pci_perr_n,

pci_serr_n, pci_devsel_n, pci_lock_n³

pci_clk rising

3

5

—

3

5

—

3

5

—

ns

pci_idsel, pci_req_n[2], pci_req_n[1], pci_req_n[0], Tsu

pci_gnt_n[0], pci_inta_n

pci_gnt_n[0]

Tsu

pci_clk rising

5

0

—

5

0

—

5

0

—

ns

pci_ad[31:0], pci_cbe_n[3:0], pci_par, pci_frame_n, Thld

pci_trdy_n, pci_irdy_n, pci_stop_n, pci_perr_n,

pci_serr_n, pci_rst_n, pci_devsel_n, pci_lock_n³

ns Per PCI 2.2

pci_idsel, pci_req_n[2], pci_req_n[1], pci_req_n[0], Thld

pci_gnt_n[0], pci_inta_n

pci_clk rising

0

—

0

—

0

—

ns

pci_eeprom_mdi

Tsu

pci_clk rising,

15

12

10

pci_eeprom_sk falling

Table 6 AC Timing Characteristics - RC32334 (Part 1 of 4)

15 of 30

August 31, 2004

IDT 79RC32334—Rev. Y

RC32334¹RC32334¹RC32334¹

100MHz 133MHz 150MHz

User

Manual

Reference

Edge

Signal

Symbol

Unit

Timing

Diagram

Reference

Min

Max

Min

Max

Min

Max

pci_eeprom_mdi

Thld

Tdo

pci_clk rising,

pci_eeprom_sk falling

15

—

12

—

10

—

ns

pci_eeprom_mdo, pci_eeprom_cs

pci_clk rising,

pci_eeprom_sk falling

—

15

—

12

—

10

pci_eeprom_sk

pci_clk rising

—

2

15

6

—

2

12

6

—

2

10

6

ns

pci_ad[31:0], pci_cbe_n[3:0], pci_par, pci_frame_n, Tdo

pci_trdy_n, pci_irdy_n, pci_stop_n, pci_perr_n,

pci_serr_n, pci_devsel_n

Per PCI 2.2

pci_req_n[0], pci_gnt_[2], pci_gnt_n[1],

pci_gnt_n[0], pci_inta_n

Tdo

pci_clk rising

2

6

2

6

2

6

ns

SDRAM Controller

sdram_245_dt_r_n

Tdo8

Tdo9

cpu_masterclk rising

—

15

12

—

12

9

—

10

8

ns

sdram_ras_n, sdram_cas_n, sdram_we_n,

sdram_cs_n[3:0], sdram_s_n[1:0],

sdram_bemask_n[3:0], sdram_cke

sdram_addr_12

Tdo10

Tdo11

Tdoh4

cpu_masterclk rising

—

1

12

—

1

9

—

1

8

ns

Chapter 11,

Figures 11.4

and 11.5

sdram_245_oe_n

sdram_245_dt_r_n

—

sdram_ras_n, sdram_cas_n, sdram_we_n,

sdram_cs_n[3:0], sdram_s_n[1:0],

sdram_bemask_n[3:0] sdram_cke,

sdram_addr_12, sdram_245_oe_n

2.5

DMA

dma_ready_n[1:0], dma_done_n[1:0]

Interrupt Handling

cpu_int_n[5:4], cpu_int_n[2:0], cpu_nmi_n

PIO

Tsu7

cpu_masterclk rising

9

1

—

7

1

—

6

1

—

ns Chapter 13,

Figure 13.4

Thld9

ns

Tsu9

cpu_masterclk rising

9

1

—

9

1

—

6

1

—

ns Chapter 14,

Figure 14.12

Thld13

ns

PIO[15:0]

Tsu7

cpu_masterclk rising

9

1

—

15

—

7

1

—

12

—

6

1

—

10

—

ns

PIO[15:0]

Thld9

Tdo16

Tdo19

Tdoh7

ns Chapter 15,

Figures 15.9

PIO[15:10], PIO[8:0]

PIO[9]

—

1

—

1

—

1

ns

and 15.10

ns

PIO[15:10], PIO[8:0]

PIO[9]

ns

1

Timer

timer_tc_n[0], timer_gate_n[0]

Tsu8

cpu_masterclk rising

9

1

—

15

—

7

1

—

12

—

6

1

—

10

—

ns

Thld10

Tdo15

Tdoh6

ns Chapter 16,

Figures 16.6

—

1

—

1

—

1

ns

and 16.7

ns

Table 6 AC Timing Characteristics - RC32334 (Part 2 of 4)

16 of 30

August 31, 2004

IDT 79RC32334—Rev. Y

RC32334¹RC32334¹RC32334¹

100MHz 133MHz 150MHz

User

Manual

Reference

Edge

Signal

Symbol

Unit

Timing

Diagram

Reference

Min

Max

Min

Max

Min

Max

UARTs

uart_rx[1:0], uart_tx[1:0], uart_cts_n[0],

uart_dsr_n[0], uart_dtr_n[0], uart_rts_n[0]

Tsu7

cpu_masterclk rising

15

—

1

—

15

—

12

—

1

—

12

—

10

—

1

—

10

—

ns

Chapter 17,

Figure 17.16

uart_rx[1:0], uart_tx[1:0], uart_cts_n[0],

uart_dsr_n[0], uart_dtr_n[0], uart_rts_n[0]

Thld9

Tdo16

Tdoh8

uart_rx[1:0], uart_tx[1:0], uart_cts_n[0],

uart_dsr_n[0], uart_dtr_n[0], uart_rts_n[0]

uart_rx[1:0], uart_tx[1:0], uart_cts_n[0],

uart_dsr_n[0], uart_dtr_n[0], uart_rts_n[0]

SPI Interface

spi_clk, spi_mosi, spi_miso

Reset

Tsu7

cpu_masterclk rising

15

—

1

—

15

—

12

—

1

—

12

—

10

—

1

—

10

—

ns

Chapter 18,

Figures 18.8

and 18.9

Thld9

Tdo16

Tdoh8

mem_addr[19:17]

Tsu10

Thld10

Tsu22

Thld22

cpu_coldreset_n rising 10

—

10

1

—

10

1

—

ms Chapter 19

Figures 19.8

and 19.9

mem_addr[19:17]

cpu_coldreset_n rising

cpu_masterclk rising

1

9

1

ns

mem_addr[22:20],

mem_addr[22:20]

7

6

1

Debug Interface

debug_cpu_dma_n, debug_cpu_ack_n,

debug_cpu_ads_n, debug_cpu_i_d_n,

ejtag_pcst[2:0]

Tsu20

cpu_coldreset_n rising 10

—

10

1

—

10

1

—

ms

debug_cpu_dma_n, debug_cpu_ack_n,

debug_cpu_ads_n, debug_cpu_i_d_n,

ejtag_pcst[2:0]

Thld20

cpu_coldreset_n rising

1

ns Chapter 19,

Figure 19.9 and

Chapter 9,

Figure 9.2

debug_cpu_dma_n, debug_cpu_ack_n,

debug_cpu_ads_n, debug_cpu_i_d_n

Tdo20

cpu_masterclk rising

—

1

15

—

1

12

—

1

10

—

ns

debug_cpu_dma_n, debug_cpu_ack_n,

debug_cpu_ads_n, debug_cpu_i_d_n

Tdoh20

JTAG Interface

jtag_tms, jtag_tdi, jtag_trst_n

jtag_tdo

t₅

t₆

t₄

jtag_tck rising

jtag_tck falling

10

—

10

—

10

—

10

ns

See Figure 4

below.

Table 6 AC Timing Characteristics - RC32334 (Part 3 of 4)

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August 31, 2004

IDT 79RC32334—Rev. Y

RC32334¹RC32334¹RC32334¹

100MHz 133MHz 150MHz

User

Manual

Reference

Edge

Signal

Symbol

Unit

Timing

Diagram

Reference

Min

Max

Min

Max

Min

Max

EJTAG Interface

ejtag_tms, ejtag_debugboot

jtag_tdo Output Delay Time

jtag_tdi Input Setup Time

jtag_tdi Input Hold Time

jtag_trst_n Low Time

t₅

t₆

jtag_tclk rising

4

2

—

6

4

2

—

6

4

2

—

6

ns See Figure 4

below.

jtag_clk rising

jtag_tck falling

jtag_tck rising

—

ns

t_{TDODO, 4}

t_{TDIS, 5}

t_{TDIH, 6}

t_{TRSTLow, 12}

t

—

4

—

4

—

4

ns

t

—

3

—

3

—

3

t

2

t

100

3

100

3

100

3

jtag_trst_n Removal Time

ejtag_tpc Output Delay Time

ejtag_pcst Output Delay Time

t_TRSTR,t₁₃jtag_tck rising

t_{TPCDO, 8}

t

ejtag_dclk rising

-1

t_{PCSTDO, 7}

t

3

Table 6 AC Timing Characteristics - RC32334 (Part 4 of 4)

1.

At all pipeline frequencies.

2.

Guaranteed by design.

3.

pci_rst_n is tested per PCI 2.2 as an asynchronous signal.

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August 31, 2004

IDT 79RC32334—Rev. Y

Standard EJTAG Timing — RC32334

Figure 4 represents the timing diagram for the EJTAG interface signals.

The standard JTAG connector is a 10-pin connector providing 5 signals and 5 ground pins. For Standard EJTAG, a 24-pin connector has been

chosen providing 12 signals and 12 ground pins. This guarantees elimination of noise problems by incorporating signal-ground type arrangement.

Refer to the RC32334 User Reference Manual for connector pinout and mechanical specifications.

ejtag_tpc,ejtag_pcst[2:0] capture

t3

jtag_tck

t14

t11

t15

t1

t2

ejtag_dclk

t15

jtag_tdi/ejtag_dint_n

ejtag_tms

t9

t10

ejtag_tpc

ejtag_pcst

t5

t6

jtag_tdo/ejtag_tpc,

ejtag_tpc[8:2]

jtag_tdo

t4

jtag_tdo

t8

t7

ejtag_pcst[2:0]

jtag_trst_n

t13

Notes to diagram:

t1 = t_TCKlow

t2 = t_TCKHIGH

t3 = t_TCK

t11 = t_DCK

t12 = t_TRSTDO

t13 = t_TRSTR

t12

t4 = t_TDODO

t5 = t_TDIS

t14 = t_{TCK RISE, tTCK FALL}

t15 = t_{DCK RISE, DCK FALL}

t

t6 = t_TDIH

t7 = t_PCSTDO

t8 = t_TPCDO

t9 = t_DCKHIGH

t10 = t_DCKLOW

Figure 4 Standard EJTAG Timing

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IDT 79RC32334—Rev. Y

Output Loading for AC Testing

To Device

Under Test

–

V_REF

+1.5V

+

C

LD

Signal

Cld

All High Drive Signals

All Low Drive Signals

50 pF

25 pF

Figure 5 Output Loading for AC Testing

Note: PCI pins have been correlated to PCI 2.2.

Recommended Operation Temperature and Supply Voltage

Grade

Temperature

Gnd

V_ccIO

V_ccCore

V_ccP

Commercial

Industrial

0°C to +70°C (Ambient)

-40°C to +85°C (Ambient)

0V

3.3V±5%

Table 7 Temperature and Voltage

DC Electrical Characteristics — RC32334

Commercial Temperature Range—RC32334

(Ta = 0°C to +70°C Commercial, Ta = -40°C to +85°C Industrial, V_ccI/O = +3.3V 5%, V_ccCore = +3.3V 5%)

RC32334¹

Parameter

Pin Numbers

Conditions

Minimum Maximum

Input Pads

V_IL

V_IH

V_OL

V_OH

V_IL

—

2.0V

—

0.8V

—

B14, E13, F4, K1, L2, M1, M3, M4, M14, N1-N3, P14, R2, R16

—

|I_OUT| = 6mA

|I_OUT| = 8mA

—

LOW Drive

Output

Pads

0.4V

—

A1, A12, A15, A16, B1, B2, B12, B15, C1-C3, C12, C13, C14,

D12, D13, E1- E4, F1, F2, G1-G4, H1, H2, J1, J2, K2-K4, L1, L3,

L4, P3, P14, R2, R15, R16, T16

V_cc- 0.4V

—

0.8V

—

V_IH

V_OL

V_OH

V_IL

2.0V

—

HIGH

Drive Out-

put Pads

0.4V

—

A2-A4, A6-A11, A13, A14, B3, B4, B6-B11, B13, B16, C4, C6-C8,

C10, C11, C15, C16, D1-D4, D6, D7, D10, D11, D14-D16, E14,

E15, F3, F13-F16, G13-G16, H15, H16, J13, J14, K5, K13, K14,

K16, L13-L16, M2, M13, M16, P2, P4, R1, R3, R4

|I_OUT| = 7mA

|I_OUT| = 16mA

—

V_cc- 0.4V

—

0.8V

—

V_IH

V_IL

2.0V

—

PCI Drive

—

P1, R1, R10, T2, T3

Per PCI 2.2

Input Pads

V_IH

—

Table 8 DC Electrical Characteristics - RC32334 (Part 1 of 2)

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IDT 79RC32334—Rev. Y

RC32334¹

Parameter

Pin Numbers

Conditions

Minimum Maximum

PCI Drive

Output

Pads

V_OL

V_OH

V_IL

—

M15, N4-N7, N10-N16, P5-P13, P15, P16, R5-R9, R11-R14, T4-

T15

Per PCI 2.2

—

V_IH

C_IN

—

All Pads

—

10pF

12pF

8pF

10pF

10µA

50µA

All input pads except T3 and R3

—

Per PCI 2.2

2

C_IN

5pF

—

T3

3

C_IN

R3

Per PCI 2.2

C_OUT

—

All output pads

—

I/O_LEAK

—

All non-internal pull-up pins

All internal pull-up pins

Input/Output Leakage

—

Table 8 DC Electrical Characteristics - RC32334 (Part 2 of 2)

1.

At all pipeline frequencies.

Applies only to pad T3.

Applies only to pad R3.

2.

3.

Capacitive Load Deration — RC32334

Refer to the IDT document 79RC32334 IBIS Model located on the company’s web site.

Power Consumption — RC32334

Note: This table is based on a 2:1 pipeline-to-bus clock ratio.

100MHz

RC32334

133MHz

RC32334

150MHz

RC32334

Parameter

Unit

Conditions

Typical Max.

I_CC

Normal mode

Standby mode¹

Normal mode

360

250

1.2

480

370

1.7

480

330

1.5

630

480

2.2

550

390

1.7

700

540

2.4

mA

W

C_L= (See Figure 5, Output Loading for

AC Testing)

T_a= 25^oC

Power

Dissipation

V_cccore = 3.46V (for max. values)

V_ccI/O = 3.46V (for max. values)

V_cccore = 3.3V (for typical values)

V_ccI/O = 3.3V (for typical values)

Standby mode¹

.87

1.3

1.1

1.7

1.3

1.9

W

Table 9 Power Consumption

RISCore 32300 CPU core enters Standby mode by executing WAIT instructions. On-chip logic outside the CPU core continues to function.

1.

Power Ramp-up

There is no special requirement for how fast V_ccI/O ramps up to 3.3V. However, all timing references are based on a stable V_ccI/O.

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IDT 79RC32334—Rev. Y

Power Curves

The following two graphs contain the simulated power curves that show power consumption at various bus frequencies.

Note: Only pipeline frequencies that are integer multiples (2x, 3x, 4x) of bus frequencies are supported.

600.0

500.0

2x

3x

400.0

4x

300.0

200.0

100.0

15 20 25 30 35 40 45 50 55 60 65 70 75

System Bus Speed (MHz)

Figure 6 Typical Power Usage - RC32334

.

800.0

700.0

2x

600.0

3x

500.0

4x

400.0

300.0

200.0

100.0

15 20 25 30 35 40 45 50 55 60 65 70 75

System Bus Speed (MHz)

Figure 7 Maximum Power Usage - RC32334

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IDT 79RC32334—Rev. Y

Absolute Maximum Ratings

Symbol

Parameter

Min¹

Max¹

Unit

V_CC

Supply Voltage

-0.3

-0.6

-40

4.0

5.5

—

V

Vi

Input Voltage

V

Vimin

Tstg

Input Voltage - undershoot²

Storage Temperature

125

degrees C

Table 10 Absolute Maximum Ratings

1.

Functional and tested operating conditions are given in Table 7. Absolute maximum ratings are stress ratings only, and

functional operation is not guaranteed beyond recommended operating voltages and temperatures. Stresses beyond those

listed may affect device reliability or cause permanent damage to the device.

2.

All PCI pads are fully compatible with PCI Specification version 2.2.

Package Pin-out — 256-PBGA Pinout for RC32334

The following table lists the pin numbers and signal names for the RC32334. Signal names ending with an “_n” are active when low.

Function

uart_cts_n[0]

Alt Pin

Function

mem_cs_n[4]

Alt Pin

Function

Alt Pin

Function

cpu_int_n[1]

Alt

A1

A2

A3

A4

A5

A6

A7

A8

A9

1

E1

E2

E3

E4

E5

E6

E7

E8

E9

J1

debug_cpu_dma_n

1

N1

N2

N3

N4

N5

N6

N7

N8

N9

sdram_245_oe_n

sdram_cas_n

sdram_bemask_n[1]

sdram_ras_n

mem_cs_n[5]

mem_cs_n[3]

mem_cs_n[2]

J2

debug_cpu_ack_n

1

cpu_int_n[0]

jtag_tdi

J3

V_ccIO

J4

V_ss

pci_ad[30]

pci_ad[26]

pci_ad[23]

pci_ad[19]

V_cccore

V_ss

V

_ccIO

J5

V_ccIO

mem_addr[3]

mem_addr[7]

mem_addr[11]

sdram_cke

1

J6

V_ss

J7

V_ss

V_ccIO

_ccIO

J8

V_ss

V

J9

V_ss

A10 sdram_bemask_n[2]

A11 mem_addr[15]

A12 mem_addr[19]

A13 mem_data[10]

A14 mem_data[20]

A15 mem_addr[23]

A16 timer_tc_n[0]

E10 V_ccIO

J10

J11

J12

J13

J14

J15

J16

K1

K2

K3

V_ss

N10 pci_trdy_n

N11 pci_perr_n

N12 pci_ad[15]

N13 pci_ad[1]

N14 pci_ad[3]

N15 pci_ad[4]

N16 pci_ad[2]

1

E11

E12

V

_ccIO

V_ss

V_ccIO

E13 cpu_masterclk

E14 mem_data[15]

E15 mem_data[16]

mem_data[26]

mem_data[5]

V

_cccore

2

1

E16

F1

F2

F3

F4

F5

F6

F7

F8

V

_cccore

V_ss

B1

B2

B3

B4

B5

B6

B7

B8

uart_rts_n[0]

mem_cs_n[0]

mem_cs_n[1]

mem_oe_n

ejtag_debugboot

ejtag_dclk

debug_cpu_i_d_n

debug_cpu_ads_n

V_ccIO

P1

P2

P3

P4

P5

P6

P7

P8

pci_rst_n

uart_dsr_n[0]

sdram_we_n

pci_gnt_n[2]

dma_ready_n[1]

pci_req_n[0]

pci_ad[27]

1

2

1

sdram_bemask_n[0]

sdram_cs_n[1]

mem_addr[2]

mem_addr[6]

mem_addr[10]

mem_wait_n

1

K4

K5

K6

K7

K8

V

_ccIO

1

V_ss

pci_cbe_n[3]

pci_ad[20]

V_ss

pci_ad[16]

Table 11 RC32334 256-pin PBGA Package Pin-Out (Part 1 of 3)

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August 31, 2004

IDT 79RC32334—Rev. Y

Function

Alt Pin

Function

Alt Pin

Function

Alt Pin

Function

pci_cbe_n[2]

Alt

B9

sdram_addr_12

F9

V_ss

K9

V_ss

P9

B10 sdram_bemask_n[3]

B11 mem_addr[16]

B12 mem_addr[20]

B13 mem_data[11]

B14 cpu_coldreset_n

B15 mem_addr[25]

B16 mem_data[12]

F10 V_ss

F11 V_ss

K10 V_ss

K11 V_ss

P10 pci_devsel_n

P11 pci_serr_n

P12 pci_ad[14]

P13 pci_ad[11]

P14 cpu_int_n[5]

P15 pci_ad[6]

P16 pci_ad[5]

1

F12

V

_ccIO

K12 V_ccIO

F13 mem_data[1]

F14 mem_data[30]

F15 mem_data[31]

F16 mem_data[0]

K13 cpu_dt_r_n

K14 mem_data[6]

K15 mem_data[24]

K16 mem_data[25]

2

C1

C2

C3

C4

C5

C6

C7

C8

C9

uart_rx[0]

1

G1

G2

G3

G4

G5

G6

G7

G8

G9

dma_ready_n[0]

mem_245_oe_n

spi_mosi

2

L1

ejtag_pcst[0]

jtag_trst_n

ejtag_pcst[1]

ejtag_pcst[2]

V_ccIO

R1

R2

R3

R4

R5

R6

R7

R8

R9

pci_req_n[2]

cpu_int_n[2]

pci_gnt_n[1]

pci_gnt_n[0]

pci_ad[29]

pci_ad[25]

pci_ad[22]

pci_ad[18]

pci_irdy_n

1

2

uart_tx[0]

L2

uart_dtr_n[0]

sdram_cs_n[0]

sdram_s_n[0]

mem_addr[4]

mem_addr[9]

output_clk

2

L3

1

spi_miso

L4

V

_ccIO

L5

1

V_ss

L6

V_ss

L7

V_ss

L8

V_ss

mem_addr[12]

L9

V_ss

C10 sdram_cs_n[3]

C11 mem_addr[14]

C12 mem_addr[18]

C13 mem_addr[22]

C14 mem_addr[24]

C15 mem_data[19]

C16 mem_data[13]

G10 V_ss

G11 V_ss

L10

L11

L12

L13

L14

L15

L16

M1

M2

M3

M4

M5

M6

M7

M8

M9

V_ss

R10 pci_lock_n

R11 pci_cbe_n[1]

R12 pci_ad[12]

R13 pci_ad[10]

R14 pci_cbe_n[0]

R15 uart_tx[1]

1

V_ss

G12

V

_ccIO

V_ccIO

G13 mem_data[3]

G14 mem_data[28]

G15 mem_data[29]

G16 mem_data[2]

mem_data[7]

mem_data[8]

mem_data[22]

mem_data[23]

jtag_tms

jtag_tdo

ejtag_tms

jtag_tck

V_ccIO

1

R16 cpu_int_n[4]

D1

D2

D3

D4

D5

D6

D7

D8

D9

mem_we_n[1]

mem_we_n[3]

mem_we_n[2]

mem_we_n[0]

sdram_s_n[1]

mem_addr[5]

mem_addr[8]

V_ss

H1

H2

H3

H4

H5

H6

H7

H8

H9

spi_ss_n

spi_sck

1

2

T1

T2

T3

T4

T5

T6

T7

T8

T9

V_ss

pci_req_n[1]

pci_clk

V

_ccIO

_cccore

pci_ad[31]

pci_ad[28]

pci_ad[24]

pci_ad[21]

pci_ad[17]

pci_frame_n

V_ccIO

V_ss

1

V_ccIO

V_ss

V_ccIO

V_ss

V_ccIO

V

_cccore

V_ss

V_ccIO

D10 sdram_cs_n[2]

D11 mem_addr[13]

D12 mem_addr[17]

D13 mem_addr[21]

H10 V_ss

H11 V_ss

M10 V_ccIO

T10 pci_stop_n

T11 pci_par

1

M11 V_ccIO

H12

V

_ccIO

M12 V_ccIO

T12 pci_ad[13]

T13 pci_ad[9]

H13 V_ssP

M13 mem_data[9]

Table 11 RC32334 256-pin PBGA Package Pin-Out (Part 2 of 3)

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August 31, 2004

IDT 79RC32334—Rev. Y

Pin Function

Alt Pin

H14 V_ccP

Function

Alt Pin

Function

Alt Pin

Function

Alt

D14 mem_data[17]

D15 mem_data[14]

D16 mem_data[18]

M14 cpu_nmi_n

T14 pci_ad[8]

H15 mem_data[27]

H16 mem_data[4]

M15 pci_ad[0]

T15 pci_ad[7]

T16 uart_rx[1]

M16 mem_data[21]

1

Table 11 RC32334 256-pin PBGA Package Pin-Out (Part 3 of 3)

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August 31, 2004

IDT 79RC32334—Rev. Y

Pin Layout

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

A

B

C

D

E

F

Vss Vcc Core

Vcc Core

G

H

J

Vcc Core

Vss

Vcc IO

VccP

VssP

Vss

Vcc Core

K

L

M

N

P

R

T

Vcc I/O

Vss

Vcc Core

Vss

The lighter shaded area shows the ground pins (Vss)

The darker shaded area shows the supply voltage pins (Vcc I/O)

Vcc Core

VccP, VssP

Figure 8 RC32334 Chip — Top View

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August 31, 2004

IDT 79RC32334—Rev. Y

RC32334 Alternate Signal Functions

Alt #1

PIO[15]

Alt #2

Alt #1

PIO[13]

Alt #2

Alt #1

Alt #2

A1

A6

A7

A8

C3

C6

C7

C3

H2

J1

PIO[9]

pci_eeprom_sk

sdram_addr[3]

sdram_addr[7]

sdram_addr[11]

sdram_addr[4]

sdram_addr[9]

modebit[6]

modebit[4]

modebit[3]

modebit[5]

J2

C11 sdram_addr[14]

C12 modebit[8]

K3

K4

A11 sdram_addr[15]

A12 modebit[9]

A16 PIO[2]

C13 reset_boot_mode[1]

K13 mem_245_dt_r_n

sdram_245_dt_r_n

timer_gate_n[0]

D6

D7

sdram_addr[5]

sdram_addr[8]

L1

L3

L4

P2

P3

R1

R3

modebit[0]

B1

B2

B6

B7

B8

PIO[12]

modebit[1]

PIO[14]

D11 sdram_addr[13]

D12 modebit[7]

modebit[2]

sdram_addr[2]

sdram_addr[6]

sdram_addr[10]

pci_inta_n (satellite)

PIO[0]

D13 reset_boot_mode[0]

dma_done_n[1]

F4

G1

G3

G4

H1

sdram_wait_n

PIO[1]

pci_idsel (satellite)

B11 sdram_addr[16]

dma_done_n[0]

pci_eeprom_mdo

pci_eeprom_mdi

pci_eeprom_cs (satellite) PIO[11]

B12 reset_pci_host_mode

PIO[10]

PIO[7]

R15 PIO[3]

C1

C2

PIO[6]

PIO[5]

T2

Unused (satellite)

PIO[8]

T16 PIO[4]

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IDT 79RC32334—Rev. Y

RC32334 Package Drawing — 256-pin PBGA

28 of 30

August 31, 2004

IDT 79RC32334—Rev. Y

RC32334 Package Drawing — Page Two

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August 31, 2004

IDT 79RC32334—Rev. Y

Ordering Information

79RCXX

V

DDD

SSS

PP

CPU

Frequency

Package

Temp range/

Process

Product

Type

Operating

Voltage

Device

Type

Blank = Commercial Temperature (0° C to +70° C Ambient)

I = Industrial Temperature (-40° C to +85° C Ambient)

BB = 256-pin PBGA

BBG = 256-pin PBGA (Green package)

100 MHz

133MHz

150MHz

334

V = 3.3V ±5%

79RC32 =

32-bit family product

Valid Combinations

79RC32V334 - 100BB, 133BB, 150BB

Commercial

79RC32V334 - 100BBG, 133BBG, 150BBG

Commercial Green

79RC32V334 - 100BBI, 133BBI, 150BBI

Industrial

79RC32V334 - 100BBGI, 133BBGI, 150BBGI

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August 31, 2004


型号：	IDT79RC32V334-100BBI
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	RISC Microcontroller, 32-Bit, 100MHz, PBGA256, 17 X 17 MM, PLASTIC, BGA-256 时钟微控制器外围集成电路
文件：	总30页 (文件大小：462K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT79RC32V334-100BBI [IDT]

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