首页 |元器件品牌

IDT79RC32V334-133BB8 [IDT]

RISC Microcontroller, 32-Bit, 133MHz, PBGA256, 17 X 17 MM, PLASTIC, BGA-256;
IDT79RC32V334-133BB8
型号： IDT79RC32V334-133BB8
厂家： INTEGRATED DEVICE TECHNOLOGY    INTEGRATED DEVICE TECHNOLOGY
描述：

RISC Microcontroller, 32-Bit, 133MHz, PBGA256, 17 X 17 MM, PLASTIC, BGA-256

时钟 微控制器 外围集成电路
文件： 总47页 (文件大小：602K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
IDTTM InterpriseTM Integrated  
Communications Processor  
79RC32355  
◆
SDRAM Controller  
2 memory banks, non-interleaved, 512 MB total  
Features List  
–
–
–
–
–
–
◆
RC32300 32-bit Microprocessor  
32-bit wide data path  
Supports 4-bit, 8-bit, and 16-bit wide SDRAM chips  
SODIMM support  
Stays on page between transfers  
Automatic refresh generation  
–
–
–
–
–
–
–
–
–
–
Enhanced MIPS-II ISA  
Enhanced MIPS-IV cache prefetch instruction  
DSP Instructions  
MMU with 16-entry TLB  
8KB Instruction Cache, 2-way set associative  
2KB Data Cache, 2-way set associative  
Per line cache locking  
Write-through and write-back cache management  
Debug interface through the EJTAG port  
Big or Little endian support  
◆
Peripheral Device Controller  
–
26-bit address bus  
32-bit data bus with variable width support of 8-,16-, or 32-bits  
8-bit boot ROM support  
6 banks available, up to 64MB per bank  
Supports Flash ROM, PROM, SRAM, dual-port memory, and  
peripheral devices  
–
–
–
–
◆
◆
Interrupt Controller  
Allows status of each interrupt to be read and masked  
–
I C  
–
–
–
–
Supports external wait-state generation, Intel or Motorola style  
Write protect capability  
Direct control of optional external data transceivers  
2
2
Flexible I C standard serial interface to connect to a variety of  
peripherals  
◆
System Integrity  
–
–
Standard and fast mode timing support  
Configurable 7 or 10-bit addressable slave  
–
Programmable system watchdog timer resets system on time-  
out  
◆
UARTs  
–
Programmable bus transaction times memory and peripheral  
transactions and generates a warm reset on time-out  
–
–
Two 16550 Compatible UARTs  
Baud rate support up to 1.5 Mb/s  
◆
DMA  
◆
◆
Counter/Timers  
–
General Purpose I/O Pins (GPIOP)  
–
–
–
16 DMA channels  
Three general purpose 32-bit counter/timers  
Services on-chip and external peripherals  
Supports memory-to-memory, memory-to-I/O, and I/O-to-I/O  
transfers  
–
36 individually programmable pins  
Each pin programmable as input, output, or alternate function  
Input can be an interrupt or NMI source  
–
–
–
–
Supports flexible descriptor based operation and chaining via  
linked lists of records (scatter / gather capability)  
Supports unaligned transfers  
Input can also be active high or active low  
–
–
Supports burst transfers  
Block Diagram  
RC32300  
CPU Core  
Interrupt  
Controller  
:
:
10/100  
USB  
Interface  
ICE  
EJTAG  
Ethernet  
Interface  
MMU  
Watchdog  
Timer  
3 Counter  
Timers  
16 Channel  
DMA  
I. Cache  
D. Cache  
Controller  
Arbiter  
SDRAM &  
Device  
Controller  
2
TDM  
Interface  
GPIO  
Interface  
ATM  
Interface  
2 UARTS  
(16550)  
I C  
Ext. Bus  
Master  
Controller  
Utopia 1 / 2  
2
TDM Bus  
GPIO Pins  
I C Bus  
Memory &  
Peripheral Bus  
Ch. 2  
Ch. 1  
Serial Channels  
Figure 1 RC32355 Internal Block Diagram  
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.  
1 of 47  
May 25, 2004  
DSC 5900  
© 2004 Integrated Device Technology, Inc.  
IDT 79RC32355  
◆
◆
ATM SAR  
USB  
–
Can be configured as one UTOPIA level 1 interface or 1  
UTOPIA level 2 interface with 2 address lines (3 PHYs max)  
Supports 25Mb/s and faster ATM  
Supports UTOPIA data path interface operation at speeds up  
to 33 MHz  
Supports standard 53-byte ATM cells  
Performs HEC generation and checking  
Cell processing discards short cells and clips long cells  
16 cells worth of buffering  
UTOPIA modes: 8 cell input buffer and 8 cell output buffer  
Hardware support for CRC-32 generation and checking for  
AAL5  
Hardware support for CRC-10 generation and checking  
Virtual caching receive mechanism supports reception of any  
length packet without CPU intervention on up to eight simulta-  
neously active receive channels  
–
–
–
–
–
–
–
Revision 1.1 compliant  
USB slave device controller  
th  
–
–
Supports a 6 USB endpoint  
Full speed operation at 12 Mb/s  
Supports control, interrupt, bulk and isochronous endpoints  
Supports USB remote wakeup  
–
–
–
–
–
–
Integrated USB transceiver  
◆
TDM  
–
Serial Time Division Multiplexed (TDM) voice and data inter-  
face  
Provides interface to telephone CODECs and DSPs  
Interface to high quality audio A/Ds and D/As with external  
glue logic  
Support 1 to 128 8-bit time slots  
Compatible with Lucent CHI, GCI, Mitel ST-bus, K2 and SLD  
busses  
Supports data rates of up to 8.192 Mb/s  
Supports internal or external frame generation  
Supports multiple non-contiguous active input and output time  
slots  
–
–
–
–
–
–
–
Frame Mode transmit mechanism supports transmission of  
any length packet without CPU intervention  
–
–
–
◆
System Features  
–
–
–
–
JTAG Interface (IEEE Std. 1149.1 compatible)  
208 pin PQFP package  
2.5V core supply and 3.3V I/O supply  
Up to 180 MHz pipeline frequency and up to 75 MHz bus  
frequency  
◆
◆
EJTAG  
–
–
Run-time Mode provides a standard JTAG interface  
Real-Time Mode provides additional pins for real-time trace  
information  
Ethernet  
–
–
Full duplex support for 10 and 100 Mb/s Ethernet  
IEEE 802.3u compatible Media Independent Interface (MII)  
with serial management interface  
–
–
–
IEEE 802.3u auto-negotiation for automatic speed selection  
Flexible address filtering modes  
64-entry hash table based multicast address filtering  
RC32300 CPU Core  
Clock  
32-bit Data Bus  
Timers  
Data Buffers  
SDRAM Ctl  
Memory &  
Debug port  
UART  
Interrupt Ctl  
SDRAM  
DMA  
Channels  
Memory & I/O  
I/O Controller  
USB to PC  
Echo  
USB  
Transmission  
Convergence  
ATM I/F  
TDM  
Ethernet MAC  
Codec  
SLIC  
Data Pump  
AFE  
MII I/F  
Ethernet Transceiver  
Ethernet to PC  
POTS telephone  
RJ11  
Figure 2 Example of xDSL Residential Gateway Using RC32355  
2 of 47  
May 25, 2004  
IDT 79RC32355  
DMA Controller  
Device Overview  
The DMA controller off-loads the CPU core from moving data among  
the on-chip interfaces, external peripherals, and memory. The DMA  
controller supports scatter / gather DMA with no alignment restrictions,  
appropriate for communications and graphics systems.  
The RC32355 is a “System on a Chip” which contains a high perfor-  
mance 32-bit microprocessor. The microprocessor core is used exten-  
sively at the heart of the device to implement the most needed  
functionalities in software with minimal hardware support. The high  
performance microprocessor handles diverse general computing tasks  
and specific application tasks that would have required dedicated hard-  
ware. Specific application tasks implemented in software can include  
routing functions, fire wall functions, modem emulation, ATM SAR  
emulation, and others.  
TDM Bus Interface  
The RC32355 incorporates an industry standard TDM bus interface  
to directly access external devices such as telephone CODECs and  
quality audio A/Ds and D/As. This feature is critical for applications, such  
as cable modems and xDSL modems, that need to carry voice along  
with data to support Voice Over IP capability.  
The RC32355 meets the requirements of various embedded commu-  
nications and digital consumer applications. It is a single chip solution  
that incorporates most of the generic system functionalities and applica-  
tion specific interfaces that enable rapid time to market, very low cost  
systems, simplified designs, and reduced board real estate.  
Ethernet Interface  
The RC32355 contains an on-chip Ethernet MAC capable of 10 and  
100 Mbps line interface with an MII interface. It supports up to 4 MAC  
addresses. In a SOHO router, the high performance RC32300 CPU core  
routes the data between the Ethernet and the ATM interface. In other  
applications, such as high speed modems, the Ethernet interface can be  
used to connect to the PC.  
CPU Execution Core  
The RC32355 is built around the RC32300 32-bit high performance  
microprocessor core. The RC32300 implements the enhanced MIPS-II  
ISA and helps meet the real-time goals and maximize throughput of  
communications and consumer systems by providing capabilities such  
as a prefetch instruction, multiple DSP instructions, and cache locking.  
The DSP instructions enable the RC32300 to implement 33.6 and  
56kbps modem functionality in software, removing the need for external  
dedicated hardware. Cache locking guarantees real-time performance  
by holding critical DSP code and parameters in the cache for immediate  
availability. The microprocessor also implements an on-chip MMU with a  
TLB, making the it fully compliant with the requirements of real time  
operating systems.  
USB Device Interface  
The RC32355 includes the industry standard USB device interface to  
enable consumer appliances to directly connect to the PC.  
ATM SAR  
The RC32355 includes a configurable ATM SAR that supports a  
UTOPIA level 1 or a UTOPIA level 2 interface. The ATM SAR is imple-  
mented as a hybrid between software and hardware. A hardware block  
provides the necessary low level blocks (like CRC generation and  
checking and cell buffering) while the software is used for higher level  
SARing functions. In xDSL modem applications, the UTOPIA port inter-  
faces directly to an xDSL chip set. In SOHO routers or in a line card for a  
Layer 3 switch, it provides access to an ATM network.  
Memory and I/O Controller  
The RC32355 incorporates a flexible memory and peripheral device  
controller providing support for SDRAM, Flash ROM, SRAM, dual-port  
memory, and other I/O devices. It can interface directly to 8-bit boot  
ROM for a very low cost system implementation. It enables access to  
very high bandwidth external memory (380 MB/sec peak) at very low  
system costs. It also offers various trade-offs in cost / performance for  
the main memory architecture. The timers implemented on the RC32355  
satisfy the requirements of most RTOS.  
Enhanced JTAG Interface for ICE  
For low-cost In-Circuit Emulation (ICE), the RC32300 CPU core  
includes an Enhanced JTAG (EJTAG) interface. This interface consists  
of two operation modes: Run-Time Mode and Real-Time Mode.  
The Run-Time Mode provides a standard JTAG interface for on-chip  
debugging, and the Real-Time Mode provides additional status pins—  
PCST[2:0]—which are used in conjunction with the JTAG pins for real-  
time trace information at the processor internal clock or any division of  
the pipeline clock.  
3 of 47  
May 25, 2004  
IDT 79RC32355  
Thermal Considerations  
The RC32355 consumes less than 2.5 W peak power. It is guaran-  
teed in a ambient temperature range of 0° to +70° C for commercial  
temperature devices and - 40° to +85° for industrial temperature  
devices.  
Revision History  
March 29, 2001: Initial publication.  
September 24, 2001: Removed references to DPI interface.  
Removed references to “edge-triggered interrupt input” for GPIO pins.  
Changed 208-pin package designation from DP to DH.  
October 10, 2001: Revised AC timing characteristics in Tables 5, 6,  
7, 8, 10, 12, and 15. Revised values in Table 18, “DC Electrical Charac-  
teristics”; Table 20, “RC32355 Power Consumption”; and Figure 23,  
“Typical Power Usage.” Changed data sheet from Preliminary to Final.  
October 23, 2001: Revised Figure 23, “Typical Power Usage.”  
November 1, 2001: Added Input Voltage Undershoot parameter and  
a footnote to Table 21.  
January 30, 2002: In Table 6, changed values from 1.5 to 1.2 for the  
following signals: MDATA Tdo1, MADDR Tdo2, CASN Tdo3, CKENP  
Tdo4, BDIRN Tdo5, BOEN Tdo6.  
May 20, 2002: Changed values in Table 20, Power Consumption.  
September 19, 2002: Added COLDRSTN Trise1 parameter to Table  
5, Reset and System AC Timing Characteristics.  
December 6, 2002: In Features section, changed UART speed from  
115 Kb/s to 1.5 Mb/s.  
December 17, 2002: Added V parameter to Table 18, DC Elec-  
OH  
trical Characteristics.  
January 27, 2004: Added 180MHz speed grade.  
May 25, 2004: In Table 7, signals MIIRXCLK and MIITXCLK, the Min  
and Max values for 10 Mbps Thigh1/Tlow1 were changed to 140 and  
260 respectively and the Min and Max values for 100 Mbps Thigh1/  
Tlow1 were changed to 14.0 and 26.0 respectively.  
4 of 47  
May 25, 2004  
IDT 79RC32355  
Pin Description Table  
The following table lists the functions of the pins provided on the RC32355. Some of the functions listed may be multiplexed onto the same pin.  
To define the active polarity of a signal, a suffix will be used. Signals ending with an “N” should be interpreted as being active, or asserted, when at  
a logic zero (low) level. All other signals (including clocks, buses and select lines) will be interpreted as being active, or asserted when at a logic one  
(high) level.  
Note: The input pads of the RC32355 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels.  
This is especially critical for unused control signal inputs (such as BRN) which, if left floating, could adversely affect the RC32355’s opera-  
tion. Also, any input pin left floating can cause a slight increase in power consumption.  
Name  
System  
Type I/O Type  
Description  
CLKP  
I
I
Input  
STI1  
System Clock input. This is the system master clock input. The RISCore 32300 pipeline frequency is a multiple (x2, x3, or  
x4) of this clock frequency. All other logic runs at this frequency or less.  
COLDRSTN  
RSTN  
Cold Reset. The assertion of this signal low initiates a cold reset. This causes the RC32355 state to be initialized, boot  
configuration to be loaded, and the internal processor PLL to lock onto the system clock (CLKP).  
I/O  
Low Drive Reset. This bidirectional signal is either driven low or tri-stated, an external pull-up is required to supply the high state. The  
with STI RC32355 drives RSTN low during a reset (to inform the external system that a reset is taking place) and then tri-states it.  
The external system can drive RSTN low to initiate a warm reset, and then should tri-state it.  
SYSCLKP  
O
High Drive System clock output. This is a buffered and delayed version of the system clock input (CLKP). All SDRAM transactions  
are synchronous to this clock. This pin should be externally connected to the SDRAMs and to the RC32355 SDCLKINP pin  
(SDRAM clock input).  
Memory and Peripheral Bus  
MADDR[25:0]  
O
[21:0] High Memory Address Bus. 26-bit address bus for memory and peripheral accesses. MADDR[20:17] are used for the  
Drive  
SODIMM data mask enables if SODIMM mode is selected.  
[25:22] Low MADDR[22] Primary function: General Purpose I/O, GPIOP[27].  
Drive with MADDR[23] Primary function: General Purpose I/O, GPIOP[28].  
STI  
MADDR[24] Primary function: General Purpose I/O, GPIOP[29].  
MADDR[25] Primary function: General Purpose I/O, GPIOP[30].  
MDATA[31:0]  
BDIRN  
I/O High Drive Memory Data Bus. 32-bit data bus for memory and peripheral accesses.  
O
High Drive External Buffer Direction. External transceiver direction control for the memory and peripheral data bus, MDATA[31:0]. It  
is asserted low during any read transaction, and remains high during write transactions.  
BOEN[1:0]  
O
High Drive External Buffer Output Enable. These signals provide two output enable controls for external data bus transceivers on  
the memory and peripheral data bus, MDATA. BOEN[0] is asserted low during external device read transactions. BOEN[1]  
is asserted low during SDRAM read transactions.  
BRN  
I
O
I
STI  
External Bus Request. This signal is asserted low by an external master device to request ownership of the memory and  
peripheral bus.  
BGN  
Low Drive External Bus Grant. This signal is asserted low by RC32355 to indicate that RC32355 has relinquished ownership of the  
local memory and peripheral bus to an external master.  
WAITACKN  
STI  
Wait or Transfer Acknowledge. When configured as wait, this signal is asserted low during a memory and peripheral  
device bus transaction to extend the bus cycle. When configured as transfer acknowledge, this signal is asserted low dur-  
ing a memory and peripheral device bus transaction to signal the completion of the transaction.  
CSN[5:0]  
O
[3:0]  
Device Chip Select. These signals are used to select an external device on the memory and peripheral bus during device  
High Drive transactions. Each bit is asserted low during an access to the selected external device.  
CSN[4] Primary function: General purpose I/O, GPIOP[16].  
[5:4]  
CSN[5] Primary function: General purpose I/O, GPIOP[17].  
Low Drive  
Table 1 Pin Descriptions (Part 1 of 8)  
5 of 47  
May 25, 2004  
IDT 79RC32355  
Name Type I/O Type  
Description  
RWN  
O
O
O
High Drive Read or Write. This signal indicates if the transaction on the memory and peripheral bus is a read transaction or a write  
transaction. A high level indicates a read from an external device, a low level indicates a write to an external device.  
OEN  
High Drive Output Enable. This signal is asserted low when data should be driven by an external device during device read transac-  
tions on the memory and peripheral bus.  
BWEN[3:0]  
High Drive SDRAM Byte Enable Mask or Memory and I/O Byte Write Enables. These signals are used as data input/output masks  
during SDRAM transactions and as byte write enable signals during device controller transactions on the memory and  
peripheral bus. They are active low.  
BWEN[0] corresponds to byte lane MDATA[7:0].  
BWEN[1] corresponds to byte lane MDATA[15:8].  
BWEN[2] corresponds to byte lane MDATA[23:16].  
BWEN[3] corresponds to byte lane MDATA[31:24].  
SDCSN[1:0]  
RASN  
O
O
O
High Drive SDRAM Chip Select. These signals are used to select the SDRAM device on the memory and peripheral bus. Each bit is  
asserted low during an access to the selected SDRAM.  
High Drive SDRAM Row Address Strobe. The row address strobe asserted low during memory and peripheral bus SDRAM transac-  
tions.  
CASN  
High Drive SDRAM Column Address Strobe. The column address strobe asserted low during memory and peripheral bus SDRAM  
transactions.  
SDWEN  
CKENP  
O
O
High Drive SDRAM Write Enable. Asserted low during memory and peripheral bus SDRAM write transactions.  
Low Drive SDRAM Clock Enable. Asserted high during active SDRAM clock cycles.  
Primary function: General Purpose I/O, GPIOP[21].  
SDCLKINP  
I
STI  
SDRAM Clock Input. This clock input is a delayed version of SYSCLKP. SDRAM read data is sampled into the RC32355  
on the rising edge of this clock.  
ATM Interface  
ATMINP[11:0]  
ATMIOP[1:0]  
I
STI  
ATM PHY Inputs. These pins are the inputs for the ATM interface.  
I/O  
Low Drive ATM PHY Bidirectional Signals. These pins are the bidirectional pins for the ATM interface.  
with STI  
ATMOUTP[9:0]  
TXADDR[1:0]  
O
O
Low Drive ATM PHY Outputs. These pins are the outputs for the ATM interface.  
Low Drive ATM Transmit Address [1:0]. 2-bit address bus used for transmission in Utopia-2 mode.  
TXADDR[0] Primary function: General purpose I/O, GPIOP[22].  
TXADDR[1] Primary function: General purpose I/O, GPIOP[23].  
RXADDR[1:0]  
O
Low Drive ATM Receive Address [1:0]. 2-bit address bus for receiving in Utopia-2 mode.  
RXADDR[0] Primary function: General purpose I/O, GPIOP[24].  
RXADDR[1] Primary function: General purpose I/O, GPIOP[25].  
TDM Bus  
TDMDOP  
O
I
High Drive TDM Serial Data Output. Serial data is driven by the RC32355 on this signal during an active output time slot. During inac-  
tive time slots this signal is tri-stated.  
Primary function: General purpose I/O, GPIOP[32].  
TDMDIP  
TDMFP  
STI  
TDM Serial Data Input. Serial data is received by the RC32355 on this signal during active input time slots.  
Primary function: General purpose I/O, GPIOP[33].  
I/O High Drive TDM Frame Signal. A transition on this signal, the active polarity of which is programmable, delineates the start of a new  
TDM bus frame. TDMFP is driven if the RC32355 is a master, and is received if it is a slave.  
Primary function: General purpose I/O, GPIOP[34].  
TDMCLKP  
I
STI  
TDM Clock. This input clock controls the rate at which data is sent and received on the TDM bus.  
Primary function: General purpose I/O, GPIOP[35].  
Table 1 Pin Descriptions (Part 2 of 8)  
6 of 47  
May 25, 2004  
IDT 79RC32355  
Name  
TDMTEN  
Type I/O Type  
Description  
O
Low Drive TDM External Buffer Enable. This signal controls an external tri-state buffer output enable connected to the TDM output  
data, TDMDOP. It is asserted low when the RC32355 is driving data on TDMDOP.  
Primary function: General Purpose I/O, GPIOP[26]  
General Purpose Input/Output  
GPIOP[0]  
GPIOP[1]  
GPIOP[2]  
I/O  
I/O  
I/O  
Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.  
Alternate function: UART channel 0 serial output, U0SOUTP.  
with STI  
Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.  
Alternate function: UART channel 0 serial input, U0SINP.  
Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.  
with STI  
1st Alternate function: UART channel 0 ring indicator, U0RIN.  
with STI  
2nd Alternate function: JTAG boundary scan tap controller reset, JTAG_TRST_N.  
GPIOP[3]  
GPIOP[4]  
I/O  
I/O  
Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.  
Alternate function: UART channel 0 data carrier detect, U0DCRN.  
with STI  
Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.  
1st Alternate function: UART channel 0 data terminal ready, U0DTRN.  
2nd Alternate function: CPU or DMA transaction indicator, CPUP.  
with STI  
GPIOP[5]  
GPIOP[6]  
GPIOP[7]  
I/O  
I/O  
I/O  
Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.  
Alternate function: UART channel 0 data set ready, U0DSRN.  
with STI  
Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.  
Alternate function: UART channel 0 request to send, U0RTSN.  
with STI  
Low Drive General Purpose I/O.  
This pin can be configured as a general purpose I/O pin.  
Alternate function: UART channel 0 clear to send, U0CTSN.  
with STI  
GPIOP[8]  
GPIOP[9]  
GPIOP[10]  
GPIOP[11]  
GPIOP[12]  
GPIOP[13]  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.  
1st Alternate function: UART channel 1 serial output, U1SOUTP.  
2nd Alternate function: Active DMA channel code, DMAP[3].  
with STI  
Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.  
1st Alternate function: UART channel 1 serial input, U1SINP.  
2nd Alternate function: Active DMA channel code, DMAP[2].  
with STI  
Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.  
1st Alternate function: UART channel 1 data terminal ready, U1DTRN.  
2nd Alternate function: ICE PC trace status, EJTAG_PCST[0].  
with STI  
Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.  
1st Alternate function: UART channel 1 data set ready, U1DSRN.  
2nd Alternate function: ICE PC trace status, EJTAG_PCST[1].  
with STI  
Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.  
1st Alternate function: UART channel 1 request to send, U1RTSN.  
2nd Alternate function: ICE PC trace status, EJTAG_PCST[2].  
with STI  
Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.  
1st Alternate function: UART channel 1 clear to send, U1CTSN.  
2nd Alternate function: ICE PC trace clock, EJTAG_DCLK.  
with STI  
GPIOP[14]  
GPIOP[15]  
GPIOP[16]  
I/O  
I/O  
Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.  
Alternate function: I2C interface data, SDAP.  
with STI  
Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.  
Alternate function: I2C interface clock, SCLP.  
with STI  
I/O High Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.  
Alternate function: Memory and peripheral bus chip select, CSN[4].  
Table 1 Pin Descriptions (Part 3 of 8)  
7 of 47  
May 25, 2004  
IDT 79RC32355  
Name  
GPIOP[17]  
Type I/O Type  
Description  
I/O High Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.  
Alternate function: Memory and peripheral bus chip select, CSN[5].  
GPIOP[18]  
GPIOP[19]  
GPIOP[20]  
GPIOP[21]  
GPIOP[22]  
GPIOP[23]  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.  
Alternate function: External DMA device request, DMAREQN.  
with STI  
Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.  
Alternate function: External DMA device done, DMADONEN.  
with STI  
with STI  
with STI  
Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.  
Alternate function: USB start of frame, USBSOF.  
Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.  
Alternate function: SDRAM clock enable CKENP.  
Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.  
Alternate function: ATM transmit PHY address, TXADDR[0].  
with STI  
Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.  
1st Alternate function: ATM transmit PHY address, TXADDR[1].  
2nd Alternate function: Active DMA channel code, DMAP[0].  
with STI  
GPIOP[24]  
GPIOP[25]  
I/O  
I/O  
Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.  
Alternate function: ATM receive PHY address, RXADDR[0].  
with STI  
Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.  
1st Alternate function: ATM receive PHY address, RXADDR[1].  
2nd Alternate function: Active DMA channel code, DMAP[1].  
with STI  
GPIOP[26]  
GPIOP[27]  
GPIOP[28]  
GPIOP[29]  
GPIOP[30]  
GPIOP[31]  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.  
Alternate function: TDM external buffer enable, TDMTEN.  
with STI  
with STI  
with STI  
with STI  
Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.  
Alternate function: Memory and peripheral bus address, MADDR[22].  
Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.  
Alternate function: Memory and peripheral bus address, MADDR[23].  
Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.  
Alternate function: Memory and peripheral bus address, MADDR[24].  
Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.  
Alternate function: Memory and peripheral bus address, MADDR[25].  
with STI  
Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.  
1ST Alternate function: DMA finished, DMAFIN.  
with STI  
2nd Alternate function: EJTAG/ICE reset, EJTAG_TRST_N.  
GPIOP[32]  
GPIOP[33]  
GPIOP[34]  
GPIOP[35]  
I/O High Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.  
Alternate function: TDM interface data output, TDMDOP. At reset, this pin defaults to the primary function, GPIOP[32].  
I/O  
Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.  
Alternate function: TDM interface data input, TDMDIP. At reset, this pin defaults to the primary function, GPIOP[33].  
with STI  
I/O High Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.  
Alternate function: TDM interface frame signal, TDMFP. At reset, this pin defaults to the primary function, GPIOP[34].  
I/O  
Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.  
Alternate function: TDM interface clock, TDMCLKP. At reset, this pin defaults to the primary function, GPIOP[35].  
with STI  
DMA  
DMAFIN  
O
Low  
External DMA finished. This signal is asserted low by the RC32355 when the number of bytes specified in the DMA  
descriptor have been transferred to or from an external device.  
Primary function: General Purpose I/O, GPIOP[31]. At reset, this pin defaults to primary function GPIOP[31].  
2nd Alternate function: EJTAG_TRST_N.  
Table 1 Pin Descriptions (Part 4 of 8)  
8 of 47  
May 25, 2004  
IDT 79RC32355  
Name  
DMAREQN  
Type I/O Type  
Description  
I
STI  
External DMA Device Request. The external DMA device asserts this pin low to request DMA service.  
Primary function: General purpose I/O, GPIOP[18]. At reset, this pin defaults to primary function GPIOP[18].  
DMADONEN  
I
STI  
External DMA Device Done. The external DMA device asserts this signal low to inform the RC32355 that it is done with  
the current DMA transaction.  
Primary function: General purpose I/O, GPIOP[19]. At reset, this pin defaults to primary function GPIOP[19].  
USB  
USBCLKP  
USBDN  
USBDP  
USBSOF  
I
STI  
USB  
USB  
USB Clock. 48 MHz clock input used as time base for the USB interface.  
USB D- Data Line. This is the negative differential USB data signal.  
USB D+ Data Line. This is the positive differential USB data signal.  
I/O  
I/O  
O
Low Drive USB start of frame.  
Primary function: General Purpose I/O, GPIOP[20]. At reset, this pin defaults to primary function GPIOP[20].  
Ethernet  
MIICOLP  
MIICRSP  
MIIMDCP  
I
I
STI  
STI  
MII Collision Detected. This signal is asserted by the ethernet PHY when a collision is detected.  
MII Carrier Sense. This signal is asserted by the ethernet PHY when either the transmit or receive medium is not idle.  
O
Low Drive MII Management Data Clock. This signal is used as a timing reference for transmission of data on the management inter-  
face.  
MIIMDIOP  
I/O  
Low Drive MII Management Data. This bidirectional signal is used to transfer data between the station management entity and the  
ethernet PHY.  
with STI  
MIIRXCLKP  
MIIRXDP[3:0]  
MIIRXDVP  
MIIRXERP  
I
I
I
I
STI  
MII Receive Clock. This clock is a continuous clock that provides a timing reference for the reception of data.  
MII Receive Data. This nibble wide data bus contains the data received by the ethernet PHY.  
MII Receive Data Valid. The assertion of this signal indicates that valid receive data is in the MII receive data bus.  
STI  
STI  
STI  
MII Receive Error. The assertion of this signal indicates that an error was detected somewhere in the ethernet frame cur-  
rently being sent in the MII receive data bus.  
MIITXCLKP  
MIITXDP[3:0]  
MIITXENP  
MIITXERP  
I
STI  
MII Transmit Clock. This clock is a continuous clock that provides a timing reference for the transfer of transmit data.  
O
O
O
Low Drive MII Transmit Data. This nibble wide data bus contains the data to be transmitted.  
Low Drive MII Transmit Enable. The assertion of this signal indicates that data is present on the MII for transmission.  
Low Drive MII Transmit Coding Error. When this signal is asserted together with MIITXENP, the ethernet PHY will transmit symbols  
which are not valid data or delimiters.  
I2C  
SCLP  
I/O  
I/O  
Low Drive I2C Interface Clock. An external pull-up is required on SCLP, see the I2C spec.2  
Primary function: General purpose I/O, GPIOP[15]. At reset, this pin defaults to primary function GPIOP[15].  
with STI  
SDAP  
Low Drive I2C Interface Data Pin. An external pull-up is required on SDAP, see the I2C spec.2  
Primary function: General purpose I/O, GPIOP[14]. At reset, this pin defaults to primary function GPIOP[14].  
with STI  
EJTAG  
JTAG_TCK  
I
I
STI  
STI  
JTAG Clock. This is an input test clock, used to shift data into or out of the boundary scan logic. This signal requires an  
external resistor, listed in Table 16.  
JTAG_TDI  
JTAG Data Input. This is the serial data shifted into the boundary scan logic. This signal requires an external resistor,  
listed in Table 16. This is also used to input EJTAG_DINTN during EJTAG/ICE mode. EJTAG_DINTN is an interrupt to  
switch the PC trace mode off.  
JTAG_TDO  
O
Low Drive JTAG Data Output. This is the serial data shifted out from the boundary scan logic. When no data is being shifted out, this  
signal is tri-stated. This signal requires an external resistor, listed in Table 16. This is also used to output the EJTAG_TPC  
during EJTAG/ICE mode. EJTAG_TPC is the non-sequential program counter output.  
Table 1 Pin Descriptions (Part 5 of 8)  
9 of 47  
May 25, 2004  
IDT 79RC32355  
Name  
JTAG_TMS  
Type I/O Type  
Description  
I
STI  
JTAG Mode Select. This input signal is decoded by the tap controller to control test operation. This signal requires an  
external resistor, listed in Table 16.  
EJTAG_PCST[0]  
EJTAG_PCST[1]  
EJTAG_PCST[2]  
EJTAG_DCLK  
O
Low Drive PC trace status. This bus gives the PC trace status information during EJTAG/ICE mode. EJTAG/ICE enable is selected  
during reset using the boot configuration and overrides the selection of the Primary and Alternate functions. This signal  
requires an external resistor, listed in Table 16.  
Primary function: General Purpose I/O, GPIOP[10].  
1st Alternate function: UART channel 1 data terminal ready, U1DTRN.  
O
O
O
I
Low Drive PC trace status. This bus gives the PC trace status information during EJTAG/ICE mode. EJTAG/ICE enable is selected  
during reset using the boot configuration and overrides the selection of the Primary and Alternate functions. This signal  
requires an external resistor, listed in Table 16.  
Primary function: General Purpose I/O, GPIOP[11]. At reset, this pin defaults to primary function GPIOP[11].  
1st Alternate function: UART channel 1 data set ready, U1DSRN.  
Low Drive PC trace status. This bus gives the PC trace status information during EJTAG/ICE mode. EJTAG/ICE enable is selected  
during reset using the boot configuration and overrides the selection of the Primary and Alternate functions. This signal  
requires an external resistor, listed in Table 16.  
Primary function: General Purpose I/O, GPIOP[12].  
1st Alternate function: UART channel 1 request to send, U1RTSN.  
Low Drive PC trace clock. This is used to capture address and data during EJTAG/ICE mode. EJTAG/ICE enable is selected during  
reset using the boot configuration and overrides the selection of the Primary and Alternate functions. This signal requires  
an external resistor, listed in Table 16.  
Primary function: General Purpose I/O, GPIOP[13].  
1st Alternate function: UART channel 1 clear to send, U1CTSN.  
EJTAG_TRST_N  
STI  
EJTAG Test Reset. EJTAG_TRST_N is an active-low signal for asynchronous reset of only the EJTAG/ICE controller.  
EJTAG_TRST_N requires an external pull-up on the board. EJTAG/ICE enable is selected during reset using the boot con-  
figuration and overrides the selection of the Primary and Alternate functions. This signal requires an external resistor, listed  
in Table 16.  
Primary: General Purpose I/O, GPIOP[31]  
1st Alternate function: DMA finished output, DMAFIN.  
JTAG_TRST_N  
I
STI  
JTAG Test Reset. JTAG_TRST_N is an active-low signal for asynchronous reset of only the JTAG boundary scan control-  
ler. JTAG_TRST_N requires an external pull-down on the board that will hold the JTAG boundary scan controller in reset  
when not in use if selected. JTAG reset enable is selected during reset using the boot configuration and overrides the  
selection of the Primary and Alternate functions.  
Primary function: General Purpose I/O, GPIOP[2].  
1st Alternate function: UART channel 0 ring indicator, U0RIN.  
Debug  
INSTP  
O
O
Low Drive Instruction or Data Indicator. This signal is driven high during CPU instruction fetches and low during CPU data transac-  
tions on the memory and peripheral bus.  
CPUP  
Low Drive CPU or DMA Transaction Indicator. This signal is driven high during CPU transactions and low during DMA transactions  
on the memory and peripheral bus if CPU/DMA Transaction Indicator Enable is enabled. CPU/DMA Status mode enable is  
selected during reset using the boot configuration and overrides the selection of the Primary and Alternate functions.  
Primary function: General Purpose I/O, GPIOP[4].  
1st Alternate function: UART channel 0 data terminal ready U0DTRN.  
DMAP[0]  
DMAP[1]  
O
O
Low Drive Active DMA channel code. DMA debug enable is selected during reset using the boot configuration and overrides the  
selection of the Primary and Alternate functions.  
Primary function: General Purpose I/O, GPIOP[23].  
1st Alternate function: TXADDR[1].  
Low Drive Active DMA channel code. DMA debug enable is selected during reset using the boot configuration and overrides the  
selection of the Primary and Alternate functions.  
Primary function: General Purpose I/O, GPIOP[25].  
1st Alternate function: RXADDR[1].  
Table 1 Pin Descriptions (Part 6 of 8)  
10 of 47  
May 25, 2004  
IDT 79RC32355  
Name  
DMAP[2]  
Type I/O Type  
Description  
O
Low Drive Active DMA channel code. DMA debug enable is selected during reset using the boot configuration and overrides the  
selection of the Primary and Alternate functions.  
Primary function: General Purpose I/O, GPIOP[9].  
1st Alternate function: U1SINP.  
DMAP[3]  
O
Low Drive Active DMA channel code. DMA debug enable is selected during reset using the boot configuration and overrides the  
selection of the Primary and Alternate functions.  
Primary function: General Purpose I/O, GPIOP[8].  
1st Alternate function: U1SOUTP.  
UART  
U0SOUTP  
I
I
I
STI  
STI  
STI  
UART channel 0 serial transmit.  
Primary function: General Purpose I/O, GPIOP[0]. At reset, this pin defaults to primary function GPIOP[0].  
U0SINP  
U0RIN  
UART channel 0 serial receive.  
Primary function: General Purpose I/O, GPIOP[1]. At reset, this pin defaults to primary function GPIOP[1].  
UART channel 0 ring indicator.  
Primary function: General Purpose I/O, GPIOP[2]. At reset, this pin defaults to primary function GPIOP[2] if JTAG reset  
enable is not selected during reset using the boot configuration.  
2nd Alternate function: JTAG boundary scan reset, JTAG_TRST_N.  
U0DCRN  
U0DTRN  
I
STI  
UART channel 0 data carrier detect.  
Primary function: General Purpose I/O, GPIOP[3]. At reset, this pin defaults to primary function GPIOP[3].  
O
Low Drive UART channel 0 data terminal ready.  
Primary function: General Purpose I/O, GPIOP[4]. At reset, this pin defaults to primary function GPIOP[4] if CPU/DMA Sta-  
tus Mode enable is not selected during reset using the boot configuration.  
2nd Alternate function: CPU or DMA transaction indicator, CPUP.  
U0DSRN  
U0RTSN  
U0CTSN  
U0SOUTP  
I
STI  
UART channel 0 data set ready.  
Primary function: General Purpose I/O, GPIOP[5]. At reset, this pin defaults to primary function GPIOP[5].  
O
I
Low Drive UART channel 0 request to send.  
Primary function: General Purpose I/O, GPIOP[6]. At reset, this pin defaults to primary function GPIOP[6].  
STI  
UART channel 0 clear to send.  
Primary function: General Purpose I/O, GPIOP[7]. At reset, this pin defaults to primary function GPIOP[7].  
O
Low Drive UART channel 1 serial transmit.  
Primary function: General Purpose I/O, GPIOP[8]. At reset, this pin defaults to primary function GPIOP[8] if DMA Debug  
enable is not selected during reset using the boot configuration.  
2nd Alternate function: DMA channel, DMAP[3].  
U1SINP  
U1DTRN  
U1DSRN  
U1RTSN  
I
STI  
UART channel 1 serial receive.  
Primary function: General Purpose I/O, GPIOP[9]. At reset, this pin defaults to primary function GPIOP[9] if DMA Debug  
enable is not selected during reset using the boot configuration.  
2nd Alternate function: DMA channel, DMAP[2].  
O
I
Low Drive UART channel 1 data terminal ready.  
Primary function: General Purpose I/O, GPIOP[10]. At reset, this pin defaults to primary function GPIOP[10] if ICE Interface  
enable is not selected during reset using the boot configuration.  
Alternate function: PC trace status bit 0, EJTAG_PCST[0].  
STI  
UART channel 1 data set ready.  
Primary function: General Purpose I/O, GPIOP[11]. At reset, this pin defaults to primary function GPIOP[11] if ICE Interface  
enable is not selected during reset using the boot configuration.  
2nd Alternate function: PC trace status bit 1, EJTAG_PCST[1].  
O
Low Drive UART channel 1 request to send.  
Primary function: General Purpose I/O, GPIOP[12]. At reset, this pin defaults to primary function GPIOP[12] if ICE Interface  
enable is not selected during reset using the boot configuration.  
2nd Alternate function: PC trace status bit 2, EJTAG_PCST[2].  
Table 1 Pin Descriptions (Part 7 of 8)  
11 of 47  
May 25, 2004  
IDT 79RC32355  
Name  
U1CTSN  
Type I/O Type  
STI  
Description  
I
UART channel 1 clear to send.  
Primary function: General Purpose I/O, GPIOP[13]. At reset, this pin defaults to primary function GPIOP[13] if ICE Interface  
enable is not selected during reset using the boot configuration.  
2nd Alternate function: PC trace clock, EJTAG_DCLK.  
Table 1 Pin Descriptions (Part 8 of 8)  
1. Schmitt Trigger Input.  
2. 2I2C - Bus Specification by Philips Semiconductors.  
Boot Configuration Vector  
The boot configuration vector is read into the RC32355 during cold reset. The vector defines parameters in the RC32355 that are essential to oper-  
ation when cold reset is complete.  
The encoding of boot configuration vector is described in Table 2, and the vector input is illustrated in Figure 6.  
Signal  
Name/Description  
MDATA[2:0]  
Clock Multiplier. This field specifies the value by which the system clock (CLKP) is multiplied internally to generate the CPU pipeline clock.  
0x0 - multiply by 2  
0x1 - multiply by 3  
0x2 - multiply by 4  
0x3 - reserved  
0x4 - reserved  
0x5 - reserved  
0x6 - reserved  
0x7 - reserved  
MDATA[3]  
Endian. This bit specifies the endianness of RC32355.  
0x0 - little endian  
0x1 - big endian  
MDATA[4]  
MDATA[5]  
Reserved. Must be set to 0.  
Debug Boot Mode. When this bit is set, the RC32355 begins executing from address 0xFF20_0200 rather than 0xBFC0_0000 following a reset.  
0x0 - regular mode (processor begins executing at 0xBFC0_0000)  
0x1 - debug boot mode (processor begins executing at 0xFF20_0200)  
MDATA[7:6]  
MDATA[8]  
Boot Device Width. This field specifies the width of the boot device.  
0x0 - 8-bit boot device width  
0x1 - 16-bit boot device width  
0x2 - 32-bit boot device width  
0x3 - reserved  
EJTAG/ICE Interface Enable. When this bit is set, Alternate 2 pin functions EJTAG_PCST[2:0], EJTAG_DCLK, and EJTAG_TRST_N are  
selected.  
0x0 - GPIOP[31, 13:10] pins behaves as GPIOP  
0x1 - GPIOP[31] pin behaves as EJTAG_TRST_N,  
GPIOP[12:10] pins behave as EJTAG_PCST[2:0], and  
GPIOP[13] pin behaves as EJTAG_DCLK  
MDATA[9]  
Fast Reset. When this bit is set, RC32355 drives RSTN for 64 clock cycles, used during test only. Clear this bit for normal operation.  
0x0 - Normal reset: RC32355 drives RSTN for minimum of 4096 clock cycles  
0x1 - Fast Reset: RC32355 drives RSTN for 64 clock cycles (test only)  
MDATA[10]  
DMA Debug Enable. When this bit is set, Alternate 2 pin function, DMAP is selected. DMAP provides the DMA channel number during memory  
and peripheral bus DMA transactions.  
0x0 - GPIOP[8, 9, 25, 23] pins behave as GPIOP  
0x1 - GPIOP[8, 9, 25, 23] pins behave as DMAP[3:0]  
Table 2 Boot Configuration Vector Encoding (Part 1 of 2)  
12 of 47  
May 25, 2004  
 
IDT 79RC32355  
Signal  
Name/Description  
MDATA[11]  
Hold SYSCLKP Constant. For systems that do not require a SYSCLKP output and can instead use CLKP, setting this bit to a one causes the  
SYSCLKP output to be held at a constant level. This may be used to reduce EMI.  
0x0 - Allow SYSCLKP to toggle  
0x1 - Hold SYSCLKP constant  
MDATA[12]  
MDATA[13]  
JTAG Boundary Scan Reset Enable. When this bit is set, Alternate 2 pin function, JTAG_TRST_N is selected.  
0x0 - GPIOP[2] pin behaves as GPIOP  
0x1 - GPIOP[2] pin behaves as JTAG_TRST_N  
CPU / DMA Transaction Indicator Enable. When this bit is set, Alternate 2 pin function, CPUP is selected.  
0x0 - GPIOP[4] pin behaves as GPIOP  
0x1 - GPIOP[4] pin behaves as CPUP  
MDATA[15:14] Reserved. These pins must be driven low during boot configuration.  
Table 2 Boot Configuration Vector Encoding (Part 2 of 2)  
13 of 47  
May 25, 2004  
IDT 79RC32355  
Logic Diagram  
The following Logic Diagram shows the primary pin functions of the RC32355.  
CLKP  
SYSCLKP  
COLDRSTN  
RSTN  
22  
32  
4
MADDR[21:0]  
MDATA[31:0]  
BWEN[3:0]  
OEN  
USBDP  
USBDN  
RWN  
4
CSN[3:0]  
WAITACKN  
BRN  
USBCLKP  
4
MIIRXDP[3:0]  
BGN  
MIIRXDVP  
MIIRXERP  
MIIRXCLKP  
MIICRSP  
RASN  
CASN  
SDWEN  
SDCSN[1:0]  
BOEN[1:0]  
BDIRN  
2
2
MIICOLP  
4
MIITXDP[3:0]  
MIITXENP  
MIITXERP  
MIITXCLKP  
MIIMDCP  
RC32355  
Logic  
SDCLKINP  
Diagram  
12  
2
ATMINP[11:0]  
ATMIOP[1:0]  
ATMOUTP[9:0]  
(Primary  
Functions)  
10  
MIIMDIOP  
JTAG_TCK  
JTAG_TMS  
JTAG_TDI  
JTAG_TDO  
INSTP  
4
GPIOP[35:32]  
GPIOP[31:0]  
VccCore  
VccI/O  
Vss  
VccP (PLL)  
VssP (PLL)  
32  
Figure 3 Logic Diagram  
14 of 47  
May 25, 2004  
IDT 79RC32355  
Clock Parameters  
(Ta = 0°C to +70°C Commercial, Ta = -40°C to +85°C Industrial, Vcc I/O = +3.3V±5%,V Core and V P = +2.5V±5%)  
cc  
cc  
133MHz  
150MHz  
180MHz  
Timing  
Diagram  
Reference  
Parameter  
Symbol Reference  
Edge  
Units  
Min  
Max  
Min  
Max  
Min  
Max  
Internal CPU pipeline clock1  
CLKP2,3,4  
Frequency  
Frequency  
Tperiod1  
Thigh1  
Tlow1  
none  
none  
100  
25  
15  
6
133  
67  
40  
—
100  
25  
150  
75  
100  
25  
180  
90  
MHz  
MHz  
ns  
Figure 4  
13.3  
5.4  
5.4  
—
40  
11.1  
5.4  
5.4  
—
40  
—
—
ns  
6
—
—
—
ns  
Trise1  
—
—
—
3
2.5  
2.5  
±200  
2.5  
2.5  
±200  
ns  
Tfall1  
3
—
—
ns  
Tjitter  
±250  
—
—
ps  
1 The CPU pipeline clock speed is selected during cold reset by the boot configuration vector (see Table 2).  
2 Ethernet clock (MIIRXCLKP and MIITXCLKP) frequency must be equal to or less than 1/2 CLKP frequency.  
3 USB clock (USBCLKP) frequency must be less than CLKP frequency.  
4 ATM Utopia clock (RXCLKP and TXCLKP) frequency must be equal to or less than 1/2 CLKP frequency.  
Table 3 Clock Parameters  
Tlow1  
Thigh1  
Tperiod1  
CLKP  
Trise1  
Tfall1  
Tjitter  
Tjitter  
Figure 4 Clock Parameters Waveform  
15 of 47  
May 25, 2004  
 
IDT 79RC32355  
AC Timing Definitions  
Below are examples of the AC timing characteristics used throughout this document.  
Tlow  
Tperiod  
Thigh  
clock  
Tdo  
Tzd  
Tdo  
Tdz  
Tjitter  
Trise  
Tfall  
Output signal 1  
Output signal 2  
Tsu  
Thld  
Input Signal 1  
Signal  
Tpw  
Figure 5 AC Timing Definitions Waveform  
Symbol  
Definition  
Tperiod  
Tlow  
Clock period.  
Clock low. Amount of time the clock is low in one clock period.  
Clock high. Amount of time the clock is high in one clock period.  
Rise time. Low to high transition time.  
Thigh  
Trise  
Tfall  
Fall time. High to low transition time.  
Tjitter  
Tdo  
Jitter. Amount of time the reference clock (or signal) edge can vary on either the rising or falling edges.  
Data out. Amount of time after the reference clock edge that the output will become valid. The minimum time represents the data output hold.  
The maximum time represents the earliest time the designer can use the data.  
Tzd  
Tdz  
Tsu  
Thld  
Tpw  
Z state to data valid. Amount of time after the reference clock edge that the tri-stated output takes to become valid.  
Data valid to Z state. Amount of time after the reference clock edge that the valid output takes to become tri-stated.  
Input set-up. Amount of time before the reference clock edge that the input must be valid.  
Input hold. Amount of time after the reference clock edge that the input must remain valid.  
Pulse width. Amount of time the input or output is active.  
Table 4 AC Timing Definitions  
16 of 47  
May 25, 2004  
IDT 79RC32355  
AC Timing Characteristics  
(Ta = 0°C to +70°C Commercial, Ta = -40°C to +85°C Industrial, Vcc I/O = +3.3V±5%,V Core = +2.5V±5%, V P = +2.5V±5%)  
cc  
cc  
133MHz  
150MHz  
180MHz  
Timing  
Reference  
Edge  
Signal  
Symbol  
Unit Conditions Diagram  
Reference  
Min  
Max  
Min  
Max  
Min  
Max  
Reset and System  
COLDRSTN  
Tpw1  
Trise1  
Tdo2  
none  
none  
110  
—
—
5.0  
10.7  
—
110  
—
—
5.0  
10.7  
—
110  
—
—
5.0  
10.7  
—
ms  
ns  
ns  
ns  
Figure 6  
Figure 7  
RSTN1  
CLKP rising  
4.0  
3
4.0  
3
4.0  
3
MDATA[15:0]  
Boot Configuration  
Vector  
Thld3  
COLDRSTN  
rising  
INSTP  
Tdo  
Tdo  
Tdo  
Tpw  
Tpw  
Tdo  
Tsu  
Thld  
Tdo  
CLKP rising  
CLKP rising  
CLKP rising  
none  
5.0  
3.5  
8.0  
7.0  
6.6  
—
5.0  
3.5  
8.0  
7.0  
6.6  
—
5.0  
3.5  
8.0  
7.0  
6.6  
—
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CPUP  
DMAP  
3.5  
3.5  
3.5  
DMAREQN2  
DMADONEN2  
DMAFIN  
BRN  
(CLKP+7)  
(CLKP+7)  
3.5  
(CLKP+7)  
(CLKP+7)  
3.5  
(CLKP+7)  
(CLKP+7)  
3.5  
none  
—
—
—
CLKP rising  
CLKP rising  
5.9  
—
5.9  
—
5.9  
—
1.6  
1.6  
1.6  
0
—
0
—
0
—
BGN  
CLKP rising  
3.3  
5.8  
3.3  
5.8  
3.3  
5.8  
1 RSTN is a bidirectional signal. It is treated as an asynchronous input.  
2 DMAREQN and DMADONEN minimum pulse width equals the CLKP period plus 7ns.  
Table 5 Reset and System AC Timing Characteristics  
17 of 47  
May 25, 2004  
IDT 79RC32355  
2
3
4
5
6
7
8
1
CLKP  
SYSCLKP  
Trise1  
Thld3  
COLDRSTN  
RSTN  
Tdo2  
FFFF_FFFF  
BOOT VECT  
MDATA[31:0]  
BDIRN  
BOEN[0]  
>= 100 ms  
Tpw1  
>=10ms  
>= 4096 CLKP clock cycles  
OR  
>= 64 CLKP clock cycles  
>= 4096 CLKP clock cycles  
OR  
>= 64 CLKP clock cycles  
*
*
*
Selection of 4096 or 64 cycles is selected by the boot configuration vector (fast reset).  
1.  
2.  
3.  
4.  
COLDRSTN asserted by external logic.  
The RC32355 asserts RSTN, asserts BOEN[0] low, drives BDIRN low, and tri-states the data bus in response.  
External logic begins driving valid boot configuration vector on the data bus, and the RC32355 starts sampling it.  
External logic negates COLDRSTN and tri-states the boot configuration vector on MDATA[15:0]. The boot configuration vector must not be tri-stated before COLDRSTN is deas-  
serted. The RC32355 stops sampling the boot configuration vector.  
5.  
6.  
7.  
8.  
The RC32355 starts driving the data bus, MDATA[31:0], deasserts BOEN[0] high, and drives BDIRN high.  
SYSCLKP may be held constant after this point if Hold SYSCLKP Constant is selected in the boot configuration vector.  
RSTN negated by RC32355.  
CPU begins executing by taking MIPS reset exception, and the RC32355 starts sampling RSTN as a warm reset input.  
Figure 6 Cold Reset AC Timing Waveform  
1
2
3
4
5
CLKP  
COLDRSTN  
RSTN  
FFFF_FFFF  
MDATA[31:0]  
Active  
Deasserted  
Active  
Mem Control Signals  
>= 4096 CLKP clock cycles  
OR  
>= 64 CLKP clock cycles  
(RSTN ignored during this period  
to allow pull-up to drive signal high)  
>= 4096 CLKP clock cycles  
OR  
>= 64 CLKP clock cycles  
*
*
*
Selection of 4096 or 64 cycles is selected by the boot configuration vector (fast reset).  
1.  
2.  
3.  
4.  
5.  
Warm reset condition caused by either RSTN asserted, write to reset register, or bus transaction timer time-out. The RC32355 asserts RSTN output low in response.  
The RC32355 tri-states the data bus, MDATA[31:0], and deasserts all memory control signals, such as RASN, CASN, RWN, OEN, etc.  
The RC32355 deasserts RSTN.  
The RC32355 starts driving the data bus, MDATA[31:0], again, but does not sample the RSTN input.  
CPU begins executing by taking a MIPS soft reset exception and also starts sampling the RSTN input again.  
Figure 7 Warm Reset AC Timing Waveform  
18 of 47  
May 25, 2004  
IDT 79RC32355  
133MHz 150MHz 180MHz  
Timing  
Conditions Diagram  
Reference  
Reference  
Edge  
Signal  
Symbol  
Unit  
Min Max Min Max Min Max  
Memory and Peripheral Bus - SDRAM Access  
MDATA[31:0]  
Tsu1  
Thld1  
Tdo1  
Tdz1  
Tzd1  
Tdo2  
SDCLKINP  
rising  
2.5  
1.5  
1.2  
—
—
—
2.5  
1.5  
1.2  
—
—
—
2.5  
1.5  
1.2  
—
—
—
ns  
ns  
ns  
ns  
ns  
ns  
Figure 8  
Figure 9  
Figure 10  
SYSCLKP  
rising  
5.8  
5.0  
—
5.8  
5.0  
—
5.8  
5.0  
—
1.0  
1.2  
1.0  
1.2  
1.0  
1.2  
MADDR[20:2],  
BWEN[3:0]  
SYSCLKP  
rising  
5.3  
5.3  
5.3  
CASN, RASN,  
SDCSN[1:0], SDWEN  
Tdo3  
Tdo4  
Tdo5  
Tdo6  
SYSCLKP  
rising  
1.2  
1.2  
1.2  
1.2  
5.3  
5.3  
5.3  
5.3  
1.2  
1.2  
1.2  
1.2  
5.3  
5.3  
5.3  
5.3  
1.2  
1.2  
1.2  
1.2  
5.3  
5.3  
5.3  
5.3  
ns  
ns  
ns  
ns  
CKENP  
BDIRN  
SYSCLKP  
rising  
SYSCLKP  
rising  
BOEN[1:0]  
SYSCLKP  
rising  
SYSCLKP rising  
SDCLKINP  
Tdo7  
CLKP rising  
none  
0.5  
15  
6.0  
—
0
5.0  
50  
0.5  
13.3  
5.4  
—
5.0  
50  
0.5  
13.3  
5.4  
—
5.0  
50  
ns  
ns  
ns  
ns  
ns  
Tperiod8  
Thigh8,Tlow8  
Trise8,Tfall8  
Tdelay8  
—
—
—
3.0  
4.8  
2.5  
4.8  
2.5  
4.8  
SYSCLKP  
rising  
0
0
Table 6 Memory and Peripheral Bus AC Timing Characteristics (Part 1 of 2)  
19 of 47  
May 25, 2004  
IDT 79RC32355  
133MHz 150MHz 180MHz  
Timing  
Conditions Diagram  
Reference  
Reference  
Edge  
Signal  
Symbol  
Unit  
Min Max Min Max Min Max  
Memory and Peripheral Bus - Device Access  
MDATA[31:0]  
Tsu1  
Thld1  
Tdo1  
Tdz1  
Tzd1  
Tsu  
CLKP rising  
2.5  
1.5  
2.0  
—
—
—
2.5  
1.5  
2.0  
—
—
—
2.5  
1.5  
2.0  
—
—
—
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Figure 11  
Figure 12  
6.5  
9.0  
—
6.5  
9.0  
—
6.5  
9.0  
—
2.0  
2.5  
1.5  
2.0  
—
2.0  
2.5  
1.5  
2.0  
—
2.0  
2.5  
1.5  
2.0  
—
WAITACKN, BRN  
MADDR[21:0]  
CLKP rising  
CLKP rising  
—
—
—
Thld  
—
—
—
Tdo2  
Tdz2  
Tzd2  
Tdo3  
Tdz3  
Tzd3  
Tdo4  
Tdz4  
Tzd4  
Tdo5  
Tdz5  
Tzd5  
Tdo6  
Tdz6  
Tzd6  
Tdo7  
Tdz7  
Tzd7  
6.0  
9.0  
—
6.0  
9.0  
—
6.0  
9.0  
—
2.0  
2.5  
—
2.0  
2.5  
—
2.0  
2.5  
—
MADDR[25:22]  
CLKP rising  
CLKP rising  
CLKP rising  
CLKP rising  
CLKP rising  
6.5  
9.0  
—
6.5  
9.0  
—
6.5  
9.0  
—
2.0  
2.0  
—
2.0  
2.0  
—
2.0  
2.0  
—
BDIRN, BOEN[0]  
6.0  
9.0  
—
6.0  
9.0  
—
6.0  
9.0  
—
2.0  
2.0  
—
2.0  
2.0  
—
2.0  
2.0  
—
BGN, BWEN[3:0], OEN,  
RWN  
6.0  
9.0  
—
6.0  
9.0  
—
6.0  
9.0  
—
2.0  
1.7  
—
2.0  
1.7  
—
2.0  
1.7  
—
CSN[3:0]  
CSN[5:4]  
5.0  
9.0  
—
5.0  
9.0  
—
5.0  
9.0  
—
2.0  
2.5  
—
2.0  
2.5  
—
2.0  
2.5  
—
6.0  
9.0  
—
6.0  
9.0  
—
6.0  
9.0  
—
2.0  
2.0  
2.0  
Table 6 Memory and Peripheral Bus AC Timing Characteristics (Part 2 of 2)  
Note: The RC32355 provides bus turnaround cycles to prevent bus contention when going from a read to write, write to read, and during  
external bus ownership. For example, there are no cycles where an external device and the RC32355 are both driving. See the chapters  
“Device Controller,” “Synchronous DRAM Controller,” and “Bus Arbitration” in the RC32355 User Reference Manual.  
20 of 47  
May 25, 2004  
IDT 79RC32355  
CLKP  
Tdo7  
SYSCLKP  
SDRAM CAS Latency  
Tdelay8  
Tdo2  
Addr  
MADDR[21:0]  
BWEN[3:0]  
CMD[2:0]*  
SDCSN[1:0]  
BDIRN  
Tdo2  
BE's  
1111  
NOP  
11  
1111  
NOP  
11  
Tdo3  
READ  
Tdo3  
Chip-Sel  
Tdo5  
Tdo5  
Tdo6  
Tdz1  
Tdo6  
BOEN[1:0]  
MDATA[31:0]  
11  
Buffer Enables  
Tsu1  
11  
Thld1  
Tzd1  
Data  
RC32355  
samples  
read data  
SDCLKINP  
* NOTE: CMD[2:0] = {RASN, CASN, SDWEN}  
Figure 8 Memory and Peripheral Bus AC Timing Waveform - SDRAM Read Access  
Vcc  
RSTN  
pull-up  
SYSCLKP  
COLDRSTN  
CLKLP  
Tdelay8  
RC32355  
SDCLKINP  
Memory Bus  
external  
buffer  
SRAM,  
EPROM,  
etc.  
SDRAM  
Figure 9 SYSCLKP - SDCLKINP Relationship  
21 of 47  
May 25, 2004  
IDT 79RC32355  
CLKP  
Tdo7  
SYSCLKP  
SDRAM  
samples  
write data  
Tdo2  
Tdo2  
MADDR[21:0]  
BWEN[3:0]  
CMD[2:0]*  
SDCSN[1:0]  
BDIRN  
Addr  
BE's  
1111  
1111  
Tdo3  
NOP  
WRITE  
NOP  
Tdo3  
11  
Chip-Sel  
11  
Tdo5  
Tdo6  
Buff Enable  
BOEN[1:0]  
MDATA[31:0]  
11  
11  
Tdo1  
Data  
* NOTE: CMD[2:0] = {RASN, CASN, SDWEN}  
Figure 10 Memory and Peripheral Bus AC Timing Waveform - SDRAM Write Access  
22 of 47  
May 25, 2004  
IDT 79RC32355  
CLKP  
Tdo2  
Addr[21:0]  
MADDR[21:0]  
Tdo3  
MADDR[25:22]  
RWN  
Addr[25:22]  
Tdo6  
Tdo6  
CSN[3:0]  
1111  
BWEN[3:0]  
Tdo5  
Tdo5  
OEN  
Thld1  
Tsu1  
Data  
Tdz1  
Tzd1  
MDATA[31:0]  
BDIRN  
RC32355  
samples  
read data  
Tdo4  
Tdo4  
Tdo4  
Tdo4  
BOEN[0]  
WAITACKN  
Figure 11 Memory and Peripheral Bus AC Timing Waveform - Device Read Access  
23 of 47  
May 25, 2004  
IDT 79RC32355  
CLKP  
MADDR[21:0]  
MADDR[25:22]  
RWN  
Tdo2  
Addr[21:0]  
Tdo3  
Tdo5  
Addr[25:22]  
Tdo6  
CSNx  
Tdo5  
Byte Enables  
BWEN[3:0]  
OEN  
1111  
1111  
Tdo1  
Data  
MDATA[31:0]  
BDIRN  
Tdo4  
BOEN[0]  
WAITACKN  
Figure 12 Memory AC and Peripheral Bus Timing Waveform - Device Write Access  
24 of 47  
May 25, 2004  
IDT 79RC32355  
133MHz  
Min Max  
150MHz  
Min Max  
180MHz  
Min Max  
Timing  
Unit Conditions Diagram  
Reference  
Reference  
Edge  
Signal  
Symbol  
Ethernet1,2  
MIIRXCLKP, MIITXCLKP  
Tperiod1  
Thigh1,Tlow1  
Trise1,Tfall1  
Tperiod1  
Thigh1,Tlow1  
Trise1,Tfall1  
Tsu2  
none  
none  
399.96 400.04 399.96 400.04 399.96 400.04  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
10 Mbps  
Figure 13  
140  
—
260  
3
140  
—
260  
3
140  
—
260  
3
MIIRXCLKP, MIITXCLKP  
39.996 40.004 39.996 40.004 39.996 40.004  
100 Mbps  
14  
—
5
26  
2
14  
—
5
26  
2
14  
—
5
26  
2
MIIRXDP[3:0],  
MIIRXDVP, MIIRXERP  
MIIRXCLKP  
rising  
—
—
13  
—
—
13  
—
—
13  
Thld2  
3
3
3
MIITXDP[3:0],MIITXENP,  
MIITXERP  
Tdo3  
MIITXCLKP  
rising  
7
7
7
MIIMDCP  
MIIMDIOP  
Tperiod4  
Thigh4,Tlow4  
Trise4  
none  
30  
14  
—
—
6
—
—
11  
8
27  
13  
—
—
6
—
—
11  
8
27  
13  
—
—
6
—
—
11  
8
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Tfall4  
Tsu5  
MIIMDCP  
rising  
—
—
7
—
—
7
—
—
7
Thld5  
0.5  
0.5  
0.5  
Tdo5  
3
3
3
1 Ethernet clock (MIIRXCLKP and MIITXCLKP) frequency must be equal to or less than 1/2 CLKP frequency.  
2 MIICOLP and MIICRSP are asynchronous signals.  
Table 7 Ethernet AC Timing Characteristics  
25 of 47  
May 25, 2004  
IDT 79RC32355  
Thigh1  
Tperiod1  
Tlow1  
Tlow1  
Tlow4  
MIIRXCLKP  
Thld2  
Tsu2  
MIIRXDVP, MIIRXDP[3:0], MIIRXERP  
Thigh1  
Tperiod1  
MIITXCLKP  
Tdo3  
Tdo3  
MIITXENP, MIITXDP[3:0], MMTXERP  
Thigh4  
Tperiod4  
MIIMDCP  
Tdo5  
Tdo5  
MIIMDIOP (output)  
Thld5  
Tsu5  
MIIMDIOP (input)  
Figure 13 Ethernet AC Timing Waveform  
26 of 47  
May 25, 2004  
IDT 79RC32355  
133MHz 150MHz 180MHz  
Timing  
Diagram  
Reference  
Reference  
Edge  
Signal  
Symbol  
Unit Conditions  
Min Max Min Max Min Max  
ATM Interface, Utopia Mode1, 2  
RXCLKP, TXCLKP1  
Tperiod1  
none  
none  
none  
—
16  
—
—
12  
—
—
8
40  
—
4
—
16  
—
—
12  
—
—
8
40  
—
4
—
16  
—
—
12  
—
—
8
40  
—
4
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
25 MHz Utopia  
33 MHz Utopia  
50 MHz Utopia  
Figure 14  
Thigh1,Tlow1  
Trise1,Tfall1  
Tperiod1  
RXCLKP, TXCLKP1  
RXCLKP, TXCLKP  
TXFULLN  
30  
—
3
30  
—
3
30  
—
3
Thigh1,Tlow1  
Trise1,Tfall1  
Tperiod1  
20  
—
2
20  
—
2
20  
—
2
Thigh,Tlow1  
Trise1,Tfall1  
Tsu2  
—
2
—
2
—
2
TXCLKP  
rising  
—
—
8
—
—
8
—
—
8
Thld2  
2
2
2
TXDATA[7:0], TXSOC,  
TXENBN, TXADDR[1:0]  
Tdo3  
TXCLKP  
rising  
4
4
4
RXDATA[7:0], RXEMP-  
TYN, RXSOC  
Tsu4  
Thld4  
Tdo5  
RXCLKP  
rising  
3
2
3
—
—
8
3
2
3
—
—
8
3
2
3
—
—
8
ns  
ns  
ns  
RXADDR[1:0], RXENBN  
RXCLKP  
rising  
Table 8 ATM AC Timing Characteristics  
1. ATM Utopia clock (RXCLKP and TXCLKP) frequency must be equal to or less than 1/2 CLKP frequency.  
2. All Utopia Mode pins are multiplexed on the ATM interface pins as described in Table 9.  
27 of 47  
May 25, 2004  
 
IDT 79RC32355  
Tperiod1  
TXCLKP  
TXFULL  
Tsu2  
Thld2  
Tdo3  
TXDATA,TXSOC,TXENB,TXADDR  
RXCLKP  
Tperiod1  
Tperiod6  
Tperiod6  
Tsu4  
Thld4  
RXDATA, RXEMPTY, RXSOC  
RXADDR, RXENB  
O0CLKP, O1CLKP  
O0DP, O0FRMP  
Tdo5  
Tdo7  
Tdo8  
O1DP, O1FRMP  
I0CLKP, I1CLKP  
Tsu9  
Thld9  
I0DP  
Thld10  
Tsu10  
I1DP  
Figure 14 ATM AC Timing Waveform  
28 of 47  
May 25, 2004  
IDT 79RC32355  
ATM Pin Name  
ATMINP[0]  
Utopia Level 1  
Utopia Level 2  
RXDATA[0]  
RXDATA[1]  
RXDATA[2]  
RXDATA[3]  
RXDATA[4]  
RXDATA[5]  
RXDATA[6]  
RXDATA[7]  
RXCLKP  
RXDATA[0]  
RXDATA[1]  
RXDATA[2]  
RXDATA[3]  
RXDATA[4]  
RXDATA[5]  
RXDATA[6]  
RXDATA[7]  
RXCLKP  
ATMINP[1]  
ATMINP[2]  
ATMINP[3]  
ATMINP[4]  
ATMINP[5]  
ATMINP[6]  
ATMINP[7]  
ATMINP[8]  
ATMINP[9]  
ATMINP[10]  
ATMINP[11]  
ATMIOP[0]  
ATMIOP[1]  
ATMOUTP[0]  
ATMOUTP[1]  
ATMOUTP[2]  
ATMOUTP[3]  
ATMOUTP[4]  
ATMOUTP[5]  
ATMOUTP[6]  
ATMOUTP[7]  
ATMOUTP[8]  
ATMOUTP[9]  
GPIOP[22]  
RXEMPTYN  
RXSOC  
RXEMPTYN  
RXSOC  
TXFULLN  
RXENBN  
TXFULLN  
RXENBN  
TXCLKP  
TXCLKP  
TXDATA[0]  
TXDATA[1]  
TXDATA[2]  
TXDATA[3]  
TXDATA[4]  
TXDATA[5]  
TXDATA[6]  
TXDATA[7]  
TXSOC  
TXDATA[0]  
TXDATA[1]  
TXDATA[2]  
TXDATA[3]  
TXDATA[4]  
TXDATA[5]  
TXDATA[6]  
TXDATA[7]  
TXSOC  
TXENBN  
TXENBN  
TXADDR[0]  
TXADDR[1]  
RXADDR[0]  
RXADDR[1]  
GPIOP[23]  
GPIOP[24]  
GPIOP[25]  
Table 9 ATM I/O Pin Multiplexing  
29 of 47  
May 25, 2004  
IDT 79RC32355  
133MHz 150MHz 180MHz  
Timing  
Diagram  
Reference  
Reference  
Edge  
Signal  
Symbol  
Unit Conditions  
Min Max Min Max Min Max  
TDM  
TDMCLKP1  
Tperiod1  
Thigh1  
Tlow1  
Trise1  
Tfall1  
Tsu2  
none  
—
62.5  
62.5  
—
—
4
125  
—
—
3
—
31.2  
31.2  
—
—
4
62.5  
—
—
3
—
31.2  
31.2  
—
—
4
62.5  
—
—
3
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Figure 15  
Figure 16  
3
3
3
TDMFP  
TDMCLKP  
rising or falling  
—
—
9
—
—
9
—
—
9
Thld2  
Tdo2  
1
1
1
2
2
2
TDMDIP  
Tsu3  
TDMCLKP  
rising or falling  
4
—
—
9
4
—
—
9
4
—
—
9
Thld3  
Tdo4  
1
1
1
TDMDOP  
TDMCLKP  
rising or falling  
2
2
2
Tdz4  
—
3
12  
—
9
—
3
12  
—
9
—
3
12  
—
9
Tzd4  
TDMTEN  
Tdo5  
TDMCLKP  
2
2
2
rising or falling  
1The rising or falling edge of TDMCLKP is used as the reference clock edge for the timing depending on the TDM bus mode and protocol selection.  
Table 10 TDM AC Timing Characteristics  
Trise1  
Tfall1  
Tperiod1  
Thigh1  
Tlow1  
TDMCLKP  
TDMFP  
Tdo2  
Tdo2  
Tdo4  
Tdo4  
TDMDOP  
TDMDIP  
TDMTEN  
Tsu3  
Thld3  
Tdo5  
Figure 15 TDM AC Timing Waveform, Master Mode  
30 of 47  
May 25, 2004  
 
IDT 79RC32355  
TDMCLKP  
Thld2  
Tsu2  
TDMFP  
Tdo4 Tdo4  
TDMDOP  
Thld3  
Tsu3  
Tdo5  
TDMDIP  
TDMTEN  
Tdo5  
Figure 16 TDM AC Timing Waveform, Slave Mode  
31 of 47  
May 25, 2004  
IDT 79RC32355  
133MHz  
150MHz  
180MHz  
Timing  
Diagram  
Reference  
Reference  
Edge  
Signal  
Symbol  
Unit  
Conditions  
Min Max Min Max Min Max  
USB  
USBCLKP1  
Tperiod1  
Thigh1,Tlow1  
Trise1,Tfall1  
Tjitter1  
none  
19.79 21.87 19.79 21.87 19.79 21.87  
ns  
ns  
ns  
ns  
Figure 17  
8.3  
—
—
3
8.3  
—
—
3
8.3  
—
—
3
—
0.8  
—
0.8  
—
0.8  
1/4th of the mini-  
mum Source data  
jitter  
USBDN, USBDP  
Trise2  
Tfall2  
4
20  
4
20  
4
20  
ns  
Universal Serial Bus  
Specification  
(USBS) Revision  
1.1: Figures 7.6 and  
7.7.  
4
20  
4
20  
4
20  
ns  
%
USBS Revision 1.1:  
Figures 7.6 and 7.7.  
USBDN and USBDP  
Rise and Fall Time  
Matching  
90 111.11 90 111.11 90 111.11  
USBS Revision 1.1:  
Note 10, Section  
7.1.2.  
Data valid period  
Tstate  
60  
—
—
60  
—
—
60  
—
—
ns  
ns  
Skew between USBDN  
and USBDP  
0.4  
0.4  
0.4  
USBS Revision 1.1:  
Section 7.1.3  
Source data jitter  
Receive data jitter  
Source EOP length  
Receive EOP length  
EOP jitter  
—
—
3.5  
12  
175  
—
—
—
3.5  
12  
175  
—
—
—
3.5  
12  
175  
—
ns  
ns  
USBS Revision 1.1:  
Table 7-6  
Tseop  
Treop  
160  
82  
-2  
160  
82  
-2  
160  
82  
-2  
ns  
ns  
5
5
5
ns  
Full-speed Data Rate  
Tfdrate  
11.97 12.03 11.97 12.03 11.97 12.03  
MHz  
Average bit rate,  
USBS Section  
7.1.11.  
Frame Interval  
0.9995 1.0005 0.9995 1.0005 0.9995 1.0005  
ms  
ns  
ns  
USBS Section  
7.1.12.  
Consecutive Frame  
Interval Jitter  
—
—
42  
—
—
42  
—
—
42  
Without frame  
adjustment.  
126  
126  
126  
With frame adjust-  
ment.  
1 USB clock (USBCLKP) frequency must be less than CLKP frequency.  
Table 11 USB AC Timing Characteristics  
32 of 47  
May 25, 2004  
IDT 79RC32355  
Tfall1  
USBCLKP  
Tperiod1  
Tlow1  
Thigh1  
Trise1  
Tjitter1  
Tstate  
90%  
USBDN  
USBDP  
90%  
10%  
10%  
Trise2  
Tfall2  
Tfdrate  
USBDN  
USBDP  
Tseop  
Treop  
Figure 17 USB AC Timing Waveform  
133MHz 150MHz 180MHz  
Timing  
Reference  
Signal  
Symbol  
Unit Conditions Diagram  
Reference  
Edge  
Min Max Min Max Min Max  
UART  
U0SINP, U0RIN, U0DCDN,  
U0DSRN, U0CTSN, U1SINP,  
U1DSRN, U1CTSN  
Tsu1  
Thld1  
CLKP rising  
5
3
—
—
5
3
—
—
5
3
—
—
ns  
ns  
U0SOUTP, U0DTRN, U0RTSN,  
U1SOUTP, U1DTRN, U1RTSN  
Tdo1  
CLKP rising  
1
12  
1
12  
1
12  
ns  
1 These are asynchronous signals and the values are provided for ATE (test) only.  
Table 12 UART AC Timing Characteristics  
33 of 47  
May 25, 2004  
IDT 79RC32355  
133MHz 150MHz 180MHz  
Timing  
Unit Conditions Diagram  
Reference  
Reference  
Edge  
Signal  
Symbol  
Min Max Min Max Min Max  
I2C1  
SCLP  
Frequency  
Thigh1  
Tlow1  
Trise1  
Tfall1  
none  
0
100  
—
0
4.0  
4.7  
—
100  
—
0
4.0  
4.7  
—
100  
—
kHz 100 KHz  
Figure 18  
4.0  
4.7  
—
µs  
µs  
ns  
ns  
ns  
µs  
ns  
ns  
µs  
µs  
µs  
µs  
—
—
—
1000  
300  
—
1000  
300  
—
1000  
300  
—
—
—
—
SDAP  
Tsu2  
SCLP rising  
250  
0
250  
0
250  
0
Thld2  
3.45  
1000  
300  
—
3.45  
1000  
300  
—
3.45  
1000  
300  
—
Trise2  
Tfall2  
—
—
—
—
—
—
Start or repeated start condition  
Stop condition  
Tsu3  
SDAP falling  
SDAP rising  
4.7  
4.0  
4.0  
4.7  
4.7  
4.0  
4.0  
4.7  
4.7  
4.0  
4.0  
4.7  
Thld3  
—
—
—
Tsu4  
—
—
—
Bus free time between a stop and  
start condition  
Tdelay5  
—
—
—
SCLP  
Frequency  
Thigh1  
Tlow1  
Trise1  
Tfall1  
none  
0
400  
—
0
0.6  
1.3  
—
400  
—
0
0.6  
1.3  
—
400  
—
kHz 400 KHz  
0.6  
1.3  
—
µs  
µs  
ns  
ns  
ns  
µs  
ns  
ns  
µs  
µs  
µs  
µs  
—
—
—
300  
300  
—
300  
300  
—
300  
300  
—
—
—
—
SDAP  
Tsu2  
SCLP rising  
100  
0
100  
0
100  
0
Thld2  
0.9  
300  
300  
—
0.9  
300  
300  
—
0.9  
300  
300  
—
Trise2  
Tfall2  
—
—
—
—
—
—
Start or repeated start condition  
Stop condition  
Tsu3  
SDAP falling  
SDAP rising  
0.6  
0.6  
0.6  
1.3  
0.6  
0.6  
0.6  
1.3  
0.6  
0.6  
0.6  
1.3  
Thld3  
—
—
—
Tsu4  
—
—
—
Bus free time between a stop and  
start condition  
Tdelay5  
—
—
—
Table 13 I2C AC Timing Characteristics  
1. For more information see the I2C-Bus specification by Philips Semiconductor  
34 of 47  
May 25, 2004  
IDT 79RC32355  
Tdelay5  
Tsu4  
SDAP  
Tlow1  
Thld2  
Tsu2  
Thld3  
Tsu3  
Thld3  
Thigh1  
SCLP  
Figure 18 I2C AC Timing Waveform  
133MHz  
150MHz  
180MHz  
Timing  
Diagram  
Reference  
Reference  
Edge  
Signal  
Symbol  
Unit  
Conditions  
Min Max Min Max Min Max  
GPIOP  
GPIOP[31:0]1  
Tsu1  
Thld1  
Tdo1  
Tsu1  
Thld1  
Tdo1  
CLKP rising  
4
1.4  
2
—
—
8
4
1.4  
2
—
—
8
4
1.4  
2
—
—
8
ns  
ns  
ns  
ns  
ns  
ns  
Figure 19  
GPIOP[35:32]2  
3
—
—
8
3
—
—
8
3
—
—
8
1
1
1
3
3
3
1 GPIOP[31:0] are controlled through the GPIO interface. GPIO[31:0] are asynchronous signals, the values are provided for ATE (test) only.  
2 GPIOP[35:32] are controlled through the TDM interface.  
Table 14 GPIOP AC Timing Characteristics  
CLKP  
Tdo1  
Tdo1  
GPIOP (output)  
GPIOP (input)  
Thld1  
Tsu1  
Figure 19 GPIOP AC Timing Waveform  
35 of 47  
May 25, 2004  
 
IDT 79RC32355  
133MHz  
150MHz  
180MHz  
Timing  
Unit Conditions Diagram  
Reference  
Reference  
Edge  
Signal  
Symbol  
Min Max Min Max Min Max  
EJTAG and JTAG  
JTAG_TCK  
Tperiod1  
Thigh1, Tlow1  
Trise1, Tfall1  
Tperiod2  
Thigh2, Tlow2  
Trise2, Tfall2  
Tsu3  
none  
none  
100  
40  
—
—
100  
40  
—
—
100  
40  
—
—
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Figure 20  
—
5
—
5
—
5
EJTAG_DCLK1  
7.5  
2.5  
—
10.0  
—
6.7  
2.5  
—
10.0  
—
5.6  
2.5  
—
10.0  
—
3.5  
—
3.5  
—
3.5  
—
JTAG_TMS, JTAG_TDI,  
JTAG_TRST_N  
JTAG_TCK rising  
JTAG_TCK falling  
3.0  
1.0  
2.0  
3.0  
1.0  
2
3.0  
1.0  
2
Thld3  
—
—
—
JTAG_TDO  
Tdo4  
12.0  
1.0  
—
12.0  
1.0  
—
12.0  
1.0  
—
Tdo5  
EJTAG_DCLK rising -0.72  
-0.72  
100  
2
-0.72  
100  
2
JTAG_TRST_N  
EJTAG_PCST[2:0]  
Tpw6  
none  
100  
2
Tsu6  
JTAG_TCK rising  
—
—
—
Tdo7  
EJTAG_DCLK rising -0.32  
3.3  
-0.32  
3.3  
-0.32  
3.3  
1. EJTAG_DCLK is equal to the internal CPU pipeline clock.  
2. A negative delay denotes the amount of time before the reference clock edge.  
Table 15 JTAG AC Timing Characteristics  
Tperiod1  
EJTAG TPC, TCST capture  
Tperiod2  
JTAG_TCK  
Trise1  
Tfall1  
Thigh1  
Tlow1  
EJTAG_DCLK  
Thigh2  
Tfall2  
Tlow2  
Trise2  
JTAG_TMS,  
JTAG_TDI  
Thld3  
TDO  
Tsu3  
TPC  
TDO  
Tdo4  
JTAG_TDO  
Tdo5  
EJTAG_PCST  
PCST  
Tdo7  
JTAG_TRST_N  
EJTAG_TRST_N  
Tsu6  
Tpw6  
Figure 20 JTAG AC Timing Waveform  
36 of 47  
May 25, 2004  
 
 
IDT 79RC32355  
Table 16 shows the pin numbering for the Standard EJTAG connector. All the even numbered pins are connected to ground. Multiplexing of pin  
functions should be considered when connecting EJTAG_TRST_N and EJTAG_PCST.  
For details on using the JTAG connector, see the JTAG chapters in the RC32355 user reference manual.  
PIN  
SIGNAL  
RC32355 I/O  
TERMINATION1  
1
EJTAG_TRST_N  
Input  
10 kΩ pull-down resistor. A pull-down resistor will hold the EJTAG controller in reset when not in use  
if the EJTAG_TRST_N function is selected with the boot configuration vector. Refer to the User Man-  
ual.  
3
5
7
9
JTAG_TDI  
Input  
Output  
Input  
10 kΩ pull-up resistor  
JTAG_TDO  
33 Ω series resistor  
JTAG_TMS  
10 kΩ pull-up resistor  
10 kΩ pull-up resistor2  
JTAG_TCK  
Input  
11  
13  
15  
17  
19  
21  
System Reset  
EJTAG_PCST[0]  
EJTAG_PCST[1]  
EJTAG_PCST[2]  
EJTAG_DCLK  
Debug Boot  
Input  
10 kΩ pull-up resistor is used if it is combined with the system cold reset control, COLDRSTN.  
Output  
Output  
Output  
Output  
Input  
33 Ω series resistor  
33 Ω series resistor  
33 Ω series resistor  
33 Ω series resistor  
This can be connected to the boot configuration vector to control debug boot mode if desired. Refer  
to Table 2 on page 12 and the RC32355 user reference manual.  
23  
VCCI/O  
Output  
Used to sense the circuit board power. Must be connected to the VCC I/O supply of the circuit board.  
Table 16 Pin Numbering of the JTAG and EJTAG Target Connector  
1. The value of the series resistor may depend on the actual printed circuit board layout situation.  
2. JTAG_TCK pull-up resistor is not required according to the JTAG (IEEE1149) standard. It is indicated here to prevent a floating CMOS input when the EJTAG connector is  
unconnected.  
AC Test Conditions  
1.5V  
50 Ω  
RC32355  
Output  
Test  
Point  
.
50 Ω  
Parameter  
Value  
Units  
Input pulse levels  
Input rise/fall  
0 to 3.0  
3.5  
V
ns  
V
Input reference level  
Output reference levels  
AC test load  
1.5  
1.5  
V
25  
pF  
Figure 21 Output Loading for AC Timing  
37 of 47  
May 25, 2004  
 
IDT 79RC32355  
Phase-Locked Loop (PLL)  
The processor aligns the pipeline clock, PClock, to the master input clock (CLKP) by using an internal phase-locked loop (PLL) circuit that gener-  
ates aligned clocks. Inherently, PLL circuits are only capable of generating aligned clocks for master input clock (CLKP) frequencies within a limited  
range.  
PLL Analog Filter  
The storage capacitor required for the Phase-Locked Loop circuit is contained in the RC32355. However, it is recommended that the system  
designer provide a filter network of passive components for the PLL power supply.  
VCCP (PLL circuit power) and VSSP (PLL circuit ground) should be isolated from VCC Core (core power) and VSS (common ground) with a filter  
circuit such as the one shown in Figure 22.  
Because the optimum values for the filter components depend upon the application and the system noise environment, these values should be  
considered as starting points for further experimentation within your specific application.  
RC32355  
10 ohm1  
Vcc  
Vss  
VccP  
10 µF  
0.1 µF  
100 pF  
VssP  
1.This resistor may be required in noisy circuit environments.  
Figure 22 PLL Filter Circuit for Noisy Environments  
Recommended Operating Temperature and Supply Voltage  
Vss1  
VccCore3  
Grade  
Temperature  
VccI/O2  
VssP5  
VccP4  
Commercial  
Industrial  
0°C to +70°C Ambient  
-40°C+ 85°C Ambient  
0V  
0V  
3.3V±5%  
3.3V±5%  
2.5V±5%  
2.5V±5%  
1 Vss supplies a common ground.  
2 VccI/O is the I/O power.  
3 VccCore is the internal logic power.  
4 VccP is the phase lock loop power.  
5VssP is the phase lock loop ground.  
Table 17 Temperature and Voltage  
Capacitive Load Deration  
Refer to the RC32355 IBIS Model which can be found at the IDT web site (www.idt.com).  
38 of 47  
May 25, 2004  
 
 
IDT 79RC32355  
Power-on RampUp  
The 2.5V core supply (and 2.5V V PLL supply) can be fully powered without the 3.3V I/O supply. However, the 3.3V I/O supply cannot exceed the  
cc  
2.5V core supply by more than 1 volt during power up. A sustained large power difference could potentially damage the part. Inputs should not be  
driven until the part is fully powered. Specifically, the input high voltages should not be applied until the 3.3V I/O supply is powered.  
There is no special requirement for how fast V I/O ramps up to 3.3V. However, all timing references are based on a stable V I/O.  
cc  
cc  
DC Electrical Characteristics  
(T  
= 0°C to +70°C Commercial, T  
= -40°C to +85°C Industrial, Vcc I/O = +3.3V±5%, V Core and V P = +2.5V±5%)  
ambient  
ambient cc cc  
Para-  
Min  
Max  
Unit  
Pin Numbers  
Conditions  
VOL = 0.4V  
meter  
LOW Drive  
IOL  
IOH  
VIL  
VIH  
7.3  
-8.0  
—
—
—
mA  
mA  
V
1-4,6-8,10-16,18,20-25,27-29,32,33,35-37,  
39-42,44,46-48,50,52,53,56,58-60,62-69,  
71-77,82-85,87-94,96-99,101-105,167,  
205-208  
Output with  
Schmitt Trigger  
Input (STI)  
VOH = (V I/O - 0.4)  
cc  
0.8  
—
—
2.0  
V
(V I/O  
cc  
+ 0.5)  
VOH  
IOL  
Vcc - 0.4  
9.4  
V
mA  
mA  
V
—
—
HIGH Drive  
Output with  
Standard Input  
—
49,51,54,55,106-108,110,112-117,119,  
121,123-128,130,132-137,139,141,143,  
150,152,154-159,161,163-166,168-170,  
172,174-179,181,185-190,192,194-200,  
202,204  
VOL = 0.4V  
IOH  
VIL  
VIH  
-15  
—
VOH = (V I/O - 0.4)  
cc  
—
0.8  
—
—
2.0  
V
(V I/O  
cc  
+ 0.5)  
VOH  
IOL  
Vcc - 0.4  
39  
V
—
—
Clock Drive  
Output  
—
mA  
mA  
pF  
183  
VOL = 0.4V  
IOH  
-24  
—
VOH = (V I/O - 0.4)  
cc  
Capacitance  
Leakage  
CIN  
—
10  
All pins  
All pins  
—
—
I/OLEAK  
—
20  
µA  
Table 18 DC Electrical Characteristics  
39 of 47  
May 25, 2004  
IDT 79RC32355  
USB Electrical Characteristics  
Parameter  
Min  
Max  
Unit  
Conditions  
USB Interface  
Vdi  
Differential Input Sensitivity  
-0.2  
0.8  
V
V
I(D+)-(D-)I  
Vcm  
Differential Input Common Mode  
Range  
2.5  
Vse  
Cin  
Ili  
Single ended Receiver Threshold  
Transceiver Capacitance  
0.8  
-10  
2.8  
28  
2.0  
20  
10  
V
pF  
µA  
Hi-Z State Data Line Leakage  
0V < Vin < 3.3V  
USB Upstream/Downstream Port  
Voh  
Vol  
Zo  
Static Output High  
3.6  
0.3  
44  
V
V
15km + 5% to Gnd  
Including Rext = 20 Ω  
Static Output Low  
USB Driver Output Impedance  
Ω
Table 19 USB Interface Characteristics  
Power Consumption  
Note: This table is based on a 2:1 CPU pipeline to system (PClock to CLKP) clock ratio.  
Parameter  
133MHz  
150MHz  
180MHz  
Unit  
Conditions  
Typical Max.  
Typical Max.  
Typical Max.  
I
CC I/O  
80  
130  
100  
450  
360  
1.46  
1.22  
150  
120  
500  
400  
1.73  
1.47  
170  
mA  
mA  
mA  
W
ICC core  
Normal mode  
400  
320  
1.26  
1.06  
450  
370  
500  
410  
550  
450  
CL = 25pF (affects I/O)  
Ta = 25oC  
VccP = 2.625V (for max. values)  
Standby mode1  
Normal mode  
Standby mode1  
Power  
Dissipation  
1.63  
1.42  
1.86  
1.59  
2.03  
1.77  
V
core = 2.625V (for max. values)  
cc  
cc  
V I/O = 3.46V (for max. values)  
VccP = 2.5V (for typical values)  
W
V
core = 2.5V (for typical values)  
cc  
cc  
V I/O = 3.3V (for typical values)  
1. RISCore 32300 CPU core enters Standby mode by executing WAIT instructions; however, other logic continues to function. Standby mode reduces power consumption by 0.6  
mA per MHz of the CPU pipeline clock, PClock.  
Table 20 RC32355 Power Consumption  
40 of 47  
May 25, 2004  
 
IDT 79RC32355  
Power Curve  
The following graph contains a power curve that shows power consumption at various bus frequencies.  
Note: The system clock (CLKP) can be multiplied by 2, 3, or 4 to obtain the CPU pipeline clock (PClock) speed.  
Typical Power Curve  
2.2  
2.0  
1.8  
1.6  
1.4  
2x  
1.2  
1.0  
0.8  
0.6  
40  
45  
50  
55  
60  
65  
70  
75  
80  
85  
90  
System Bus Speed (MHz)  
Figure 23 Typical Power Usage  
Absolute Maximum Ratings  
Symbol  
VCCI/O  
Parameter  
Min1  
Max1  
Unit  
I/O Supply Voltage  
Core Supply Voltage  
PLL Supply Voltage  
Input Voltage - undershoot  
I/O Input Voltage  
-0.3  
-0.3  
-0.3  
-0.6  
Gnd  
-40  
3.465  
V
VCCCore  
VCCP  
Vimin  
Vi  
3.0  
V
3.0  
—
V
V
V
VCCI/O+0.6  
85  
Ta,  
Industrial  
Ambient Operating  
Temperature  
degrees C  
Tstg  
Storage Temperature  
-40  
125  
degrees C  
Table 21 Absolute Maximum Ratings  
1. Functional and tested operating conditions are given in Table 17. Absolute maximum ratings are stress ratings only,  
and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability  
or cause permanent damage to the device.  
41 of 47  
May 25, 2004  
 
IDT 79RC32355  
Package Pin-out — 208-Pin PQFP  
The following table lists the pin numbers and signal names for the RC32355.  
Pin  
Function  
ATMOUTP[0]  
Alt Pin  
Function  
JTAG_TDO  
Alt Pin  
Function  
BGN  
Alt Pin  
Function  
Alt  
1
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
105  
157 MDATA[28]  
2
ATMOUTP[1]  
ATMINP[02]  
ATMOUTP[2]  
Vss  
GPIOP[16]  
GPIOP[17]  
GPIOP[18]  
Vss  
1
1
1
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
126  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
CSN[0]  
158 MDATA[13]  
159 MDATA[29]  
160 Vcc I/O  
3
CSN[1]  
4
CSN[2]  
5
Vcc I/O  
161 MDATA[14]  
162 Vss  
6
ATMOUTP[3]  
ATMINP[03]  
ATMOUTP[4]  
Vcc I/O  
JTAG_TCK  
GPIOP[19]  
GPIOP[20]  
Vcc I/O  
CSN[3]  
7
1
1
Vss  
163 MDATA[30]  
164 MDATA[15]  
165 MDATA[31]  
166 CLKP  
8
OEN  
9
RWN  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
ATMOUTP[5]  
ATMINP[04]  
ATMOUTP[6]  
ATMOUTP[7]  
ATMINP[05]  
ATMOUTP[8]  
ATMOUTP[9]  
Vss  
GPIOP[21]  
JTAG_TDI  
GPIOP[22]  
GPIOP[23]  
GPIOP[24]  
JTAG_TMS  
GPIOP[25]  
GPIOP[26]  
Vss  
1
BDIRN  
BOEN[0]  
BOEN[1]  
BWEN[0]  
Vcc I/O  
167 WAITACKN  
168 MADDR[00]  
169 MADDR[11]  
170 MADDR[01]  
171 Vcc I/O  
1
2
1
BWEN[1]  
Vss  
2
1
172 MADDR[12]  
173 Vss  
BWEN[2]  
Vcc Core  
BWEN[3]  
MDATA[00]  
MDATA[16]  
MDATA[01]  
MDATA[17]  
MDATA[02]  
Vcc I/O  
ATMINP[06]  
Vcc Core  
174 MADDR[02]  
175 MADDR[13]  
176 MADDR[03]  
177 MADDR[14]  
178 MADDR[04]  
179 MADDR[15]  
180 Vcc I/O  
GPIOP[27]  
COLDRSTN  
GPIOP[28]  
GPIOP[29]  
GPIOP[30]  
GPIOP[31]  
USBCLKP  
Vcc I/O  
1
GPIOP[00]  
GPIOP[01]  
ATMINP[07]  
GPIOP[02]  
GPIOP[03]  
ATMINP[08]  
Vcc I/O  
1
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
1
1
1
1
2
2
1
181 MADDR[05]  
182 Vcc Core  
183 SYSCLKP  
184 Vss  
MDATA[18]  
Vss  
GPIOP[04]  
GPIOP[05]  
ATMINP[09]  
VccP1  
2
1
USBDN  
USBDP  
MDATA[03]  
MDATA[19]  
MDATA[04]  
MDATA[20]  
MDATA[05]  
MDATA[21]  
Vcc Core  
Vss  
185 MADDR[16]  
186 MADDR[06]  
187 MADDR[17]  
188 MADDR[07]  
189 MADDR[18]  
190 MADDR[08]  
MIICRSP  
MIICOLP  
MIITXDP[0]  
MIITXDP[1]  
Vcc Core  
VssP1  
ATMINP[10]  
GPIOP[06]  
Vss  
1
Table 22: 208-pin QFP Package Pin-Out (Part 1 of 2)  
42 of 47  
May 25, 2004  
IDT 79RC32355  
Pin  
Function  
Alt Pin  
Function  
MIITXDP[2]  
Alt Pin  
Function  
Alt Pin  
Function  
Alt  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
GPIOP[07]  
ATMINP [11]  
GPIOP[08]  
Vcc Core  
GPIOP[09]  
GPIOP[10]  
GPIOP[11]  
GPIOP[12]  
Vcc I/O  
1
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
139  
140  
141  
142  
143  
144  
145  
146  
147  
148  
149  
150  
151  
152  
153  
154  
155  
156  
MDATA[06]  
Vcc I/O  
191 Vcc I/O  
MIITXDP[3]  
MIITXENP  
MIITXCLKP  
MIITXERP  
MIIRXERP  
MIIRXCLKP  
MIIRXDVP  
Vcc I/O  
192 MADDR[19]  
193 Vss  
2
MDATA[22]  
Vss  
194 MADDR[09]  
195 MADDR[20]  
196 MADDR[10]  
197 MADDR[21]  
198 CASN  
2
2
2
2
MDATA[07]  
MDATA[23]  
SDCLKINP  
MDATA[08]  
MDATA[24]  
MDATA[09]  
MDATA[25]  
MDATA[10]  
Vcc I/O  
199 RASN  
GPIOP[13]  
Vss  
2
MIIRXDP[0]  
MIIRXDP[1]  
MIIRXDP[2]  
MIIRXDP[3]  
200 SDWEN  
201 Vcc I/O  
GPIOP[14]  
GPIOP[15]  
GPIOP[35]  
GPIOP[34]  
GPIOP[33]  
GPIOP[32]  
INSTP  
1
1
1
1
1
1
202 SDCSN[0]  
203 Vss  
100 Vss  
MDATA[26]  
Vss  
204 SDCSN[1]  
205 ATMINP[00]  
206 ATMIOP[0]  
207 ATMIOP[1]  
208 ATMINP[01]  
101 MIIDCP  
102 MIIDIOP  
103 RSTN  
104 BRN  
MDATA[11]  
MDATA[27]  
MDATA[12]  
1 VccP and VssP are the Phase Lock Loop (PLL) power and ground. PLL power and ground should be supplied through a special filter circuit.  
Table 22: 208-pin QFP Package Pin-Out (Part 2 of 2)  
43 of 47  
May 25, 2004  
IDT 79RC32355  
Alternate Pin Functions  
Pin  
20  
Primary  
GPIOP[00]  
Alt #1  
U0SOUTP  
Alt #2  
Pin  
Primary  
GPIOP[32]  
Alt #1  
TDMDOP  
Alt #2  
51  
54  
55  
56  
59  
60  
62  
64  
65  
66  
68  
69  
71  
73  
74  
75  
76  
21  
23  
24  
27  
28  
33  
35  
37  
39  
40  
41  
42  
44  
46  
47  
48  
49  
50  
GPIOP[01]  
GPIOP[02]  
GPIOP[03]  
GPIOP[04]  
GPIOP[05]  
GPIOP[06]  
GPIOP[07]  
GPIOP[08]  
GPIOP[09]  
GPIOP[10]  
GPIOP[11]  
GPIOP[12]  
GPIOP[13]  
GPIOP[14]  
GPIOP[15]  
GPIOP[35]  
GPIOP[34]  
GPIOP[33]  
U0SINP  
U0RIN  
GPIOP[16]  
GPIOP[17]  
GPIOP[18]  
GPIOP[19]  
GPIOP[20]  
GPIOP[21]  
GPIOP[22]  
GPIOP[23]  
GPIOP[24]  
GPIOP[25]  
GPIOP[26]  
GPIOP[27]  
GPIOP[28]  
GPIOP[29]  
GPIOP[30]  
GPIOP[31]  
CSN[4]  
JTAG_TRST_N  
CPUP  
CSN[5]  
U0DCRN  
U0DTRN  
U0DSRN  
U0RTSN  
U0CTSN  
U1SOUTP  
U1SINP  
U1DTRN  
U1DSRN  
U1RTSN  
U1CTSN  
SDAP  
DMAREQN  
DMADONEN  
USBSOF  
CKENP  
TXADDR[0]  
TXADDR[1]  
RXADDR[0]  
RXADDR[1]  
TDMTEN  
DMAP[3]  
DMAP[0]  
DMAP[2]  
EJTAG_PCST[0]  
EJTAG_PCST[1]  
EJTAG_PCST[2]  
EJTAG_DCLK  
DMAP[1]  
MADDR[22]  
MADDR[23]  
MADDR[24]  
MADDR[25]  
DMAFIN  
SCLP  
TDMCLKP  
TDMFP  
EJTAG_TRST_N  
TDMDIP  
Table 23 Alternate Pin Functions  
44 of 47  
May 25, 2004  
IDT 79RC32355  
Package Drawing - 208-pin QFP  
45 of 47  
May 25, 2004  
IDT 79RC32355  
Package Drawing - page two  
46 of 47  
May 25, 2004  
IDT 79RC32355  
Ordering Information  
YY  
XXXX  
A
999  
A
79RCXX  
Product  
Type  
Operating  
Voltage  
Device  
Type  
Temp range/  
Process  
Package  
Speed  
Commercial Temperature  
(0°C to +70°C Ambient)  
Blank  
I
Industrial Temperature  
(-40° C to +85° C Ambient)  
208-pin QFP  
DH  
133 MHz Pipeline Clk  
150 MHz Pipeline Clk  
133  
150  
180 MHz Pipeline Clk  
180  
Integrated Core Processor  
355  
T
2.5V +/-5% Core Voltage  
32-bit Embedded  
Microprocessor  
79RC32  
Valid Combinations  
79RC32T355 -133DH, 150DH, 180DH  
79RC32T355 -133DHI, 150DHI  
208-pin QFP package, Commercial Temperature  
208-pin QFP package, Industrial Temperature  
CORPORATE HEADQUARTERS  
2975 Stender Way  
Santa Clara, CA 95054  
for SALES:  
800-345-7015 or 408-727-6116  
fax: 408-330-1748  
for Tech Support:  
email: rischelp@idt.com  
phone: 408-492-8208  
www.idt.com  
47 of 47  
May 25, 2004  

相关型号：

IDT79RC32V334-133BBG

 RISC Microcontroller, 32-Bit, 133MHz, PBGA256, 17 X 17 MM, PLASTIC, BGA-256
IDT

IDT79RC32V334-133BBGGI

 RISC Microcontroller, 32-Bit, 133MHz, PBGA256, 17 X 17 MM, PLASTIC, BGA-256
IDT

IDT79RC32V334-133BBGI

 RISC Microcontroller, 32-Bit, 133MHz, PBGA256, 17 X 17 MM, PLASTIC, BGA-256
IDT

IDT79RC32V334-133BBI

 RISC Microcontroller, 32-Bit, 133MHz, PBGA256, 17 X 17 MM, PLASTIC, BGA-256
IDT

IDT79RC32V334-133BBI8

 RISC Microcontroller, 32-Bit, 133MHz, PBGA256, 17 X 17 MM, PLASTIC, BGA-256
IDT

IDT79RC32V334-133BBI9

 RISC Microcontroller, 32-Bit, 133MHz, PBGA256, PLASTIC, BGA-256
IDT

IDT79RC32V334-150BB8

 RISC Microcontroller, 32-Bit, 150MHz, PBGA256, 17 X 17 MM, PLASTIC, BGA-256
IDT

IDT79RC32V334-150BB9

 RISC Microcontroller, 32-Bit, 150MHz, PBGA256, PLASTIC, BGA-256
IDT

IDT79RC32V334-150BBGGI

 RISC Microcontroller, 32-Bit, 150MHz, PBGA256, 17 X 17 MM, PLASTIC, BGA-256
IDT

IDT79RC32V334-150BBGI

 RISC Microcontroller, 32-Bit, 150MHz, PBGA256, 17 X 17 MM, PLASTIC, BGA-256
IDT

IDT79RC32V334-150BBI8

 RISC Microcontroller, 32-Bit, 150MHz, PBGA256, 17 X 17 MM, PLASTIC, BGA-256
IDT

IDT79RC32V364-100DA

 32-Bit Microprocessor
ETC
©2020 ICPDF网 联系我们和版权申明