IDT74LVC16652APF8 [IDT]

Registered Bus Transceiver, LVC/LCX/Z Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, 0.40 MM PITCH, TVSOP-56;


型号：	IDT74LVC16652APF8
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Registered Bus Transceiver, LVC/LCX/Z Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, 0.40 MM PITCH, TVSOP-56 光电二极管输出元件逻辑集成电路电视
文件：	总8页 (文件大小：109K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT74LVC16652A

INDUSTRIALTEMPERATURERANGE

3.3VCMOS16-BITBUSREGISTEREDTRANSCEIVER

IDT74LVC16652A

3.3V CMOS 16-BIT BUS

REGISTERED TRANSCEIVER,

5 VOLT TOLERANT I/O

DESCRIPTION:

FEATURES:

The LVC16652A 16-bit registered transceiver is built using advanced

dual metal CMOS technology. This high-speed, low power device is

organized as two independent 8-bit bus transceivers with 3-state D-type

registers.Forexample,theOEABandOEBAsignalscontrolthetransceiver

functions.

• Typical tSK(o) (Output Skew) < 250ps

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

machine model (C = 200pF, R = 0)

• VCC = 3.3V ± 0.3V, Normal Range

• VCC = 2.7V to 3.6V, Extended Range

• CMOS power levels (0.4µ W typ. static)

• All inputs, outputs, and I/O are 5V tolerant

• Supports hot insertion

TheSABandtheSBAcontrolpinsareprovidedtoselecteitherrealtime

orstoreddatatransfer.Thecircuitryusedforselectcontrolwilleliminatethe

typical decoding glitch that occurs in a multiplexer during the transition

betweenstoredandrealtimedata. ALowinputlevelselectsreal-timedata

and a High level selects stored data.

• Available in SSOP, TSSOP, and TVSOP packages

Data on the A or B data bus, or both, can be stored in the internal D-flip-

flops by the Low-to-High transitions at the appropriate clock pins (CLKAB

or CLKBA), regardless of the select or enable control pins. Flow-through

organization of signal pins simplifies layout. All inputs are designed with

hysteresis for improved noise margin.

TheLVC16652Aisideallysuitedfordrivinghighcapacitanceloadsand

low-impedancebackplanes.

Allpinscanbedrivenfromeithera3.3Vor5Vdevice. Thisfeatureallows

the use of this device as a translator in a mixed 3.3V/5V supply system.

DRIVE FEATURES:

• High Output Drivers: ±24mA

• Reduced system switching noise

APPLICATIONS:

• 5V and 3.3V mixed voltage systems

• Data communication and telecommunication systems

FUNCTIONALBLOCKDIAGRAM

1OEAB

2OEAB

1OEBA

2OEBA

2CLKBA

1CLKBA

2SBA

1SBA

2CLKAB

1CLKAB

2SAB

1SAB

B REG

2A1

A REG

2B1

1A1

A REG

1B1

TO SEVEN OTHER CHANNELS

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

INDUSTRIAL TEMPERATURE RANGE

MARCH 1999

DSC-4487/2

IDT74LVC16652A

3.3VCMOS16-BITBUSREGISTEREDTRANSCEIVER

INDUSTRIALTEMPERATURERANGE

ABSOLUTEMAXIMUMRATINGS⁽¹⁾

PINCONFIGURATION

Symbol

VTERM

TSTG

Description

Terminal Voltage with Respect to GND

Storage Temperature

Max

Unit

–0.5 to +6.5

–65 to +150

–50 to +50

–50

°C

1OEBA

1OEAB

1CLKAB

1SAB

IOUT

DC Output Current

1CLKBA

1SBA

IIK

IOK

Continuous Clamp Current,

VI < 0 or VO < 0

ICC

ISS

Continuous Current through each

VCC or GND

±100

GND

1A1

GND

1B1

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

1A2

VCC

1A3

1B2

VCC

1B3

1A4

1B4

1A5

GND

1A6

1B5

GND

1B6

1B7

1B8

2B1

CAPACITANCE (TA = +25°C, F = 1.0MHz)

1A7

1A8

2A1

2A2

2A3

GND

2A4

2A5

2A6

VCC

2A7

2A8

Symbol

Parameter⁽¹⁾

Conditions

VIN = 0V

VOUT = 0V

VIN = 0V

Typ.

Max. Unit

CIN

Input Capacitance

Output Capacitance

I/O Port Capacitance

4.5

COUT

CI/O

6.5

2B2

NOTE:

1. As applicable to the device type.

2B3

GND

2B4

2B5

2B6

VCC

2B7

2B8

PINDESCRIPTION

Pin Names

Description

xAx

Data Register A Inputs

Data Register B Outputs

DataRegisterBInputs

DataRegisterAOutputs

Clock Pulse Inputs

GND

2SAB

2SBA

xBx

2CLKBA

2OEBA

2CLKAB

2OEAB

xCLKAB, xCLKBA

xSAB, xSBA

OutputDataSourceSelectInputs

OutputEnableInputs

xOEAB, xOEBA

SSOP/ TSSOP/ TVSOP

TOP VIEW

IDT74LVC16652A

INDUSTRIALTEMPERATURERANGE

3.3VCMOS16-BITBUSREGISTEREDTRANSCEIVER

FUNCTIONTABLE^(1,2)

Inputs

Data I/O⁽³⁾

xOEAB

xOEBA

xCLKAB

xCLKBA

xSAB

xSBA

xAx

xBx

Operation or Function

Isolation

H or L

Input

↑

H or L

↑

H or L

↑

Store A and B data

X⁽²⁾

Input

Unspecified⁽³⁾

Output

Input

Store A, Hold B

StoreAinbothregisters

Store B, Hold A

X⁽²⁾

Output

Input

StoreBinbothregisters

Real time B data to A bus

Store B data to A bus

Real time A data to B bus

Store A data to B bus

Store A data to B bus and

Store B data to A bus

Output

Input

H or L

Input

Output

H or L

Output

NOTES:

1. H = HIGH Voltage Level

X = Don’t Care

L = LOW Voltage Level

↑ = LOW-to-HIGH transition

2. Select Control = L: clocks can occur simultaneously.

Select Control = H: clocks can be staggered to load both registers.

3. The data output functions may be enabled or disabled by various signals at the xOEAB or xOEBA inputs. Data input functions are always enabled, i.e. data at the bus pins

will be stored on every LOW-to-HIGH transition of the clock inputs.

DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE

FollowingConditionsApplyUnlessOtherwiseSpecified:

Operating Condition: TA = –40°C to +85°C

Symbol

Parameter

Test Conditions

Min.

1.7

Typ.⁽¹⁾

—

Max.

—

Unit

VIH

Input HIGH Voltage Level

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

—

VIL

Input LOW Voltage Level

Input Leakage Current

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

—

0.7

0.8

IIH

IIL

VCC = 3.6V

VI = 0 to 5.5V

—

±5

µA

IOZH

IOZL

High Impedance Output Current

(3-State Output pins)

VCC = 3.6V

VO = 0 to 5.5V

—

±10

IOFF

VIK

Input/Output Power Off Leakage

Clamp Diode Voltage

VCC = 0V, VIN or VO ≤ 5.5V

—

±50

µA

VCC = 2.3V, IIN = –18mA

–0.7

–1.2

Input Hysteresis

VCC = 3.3V

VCC = 3.6V

—

100

—

µA

ICCL

ICCH

ICCZ

Quiescent Power Supply Current

VIN = GND or VCC

3.6 ≤ VIN ≤ 5.5V⁽²⁾

—

500

∆ICC

Quiescent Power Supply Current

Variation

One input at VCC - 0.6V, other inputs at VCC or GND

µA

NOTES:

1. Typical values are at VCC = 3.3V, +25°C ambient.

2. This applies in the disabled state only.

IDT74LVC16652A

3.3VCMOS16-BITBUSREGISTEREDTRANSCEIVER

INDUSTRIALTEMPERATURERANGE

BUS

xCLKBA xSAB

xOEAB xOEBA xCLKAB

xSBA

xOEBA

xCLKBA xSAB

xOEAB

xCLKAB

xSBA

REAL-TIME TRANSFER

BUS A TO B

REAL-TIME TRANSFER

BUS B TO A

BUS

xCLKBA xSAB

xOEBA xCLKAB

xSBA

xCLKBA xSAB

H or L

xOEAB

xOEBA xCLKAB

xOEAB

xSBA

↑

H or L

↑

STORAGE FROM

A, B, OR A AND B

TRANSFER STORED

DATATO AAND/OR B

IDT74LVC16652A

INDUSTRIALTEMPERATURERANGE

3.3VCMOS16-BITBUSREGISTEREDTRANSCEIVER

OUTPUTDRIVECHARACTERISTICS

Symbol

Parameter

TestConditions⁽¹⁾

Min.

VCC – 0.2

Max.

—

Unit

VOH

Output HIGH Voltage

VCC = 2.3V to 3.6V

IOH = – 0.1mA

IOH = – 6mA

IOH = – 12mA

VCC = 2.3V

VCC = 2.7V

VCC = 3V

—

1.7

—

2.2

—

2.4

—

VCC = 3V

IOH = – 24mA

IOL = 0.1mA

IOL = 6mA

2.2

—

VOL

OutputLOWVoltage

VCC = 2.3V to 3.6V

VCC = 2.3V

—

0.2

0.4

0.7

0.4

0.55

—

IOL = 12mA

IOL = 24mA

—

VCC = 2.7V

VCC = 3V

—

NOTE:

1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.

TA = – 40°C to + 85°C.

OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C

Symbol

Parameter

Test Conditions

Typical

Unit

CPD

PowerDissipationCapacitanceperTransceiverOutputsenabled

PowerDissipationCapacitanceperTransceiverOutputsdisabled

CL = 0pF, f = 10Mhz

CPD

IDT74LVC16652A

3.3VCMOS16-BITBUSREGISTEREDTRANSCEIVER

INDUSTRIALTEMPERATURERANGE

SWITCHINGCHARACTERISTICS⁽¹⁾

VCC = 2.7V

Max.

VCC = 3.3V ± 0.3V

Symbol

fMAX

tPLH

tPHL

tPLH

tPHL

tPLH

tPHL

tPZH

tPZL

tPHZ

tPLZ

tSU

Parameter

Min.

150

—

Min.

150

1.4

Max.

—

Unit

MHz

—

PropagationDelay

6.4

6.3

xAx to xBx or xBx to xAx

PropagationDelay

—

3.4

7.3

8.8

6.6

—

2.4

1.9

1.6

1.2

6.4

7.4

6.3

6.2

—

xCLKAB or CLKBA to xAx or xBx

PropagationDelay

xSBA or xSAB to xAx or xBx

OutputEnableTime

xOEAB or xOEBA to xAx or Bx

OutputDisableTime

xOEAB or xOEBA to xAx or Bx

Set-up Time HIGH or LOW

xAx or xBx before xCLKAB↑ or xCLKBA↑

Hold Time HIGH or LOW

xAx or xBx after xCLKAB↑ or xCLKBA↑

Clock Pulse Width HIGH or LOW

OutputSkew⁽²⁾

—

0.2

—

3.3

—

3.3

—

tSK(o)

—

500

NOTES:

1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.

2. Skew between any two outputs of the same package and switching in the same direction.

IDT74LVC16652A

INDUSTRIALTEMPERATURERANGE

3.3VCMOS16-BITBUSREGISTEREDTRANSCEIVER

TESTCIRCUITSANDWAVEFORMS

TESTCONDITIONS

VIH

SAME PHASE

INPUT TRANSITION

Symbol VCC⁽¹⁾=3.3V±0.3V VCC⁽¹⁾=2.7V VCC⁽²⁾=2.5V±0.2V

Unit

tPHL

VLOAD

VIH

2 x Vcc

Vcc

tPLH

VOH

VOL

OUTPUT

2.7

1.5

300

2.7

1.5

300

Vcc / 2

150

tPHL

tPLH

VLZ

VHZ

VIH

OPPOSITE PHASE

INPUT TRANSITION

150

LVC Link

VLOAD

Open

GND

Propagation Delay

VCC

DISABLE

ENABLE

VIH

500Ω

CONTROL

INPUT

VIN

VOUT

Pulse ^{(1, 2)}

tPZL

tPLZ

D.U.T.

Generator

VLOAD/2

V^OL+VLZ

VOL

OUTPUT

NORMALLY

LOW

SWITCH

CLOSED

500Ω

tPHZ

tPZH

VOH

VOH-VHZ

OUTPUT

NORMALLY

HIGH

SWITCH

OPEN

LVC Link

Test Circuit for All Outputs

LVC Link

DEFINITIONS:

CL = Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.

Enable and Disable Times

NOTE:

1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.

NOTES:

1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.

2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.

VIH

SWITCHPOSITION

DATA

INPUT

Test

Switch

V^LOAD

GND

t^SU

VIH

TIMING

INPUT

Open Drain

Disable Low

Enable Low

tREM

ASYNCHRONOUS

CONTROL

Disable High

Enable High

SYNCHRONOUS

CONTROL

All Other Tests

Open

tSU

LVC Link

VIH

Set-up, Hold, and Release Times

INPUT

tPLH1

t^PHL1

V^OH

LOW-HIGH-LOW

VOL

PULSE

OUTPUT 1

tSK (x)

VOH

VOL

HIGH-LOW-HIGH

PULSE

OUTPUT 2

LVC Link

tPLH2

tPHL2

Pulse Width

tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1

LVC Link

Output Skew - tSK(X)

NOTES:

1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.

2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.

IDT74LVC16652A

3.3VCMOS16-BITBUSREGISTEREDTRANSCEIVER

INDUSTRIALTEMPERATURERANGE

ORDERINGINFORMATION

IDT

LVC

XXXX

Bus-Hold

Family Device Type Package

Temp. Range

Shrink Small Outline Package

Thin Shrink Small Outline Package

Thin Very Small Outline Package

16-Bit Bus Registered Transceiver with 5 Volt

Tolerant I/O

652A

Double-Density, ±24mA

Blank No Bus-hold

-40°C to +85°C

CORPORATE HEADQUARTERS

2975StenderWay

Santa Clara, CA 95054

for SALES:

800-345-7015 or 408-727-6116

fax: 408-492-8674

for Tech Support:

logichelp@idt.com

(408) 654-6459

www.idt.com

IDT74LVC16652APF8 [IDT]

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