IDT74LVC16821APF8 [IDT]

Bus Driver, LVC/LCX/Z Series, 2-Func, 10-Bit, True Output, CMOS, PDSO56, TVSOP-56;


型号：	IDT74LVC16821APF8
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Bus Driver, LVC/LCX/Z Series, 2-Func, 10-Bit, True Output, CMOS, PDSO56, TVSOP-56 光电二极管电视
文件：	总6页 (文件大小：68K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT74LVC16821A

3.3VCMOS20-BITD-TYPEFLIP-FLOP,5VOLTTOLERANTI/O

INDUSTRIALTEMPERATURERANGE

3.3V CMOS 20-BIT D-TYPE

IDT74LVC16821A

FLIP-FLOP WITH 3-STATE OUT-

PUTS, 5 VOLT TOLERANT I/O

DESCRIPTION:

FEATURES:

The LVC16821A 20-bit Flip-Flop is built using advanced dual metal

CMOStechnology. Thisdevicecontainstwentynon-invertingD-Typeflip-

flops with 3-State outputs. The device is byte controlled with each byte

functioningidentically, butindependentofeachother. Controlpinscanbe

shorted together to obtain full 20-bit operation.

• Typical tSK(o) (Output Skew) < 250ps

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

machine model (C = 200pF, R = 0)

• VCC = 3.3V ± 0.3V, Normal Range

• VCC = 2.7V to 3.6V, Extended Range

• CMOS power levels (0.4µ W typ. static)

• All inputs, outputs, and I/O are 5V tolerant

• Supports hot insertion

The buffered output-enable (OE) inputs place the 20 outputs in either a

normal logic state (high or low) or a high-impedance state. In the high-

impedancestate,theoutputsneitherloadnordrivethebuslinessignificantly.

The high-impedance state and increased drive provide the capability to

drive bus lines without the need for interface drive or pullup components.

OE inputsdonotaffecttheinternaloperationoftheflip-flops. Olddatacan

be retained or new data can be entered while the outputs are in the high-

impedancestate.

Allpinscanbedrivenfromeither3.3Vor5Vdevices. Thisfeatureallows

the use of this device as a Flip-Flop in a mixed 3.3V/5V supply system.

The LVC16821A has been designed with a ±24mA output driver. This

driver is capable of driving a moderate to heavy load while maintaining

speedperformance.

• Available in SSOP, TSSOP, and TVSOP packages

DRIVE FEATURES:

• High Output Drivers: ±24mA

• Reduced system switching noise

APPLICATIONS:

• 5V and 3.3V mixed voltage systems

• Data communication and telecommunication systems

FUNCTIONALBLOCKDIAGRAM

OE1

OE2

CLK1

CLK2

CLK

O10

D10

TO NINE OTHER CHANNELS (1-9)

TO NINE OTHER CHANNELS (11-19)

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

INDUSTRIAL TEMPERATURE RANGE

FEBRUARY 2000

DSC-4603/1

IDT74LVC16821A

3.3VCMOS20-BITD-TYPEFLIP-FLOP,5VOLTTOLERANTI/O

INDUSTRIALTEMPERATURERANGE

ABSOLUTEMAXIMUMRATINGS⁽¹⁾

PINCONFIGURATION

Symbol

VTERM

TSTG

Description

Terminal Voltage with Respect to GND

Storage Temperature

Max

Unit

–0.5 to +6.5

–65 to +150

–50 to +50

–50

°C

OE1

CLK1

IOUT

DC Output Current

IIK

IOK

Continuous Clamp Current,

VI < 0 or VO < 0

ICC

ISS

Continuous Current through each

VCC or GND

±100

GND

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

VCC

CAPACITANCE (TA = +25°C, F = 1.0MHz)

GND

Symbol

Parameter⁽¹⁾

Conditions

VIN = 0V

VOUT = 0V

VIN = 0V

Typ.

Max. Unit

CIN

Input Capacitance

Output Capacitance

I/O Port Capacitance

4.5

COUT

CI/O

6.5

NOTE:

1. As applicable to the device type.

O10

D10

D11

O11

O12

D12

GND

D13

D14

PINDESCRIPTION

GND

Pin Names

Description

O13

O14

Data Inputs

3-StateOutputs

Clock Input

CLKx

OEx

O15

VCC

O16

D15

VCC

OutputEnableInputs(ActiveLOW)

D16

D17

O17

FUNCTIONTABLE⁽¹⁾

GND

D18

Inputs

Output

O18

O19

CLKx

OEx

D19

↑

CLK2

OE2

↑

O⁽²⁾

H or L

SSOP/ TSSOP/ TVSOP

TOP VIEW

NOTES:

1. H = HIGH Voltage Level

L = LOW Voltage Level

X = Don’t Care

Z = High Impedance

↑ = LOW-to-HIGH transition

2. Output level before LOW-to-HIGH clock transition.

IDT74LVC16821A

3.3VCMOS20-BITD-TYPEFLIP-FLOP,5VOLTTOLERANTI/O

INDUSTRIALTEMPERATURERANGE

DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE

FollowingConditionsApplyUnlessOtherwiseSpecified:

Operating Condition: TA = –40°C to +85°C

Symbol

Parameter

Test Conditions

Min.

1.7

Typ.⁽¹⁾

—

Max.

—

Unit

VIH

Input HIGH Voltage Level

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

—

VIL

Input LOW Voltage Level

Input Leakage Current

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

—

0.7

0.8

IIH

IIL

VCC = 3.6V

VI = 0 to 5.5V

—

±5

µA

IOZH

IOZL

High Impedance Output Current

(3-State Output pins)

VCC = 3.6V

VO = 0 to 5.5V

—

±10

IOFF

VIK

Input/Output Power Off Leakage

Clamp Diode Voltage

VCC = 0V, VIN or VO ≤ 5.5V

—

±50

µA

VCC = 2.3V, IIN = –18mA

–0.7

–1.2

Input Hysteresis

VCC = 3.3V

VCC = 3.6V

—

100

—

µA

ICCL

ICCH

ICCZ

Quiescent Power Supply Current

VIN = GND or VCC

3.6 ≤ VIN ≤ 5.5V⁽²⁾

—

500

∆ICC

Quiescent Power Supply Current

Variation

One input at VCC - 0.6V, other inputs at VCC or GND

µA

NOTES:

1. Typical values are at VCC = 3.3V, +25°C ambient.

2. This applies in the disabled state only.

OUTPUTDRIVECHARACTERISTICS

Symbol

Parameter

TestConditions⁽¹⁾

Min.

VCC – 0.2

Max.

—

Unit

VOH

Output HIGH Voltage

VCC = 2.3V to 3.6V

IOH = – 0.1mA

IOH = – 6mA

IOH = – 12mA

VCC = 2.3V

VCC = 2.7V

VCC = 3V

—

1.7

—

2.2

—

2.4

—

VCC = 3V

IOH = – 24mA

IOL = 0.1mA

IOL = 6mA

2.2

—

VOL

OutputLOWVoltage

VCC = 2.3V to 3.6V

VCC = 2.3V

—

0.2

0.4

0.7

0.4

0.55

—

IOL = 12mA

IOL = 24mA

—

VCC = 2.7V

VCC = 3V

—

NOTE:

1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.

TA = – 40°C to + 85°C.

IDT74LVC16821A

3.3VCMOS20-BITD-TYPEFLIP-FLOP,5VOLTTOLERANTI/O

INDUSTRIALTEMPERATURERANGE

OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C

Symbol

Parameter

Test Conditions

Typical

—

Unit

CPD

PowerDissipationCapacitanceperOutputsenabled

PowerDissipationCapacitanceperOutputsdisabled

CL = 0pF, f = 10Mhz

CPD

—

SWITCHINGCHARACTERISTICS⁽¹⁾

VCC = 2.7V

Max.

VCC = 3.3V ± 0.3V

Symbol

tPLH

tPHL

tPZL

tPZH

tPLZ

tPHZ

tSU

Parameter

Min.

Max.

Unit

PropagationDelay

CLKx to Ox

1.5

6.5

1.5

6.2

OutputEnableTime

OEx to Ox

1.5

6.5

OutputDisableTime

OEx to Ox

Set-up Time HIGH or LOW, Dx to CLK

Hold Time HIGH or LOW, Dx to CLK

Clock Pulse Width

OutputSkew⁽²⁾

2.5

1.5

3.3

—

2.5

1.5

3.3

—

tSK(o)

—

500

NOTES:

1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.

2. Skew between any two outputs of the same package and switching in the same direction.

IDT74LVC16821A

3.3VCMOS20-BITD-TYPEFLIP-FLOP,5VOLTTOLERANTI/O

INDUSTRIALTEMPERATURERANGE

TESTCIRCUITSANDWAVEFORMS

TESTCONDITIONS

VIH

SAME PHASE

INPUT TRANSITION

Symbol VCC⁽¹⁾=3.3V±0.3V VCC⁽¹⁾=2.7V VCC⁽²⁾=2.5V±0.2V

Unit

tPHL

VLOAD

VIH

2 x Vcc

Vcc

tPLH

VOH

VOL

OUTPUT

2.7

1.5

300

2.7

1.5

300

Vcc / 2

150

tPHL

tPLH

VLZ

VHZ

VIH

OPPOSITE PHASE

INPUT TRANSITION

150

LVC Link

VLOAD

Open

GND

Propagation Delay

VCC

DISABLE

ENABLE

VIH

500Ω

CONTROL

INPUT

VIN

VOUT

Pulse ^{(1, 2)}

tPZL

tPLZ

D.U.T.

Generator

VLOAD/2

V^OL+VLZ

VOL

OUTPUT

NORMALLY

LOW

SWITCH

CLOSED

500Ω

tPHZ

tPZH

VOH

VOH-VHZ

OUTPUT

NORMALLY

HIGH

SWITCH

OPEN

LVC Link

Test Circuit for All Outputs

LVC Link

DEFINITIONS:

CL = Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.

Enable and Disable Times

NOTE:

1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.

NOTES:

1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.

2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.

VIH

SWITCHPOSITION

DATA

INPUT

Test

Switch

V^LOAD

GND

t^SU

VIH

TIMING

INPUT

Open Drain

Disable Low

Enable Low

tREM

ASYNCHRONOUS

CONTROL

Disable High

Enable High

SYNCHRONOUS

CONTROL

All Other Tests

Open

tSU

LVC Link

VIH

Set-up, Hold, and Release Times

INPUT

tPLH1

t^PHL1

V^OH

LOW-HIGH-LOW

VOL

PULSE

OUTPUT 1

tSK (x)

VOH

VOL

HIGH-LOW-HIGH

PULSE

OUTPUT 2

LVC Link

tPLH2

tPHL2

Pulse Width

tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1

LVC Link

Output Skew - tSK(X)

NOTES:

1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.

2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.

IDT74LVC16821A

3.3VCMOS20-BITD-TYPEFLIP-FLOP,5VOLTTOLERANTI/O

INDUSTRIALTEMPERATURERANGE

ORDERINGINFORMATION

IDT

LVC

XXXX

Device Type Package

Temp. Range

Bus-Hold

Family

Shrink Small Outline Package

Thin Shrink Small Outline Package

Thin Very Small Outline Package

20-Bit D-Type Flip-Flop with 3-State Outputs,

5V Tolerant I/O

821A

Double-Density, ±24mA

Blank No Bus-hold

74 -40°C to +85°C

CORPORATE HEADQUARTERS

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Santa Clara, CA 95054

for SALES:

800-345-7015 or 408-727-6116

fax: 408-492-8674

for Tech Support:

logichelp@idt.com

(408) 654-6459

www.idt.com

IDT74LVC16821APF8 [IDT]

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