IDT74ALVCH162525PA8 [IDT]
Registered Bus Transceiver, ALVC/VCX/A Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, 0.50 MM PITCH, TSSOP-56;
| 型号： | IDT74ALVCH162525PA8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Registered Bus Transceiver, ALVC/VCX/A Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, 0.50 MM PITCH, TSSOP-56 光电二极管 逻辑集成电路 |
| 文件： | 总7页 (文件大小：132K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V CMOS 18-BIT REGIS-
TERED BUS TRANSCEIVER
IDT74ALVCH162525
WITH 3-STATE OUTPUTS
AND BUS-HOLD
FEATURES:
metal CMOS technology. Data flow in each direction is controlled by
output-enable (OEAB and OEBA) and clock-enable (CLKENAB and
–
–
–
0.5 MICRON CMOS Technology
TypicaltSK(0) (Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
0.635mm pitch SSOP, 0.50mm pitch TSSOP,
and 0.40mm pitch TVSOP packages
CLKENBA) inputs. For the A-to-B data flow, the data flows through a
single register. The B-to-A data can flow through a four-stage pipeline
register path, or through a single register path, depending on the state
of the select (SEL) input. Data is stored in the internal registers on the low-
to-high transition of the clock (CLK) input, provided that the appropriate
CLKEN inputs are low. The A-to-B data transfer is synchronized to the
CLKAB input, and B-to-A data transfer is synchronized with the CLK1BA
and CLK2BA inputs.
–
–
–
–
–
–
–
Extended commercial range of – 40°C to + 85°C
VCC = 3.3V ± 0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
VCC = 2.5V ± 0.2V
CMOS power levels (0.4µW typ. static)
Rail-to-Rail output swing for increased noise margin
The ALVCH162525 has series resistors in the device output structure
ofthe “B”portwhichwillsignificantlyreduce line noise whenusedwithlight
loads. This driver has been designed to drive ±12mA at the designated
threshold levels. The “A” port has a ±24mA driver.
Drive Features for ALVCH162525:
–
–
High Output Drivers: ±24mA (A port)
Balanced Output Drivers: ±12mA (B port)
To ensure the high-impedance state during power up or power down,
OE should be tied to VCC through a pullup resistor; the minimum value
of the resistor is determined by the current-sinking capability of the
driver.
APPLICATIONS:
• 3.3V High Speed Systems
• 3.3V and lower voltage computing systems
The ALVCH162525 has “bus-hold” which retains the inputs’ last state
whenever the input bus goes to a high impedance. This prevents floating
inputs and eliminates the need for pull-up/down resistors.
DESCRIPTION:
This 18-bit registered bus transceiver is built using advanced dual
Functional Block Diagram
55
CLK AB
30
CLK1BA
29
CLK2BA
28
CLKENBA
1
CLKENAB
2
OEAB
27
OEBA
56
SEL
CE
CE
C1
CE
C1
1D
CE
1
0
C1
1D
C1
1D
3
A1
54
1D
B1
CE
C1
1D
1 of 18 Channels
To 17 Other Channels
EXTENDED COMMERCIAL TEMPERATURE RANGE
MARCH1999
1
c
1999 Integrated Device Technology, Inc.
DSC-4220/-
IDT74ALVCH162525
3.3V CMOS 18-BIT REGISTERED BUS TRANSCEIVER
EXTENDED COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATING (1)
PIN CONFIGURATION
Symbol
Description
Terminal Voltage
Max.
Unit
(2)
VTERM
– 0.5 to + 4.6
V
1
2
3
4
5
6
CLKENAB
OEAB
56
55
SEL
CLKAB
B1
with Respect to GND
Terminal Voltage
(3)
VTERM
– 0.5 to
VCC + 0.5
V
with Respect to GND
Storage Temperature
A1
GND
A2
54
53
52
51
50
49
48
TSTG
IOUT
IIK
– 65 to + 150
°C
GND
B2
DC Output Current
– 50 to + 50
± 50
mA
mA
Continuous Clamp Current,
VI < 0 or VI > VCC
Continuous Clamp Current, VO < 0
A3
VCC
A4
B3
7
8
9
IOK
– 50
mA
mA
VCC
ICC
ISS
Continuous Current through
each VCC or GND
±100
B4
A5
B5
NEW16link
NOTES:
A6
10
11
12
B6
47
46
45
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
GND
A7
GND
B7
13
14
A8
A9
B8
44
43
SO56-1
SO56-2
SO56-3
2. V
CC terminals.
B9
3. All terminals except VCC.
15
A10
A11
42
41
40
39
38
37
36
35
34
33
32
31
30
29
B10
B11
16
17
18
CAPACITANCE (TA = +25oC, f = 1.0MHz)
Symbol
A12
GND
A13
B12
Parameter(1)
Conditions
Typ.
Max.
Unit
GND
B13
CIN
Input Capacitance
VIN = 0V
5
7
pF
19
20
A14
B14
COUT
CI/O
Output
Capacitance
I/O Port
VOUT = 0V
VIN = 0V
7
7
9
9
pF
pF
A15
21
22
23
24
25
B15
VCC
A16
VCC
B16
Capacitance
NEW16link
NOTE:
1. As applicable to the device type.
A17
B17
GND
GND
A18
26
27
28
B18
PIN DESCRIPTION
Pin Names
OEBA
CLK1BA
Description
CLKAB
Clock Input for the A to B direction
CLKENBA
CLK2BA
CLK1BA
CLK2BA
Clock Input for the B to A pipeline register
Clock Input for the B to A output register
CLKENBA Clock Enable for the CLK1BA and CLK2BA clocks (Active LOW)
SSOP/
TSSOP/TVSOP
TOP VIEW
CLKENAB
OEAB
OEBA
SEL
Clock Enable for the CLKAB clock (Active LOW)
Output Enable for the B port (Active LOW)
Output Enable for the A port (Active LOW)
Select pin for pipelined/non-pipelined mode in
the B-to-A direction (Active LOW)
A-to-B Data Inputs or B-to-A 3-State Outputs(1)
B-to-A Data Inputs or A-to-B 3-State Outputs(1)
Ax
Bx
NOTE:
1. These pins have “Bus-Hold.” All other pins are standard inputs,
outputs, or I/Os.
c 1998 Integrated Device Technology, Inc.
2
DSC-123456
IDT74ALVCH162525
3.3V CMOS 18-BIT REGISTERED BUS TRANSCEIVER
EXTENDED COMMERCIAL TEMPERATURE RANGE
(1)
FUNCTION TABLES
A-TO-B STORAGE (OEAB = L)
Inputs
Output
Bx
CLKENAB
CLKAB
Ax
(2)
H
X
X
B0
L
L
↑
↑
L
L
H
H
B-TO-A STORAGE (OEBA = L)
Inputs
Output
CLKENBA
CLK2BA
CLK1BA
SEL
Bx
Ax
(2)
H
X
X
X
X
A0
L
↑
↑
↑
↑
X
X
↑
H
H
L
L
L
H
L
L
L
H
(3)
L
L
L
(3)
H
↑
H
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
↑ = LOW-to-HIGHTransition
2. Output level before the indicated steady-state input conditions were es-
tablished
3. Three CLK1BA edges and one CLK2BA edge are needed to propagate
data from B to A when SEL is low.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = – 40°C to +85°C
Symbol
Parameter
Test Conditions
Min.
Typ.(1)
Max.
Unit
VIH
Input HIGH Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
VCC = 3.6V
1.7
—
—
V
2
—
—
—
0.7
VIL
Input LOW Voltage Level
—
—
—
—
—
—
—
—
—
V
—
0.8
IIH
Input HIGH Current
VI = VCC
—
± 5
± 5
± 10
± 10
– 1.2
—
µA
IIL
Input LOW Current
VCC = 3.6V
VI = GND
VO = VCC
VO = GND
—
IOZH
IOZL
VIK
VH
High Impedance Output Current
(3-State Output pins)
Clamp Diode Voltage
Input Hysteresis
VCC = 3.6V
—
µA
µA
V
—
VCC = 2.3V, IIN = – 18mA
VCC = 3.3V
– 0.7
100
0.1
mV
µA
ICCL
ICCH
ICCZ
∆ICC
VCC = 3.6V
VIN = GND or VCC
40
Quiescent Power Supply Current
Quiescent Power Supply
Current Variation
One input at VCC − 0.6V,
other inputs at VCC or GND
—
—
750
µA
NEW16link
NOTE:
1. Typical values are at VCC = 3.3V, +25°C ambient.
3
IDT74ALVCH162525
3.3V CMOS 18-BIT REGISTERED BUS TRANSCEIVER
EXTENDED COMMERCIAL TEMPERATURE RANGE
BUS-HOLD CHARACTERISTICS
Symbol
Parameter(1)
Test Conditions
VI = 2.0V
Min.
Typ.(2)
Max.
Unit
IBHH
Bus-Hold Input Sustain Current
VCC = 3.0V
VCC = 2.3V
VCC = 3.6V
– 75
—
—
µA
IBHL
VI = 0.8V
75
– 45
45
—
—
—
—
—
—
IBHH
IBHL
Bus-Hold Input Sustain Current
Bus-Hold Input Overdrive Current
VI = 1.7V
µA
VI = 0.7V
—
IBHHO
IBHLO
VI = 0 to 3.6V
—
± 500
µA
NEW16link
NOTES:
1. Pins with Bus-hold are identified in the pin description.
2. Typical values are at VCC = 3.3V, +25°C ambient.
OUTPUT DRIVE CHARACTERISTICS (A PORT)
Symbol
Parameter
Output HIGH Voltage
Test Conditions(1)
Min.
Max.
Unit
VOH
VCC = 2.3V to 3.6V
VCC = 2.3V
IOH = – 0.1mA
VCC – 0.2
2
—
—
V
IOH = – 6mA
IOH = – 12mA
VCC = 2.3V
1.7
2.2
2.4
2
—
VCC = 2.7V
—
VCC = 3.0V
—
VCC = 3.0V
IOH = – 24mA
IOL = 0.1mA
IOL = 6mA
—
VOL
Output LOW Voltage
VCC = 2.3V to 3.6V
VCC = 2.3V
—
0.2
0.4
0.7
0.4
0.55
V
—
IOL = 12mA
IOL = 12mA
IOL = 24mA
—
VCC = 2.7V
VCC = 3.0V
—
—
NEW16link
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate VCC range. TA = – 40°C to + 85°C.
OUTPUT DRIVE CHARACTERISTICS (B PORT)
Symbol
Parameter
Output HIGH Voltage
Test Conditions(1)
Min.
Max.
Unit
VOH
VCC = 2.3V to 3.6V
VCC = 2.3V
IOH = – 0.1mA
VCC – 0.2
—
V
IOH = – 4mA
IOH = – 6mA
IOH = – 4mA
IOH = – 8mA
IOH = – 6mA
IOH = – 12mA
IOL = 0.1mA
IOL = 4mA
1.9
1.7
2.2
2
—
—
VCC = 2.7V
VCC = 3.0V
—
—
2.4
2
—
—
VOL
Output LOW Voltage
VCC = 2.3V to 3.6V
VCC = 2.3V
—
—
—
—
—
—
—
0.2
0.4
0.55
0.4
0.6
0.55
0.8
V
IOL = 6mA
VCC = 2.7V
VCC = 3.0V
IOL = 4mA
IOL = 8mA
IOL = 6mA
IOL = 12mA
NEW16link
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate VCC range. TA = – 40°C to + 85°C.
4
IDT74ALVCH162525
3.3V CMOS 18-BIT REGISTERED BUS TRANSCEIVER
EXTENDED COMMERCIAL TEMPERATURE RANGE
o
OPERATING CHARACTERISTICS, T = 25 C
A
VCC = 2.5V ± 0.2V
VCC = 3.3V ± 0.3V
Unit
Symbol
Parameter
Power Dissipation Capacitance
Outputs enabled
Test Conditions
Typical
Typical
CPD
CL = 0pF, f = 10Mhz
—
160
pF
CPD
Power Dissipation Capacitance
Outputs disabled
—
160
pF
(1)
SWITCHING CHARACTERISTICS (A AND B PORTS)
VCC = 2.5V ± 0.2V
VCC = 2.7V
VCC = 3.3V ± 0.3V
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
fMAX
120
—
125
—
—
150
—
MHz
ns
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPZH
tPZL
tPHZ
tPLZ
tPHZ
tPLZ
tSU
Propagation Delay
CLKAB to Bx
1
1
1
1
1
1
5.5
4.5
6.7
6.1
6.3
6.3
5.4
4.4
6.8
6.1
5.4
5.4
1
1
1
1
1
1
4.7
4.2
5.7
5.1
4.9
4.9
Propagation Delay
CLK2BA to Ax
—
—
—
—
—
ns
ns
ns
ns
ns
Output Enable Time
OEAB to Bx
Output Enable Time
OEBA to Ax
Output Disable Time
OEAB to Bx
Output Disable Time
OEBA to Ax
Setup Time, Ax data before CLKAB↑
Setup Time, Bx data before CLK2BA↑
Setup Time, Bx data before CLK1BA↑
Setup Time, SEL before CLK2BA↑
Setup Time, CLKENAB before CLKAB↑
Setup Time, CLKENBA before CLK1BA↑
Setup Time, CLKENBA before CLK2BA↑
Hold Time, Ax data after CLKAB↑
Hold Time, Bx data after CLK2BA↑
Hold Time, Bx data after CLK1BA↑
Hold Time, SEL after CLK2BA↑
1.3
2.1
1.3
3.3
2.1
2.7
2.7
0.7
0.4
0.8
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.3
1.8
1.2
3.3
1.9
2.5
2.5
0.4
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.3
1.7
1.1
3.3
1.6
2.1
2.2
0.9
0.6
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
500
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
tSU
tSU
tSU
tSU
tSU
tSU
tH
tH
tH
0.4
0
tH
0.1
0.3
0.1
0
tH
Hold Time, CLKENAB after CLKAB↑
Hold Time, CLKENBA after CLK1BA↑
Hold Time, CLKENBA after CLK2BA↑
0.1
0
0.3
0
tH
tH
0
0
tW
Pulse Duration, CLK HIGH or LOW
3.2
—
3.2
—
3
(2)
tSK(o) Output Skew
—
NOTES:
1. See test circuits and waveforms. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
5
IDT74ALVCH162525
3.3V CMOS 18-BIT REGISTERED BUS TRANSCEIVER
EXTENDED COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS:
PROPAGATION DELAY
TEST CONDITIONS
Symbol
(1)
(1)
(2)
VCC = 3.3V±0.3V VCC = 2.7V VCC = 2.5V±0.2V
Unit
V
IH
VLOAD
6
6
2 xVcc
Vcc
V
SAME PHASE
INPUT TRANSITION
VT
0V
VIH
VT
2.7
1.5
300
300
50
2.7
1.5
300
300
50
V
V
tPHL
tPLH
VOH
VT
Vcc / 2
150
OUTPUT
VLZ
VHZ
CL
mV
mV
VOL
tPHL
tPLH
150
VIH
VT
0V
OPPOSITE PHASE
INPUT TRANSITION
30
pF
NEW16link
ALVC Link
TEST CIRCUITS FOR ALL OUTPUTS ENABLE AND DISABLE TIMES
VLOAD
DISABLE
VCC
ENABLE
VIH
VT
Open
GND
CONTROL
INPUT
500Ω
0V
tPZL
tPLZ
VIN
VOUT
Pulse(1, 2)
Generator
VLOAD/2
VT
D.U.T.
VLOAD/2
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
VLZ
VOL
500Ω
tPHZ
t
PZH
RT
CL
OUTPUT
NORMALLY
HIGH
VOH
VHZ
SWITCH
OPEN
VT
0V
ALVC Link
DEFINITIONS:
0V
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
ALVC Link
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
SET-UP, HOLD, AND RELEASE TIMES
VIH
DATA
INPUT
SWITCH POSITION
VT
0V
tSU
tH
Test
Switch
VIH
VT
0V
TIMING
INPUT
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
VLOAD
tREM
VIH
VT
0V
ASYNCHRONOUS
CONTROL
GND
Open
VIH
VT
0V
SYNCHRONOUS
CONTROL
tSU
tH
NEW16link
ALVC Link
OUTPUT SKEW - TSK (x)
VIH
VT
0V
INPUT
PULSE WIDTH
tPLH1
tPHL1
VOH
VT
LOW-HIGH-LOW
PULSE
VT
OUTPUT 1
tSK (x)
VOL
tSK (x)
tW
VOH
VT
HIGH-LOW-HIGH
PULSE
VT
OUTPUT 2
VOL
ALVC Link
tPLH2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
tPHL2
ALVC Link
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
6
IDT74ALVCH162525
3.3V CMOS 18-BIT REGISTERED BUS TRANSCEIVER
EXTENDED COMMERCIAL TEMPERATURE RANGE
ORDERINGINFORMATION
ALVC
X
XX
XX
Device Type Package
IDT
XX
XXX
Bus-Hold
Family
Temp. Range
Shrink Small Outline Package (SO56-1)
Thin Shrink Small Outline Package (SO56-2)
Thin Very Small Outline Package (SO56-3)
PV
PA
PF
18-Bit Registered Bus Transceiver with 3-State Outputs
525
162
Double-Density with Resistors, ±12mA (B Port)
±24mA (A Port)
H
Bus-Hold
74
-40°C to +85°C
CORPORATE HEADQUARTERS
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*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
7
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