IDT74ALVCH162601PA8 [IDT]
Registered Bus Transceiver, ALVC/VCX/A Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, 0.50 MM PITCH, TSSOP-56;型号: | IDT74ALVCH162601PA8 |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | Registered Bus Transceiver, ALVC/VCX/A Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, 0.50 MM PITCH, TSSOP-56 光电二极管 输出元件 逻辑集成电路 |
文件: | 总7页 (文件大小:76K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
3.3V CMOS 18-BIT UNIVERSAL IDT74ALVCH162601
BUS TRANSCEIVER WITH
3-STATE OUTPUTS
AND BUS-HOLD
FEATURES:
DESCRIPTION:
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
This 18-bit universal bus transceiver is built using advanced dual metal
CMOStechnology.TheALVCH162601combinesD-typelatchesandD-type
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
flip-flopstoallowdataflowintransparent,latched,clocked,andclock-enabled
modes.
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• VCC = 2.5V ± 0.2V
• CMOS power levels (0.4µ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in SSOP, TSSOP, and TVSOP packages
Dataflowineachdirectioniscontrolledbyoutput-enable(OEABandOEBA),
latch-enable(LEABandLEBA),andclock(CLKABandCLKBA)inputs.The
clockcanbecontrolledbytheclock-enable(CLKENABandCLKENBA)inputs.
ForA-to-Bdataflow,thedeviceoperatesinthetransparentmodewhenLEAB
is high. WhenLEABis low, the Adata is latchedifCLKABis heldata highor
lowlogiclevel. IfLEABislow,thedataisstoredinthelatch/flip-floponthelow-
to-hightransitionofCLKAB.WhenOEABislow,theoutputsareactive.When
OEABishigh,theoutputsareinthehigh-impedancestate.
DataflowforBtoAissimilartothatofAtoBbutusesOEBA,LEBA,CLKBA
andCLKENBA.
DRIVE FEATURES:
• High Output Drivers: ±24mA (A port)
• Balanced Output Drivers: ±12mA (B port)
TheALVCH162601hasseriesresistorsinthedeviceoutputstructureofthe
“B”portwhichwillsignificantlyreducelinenoisewhenusedwithlightloads.This
driverhasbeendesignedtodrive±12mAatthedesignatedthresholdlevels.
The “A” port has a ±24mA driver.
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
The ALVCH162601 has “bus-hold” which retains the inputs’ last state
whenevertheinputgoestoahighimpedance. Thispreventsfloatinginputsand
eliminatestheneedforpull-up/downresistors.
FUNCTIONALBLOCKDIAGRAM
1
OEAB
56
CLKENAB
55
CLKAB
2
LEAB
28
LEBA
30
CLKBA
29
CLKENBA
27
OEBA
CE
3
54
A1
1D
C1
B1
CLK
CE
1D
C1
CLK
TO 17 OTHER CHANNELS
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
MARCH 1999
1
© 1999 Integrated Device Technology, Inc.
DSC-4733/1
IDT74ALVCH162601
3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVERWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
PINCONFIGURATION
Symbol
Description
Max
Unit
V
(2)
VTERM
Terminal Voltage with Respect to GND
–0.5 to +4.6
(3)
1
2
3
4
OEAB
LEAB
A1
CLKENAB
56
55
54
53
52
VTERM
Terminal Voltage with Respect to GND –0.5 to VCC+0.5
V
TSTG
IOUT
IIK
Storage Temperature
DC Output Current
–65 to +150
–50 to +50
±50
° C
mA
mA
CLKAB
B1
Continuous Clamp Current,
VI < 0 or VI > VCC
GND
A2
GND
5
B2
B3
IOK
Continuous Clamp Current, VO < 0
–50
mA
mA
A3
6
51
50
ICC
ISS
Continuous Current through each
VCC or GND
±100
VCC
7
VCC
B4
8
A4
A5
A6
49
48
NOTES:
9
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
B5
10
11
12
13
14
15
47
46
45
44
43
B6
GND
A7
GND
B7
2. VCC terminals.
3. All terminals except VCC.
A8
B8
B9
B
A9
10
A10
A11
A12
42
41
40
39
38
37
36
35
34
33
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol
16
17
18
B11
B12
Parameter(1)
Conditions
VIN = 0V
VOUT = 0V
VIN = 0V
Typ.
Max. Unit
CIN
Input Capacitance
Output Capacitance
I/O Port Capacitance
5
7
7
7
9
9
pF
pF
pF
GND
A13
GND
COUT
CI/O
19
20
21
22
23
24
25
B13
B14
B15
A14
NOTE:
A15
1. As applicable to the device type.
VCC
A16
VCC
B16
B17
FUNCTIONTABLE(1,2)
A17
Inputs
Outputs
GND
A18
32
31
30
29
GND
B18
CLKENAB OEAB
LEAB
X
CLKAB
Ax
Bx
Z
26
27
28
X
X
X
H
H
L
H
L
L
L
L
L
L
L
X
X
X
L
CLKBA
OEBA
LEBA
H
L
CLKENBA
H
X
H
X
X
L
H
SSOP/ TSSOP/ TVSOP
TOP VIEW
L
X
B (3)
0
L
X
B (3)
0
L
↑
L
PINDESCRIPTION
L
L
↑
H
X
H
Pin Names
OEAB
Description
L
L
L or H
B (3)
A-to-BOutputEnableInput(ActiveLOW)
B-to-AOutputEnableInput(ActiveLOW)
A-to-BLatchEnableInput
0
OEBA
NOTES:
1. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA,
CLKBA, and CLKENBA.
2. H = HIGH Voltage Level
LEAB
LEBA
B-to-ALatchEnableInput
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
↑ = LOW-to-HIGH transition
CLKAB
CLKBA
Ax
A-to-B Clock Input
B-to-A Clock Input
A-to-BDataInputsorB-to-A3-StateOutputs(1)
B-to-ADataInputsorA-to-B3-StateOutputs(1)
A-to-B Clock Enable Input (Active LOW)
B-to-A Clock Enable Input (Active LOW)
3. Output level before the indicated steady-state input conditions were established.
Bx
CLKENAB
CLKENBA
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
2
IDT74ALVCH162601
INDUSTRIALTEMPERATURERANGE
3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVERWITH3-STATEOUTPUTS
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
OperatingCondition:TA = –40°C to +85°C
Symbol
Parameter
Test Conditions
Min.
1.7
2
Typ.(1)
—
Max.
—
Unit
VIH
Input HIGH Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
V
—
—
VIL
Input LOW Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
—
—
—
—
0.7
0.8
V
IIH
IIL
Input HIGH Current
VCC = 3.6V
VCC = 3.6V
VCC = 3.6V
VI = VCC
—
—
—
—
—
—
—
±5
±5
µA
µA
µ A
Input LOW Current
VI = GND
VO = VCC
VO = GND
IOZH
IOZL
VIK
VH
High Impedance Output Current
(3-State Output pins)
—
±10
±10
–1.2
—
Clamp Diode Voltage
VCC = 2.3V, IIN = –18mA
VCC = 3.3V
–0.7
V
Input Hysteresis
—
—
100
0.1
—
40
mV
µ A
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = 3.6V
VIN = GND or VCC
∆ICC
Quiescent Power Supply Current
Variation
One input at VCC - 0.6V, other inputs at VCC or GND
—
—
750
µ A
NOTE:
1. Typical values are at VCC = 3.3V, +25°C ambient.
BUS-HOLDCHARACTERISTICS
Symbol
IBHH
Parameter(1)
Test Conditions
VI = 2V
Min.
–75
75
Typ.(2)
—
Max.
—
Unit
Bus-HoldInputSustainCurrent
VCC = 3V
µ A
IBHL
VI = 0.8V
—
—
IBHH
Bus-HoldInputSustainCurrent
Bus-HoldInputOverdrive Current
VCC = 2.3V
VCC = 3.6V
VI = 1.7V
–45
45
—
—
µ A
µ A
IBHL
VI = 0.7V
—
—
IBHHO
VI = 0 to 3.6V
—
—
±500
IBHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3
IDT74ALVCH162601
3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVERWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
OUTPUTDRIVECHARACTERISTICS(APORT)
Symbol
Parameter
TestConditions(1)
Min.
VCC – 0.2
2
Max.
—
Unit
VOH
OutputHIGHVoltage
VCC = 2.3V to 3.6V
IOH = – 0.1mA
IOH = – 6mA
IOH = – 12mA
V
VCC = 2.3V
VCC = 2.3V
VCC = 2.7V
VCC = 3V
—
1.7
—
2.2
—
2.4
—
VCC = 3V
IOH = – 24mA
IOL = 0.1mA
IOL = 6mA
2
—
VOL
OutputLOWVoltage
VCC = 2.3V to 3.6V
VCC = 2.3V
—
0.2
0.4
0.7
0.4
0.55
V
—
IOL = 12mA
IOL = 12mA
IOL = 24mA
—
VCC = 2.7V
VCC = 3V
—
—
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
OUTPUTDRIVECHARACTERISTICS(BPORT)
Symbol
Parameter
TestConditions(1)
Min.
VCC – 0.2
1.9
1.7
2.2
2
Max.
—
Unit
VOH
OutputHIGHVoltage
VCC = 2.3V to 3.6V
IOH = – 0.1mA
IOH = – 4mA
IOH = – 6mA
IOH = – 4mA
IOH = – 8mA
IOH = – 6mA
IOH = – 12mA
IOL = 0.1mA
IOL = 4mA
V
VCC = 2.3V
VCC = 2.7V
VCC = 3V
—
—
—
—
2.4
2
—
—
VOL
OutputLOWVoltage
VCC = 2.3V to 3.6V
VCC = 2.3V
—
0.2
0.4
0.55
0.4
0.6
0.55
0.8
V
—
IOL = 6mA
—
VCC = 2.7V
VCC = 3V
IOL = 4mA
—
IOL = 8mA
—
IOL = 6mA
—
IOL = 12mA
—
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
4
IDT74ALVCH162601
INDUSTRIALTEMPERATURERANGE
3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVERWITH3-STATEOUTPUTS
OPERATING CHARACTERISTICS, TA = 25°C
VCC = 2.5V ± 0.2V
VCC = 3.3V ± 0.3V
Symbol
CPD
Parameter
Test Conditions
Typical
Typical
Unit
PowerDissipationCapacitanceOutputsenabled
PowerDissipationCapacitanceOutputsdisabled
CL = 0pF, f = 10Mhz
41
6
50
6
pF
CPD
SWITCHING CHARACTERISTICS (A AND B PORTS)(1)
VCC = 2.5V ± 0.2V
VCC = 2.7V
VCC = 3.3V ± 0.3V
Symbol
fMAX
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPZH
tPZL
tPZH
tPZL
tPZH
tPZL
tSU
Parameter
Min.
140
1.3
Max.
—
Min.
150
—
Max.
—
Min.
150
1.6
Max.
—
Unit
MHz
ns
PropagationDelay
4.8
5.2
4.5
Ax to Bx
PropagationDelay
1
4.3
5.5
5
—
—
—
—
—
—
—
—
—
4.6
5.9
5.3
6.3
5.8
6.7
6.1
5.3
4.8
1
4.1
5.1
4.7
5.5
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
Bx to Ax
PropagationDelay
1
1.5
1
LEXB to Ax
PropagationDelay
1
LEXB to Bx
PropagationDelay
1.5
1.3
1.6
1.1
1.8
1.3
6.1
5.6
6.1
5.5
5.7
5.2
1.6
1.4
1.6
1.1
1.8
1.8
CLKAB to Bx
PropagationDelay
CLKBA to Ax
OutputEnableTime
5.7
5.2
4.8
4.4
OEAB to Bx
OutputEnableTime
OEBA to Ax
OutputDisableTime
OEAB to Bx
OutputDisableTime
OEBA to Ax
Set-upTime,databeforeCLK↑
Set-up Time, data before LE↓, CLK HIGH
Set-upTime, data before LE↓,CLKLOW
Set-upTime,CLKENbeforeCLK↑
HoldTime,dataafterCLK↑
Hold Time, data after LE↓, CLK HIGH
Hold Time, data after LE↓, CLK LOW
Hold Time, CLKEN after CLK↑
Pulse Width, LE HIGH
Pulse Width, CLK HIGH or LOW
2.3
2
—
—
—
—
—
—
—
—
—
—
—
2.4
1.6
1.2
2
—
—
—
—
—
—
—
—
—
—
—
2.1
1.6
1.1
1.7
0.8
1.4
1.7
0.6
3.3
3.3
—
—
—
—
—
—
—
—
—
—
—
500
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
tSU
tSU
1.3
2
tSU
tH
0.7
1.3
1.7
0.3
3.3
3.3
—
0.7
1.6
2
tH
tH
tH
0.5
3.3
3.3
—
tW
tW
(2)
tSK(O)
OutputSkew
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
5
IDT74ALVCH162601
3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVERWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
TESTCIRCUITSANDWAVEFORMS
TESTCONDITIONS
VIH
VT
SAME PHASE
INPUT TRANSITION
0V
tPHL
tPLH
Symbol VCC(1)=3.3V±0.3V VCC(1)=2.7V VCC(2)=2.5V±0.2V Unit
VOH
VT
OUTPUT
VLOAD
VIH
6
6
2 x Vcc
Vcc
V
V
VOL
2.7
1.5
300
300
50
2.7
1.5
300
300
50
tPHL
tPLH
VIH
VT
0V
VT
Vcc / 2
150
V
OPPOSITE PHASE
INPUT TRANSITION
VLZ
VHZ
CL
mV
mV
pF
150
ALVC Link
30
Propagation Delay
VLOAD
Open
GND
DISABLE
VCC
ENABLE
VIH
VT
CONTROL
INPUT
500Ω
0V
tPZL
tPLZ
VIN
VOUT
Pulse(1, 2)
Generator
VLOAD/2
D.U.T.
VLOAD/2
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
VT
VLZ
VOL
500Ω
tPHZ
tPZH
RT
CL
OUTPUT
NORMALLY
HIGH
VOH
VHZ
SWITCH
OPEN
VT
0V
ALVC Link
0V
Test Circuit for All Outputs
ALVC Link
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Enable and Disable Times
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
NOTES:
VIH
VT
0V
1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns.
DATA
INPUT
tSU
tH
VIH
VT
0V
TIMING
INPUT
SWITCHPOSITION
Test
Switch
VLOAD
GND
Open
tREM
VIH
VT
0V
ASYNCHRONOUS
CONTROL
Open Drain
Disable Low
Enable Low
VIH
VT
0V
SYNCHRONOUS
CONTROL
Disable High
Enable High
tSU
tH
ALVC Link
All Other Tests
VIH
Set-up, Hold, and Release Times
VT
0V
INPUT
tPLH1
tPHL1
VOH
VT
LOW-HIGH-LOW
VT
PULSE
OUTPUT 1
OUTPUT 2
VOL
tSK (x)
tSK (x)
tW
VOH
VT
HIGH-LOW-HIGH
PULSE
VT
VOL
ALVC Link
tPLH2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
tPHL2
Pulse Width
ALVC Link
Output Skew - tSK(X)
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
6
IDT74ALVCH162601
INDUSTRIALTEMPERATURERANGE
3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVERWITH3-STATEOUTPUTS
ORDERINGINFORMATION
XX
X
XX
IDT
ALVC
XXX
XX
Bus-Hold
Family Device Type Package
Temp. Range
Shrink Small Outline Package
Thin Shrink Small Outline Package
Thin Very Small Outline Package
PV
PA
PF
18-Bit Universal Bus Transceiver with 3-State Outputs
601
162
Double-Density with Resistors, ±24mA (A port)
±12mA (B port)
H
Bus-Hold
-40°C to +85°C
74
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7
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