IDT74ALVCH16244 [IDT]
3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS AND BUS-HOLD; 3.3V CMOS 16位缓冲器/驱动器，具有三态输出和总线HOLD
| 型号： | IDT74ALVCH16244 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS AND BUS-HOLD |
| 文件： | 总6页 (文件大小：70K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V CMOS 16-BIT
IDT74ALVCH16244
BUFFER/DRIVER WITH
3-STATE OUTPUTS
AND BUS-HOLD
FEATURES:
DESCRIPTION:
• 0.5 MICRON CMOS Technology
This16-bitbuffer/driverisbuiltusingadvanceddualmetalCMOStechnol-
ogy.TheALVCH16244isdesignedspecificallytoimprovetheperformance
and density of 3-state memory address drivers, clock drivers, and bus-
oriented receivers and transmitters. The device can be used as four 4-bit
buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and
symmetricalactive-lowoutput-enable(OE)inputs.
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• VCC = 2.5V ± 0.2V
• CMOS power levels (0.4µ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in SSOP, TSSOP, and TVSOP packages
The ALVCH16244 has been designed with a ±24mA output driver. This
driveriscapableofdrivingamoderatetoheavyloadwhilemaintainingspeed
performance.
The ALVCH16244 has “bus-hold” which retains the inputs’ last state
whenevertheinputbusgoestoahighimpedance. Thispreventsfloatinginputs
andeliminatestheneedforpull-up/downresistors.
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Suitable for heavy loads
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
FUNCTIONALBLOCKDIAGRAM
25
1
1OE
3OE
13
36
47
2
3
5
1A1
3A1
1Y1
1Y2
1Y3
1Y4
3Y1
3Y2
3Y3
3Y4
35
33
32
46
44
14
16
1A2
1A3
3A2
3A3
3A4
43
6
17
1A4
24
48
2OE
2A1
4OE
4A1
30
29
27
26
41
40
38
8
9
19
20
22
23
2Y1
2Y2
2Y3
2Y4
4Y1
4Y2
4Y3
4Y4
2A2
2A3
4A2
4A3
11
12
37
2A4
4A4
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
MARCH 1999
1
© 1999 Integrated Device Technology, Inc.
DSC-4561/1
IDT74ALVCH16244
3.3VCMOS16-BITBUFFER/DRIVERWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
PINCONFIGURATION
Symbol
Description
Max
Unit
V
(2)
VTERM
Terminal Voltage with Respect to GND
–0.5 to +4.6
(3)
VTERM
Terminal Voltage with Respect to GND –0.5 to VCC+0.5
V
1OE
1Y1
1
48
47
46
45
2OE
1A1
TSTG
IOUT
IIK
Storage Temperature
DC Output Current
–65 to +150
–50 to +50
±50
°C
mA
mA
2
Continuous Clamp Current,
VI < 0 or VI > VCC
3
1Y2
1A2
GND
1Y3
4
GND
1A3
IOK
Continuous Clamp Current, VO < 0
–50
mA
mA
5
ICC
ISS
Continuous Current through each
VCC or GND
±100
44
43
42
41
40
1Y4
6
1A4
NOTES:
VCC
2Y1
7
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
VCC
2A1
8
2Y2
9
2A2
2. VCC terminals.
3. All terminals except VCC.
GND
2Y3
10
11
12
13
14
39
38
37
36
35
34
33
GND
2A3
2Y4
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol
2A4
3Y1
Parameter(1)
Conditions
VIN = 0V
VOUT = 0V
VIN = 0V
Typ.
Max. Unit
3A1
CIN
Input Capacitance
Output Capacitance
I/O Port Capacitance
5
7
7
7
9
9
pF
pF
pF
3Y2
GND
3Y3
3A2
GND
3A3
3A4
VCC
4A1
4A2
COUT
CI/O
15
16
17
NOTE:
1. As applicable to the device type.
3Y4
32
31
VCC
4Y1
18
19
20
21
22
PINDESCRIPTION
Pin Names
30
29
28
27
26
25
Description
4Y2
xOE
xAx
xYx
3-State Output Enable Inputs (Active LOW)
Data Inputs(1)
GND
4Y3
GND
4A3
3-State Outputs
NOTE:
4Y4
23
24
4A4
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
4OE
3OE
(1)
FUNCTION TABLE (EACH 4-BIT BUFFER)
SSOP/ TSSOP/ TVSOP
TOP VIEW
Inputs
Outputs
xOE
L
xAx
H
xYx
H
L
L
L
H
X
Z
NOTE:
1. H = HIGH Voltage Level
X = Don’t Care
L = LOW Voltage Level
Z = High-Impedance
2
IDT74ALVCH16244
INDUSTRIALTEMPERATURERANGE
3.3VCMOS16-BITBUFFER/DRIVERWITH3-STATEOUTPUTS
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = –40°C to +85°C
Symbol
Parameter
Test Conditions
Min.
1.7
2
Typ.(1)
—
Max.
—
Unit
VIH
Input HIGH Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
V
—
—
VIL
Input LOW Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
—
—
—
—
0.7
0.8
V
IIH
IIL
Input HIGH Current
VCC = 3.6V
VCC = 3.6V
VCC = 3.6V
VI = VCC
—
—
—
—
—
—
—
±5
±5
µA
µA
µA
Input LOW Current
VI = GND
VO = VCC
VO = GND
IOZH
IOZL
VIK
VH
High Impedance Output Current
(3-State Output pins)
—
±10
±10
–1.2
—
Clamp Diode Voltage
VCC = 2.3V, IIN = –18mA
VCC = 3.3V
–0.7
V
Input Hysteresis
—
—
100
0.1
—
40
mV
µA
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = 3.6V
VIN = GND or VCC
∆ICC
Quiescent Power Supply Current
Variation
One input at VCC - 0.6V, other inputs at VCC or GND
—
—
750
µA
NOTE:
1. Typical values are at VCC = 3.3V, +25°C ambient.
BUS-HOLDCHARACTERISTICS
Symbol
IBHH
Parameter(1)
Test Conditions
VI = 2V
Min.
–75
75
Typ.(2)
—
Max.
—
Unit
Bus-HoldInputSustainCurrent
VCC = 3V
µA
IBHL
VI = 0.8V
—
—
IBHH
Bus-HoldInputSustainCurrent
Bus-Hold Input Overdrive Current
VCC = 2.3V
VCC = 3.6V
VI = 1.7V
–45
45
—
—
µA
µA
IBHL
VI = 0.7V
—
—
IBHHO
VI = 0 to 3.6V
—
—
±500
IBHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3
IDT74ALVCH16244
3.3VCMOS16-BITBUFFER/DRIVERWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
OUTPUTDRIVECHARACTERISTICS
Symbol
Parameter
TestConditions(1)
Min.
Max.
—
Unit
VOH
Output HIGH Voltage
VCC = 2.3V to 3.6V
IOH = – 0.1mA
IOH = – 6mA
IOH = – 12mA
VCC – 0.2
V
VCC = 2.3V
VCC = 2.3V
VCC = 2.7V
VCC = 3V
2
1.7
2.2
2.4
2
—
—
—
—
VCC = 3V
IOH = – 24mA
IOL = 0.1mA
IOL = 6mA
—
VOL
OutputLOWVoltage
VCC = 2.3V to 3.6V
VCC = 2.3V
—
—
—
—
—
0.2
0.4
0.7
0.4
0.55
V
IOL = 12mA
IOL = 12mA
IOL = 24mA
VCC = 2.7V
VCC = 3V
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
OPERATING CHARACTERISTICS, TA = 25°C
VCC = 2.5V ± 0.2V
VCC = 3.3V ± 0.3V
Symbol
CPD
Parameter
Test Conditions
Typical
Typical
Unit
PowerDissipationCapacitanceOutputsenabled
PowerDissipationCapacitanceOutputsdisabled
CL = 0pF, f = 10Mhz
16
4
19
5
pF
CPD
SWITCHINGCHARACTERISTICS(1)
VCC = 2.5V ± 0.2V
Min. Max.
3.7
VCC = 2.7V
VCC = 3.3V ± 0.3V
Symbol
tPLH
Parameter
Min.
Max.
Min.
Max.
Unit
PropagationDelay
xAx to xYx
1
—
3.6
1
3
ns
ns
ns
ps
tPHL
tPZH
OutputEnableTime
xOE to xYx
1
1
5.7
5.2
—
—
—
—
5.4
4.6
—
1
1
4.4
4.1
500
tPZL
tPHZ
OutputDisableTime
tPLZ
xOE to xYx
OutputSkew(2)
tSK(o)
—
—
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
4
IDT74ALVCH16244
INDUSTRIALTEMPERATURERANGE
3.3VCMOS16-BITBUFFER/DRIVERWITH3-STATEOUTPUTS
TESTCIRCUITSANDWAVEFORMS
TESTCONDITIONS
VIH
VT
SAME PHASE
INPUT TRANSITION
0V
tPHL
tPHL
tPLH
tPLH
Symbol VCC(1)=3.3V±0.3V VCC(1)=2.7V VCC(2)=2.5V±0.2V
Unit
VOH
VT
OUTPUT
VLOAD
VIH
6
6
2 x Vcc
Vcc
V
V
VOL
2.7
1.5
300
300
50
2.7
1.5
300
300
50
VIH
VT
0V
VT
Vcc / 2
150
V
OPPOSITE PHASE
INPUT TRANSITION
VLZ
VHZ
CL
mV
mV
pF
150
ALVC Link
30
Propagation Delay
VLOAD
Open
GND
DISABLE
VCC
ENABLE
VIH
VT
CONTROL
INPUT
500Ω
0V
tPZL
tPLZ
VIN
VOUT
Pulse(1, 2)
Generator
VLOAD/2
D.U.T.
VLOAD/2
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
VT
VLZ
VOL
500Ω
tPHZ
tPZH
RT
CL
OUTPUT
NORMALLY
HIGH
VOH
VHZ
SWITCH
OPEN
VT
0V
ALVC Link
0V
Test Circuit for All Outputs
ALVC Link
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Enable and Disable Times
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
NOTES:
VIH
VT
0V
1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns.
DATA
INPUT
tSU
tH
VIH
VT
0V
TIMING
INPUT
SWITCHPOSITION
Test
Switch
VLOAD
GND
tREM
VIH
VT
0V
ASYNCHRONOUS
CONTROL
Open Drain
Disable Low
Enable Low
VIH
VT
0V
SYNCHRONOUS
CONTROL
Disable High
Enable High
tSU
tH
ALVC Link
All Other Tests
Open
VIH
Set-up, Hold, and Release Times
VT
0V
INPUT
tPLH1
tPHL1
VOH
VT
LOW-HIGH-LOW
VT
PULSE
OUTPUT 1
OUTPUT 2
VOL
tSK (x)
tSK (x)
tW
VOH
VT
HIGH-LOW-HIGH
PULSE
VT
VOL
ALVC Link
tPLH2
tPHL2
Pulse Width
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
ALVC Link
Output Skew - tSK(X)
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
IDT74ALVCH16244
3.3VCMOS16-BITBUFFER/DRIVERWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
IDT
XX
ALVC
Bus-Hold Family
XXX
XX
X
XX
Device Type Package
Temp. Range
Shrink Small Outline Package
Thin Shrink Small Outline Package
Thin Very Small Outline Package
PV
PA
PF
16-Bit Buffer/Driver with 3-State Outputs
244
16
Double-Density, ±24mA
H
Bus-Hold
74
-40°C to +85°C
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logichelp@idt.com
(408) 654-6459
www.idt.com
6
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