IDT72V3612L20PF [IDT]
3.3 VOLT CMOS SyncBiFIFO-TM 64 x 36 x 2; 3.3伏的CMOS SyncBiFIFO -TM 64 ×36× 2
| 型号： | IDT72V3612L20PF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 3.3 VOLT CMOS SyncBiFIFO-TM 64 x 36 x 2 |
| 文件： | 总25页 (文件大小：230K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3 VOLT CMOS SyncBiFIFOTM
64 x 36 x 2
IDT72V3612
• Passive parity checking on each port
FEATURES:
• Parity generation can be selected for each port
• Available in 132-pin plastic quad flat package (PQF), or space
saving 120-pin thin quad flat package (TQFP)
• Pin and functionally compatible version of the 5V operating
IDT723612
• Two independent clocked FIFOs (64 x 36 storage capacity each)
buffering data in opposite directions
• Supports clock frequencies up to 83 MHz
• Fast access times of 8ns
• Free-running CLKA and CLKB can be asynchronous or
coincident (simultaneous reading and writing of data on a
single clock edge is permitted)
• Mailbox bypass Register for each FIFO
• Programmable Almost-Full and Almost-Empty Flags
• Microprocessor interface control logic
• Industrial temperature range (–40°C +85°C) is available
DESCRIPTION:
The IDT72V3612 is a pin and functionally compatible version of the
IDT723612, designed to run off a 3.3V supply for exceptionally low-power
consumption. This device is a monolithichigh-speed, low-powerCMOSbi-
directionalclockedFIFOmemory. Itsupportsclockfrequenciesupto83MHz
• EFA , FFA , AEA , and AFA flags synchronized by CLKA
• EFB , FFB , AEB , and AFB flags synchronized by CLKB
FUNCTIONAL BLOCK DIAGRAM
CLKA
CSA
W/RA
ENA
Port-A
Control
Logic
MBF1
PEFB
MBA
Parity
Gen/Check
Mail 1
Register
PGB
RAM
ARRAY
64 x 36
36
RST
Device
Control
ODD/
EVEN
Read
Pointer
Write
Pointer
EFB
AEB
Status Flag
Logic
FFA
AFA
FIFO1
36
FS0
FS1
Programmable Flag
Offset Register
B0 - B36
A
0
- A35
FIFO2
FFB
AFB
EFA
AEA
Status Flag
Logic
Write
Pointer
Read
Pointer
36
RAM
ARRAY
64 x 36
PGA
Mail 2
Register
Parity
Gen/Check
PEFA
MBF2
CLKB
Port-B
Control
Logic
CSB
W/RB
ENB
MBB
4659 drw 01
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.SyncBiFIFOisatrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIAL TEMPERATURE RANGE
MAY 2003
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4659/1
IDT72V36123.3V,CMOSSyncBiFIFOTM
64 x 36 x 2
COMMERCIALTEMPERATURERANGE
andhasreadaccesstimesasfastas8ns. TheFIFOoperatesinIDTStandard each port are independent of one another and can be asynchronous or
mode. Two independent 64 x 36 dual-port SRAM FIFOs on board the chip coincident. The enables for each port are arranged to provide a simple bi-
bufferdatainoppositedirections. EachFIFOhasflagstoindicateemptyand directional interface between microprocessors and/or buses with synchro-
fullconditionsandtwoprogrammableflags(Almost-FullandAlmost-Empty)to nous control.
indicatewhenaselectednumberofwordsisstoredinmemory. Communication
The Full Flag (FFA, FFB) and Almost-Full (AFA, AFB) flag of a FIFO
betweeneachportcanbypasstheFIFOsviatwo36-bitmailboxregisters. Each are two-stage synchronizedtothe portclockthatwrites data toits array.
mailboxregisterhasaflagtosignalwhennewmailhasbeenstored. Parityis The Empty Flag (EFA, EFB) and Almost-Empty (AEA, AEB) flag of a
checked passively on each port and may be ignored if not desired. Parity FIFO are two stage synchronized to the port clock that reads data from
generationcanbeselectedfordatareadfromeachport. Twoormoredevices its array.
can be used in parallel to create wider data paths.
The IDT72V3612 is characterized for operation from 0
°C to 70°C.
This device is a clocked FIFO, which means each port employs a Industrialtemperaturerange(–40
°
Cto+85 C)isavailablebyspecialorder.
°
synchronous interface. All data transfers through a port are gated to the This device is fabricated using IDT's high speed, submicron CMOS
LOW-to-HIGH transition of a port clock by enable signals. The clocks for technology.
PIN CONFIGURATIONS
GND
AEA
EFA
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
GND
AEB
EFB
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
A0
B0
*
A
1
B
1
A
2
B
2
GND
GND
A
3
B
3
A
4
B
4
A
5
B
5
A
6
CC
B
6
V
VCC
A
7
B
7
A
8
B
8
A
9
B
9
GND
GND
A
10
11
B
B
V
B
B
B
10
11
CC
12
13
14
A
V
CC
98
A
12
13
14
97
A
96
A
GND
95
GND
94
A
A
A
A
A
A
15
16
17
18
19
20
B
B
B
B
B
B
15
16
17
18
19
20
93
92
91
90
89
88
GND
GND
87
A21
A22
A23
B21
B22
B23
86
85
84
4659 drw 02
*
Electricalpin1incenterofbevelededge.Pin1identifierincorner.
NOTES:
1. NC - No internal connection
2. Uses Yamaichi socket IC51-1324-828
PQFP(2) (PQ132-1, order code: PQF)
TOP VIEW
2
IDT72V36123.3V,CMOSSyncBiFIFOTM
64 x 36 x 2
COMMERCIALTEMPERATURERANGE
PINCONFIGURATIONS(CONTINUED)
A23
A22
A21
GND
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
GND
A9
B22
90
1
B21
89
2
GND
88
3
B20
87
4
B19
86
5
B18
85
6
B17
84
7
B16
83
8
B15
82
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
B14
81
B13
B12
B11
B10
GND
B9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
B8
A8
B7
A7
VCC
B6
VCC
A6
B5
A5
B4
A4
B3
A3
GND
B2
GND
A2
B1
B0
A1
A0
EFB
AEB
AFB
EFA
AEA
4659 drw 03
NOTE:
1. NC - No internal connection
TQFP (PN120-1, order code: PF)
TOP VIEW
3
IDT72V36123.3V,CMOSSyncBiFIFOTM
64 x 36 x 2
COMMERCIALTEMPERATURERANGE
PIN DESCRIPTION
Symbol
A0-A35
AEA
Name
PortAData
I/O
I/O
O
Description
36-bitbidirectionaldataportforsideA.
PortAAlmost-Empty
Flag
ProgrammableAlmost-EmptyflagsynchronizedtoCLKA. ItisLOWwhenthenumberofwordsin
(Port A) the FIFO2is less thanorequaltothe value inthe offsetregister, X.
ProgrammableAlmost-EmptyflagsynchronizedtoCLKB. ItisLOWwhenthenumberofwordsin
(PortB) FIFO1 is less than or equal to the value in the offset register, X.
Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty
(Port A) locations in FIFO1 is less than or equal to the value in the offset register, X.
Programmable Almost-Full flag synchronized to CLKB. It is LOW when the number of empty
(Port B) locations in FIFO2 is less than or equal to the value in the offset register, X.
AEB
AFA
AFB
PortBAlmost-Empty
Flag
O
Port A Almost-Full
Flag
O
Port B Almost-Full
Flag
O
B0-B35
CLKA
Port B Data.
Port A Clock
I/O
I
36-bit bidirectional data port for side B.
CLKA is a continuous clock that synchronizes all data transfers through port A and can be
asynchronous or coincident to CLKB. EFA, FFA, AFA, and AEA are synchronized to the LOW-to-
HIGH transition of CLKA.
CLKB
Port B Clock
I
CLKB is a continuous clock that synchronizes all data transfers through port B and can be
asynchronous or coincident to CLKA. EFB, FFB, AFB, and AEB are synchronized to the LOW-to-
HIGH transition of CLKB.
CSA
CSB
EFA
Port A Chip Select
Port B Chip Select
Port A Empty Flag
I
I
CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write data on port A.
The A0-A35 outputs are in the high-impedance state when CSA is HIGH.
CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port B.
The B0-B35 outputs are in the high-impedance state when CSB is HIGH.
O
EFA is synchronized to the LOW-to-HIGH transition of CLKA. When EFA is LOW, FIFO2 is empty,
(Port A) and reads from its memory are disabled. Data can be read from FIFO2 to the output register
when EFA is HIGH. EFA is forced LOW when the device is reset and is set HIGH by the second
LOW-to-HIGH transition of CLKA after data is loaded into empty FIFO2 memory.
EFB
Port B Empty Flag
O
EFB is synchronized to the LOW-to-HIGH transition of CLKB. When EFB is LOW, the FIFO1 is
(Port B) empty, and reads from its memory are disabled. Data can be read from FIFO1 to the output
register when EFB is HIGH. EFB is forced LOW when the device is reset and is set HIGH by the
second LOW-to-HIGH transition of CLKB after data is loaded into empty FIFO1 memory.
ENA
ENB
FFA
Port A Enable
Port B Enable
Port A Full Flag
I
I
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port A.
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port B.
FFA is synchronized to the LOW-to-HIGH transition of CLKA. When FFA is LOW, FIFO1 is full,
O
(Port A) and writes to its memory are disabled. FFA is forced LOW when the device is reset and is set
HIGH by the second LOW-to-HIGH transition of CLKA after reset.
FFB
Port B Full Flag
O
FFB is synchronized to the LOW-to-HIGH transition of CLKB. When FFB is LOW, FIFO2 is full,
(Port B) and writes to its memory are disabled. FFB is forced LOW when the device is reset and is set
HIGH by the second LOW-to-HIGH transition of CLKB after reset.
FS1, FS0 Flag Offset Selects
I
I
The LOW-to-HIGH transition of RST latches the values of FS0 and FS1, which selects one of four
preset values for the Almost-Full flag and Almost-Empty flag.
MBA
MBB
MBF1
Port A Mailbox
Select
A HIGH level on MBA chooses a mailbox register for a port A read or write operation. When the
A0-A35 outputs are active, a HIGH level on MBA selects data from the mail2 register for output,
and a LOW level selects FIFO2 output register data for output.
Port B Mailbox
Select
I
A HIGH level on MBB chooses a mailbox register for a port B read or write operation. When the
B0-B35 outputs are active, a HIGH level on MBB selects data from the mail1 register for output,
and a LOW level selects FIFO1 output register data for output.
Mail1 Register Flag
O
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register.
Writes to the mail1 register are inhibited while MBF1 is set LOW. MBF1 is set HIGH by a LOW-to-
HIGH transition of CLKB when a port B read is selected and MBB is HIGH. MBF1 is set HIGH
when the device is reset.
4
IDT72V36123.3V,CMOSSyncBiFIFOTM
64 x 36 x 2
COMMERCIALTEMPERATURERANGE
PINDESCRIPTION(CONTINUED)
Symbol
Name
I/O
Description
MBF2
Mail2 Register Flag
O
MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register.
Writes to the mail2 register are inhibited while MBF2 is set LOW. MBF2 is set HIGH by a LOW-to-
HIGH transition of CLKA when a port A read is selected and MBA is HIGH. MBF2 is set HIGH
when the device is reset.
ODD/
EVEN
Odd/Even Parity
Select
I
Odd parity is checked on each port when ODD/EVEN is HIGH, and even parity is checked when
ODD/EVEN is LOW. ODD/EVEN also selects the type of parity generated for each port if parity
generation is enabled for a read operation.
PEFA
Port A Parity Error
Flag
O
When any byte applied to terminals A0-A35 fails parity, PEFA is LOW. Bytes are organized as
(Port A) A0-A8, A9-A17, A18-A26, and A27-A35, with the most significant bit of each byte serving as the
parity bit. The type of parity checked is determined by the state of the ODD/EVEN input. The
parity trees used to check the A0-A35 inputs are shared by the mail2 register to generate parity if
parity generation is selected by PGA. Therefore, if a mail2 read with parity generation is setup by
having W/RA LOW, MBA HIGH, and PGA HIGH, the PEFA flag is forced HIGH regardless of the
A0-A35 inputs.
PEFB
Port B Parity Error
Flag
O
When any byte applied to terminals B0-B35 fails parity, PEFB is LOW. Bytes are organized as
(Port B) B0-B8, B9-B17, B18-B26, B27-B35 with the most significant bit of each byte serving as the parity
bit. The type of parity checked is determined by the state of the ODD/EVEN input. The parity trees
used to check the B0-B35 inputs are shared by the mail1 register to generate parity if parity
generation is selected by PGB. Therefore, if a mail1 read with parity generation is setup by having
W/RB LOW, MBB HIGH, and PGB HIGH, the PEFB flag is forced HIGH regardless of the state of
the B0-B35 inputs.
PGA
PGB
RST
Port A Parity
Generation
I
I
I
Parity is generated for data reads from port A when PGA is HIGH. The type of parity generated is
selected by the state of the ODD/EVEN input. Bytes are organized as A0-A8, A9-A17, A18-A26,
and A27-A35. The generated parity bits are output in the most significant bit of each byte.
Port B Parity
Generation
Parity is generated for data reads from port B when PGB is HIGH. The type of parity generated is
selected by the state of the ODD/EVEN input. Bytes are organized as B0-B8, B9-B17, B18-B26,
and B27-B35. The generated parity bits are output in the most significant bit of each byte.
Reset
To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of
CLKB must occur while RST is LOW. This sets the AFA, AFB, MBF1, and MBF2 flags HIGH and
the EFA, EFB, AEA, AEB, FFA, and FFB flags LOW. The LOW-to-HIGH transition of RST latches
the status of the FS1 and FS0 inputs to select Almost-Full and Almost-Empty flag offset.
W/RA
W/RB
Port A Write/Read
Select
I
I
A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-
HIGH transition of CLKA. The A0-A35 outputs are in the high-impedance state when W/RA is
HIGH.
Port B Write/Read
Select
A HIGH selects a write operation and a LOW selects a read operation on port B for a LOW-to-
HIGH transition of CLKB. The B0-B35 outputs are in the high-impedance state when W/RB is
HIGH.
5
IDT72V36123.3V,CMOSSyncBiFIFOTM
64 x 36 x 2
COMMERCIALTEMPERATURERANGE
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR
TEMPERATURE RANGE (Unless otherwise noted)(2)
Symbol
Rating
Commercial
–0.5 to +4.6
–0.5 to VCC+0.5
–0.5 to VCC+0.5
±20
Unit
V
VCC
Supply Voltage Range
Input Voltage Range
Output Voltage Range
(2)
VI
V
(2)
VO
V
IIK
Input Clamp Current, (VI < 0 or VI > VCC)
Output Clamp Current, (VO < 0 or VO > VCC)
Continuous Output Current, (VO = 0 to VCC)
Continuous Current Through VCC or GND
Storage Temperature Range
mA
mA
mA
mA
IOK
±50
IOUT
ICC
±50
±500
TSTG
–65 to 150
°C
NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at
these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended
periods may affect device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
RECOMMENDED OPERATING
CONDITIONS
Symbol
Parameter
SupplyVoltage
Min. Typ.
Max.
3.6
Unit
V
(1)
VCC
3.0 3.3
VIH
VIL
IOH
IOL
TA
HIGH Level Input Voltage
LOW-LevelInputVoltage
HIGH-LevelOutputCurrent
LOW-LevelOutputCurrent
2
—
—
—
—
—
VCC+0.5
0.8
V
—
—
—
0
V
–4
mA
mA
8
OperatingFree-air
Temperature
70
°C
NOTE:
1. For 12ns (83MHz operation), Vcc=3.3V +/-0.15V, JEDEC JESD8-A compliant
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-
AIR TEMPERATURE RANGE (Unless otherwise noted)
IDT72V3612
Commercial
tCLK = 12, 15, 20 ns
Symbol
VOH
VOL
Parameter
OutputLogic"1"Voltage
Test Conditions
IOH = –4 mA
IOL = 8 mA
Min. Typ.(1) Max. Unit
VCC = 3.0V,
VCC = 3.0V,
VCC = 3.6V,
VCC = 3.6V,
VCC = 3.6V,
VI = 0,
2.4
—
—
—
—
—
—
—
—
—
—
—
4
—
0.5
±5
V
V
OutputLogic"0"Voltage
Input Leakage Current (Any Input)
OutputLeakageCurrent
StandbyCurrent
ILI
VI = VCC or 0
VO = VCC or 0
µA
µA
µA
pF
pF
ILO
ICC(2)
±5
VI = VCC - 0.2V or 0
500
—
CIN
InputCapacitance
f = 1 MHz
f = 1 MHZ
COUT
OutputCapacitance
VO = 0,
8
—
NOTES:
1. All typical values are at VCC = 3.3V, TA = 25
2. For additional ICC information, see Figure 1, Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS).
°
C.
6
IDT72V36123.3V,CMOSSyncBiFIFOTM
64 x 36 x 2
COMMERCIALTEMPERATURERANGE
DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing the FIFO on the IDT72V3612 with CLKA and CLKB set to
S. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were disconnected to normalize
f
the graph to a zero-capacitance load. Once the capacitance load per data-output channel is known, the power dissipation can be calculated with the equation
below.
CALCULATING POWER DISSIPATION
With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of the IDT72V3612 may be calculated by:
PT = VCC x ICC(f) + Σ(CL x (VOH - VOL)2 x fO)
N
where:
N
=
=
=
=
=
number of outputs = 36
CL
fo
output capacitance load
switching frequency of an output
output HIGH level voltage
output LOW level voltage
VOH
VOL
Whennoreadsorwritesareoccurringonthisdevice,thepowerdissipatedbyasingleclock(CLKAorCLKB)inputrunningatfrequencyfS iscalculated
PT = VCC x fS x 0.025 mA/MHz
by:
175
150
fdata = 1/2 fS
T
A
= 25°C
125
100
75
C
L
= 0 pF
VCC = 3.6V
VCC = 3.3V
VCC = 3.0V
50
25
0
0
10
40
50
60
70
20
30
80
90
4663 drw 04
fS
Clock Frequency MHz
Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS)
7
IDT72V36123.3V,CMOSSyncBiFIFOTM
64 x 36 x 2
COMMERCIALTEMPERATURERANGE
DC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF
SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
Commercial: Vcc=3.3V± 0.30V; for 12ns (83MHz) operation, Vcc=3.3V ±0.15V; TA = 0° C to +70°C; JEDEC JESD8-A compliant
IDT72V3612L12 IDT72V3612L15 IDT72V3612L20
Symbol
fS
Parameter
Clock Frequency, CLKA or CLKB
Clock Cycle Time, CLKA or CLKB
Pulse Duration, CLKA and CLKB HIGH
PulseDuration, CLKAandCLKBLOW
Min.
–
Max.
83
–
Min.
–
Max.
66.7
–
Min.
–
Max.
50
–
Unit
MHz
ns
tCLK
tCLKH
tCLKL
tDS
12
5
15
6
20
8
–
–
–
ns
5
–
6
–
8
–
ns
SetupTime, A0-A35before CLKA↑ andB0-B35before
CLKB↑
4
–
4
–
5
–
ns
tENS1
SetupTime,CSA,W/RAbeforeCLKA↑;CSB,W/RB
beforeCLKB↑
3.5
–
6
–
6
–
ns
tENS2
tENS3
tPGS
SetupTime,ENA,beforeCLKA↑;ENBbeforeCLKB↑
SetupTime,MBAbeforeCLKA↑:MBBbeforeCLKB↑
SetupTime,ODD/EVENandPGAbeforeCLKA↑;
3.5
3.5
3
–
–
–
4
4
4
–
–
–
5
5
5
–
–
–
ns
ns
ns
(1)
ODD/EVENandPGBbeforeCLKB↑
tRSTS
tFSS
SetupTime, RST LOWbefore CLKA↑orCLKB↑(2)
4
4
–
–
–
–
5
5
1
1
–
–
–
–
6
6
1
1
–
–
–
–
ns
ns
ns
ns
Setup Time, FS0/FS1 before RST HIGH
tDH
HoldTime,A0-A35afterCLKA↑andB0-B35afterCLKB↑
0.5
0.5
tENH1
HoldTime,CSAW/RAafterCLKA↑;CSB,W/RBafter
CLKB↑
tENH2
tENH3
tPGH
HoldTime,ENA,afterCLKA↑;ENBafterCLKB↑
HoldTime,MBAafterCLKA↑;MBBafterCLKB↑
HoldTime,ODD/EVENandPGAafterCLKA↑;
1
1
0
–
–
–
1
1
1
–
–
–
1
1
1
–
–
–
ns
ns
ns
(1)
ODD/EVENandPGBafterCLKB↑
(2)
tRSTH
tFSH
tSKEW1(3)
HoldTime, RST LOWafterCLKA↑orCLKB↑
4
4
–
–
–
5
4
8
–
–
–
6
4
8
–
–
–
ns
ns
ns
Hold Time, FS0 and FS1 after RST HIGH
SkewTime, betweenCLKA↑ andCLKB↑forEFA, EFB,
FFA, and FFB
5.5
tSKEW2(3,4)
SkewTime,betweenCLKA↑andCLKB↑forAEA, AEB,
AFA, and AFB
14
–
14
–
16
–
ns
NOTES:
1. Only applies for a clock edge that does a FIFO read.
2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
4. Design simulated, not tested.
8
IDT72V36123.3V,CMOSSyncBiFIFOTM
64 x 36 x 2
COMMERCIALTEMPERATURERANGE
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF
SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30pF
Commercial: Vcc=3.3V± 0.30V; for 12ns (83MHz) operation, Vcc=3.3V ±0.15V; TA = 0°C to +70°C; JEDEC JESD8-A compliant
IDT72V3612L12 IDT72V3612L15 IDT72V3612L20
Symbol
tA
Parameter
Min.
1
Max.
Min.
2
Max.
10
10
10
10
10
9
Min.
2
Max.
12
Unit
ns
Access Time, CLKA↑ toA0-A35andCLKB↑ toB0-B35
Propagation Delay Time, CLKA↑ to FFA and CLKB↑ to FFB
Propagation Delay Time, CLKA↑ to EFA and CLKB↑ to EFB
Propagation Delay Time, CLKA↑ to AEA and CLKB↑ toAEB
Propagation Delay Time, CLKA↑ to AFA and CLKB↑ to AFB
8
8
8
8
8
8
tWFF
tREF
tPAE
tPAF
tPMF
1
2
2
12
ns
1
2
2
12
ns
1
2
2
12
ns
1
2
2
12
ns
Propagation Delay Time, CLKA↑ to MBF1 LOW orMBF2
HIGH and CLKB↑ to MBF2 LOW or MBF1 HIGH
1
1
1
12
ns
tPMR
tMDV
tPDPE
tPOPE
Propagation Delay Time, CLKA↑ to B0-B35(1) and CLKB↑
2
1
2
8
8
8
2
1
2
10
10
10
2
1
2
12
11.5
11
ns
ns
ns
toA0-A35(2)
Propagation Delay Time, MBA to A0-A35 valid and MBB to
B0-B35 valid
Propagation Delay Time, A0-A35 valid to PEFA valid; B0-B35
valid to PEFB valid
Propagation Delay Time, ODD/EVEN to PEFA and PEFB
2
2
8
8
2
2
10
10
2
2
12
12
ns
ns
(3)
tPOPB
PropagationDelayTime, ODD/EVEN toparitybits (A8, A17,
A26, A35) and (B8, B17, B26, B35)
tPEPE
Propagation Delay Time, W/RA, CSA, ENA, MBA or PGA to
PEFA; W/RB, CSB, ENB. MBB, PGB toPEFB
1
2
8
8
1
2
10
10
1
2
12
12
ns
ns
(3)
tPEPB
Propagation Delay Time, W/RA, CSA, ENA, MBA or PGA to
parity bits (A8, A17, A26, A35); W/RB, CSB, ENB. MBB or PGB
to parity bits (B8, B17, B26, B35)
tRSF
tEN
tDIS
Propagation Delay Time, RST to (AEA, AEB) LOW and
(AFA, AFB, MBF1, MBF2) HIGH
1
2
1
10
6
1
2
1
15
10
8
1
2
1
20
12
9
ns
ns
ns
Enable Time, CSA andW/RALOWtoA0-A35active and
CSB LOW and W/RB HIGH to B0-B35 active
Disable Time, CSA or W/RA HIGH to A0-A35 at high-
impedance andCSB HIGHorW/RBLOWtoB0-B35at
highimpedance
6
NOTES:
1. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH.
2. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
3. Only applies when reading data from a mail register.
9
IDT72V36123.3V,CMOSSyncBiFIFOTM
64 x 36 x 2
COMMERCIALTEMPERATURERANGE
Table 1.FortherelevantResetandpresetvalueloadingtimingdiagram,see
Figure 2.
SIGNALDESCRIPTIONS
RESET
FIFO WRITE/READ OPERATION
The IDT72V3612 is reset by taking the Reset (RST) input LOW for at
least four port A Clock (CLKA) and four port B Clock (CLKB) LOW-to-HIGH
transitions. The Reset input can switch asynchronously to the clocks. A
device resetinitializes the internalreadandwrite pointers ofeachFIFOand
forces the Full Flags (FFA, FFB) LOW, the Empty Flags (EFA, EFB) LOW,
the Almost-Empty flags (AEA, AEB) LOW and the Almost-Full flags (AFA,
AFB) HIGH. A reset also forces the Mailbox Flags (MBF1, MBF2) HIGH.
After a reset, FFA is set HIGH after two LOW-to-HIGH transitions of CLKA
and FFB is set HIGH after two LOW-to-HIGH transitions of CLKB. The
device must be reset after power up before data is written to its memory.
A LOW-to-HIGH transition on the RST input loads the Almost-Full and
Almost-Emptyregisters(X)withthevaluesselectedbytheFlagSelect(FS0,
FS1) inputs. The values that can be loaded into the registers are shown in
The state of port A data A0-A35 outputs is controlled by the port A Chip
Select(CSA)andtheportAWrite/Readselect(W/RA). TheA0-A35outputs
areinthehigh-impedancestatewheneitherCSAorW/RAis HIGH.TheA0-
A35 outputs are active when both CSA and W/RA are LOW.
Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH
transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA
is LOW, and FFA is HIGH. Data is read from FIFO2 to the A0-A35 outputs
by a LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is LOW,
ENAis HIGH,MBAis LOW,andEFA is HIGH(seeTable2). RelevantWrite
and Read timing diagrams for Port A can be found in Figure 3 and Figure
6.
The port B control signals are identical to those of port A. The state of
the port B data (B0-B35) outputs is controlled by the port B Chip Select
(CSB) and the port B Write/Read select (W/RB). The B0-B35 outputs are
in the high-impedance state when either CSB or W/RB is HIGH. The B0-
B35 outputs are active when both CSB and W/RB are LOW.
Data is loaded into FIFO2 from the B0-B35 inputs on a LOW-to-HIGH
transition of CLKB when CSB is LOW, W/RB is HIGH, ENB is HIGH, MBB
is LOW, and FFB is HIGH. Data is read from FIFO1 to the B0-B35 outputs
byaLOW-to-HIGHtransitionofCLKBwhenCSBisLOW,W/RBisLOW,ENB
is HIGH, MBB is LOW, and EFB is HIGH (see Table 3). Relevant Write and
Read timing diagrams for Port B can be found in Figure 4 and Figure 5.
ThesetupandholdtimeconstraintstotheportclocksfortheportChipSelects
(CSA,CSB)andWrite/Readselects(W/RA,W/RB)areonlyforenablingwrite
TABLE 1 – FLAG PROGRAMMING
ALMOST-FULL AND
ALMOST-EMPTY FLAG
OFFSET REGISTER (X)
FS1
FS0
RST
H
H
L
L
H
L
H
L
↑
↑
↑
↑
16
12
8
4
TABLE 2 – PORT-A ENABLE FUNCTION TABLE
CSA
H
L
W/RA
X
ENA
X
MBA
X
CLKA
X
Data A (A0-A35) I/O
Input
Port Functions
None
None
H
L
X
X
Input
L
H
H
L
↑
Input
FIFO1 Write
Mail1 Write
L
H
H
H
↑
Input
L
L
L
L
X
Output
None
L
L
H
L
↑
Output
FIFO2 Read
None
L
L
L
H
X
Output
L
L
H
H
↑
Output
Mail2 Read (Set MBF2 HIGH)
TABLE 3 – PORT-B ENABLE FUNCTION TABLE
CSB
H
L
W/RB
X
ENB
X
MBB
X
CLKB
X
Data B (B0-B35) I/O
Input
Port Functions
None
None
H
L
X
X
Input
L
H
H
L
↑
Input
FIFO2 Write
Mail2 Write
None
L
H
H
H
↑
Input
L
L
L
L
X
Output
L
L
H
L
↑
Output
FIFO1 read
None
L
L
L
H
X
Output
L
L
H
H
↑
Output
Mail1 Read (Set MBF1 HIGH)
10
IDT72V36123.3V,CMOSSyncBiFIFOTM
64 x 36 x 2
COMMERCIALTEMPERATURERANGE
FromthetimeawordisreadfromaFIFO,thepreviousmemorylocationisready
tobewritteninaminimumofthreecyclesoftheFullFlagsynchronizingclock.
Therefore,aFullFlagisLOWiflessthantwocyclesoftheFullFlagsynchronizing
clockhaveelapsedsincethenextmemorywritelocationhasbeenread. The
secondLOW-to-HIGHtransitionontheFullFlagsynchronizationclockafterthe
readsetstheFullFlagHIGHandthedatacanbewritteninthefollowingclock
cycle.
ALOW-to-HIGHtransitionona FullFlagsynchronizingclockbegins the
first synchronization cycle of a read if the clock transition occurs at time
tSKEW1 orgreateraftertheread. Otherwise,thesubsequentclockcyclecan
be the first synchronization cycle (see Figure 9 and Figure 10).
andreadoperationsandarenotrelatedtohigh-impedancecontrolofthedata
outputs. IfaportenableisLOWduringaclockcycle,theportchipselectand
write/readselectmaychangestatesduringthesetupandholdtimewindowof
thecycle.
SYNCHRONIZED FIFO FLAGS
Each FIFO is synchronized to its port clock through two flip-flop stages.
This is done to improve flag reliability by reducing the probability of
metastable events on the output when CLKA and CLKB operate asynchro-
nously to one another. EFA, AEA, FFA, and AFA are synchronized by
CLKA. EFB, AEB, FFB, andAFB are synchronized to CLKB. Tables 4 and
5 show the relationship of each port flag to FIFO1 and FIFO2.
ALMOST EMPTY FLAGS (AEA, AEB)
The Almost-Empty flag of a FIFO is synchronized to the port clock that
reads datafromits array. Thestatemachinethatcontrols anAlmost-Empty
flag monitors a write-pointer comparator that indicates when the FIFO
memorystatus is almost-empty, almost-empty+1, oralmost-empty+2. The
almost-empty state is defined by the value of the Almost-Full and Almost-
Empty Offset register (X). This register is loaded with one of four preset
values during a device reset (see Reset section). An Almost-Empty flag is
LOWwhenthe FIFOcontains Xorless words inmemoryandis HIGHwhen
the FIFO contains (X+1) or more words.
Two LOW-to-HIGH transitions of the Almost-Empty flag synchroniz-
ingclocks arerequiredafteraFIFOwritefortheAlmost-Emptyflagtoreflect
the new level of fill. Therefore, the Almost-Empty flag of a FIFO containing
(X+1) or more words remains LOW if two cycles of the synchronizing clock
have not elapsed since the write that filled the memory to the (X+1) level.
An Almost-Empty flag is set HIGH by the second LOW-to-HIGH transition
ofthe synchronizingclockafterthe FIFOwrite thatfills memorytothe (X+1)
level. A LOW-to-HIGH transition of an Almost-Empty flag synchronizing
clock begins the first synchronization cycle if it occurs at time tSKEW2 or
greater after the write that fills the FIFO to (X+1) words. Otherwise, the
subsequentsynchronizingclockcyclecanbethefirstsynchronizationcycle
(see Figure 11 and 12).
EMPTY FLAGS (EFA, EFB)
The Empty Flag of a FIFO is synchronized to the port clock that reads
data from its array. When the Empty Flag is HIGH, new data can be read
totheFIFOoutputregister. WhentheEmptyFlagisLOW,theFIFOisempty
and attempted FIFO reads are ignored.
The read pointer of a FIFO is incremented each time a new word is
clocked to the output register. The state machine that controls an Empty
Flag monitors a write-pointer and read-pointer comparator that indicates
when the FIFO memory status is empty, empty+1, or empty+2. A word
written to a FIFO can be read to the FIFO output register in a minimum of
three cycles of the Empty Flag synchronizing clock. Therefore, an Empty
FlagisLOWifawordinmemoryisthenextdatatobesenttotheFIFOoutput
register and two cycles of the port clock that reads data from the FIFO have
notelapsedsincethetimethewordwaswritten. TheEmptyFlagoftheFIFO
is set HIGH by the second LOW-to-HIGH transition of the synchronizing
clock, and the new data word can be read to the FIFO output register in the
following cycle.
ALOW-to-HIGHtransitiononanEmptyFlagsynchronizingclockbegins
the first synchronization cycle of a write if the clock transition occurs at time
tSKEW1orgreaterafterthewrite. Otherwise,thesubsequentclockcyclecan
be the first synchronization cycle (see Figure 7 and Figure 8).
ALMOST FULL FLAGS (AFA, AFB)
FULL FLAG (FFA, FFB)
The Almost-Full flag of a FIFO is synchronized to the port clock that
writes data to its array. The state machine that controls an Almost-Full flag
monitorsawrite-pointerandread-pointercomparatorthatindicateswhenthe
FIFOmemorystatusisalmost-full,almost-full-1,oralmost-full-2. Thealmost-full
stateisdefinedbythevalueoftheAlmost-FullandAlmost-EmptyOffsetregister
(X). Thisregisterisloadedwithoneoffourpresetvaluesduringadevicereset
(seeResetsection). AnAlmost-FullflagisLOWwhentheFIFOcontains(64-
The Full Flag of a FIFO is synchronized to the port clock that writes data
to its array. When the Full Flag is HIGH, a memory location is free in the
FIFOtoreceive newdata. Nomemorylocations are free whenthe FullFlag
isLOWandattemptedwritestotheFIFOareignored.
EachtimeawordiswrittentoaFIFO,thewritepointerisincremented. The
statemachinethatcontrolsaFullFlagmonitorsawrite-pointerandreadpointer
comparatorthatindicateswhentheFIFOmemorystatusisfull,full-1,orfull-2.
TABLE 4 – FIFO1 FLAG OPERATION
TABLE 5 – FIFO2 FLAG OPERATION
Synchronized
to CLKB
Synchronized
to CLKA
Synchronized
to CLKB
Synchronized
to CLKA
Number of Words
in the FIFO1(1)
0
Number of Words
in the FIFO2(1)
0
EFB
L
AEB
L
AFA
H
FFA
H
EFA
L
AEA
L
AFB
H
FFB
H
1 to X
H
L
H
H
1 to X
H
L
H
H
(X+1) to [64-(X+1)]
(64-X) to 63
64
H
H
H
H
(X+1) to [64-(X+1)]
(64-X) to 63
64
H
H
H
H
H
H
L
H
H
H
L
H
H
H
L
L
H
H
L
L
NOTE:
1. X is the value in the Almost-Empty flag and Almost-Full flag offset register.
11
IDT72V36123.3V,CMOSSyncBiFIFOTM
64 x 36 x 2
COMMERCIALTEMPERATURERANGE
X)ormorewordsinmemoryandisHIGHwhentheFIFOcontains[64-(X+1)] A26,andA27-A35withthemostsignificantbitofeachbyteusedastheparity
or less words. bit. PortBbytesarearrangedasB0-B8,B9-B17,B18-B26,andB27-B35,with
Two LOW-to-HIGH transitions of the Almost-Full flag synchronizing themostsignificantbitofeachbyteusedastheparitybit. Whenodd/evenparity
clockarerequiredafteraFIFOreadfortheAlmost-Fullflagtoreflectthenew is selected, a port Parity Error Flag (PEFA, PEFB) is LOW if any byte on the
level of fill. Therefore, the Almost-Full flag of a FIFO containing [64-(X+1)] porthas anodd/evennumberofLOWlevels appliedtothe bits.
orlesswordsremainsLOWiftwocyclesofthesynchronizingclockhavenot
ThefourparitytreesusedtochecktheA0-A35inputsaresharedbythe
elapsed since the read that reduced the number of words in memory to mail2registerwhenparitygenerationisselectedforportAreads(PGA=HIGH).
[64-(X+1)]. An Almost-Full flag is set HIGH by the second LOW-to-HIGH WhenaportAreadfromthemail2registerwithparitygenerationisselectedwith
transition of the synchronizing clock after the FIFO read that reduces the W/RALOW, CSA LOW, ENAHIGH, MBAHIGH, andPGAHIGH, the portA
number of words in memory to [64-(X+1)]. A second LOW-to-HIGH ParityErrorFlag(PEFA)is heldHIGHregardless ofthelevels appliedtothe
transitionofanAlmost-Fullflagsynchronizingclockbeginsthefirstsynchro- A0-A35inputs. Likewise,theparitytreesusedtochecktheB0-B35inputsare
nizationcycleifitoccursattimetSKEW2orgreaterafterthereadthatreduces sharedbythemail1registerwhenparitygenerationisselectedforportBreads
the number of words in memory to [64-(X+1)]. Otherwise, the subsequent (PGB=HIGH). WhenaportBreadfromthemail1registerwithparitygeneration
synchronizingclockcycle canbe the firstsynchronizationcycle (see Figure isselectedwithW/RBLOW,CSBLOW,ENBHIGH,MBBHIGH,andPGBHIGH,
13 and 14).
theportBParityErrorFlag(PEFB)isheldHIGHregardlessofthelevelsapplied
to the B0-B35 inputs (see Figure 17 and Figure 18).
MAILBOX REGISTERS
EachFIFOhas a 36-bitbypass registertopass commandandcontrol PARITY GENERATION
information between port A and port B without putting it in queue. The
A HIGH level on the port A Parity Generate select (PGA) or port B
Mailbox select (MBA, MBB) inputs choose between a mail register and a Parity Generate select (PGB) enables the IDT72V3612 to generate parity
FIFOforaportdatatransferoperation. ALOW-to-HIGHtransitiononCLKA bitsforportreadsfromaFIFOormailboxregister. PortAbytesarearranged
writes A0-A35 data to the mail1 register when a port A write is selected by as A0-A8, A9-A17, A18-26, and A27-A35, with the most significant bit of
CSA,W/RA,andENAandMBAHIGH. ALOW-to-HIGHtransitiononCLKB each byte used as the parity bit. Port B bytes are arranged as B0-B8, B9-
writes B0-B35 data to the mail2 register when a port B write is selected by B17, B18-B26, and B27-B35, with the most significant bit of each byte used
CSB, W/RB,andENBandMBBis HIGH. Writingdatatoamailregistersets as the parity bit. A write to a FIFO or mail register stores the levels applied
the corresponding flag (MBF1 or MBF2) LOW. Attempted writes to a mail to all thirty-six inputs regardless of the state of the Parity Generate select
register are ignored while the mail flag is LOW.
(PGA, PGB) inputs. When data is read from a port with parity generation
Whenaport's dataoutputs areactive,thedataonthebus comes from selected, the lower eight bits of each byte are used to generate a parity bit
the FIFO output register when the port Mailbox select input (MBA, MBB) is according to the level on the ODD/EVEN select. The generated parity bits
LOW and from the mail register when the port mailbox select input is HIGH. are substituted for the levels originally written to the most significant bits of
The Mail1 register Flag (MBF1) is set HIGH by a LOW-to-HIGH transition each byte as the word is read to the data outputs.
on CLKB when a port B read is selected by CSB, W/RB, and ENB and MBB
Parity bits for FIFO data are generated after the data is read from
is HIGH. The Mail2 register Flag (MBF2) is set HIGH by a LOW-to-HIGH SRAM and before the data is written to the output register. Therefore, the
transition on CLKA when port A read is selected by CSA, W/RA, and ENA port A Parity Generate select (PGA) and Odd/Even parity select (ODD/
and MBA is HIGH. The data in a mail register remains intact after it is read EVEN)havesetupandholdtimeconstraints totheportAClock(CLKA)and
and changes only when new data is written to the register. Mail register and the port B Parity Generate select (PGB) and ODD/EVEN have setup and
Mail Register Flag timing can be found in Figure 15 and Figure 16.
hold-time constraints to the port B Clock (CLKB). These timing constraints
onlyapplyforarisingclockedgeusedtoreadanewwordtotheFIFOoutput
register.
PARITY CHECKING
The portAinputs (A0-A35)andportBinputs (B0-B35)eachhave four
The circuit used to generate parity for the mail1 data is shared by the
paritytreestochecktheparityofincoming(oroutgoing)data. Aparityfailure port B bus (B0-B35) to check parity and the circuit used to generate parity
on one or more bytes of the input bus is reported by a LOW level on the port for the mail2 data is shared by the port A bus (A0-A35) to check parity. The
Parity Error Flag (PEFA, PEFB). Odd or even parity checking can be shared parity trees of a port are used to generate parity bits for the data in
selected, and the Parity Error Fags can be ignored if this feature is not amailregisterwhentheportWrite/Readselect(W/RA,W/RB)inputisLOW,
desired.
the port Mail select (MBA, MBB) input is HIGH, Chip Select (CSA, CSB) is
Paritystatus is checkedoneachinputbus accordingtothelevelofthe LOW, Enable (ENA, ENB) is HIGH, and port Parity Generate select (PGA,
Odd/Even parity (ODD/EVEN) select input. A parity error on one or more PGB)is HIGH. Generatingparityformailregisterdata does notchange the
bytesofaportisreportedbyaLOWlevelonthecorrespondingportParityError contents of the register (see Figure 19 and Figure 20).
Flag(PEFA,PEFB)output. PortAbytesarearrangedasA0-A8,A9-A17,A18-
12
IDT72V36123.3V,CMOSSyncBiFIFOTM
64 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKA
CLKB
tRSTH
t
RSTS
t
FSS
t
FSH
RST
0,1
FS1,FS0
t
WFF
t
t
WFF
REF
t
FFA
EFA
FFB
EFB
t
WFF
WFF
t
REF
t
t
PAE
AEA
AFA
PAF
t
RSF
MBF1,
MBF2
t
PAE
AEB
AFB
t
PAF
4659 drw 05
Figure 2. Device Reset and Loading the X Register with the Value of Eight
13
IDT72V36123.3V,CMOSSyncBiFIFOTM
64 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKA
FFA
CSA
HIGH
t
ENS1
t
ENH1
tENS1
t
ENH1
W/RA
t
ENS3
t
ENH3
ENH2
MBA
tENS2
tENS2
t
ENS2
tENH2
tENH2
t
ENA
tDS
tDH
(1)
W1
W2(1)
A0 - A35
No Operation
ODD/
EVEN
tPDPE
tPDPE
Valid
Valid
PEFA
4659 drw 06
NOTE:
1. Written to FIFO1.
Figure 3. Port A Write Cycle Timing for FIFO1
tCLK
tCLKH
tCLKL
CLKB
FFB
CSB
HIGH
t
ENS1
t
ENH1
ENH1
tENS1
t
W/RB
MBB
t
ENS3
ENS2
t
ENH3
tENS2
t
t
ENH2
tENH2
tENS2
tENH2
ENB
tDS
tDH
(1)
W1
W2(1)
B0 - B35
No Operation
ODD/
EVEN
tPDPE
tPDPE
Valid
Valid
PEFB
4659 drw 07
NOTE:
1. Written to FIFO2.
Figure 4. Port B Write Cycle Timing for FIFO2
14
IDT72V36123.3V,CMOSSyncBiFIFOTM
64 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKB
EFB HIGH
CSB
W/RB
MBB
ENB
t
ENS2
t
ENH2
tENH2
tENH2
t
ENS2
t
ENS2
No Operation
Word 2(1)
t
MDV
EN
t
A
tA
tDIS
t
(1)
Previous Data (1)
Word 1
B0 - B35
tPGH
tPGH
tPGS
tPGS
PGB,
ODD/
EVEN
4659 drw 08
NOTE:
1. Read from FIFO1.
Figure 5. Port B Read Cycle Timing for FIFO1
tCLK
tCLKH
tCLKL
CLKA
EFA
CSA
HIGH
W/RA
tENS2
MBA
ENA
t
ENH2
tENH2
t
ENH2
t
ENS2
tENS2
No Operation
Word 2(1)
t
MDV
t
A
tDIS
t
A
tEN
(1)
Previous Data (1)
Word 1
A0 - A35
tPGH
tPGH
tPGS
tPGS
PGA,
ODD/
EVEN
4659 drw 09
NOTE:
1. Read from FIFO2.
Figure 6. Port A Read Cycle Timing for FIFO2
15
IDT72V36123.3V,CMOSSyncBiFIFOTM
64 x 36 x 2
COMMERCIALTEMPERATURERANGE
t
CLK
t
CLKL
t
CLKH
CLKA
LOW
HIGH
CSA
W/RA
MBA
ENA
t
ENH3
t
ENS3
tENS2
tENH2
HIGH
FFA
tDS
tDH
W1
A0 - A35
t
CLK
(1)
SKEW1
t
tCLKH
tCLKL
1
2
CLKB
t
REF
t
REF
FIFO1 Empty
EFB
CSB
LOW
LOW
LOW
W/RB
MBB
tENS2
tENH2
ENB
tA
W1
B0 -B35
4659 drw 10
NOTE:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and
rising CLKB edge is less than tSKEW1, then the transition of EFB HIGH may occur one CLKB cycle later than shown.
Figure 7. EFB Flag Timing and First Data Read when FIFO1 is Empty
16
IDT72V36123.3V,CMOSSyncBiFIFOTM
64 x 36 x 2
COMMERCIALTEMPERATURERANGE
t
CLK
t
CLKH
tCLKL
CLKB
LOW
CSB
W/RB HIGH
tENS3
tENH3
MBB
tENS2
tENH2
ENB
FFB
HIGH
tDS
tDH
W1
B0 - B35
t
CLK
(1)
SKEW1
t
CLKH
t
tCLKL
1
2
CLKA
t
REF
t
REF
EFA FIFO2 Empty
CSA LOW
W/RA LOW
MBA LOW
ENA
tENS2
tENH2
tA
A0 -A35
W1
4659 drw 11
NOTE:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and
rising CLKA edge is less than tSKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown.
Figure 8. EFA Flag Timing and First Data Read when FIFO2 is Empty
17
IDT72V36123.3V,CMOSSyncBiFIFOTM
64 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKB
CSB
LOW
LOW
LOW
W/RB
MBB
tENS2
tENH2
ENB
EFB
HIGH
tA
Previous Word in FIFO1 Output Register
B0 - B35
Next Word From FIFO1
(1)
t
CLK tCLKL
tSKEW1
tCLKH
1
2
CLKA
t
WFF
t
WFF
FIFO1 Full
LOW
FFA
CSA
W/RA HIGH
tENS3
tENH3
MBA
tENS2
tENH2
ENA
tDH
tDS
A0 - A35
To FIFO1
4659 drw 12
NOTE:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and
rising CLKA edge is less than tSKEW1, then FFA may transition HIGH one CLKA cycle later than shown.
Figure 9. FFA Flag Timing and First Available Write when FIFO1 is Full.
18
IDT72V36123.3V,CMOSSyncBiFIFOTM
64 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKA
CSA
LOW
LOW
LOW
W/RA
MBA
tENS2
tENH2
ENA
EFA
HIGH
tA
Previous Word in FIFO2 Output Register
Next Word From FIFO2
A0 - A35
(1)
t
CLKH CLK tCLKL
tSKEW1
t
1
2
CLKB
t
WFF
t
WFF
FIFO2 Full
LOW
FFB
CSB
W/RB
HIGH
tENS3
tENH3
MBB
tENS2
tENH2
ENB
tDH
tDS
B0 - B35
To FIFO2
4659 drw 13
NOTE:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and
rising CLKB edge is less than tSKEW1, then FFB may transition HIGH one CLKB cycle later than shown.
Figure 10. FFB Flag Timing and First Available Write when FIFO2 is Full
CLKA
tENS2
tENH2
ENA
(1)
tSKEW2
1
2
CLKB
t
PAE
tPAE
X Words in FIFO1
(X+1) Words in FIFO1
AEB
tENH2
tENS2
ENB
4659 drw 14
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and
rising CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown.
2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = LOW, MBB = LOW).
Figure 11. Timing for AEB when FIFO1 is Almost Empty
19
IDT72V36123.3V,CMOSSyncBiFIFOTM
64 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKB
tENS2
tENH2
ENB
(1)
tSKEW2
1
2
CLKA
t
PAE
t
PAE
AEA
X Words in FIFO2
(X+1) Words in FIFO2
ENS2
t
tENH2
ENA
4659 drw 15
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and
rising CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown.
2. FIFO2 Write (CSB = LOW, W/RB = HIGH, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW).
Figure 12. Timing for AEA when FIFO2 is Almost Empty
(1)
tSKEW2
1
2
CLKA
ENA
tENH2
tENS2
t
PAF
t
PAF
(64-X) Words in FIFO1
AFA
CLKB
ENB
[64-(X+1)] Words in FIFO1
tENS2
tENH2
4659 drw 16
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge and
rising CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKA cycle later than shown.
2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = LOW, MBB = LOW).
Figure 13. Timing for AFA when FIFO1 is Almost Full
(1)
tSKEW2
1
2
CLKB
ENB
t
ENH2
PAF
tENS2
t
PAF
t
(64-X) Words in FIFO2
AFB
[64-(X+1)] Words in FIFO2
CLKA
tENS2
tENH2
ENA
4659 drw 17
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKB edge and
rising CLKA edge is less than tSKEW2, then AFB may transition HIGH one CLKB cycle later than shown.
2. FIFO2 Write (CSB = LOW, W/RB = HIGH, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW).
Figure 14. Timing for AFB when FIFO2 is Almost Full
20
IDT72V36123.3V,CMOSSyncBiFIFOTM
64 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKA
tENS1
tENH1
CSA
W/RA
MBA
tENS1
tENS1
tENS1
tENH1
tENH1
tENH1
ENA
A0 - A35
CLKB
tDH
t
DS
W1
t
PMF
t
PMF
MBF1
CSB
W/RB
MBB
ENB
tENH2
tENS2
t
MDV
tEN
t
PMR
tDIS
FIFO1 Output Register
W1 (Remains valid in Mail1 Register after read)
B0 - B35
4659 drw 18
NOTE:
1. Port B parity generation off (PGB = LOW).
Figure 15. Timing for Mail1 Register and MBF1 Flag
21
IDT72V36123.3V,CMOSSyncBiFIFOTM
64 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKB
t
ENH1
ENH1
t
ENS1
CSB
W/RB
t
t
ENS1
ENS1
ENS1
t
ENH1
ENH1
t
t
MBB
t
ENB
tDH
tDS
W1
B0 - B35
CLKA
t
PMF
t
PMF
MBF2
CSA
W/RA
MBA
ENA
tENH2
tENS2
t
MDV
tEN
t
PMR
tDIS
FIFO2 Output Register
W1 (Remains valid in Mail2 Register after read)
A0 - A35
4659 drw 19
NOTE:
1. Port A parity generation off (PGA = LOW).
Figure 16. Timing for Mail2 Register and MBF2 Flag
ODD/
EVEN
W/RA
MBA
PGA
t
PEPE
t
PEPE
tPOPE
tPOPE
PEFA
Valid
Valid
Valid
Valid
4659 drw 20
NOTE:
1. ENA is HIGH, and CSA is LOW.
Figure 17. ODD/EVEN W/RA, MBA, and PGA to PEFA Timing
22
IDT72V36123.3V,CMOSSyncBiFIFOTM
64 x 36 x 2
COMMERCIALTEMPERATURERANGE
ODD/
EVEN
W/RB
MBB
PGB
t
PEPE
tPOPE
tPEPE
tPOPE
PEFB
Valid
Valid
Valid
Valid
4659 drw 21
NOTE:
1. ENB is HIGH, and CSB is LOW.
Figure 18. ODD/EVEN W/RB, MBB, and PGB to PEFB Timing
ODD/
EVEN
LOW
CSA
W/RA
MBA
PGA
t
PEPB
tEN
tMDV
t
POPB
tPEPB
A8, A17,
A26, A35
Generated Parity
Generated Parity
Mail2 Data
4659 drw 22
Mail2
Data
NOTE:
1. ENA is HIGH.
Figure 19. Parity Generation Timing when Reading from Mail2 Register
ODD/
EVEN
LOW
CSB
W/RB
MBB
PGB
t
PEPB
t
MDV
tPOPB
tEN
tPEPB
B8, B17,
B26, B35
Generated Parity
Generated Parity
Mail1 Data
Mail1
Data
4659 drw 23
NOTE:
1. ENB is HIGH.
Figure 20. Parity Generation Timing when Reading from Mail1 Register
23
IDT72V36123.3V,CMOSSyncBiFIFOTM
64 x 36 x 2
COMMERCIALTEMPERATURERANGE
PARAMETER MEASUREMENT INFORMATION
3.3V
330Ω
From Output
Under Test
30 pF (1)
510Ω
LOAD CIRCUIT
3 V
3 V
1.5 V
High-Level
Timing
Input
1.5 V
Input
1.5 V
1.5 V
GND
GND
th
tS
tW
3 V
3 V
Data,
Enable
Input
1.5 V
1.5 V
Low-Level
Input
1.5 V
GND
GND
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3 V
Output
Enable
1.5 V
1.5 V
t
PZL
GND
tPLZ
3 V
≈ 3V
Input
1.5 V
1.5 V
1.5 V
Low-Level
Output
GND
V
OL
tPD
tPD
t
PZH
V
OH
V
OH
≈ OV
In-Phase
Output
1.5 V
1.5 V
High-Level
Output
1.5 V
V
t
PHZ
OL
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
4659 drw 24
NOTE:
1. Includes probe and jig capacitance
Figure 21. Load Circuit and Voltage Waveforms
24
ORDERING INFORMATION
IDT
XXXXXX
X
XX
X
X
Device Type Power
Speed
Package
Process/
Temperature
Range
Commercial (0°C to +70°C)
BLANK
Thin Quad Flat Pack (TQFP, PN120-1)
Plastic Quad Flat Pack (PQFP, PQ132-1)
PF
PQF
12
15
20
Clock Cycle Time (tCLK
)
Commercial Only
Low Power
Speed in Nanoseconds
L
72V3612 64 x 36 x 2 3.3V SyncBiFIFO
4659 drw 25
NOTE:
1. Industrial temperature range is available by special order.
DATASHEETDOCUMENTHISTORY
07/10/2000
05/27/2003
pg. 1.
pg. 6.
CORPORATE HEADQUARTERS
2975StenderWay
for SALES:
800-345-7015 or 408-727-6116
for Tech Support:
408-330-1753
Santa Clara, CA 95054
fax: 408-492-8674
www.idt.com
email:FIFOhelp@idt.com
25
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