IDT72V3613L15PQFG [IDT]
Bi-Directional FIFO, 64X36, 10ns, Synchronous, CMOS, PQFP132, GREEN, PLASTIC, QFP-132;
| 型号： | IDT72V3613L15PQFG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Bi-Directional FIFO, 64X36, 10ns, Synchronous, CMOS, PQFP132, GREEN, PLASTIC, QFP-132 时钟 先进先出芯片 内存集成电路 |
| 文件： | 总26页 (文件大小：261K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3VOLTCMOSCLOCKEDFIFOWITH
BUS-MATCHINGANDBYTESWAPPING
64 x 36
IDT72V3613
• Parity Generation can be selected for each Port
FEATURES:
• Available in 132-pin plastic quad flat package (PQF), or space
saving 120-pin thin quad flat package (TQFP)
• Pin and functionally compatible version of the 5V operating
IDT723613
• Industrial temperature range (–40°C to +85°C) is available
• Green parts available, see ordering information
• 64 x 36 storage capacity FIFO buffering data from Port A to Port B
• Supports clock frequencies up to 83MHz
• Fast access times of 8ns
• Free-running CLKA and CLKB may be asynchronous or
coincident (permits simultaneous reading and writing of data on
a single clock edge)
• Mailbox bypass registers in each direction
• Dynamic Port B bus sizing of 36 bits (long word), 18 bits (word),
and 9 bits (byte)
• Selection of Big- or Little-Endian format for word and byte bus
sizes
• Three modes of byte-order swapping on Port B
• Programmable Almost-Full and Almost-Empty flags
• Microprocessor interface control logic
• FF , AF flags synchronized by CLKA
• EF , AE flags synchronized by CLKB
• Passive parity checking on each Port
DESCRIPTION:
The IDT72V3613 is a pin and functionally compatible version of the
IDT723613, designed to run off a 3.3V supply for exceptionally low-power
consumption. This device is a monolithic, high-speed, low-power, CMOS
synchronous(clocked)FIFOmemorywhichsupportsclockfrequenciesupto
83MHzandhasread-accesstimesasfastas8ns.The64x36dual-portSRAM
FIFO buffers data from port A to port B. The FIFO operates in IDT Standard
modeandhasflagstoindicateemptyandfullconditions,andtwoprogrammable
flags, Almost-Full(AF)andAlmost-Empty(AE), toindicate whena selected
numberofwordsisstoredinmemory.FIFOdataonportBcanbeoutputin36-
FUNCTIONALBLOCKDIAGRAM
CLKA
CSA
W/RA
ENA
Port-A
Control
Logic
MBA
MBF1
PEFB
Parity
Gen/Check
Mail 1
Register
RST
PGB
Device
Control
ODD/
EVEN
RAM ARRAY
64 x 36
64 x 36
36
36
Read
Pointer
Write
Pointer
B0 - B35
Status Flag
FF
AF
EF
AE
Logic
FIFO
CLKB
CSB
W/RB
ENB
BE
SIZ0
SIZ1
SW0
SW1
Programmable
Flag Offset
Registers
FS0
FS1
Port-B
Control
A0 - A35
Logic
PGA
Mail 2
Register
Parity
Gen/Check
PEFA
MBF2
4661 drw 01
CIDTOandMtheMIDTElogRoaCrereIgAisteLredtrTadeEmaMrksPofInEtegRratAedTDevUiceRTeEchnoloRgy,AIncN.SyGncFEIFOisatrademarkofIntegratedDeviceTechnology,Inc.
JUNE 2005
1
2005 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4661/2
IDT72V36133.3V,CMOSCLOCKEDFIFOWITH
BUS-MATCHINGANDBYTESWAPPING64x36
COMMERCIALTEMPERATURERANGE
enable signals. The continuous clocks foreachportare independentofone
anotherandcanbeasynchronousorcoincident.Theenablesforeachportare
arrangedtoprovideasimpleinterfacebetweenmicroprocessorsand/orbuses
withsynchronousinterfaces.
The Full Flag (FF) and Almost-Full (AF) flag of the FIFO are two-stage
synchronizedtotheportclock(CLKA)thatwritesdataintoitsarray.TheEmpty
Flag(EF)andAlmost-Empty(AE)flagoftheFIFOaretwo-stagesynchronized
totheportclock(CLKB)thatreads datafromits array.
DESCRIPTION(CONTINUED)
bit,18-bit,and9-bitformatswithachoiceofBig-orLittle-Endianconfigurations.
Threemodesofbyte-orderswappingarepossiblewithanybus-sizeselection.
CommunicationbetweeneachportcanbypasstheFIFOviatwo36-bitmailbox
registers.Eachmailboxregisterhasaflagtosignalwhen newmailhasbeen
stored. Parity is checked passively on each port and may be ignored if not
desired.Paritygenerationcanbeselectedfordatareadfromeachport.Two
or more devices may be used in parallel to create wider data paths.
TheIDT72V3613ischaracterizedforoperationfrom0°Cto70°C.Industrial
temperaturerange(–40°Cto+85°C)isavailablebyspecialorder. Thisdevice
isfabricatedusingIDT'shighspeed,submicronCMOStechnology.
The IDT72V3613 is a synchronous (clocked) FIFO, meaning each port
employsasynchronousinterface.Alldatatransfersthroughaportaregated
to the LOW-to-HIGH transition of a continuous (free-running) port clock by
PINCONFIGURATION
1
A
A
A
23
22
21
B
22
21
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
2
B
3
GND
4
GND
B
B
B
B
B
B
B
B
B
B
B
20
19
18
17
16
15
14
13
12
11
10
5
A
A
A
A
A
A
A
A
A
A
A
20
19
18
17
16
15
14
13
12
11
10
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
GND
GND
B
B
B
V
B
B
B
B
9
8
7
CC
6
5
4
3
A
A
A
9
8
7
VCC
A
A
A
A
6
5
4
3
GND
GND
B2
B1
B0
A
A
A
2
1
0
EF
AE
NC
NC
NC
4661 drw 02
NOTES:
1. Pin 1 idenifier in corner.
2. NC = No internal connection
TQFP (PN120-1, order code: PF)
TOP VIEW
2
JUNE 9, 2005
IDT72V36133.3V,CMOSCLOCKEDFIFOWITH
BUS-MATCHINGANDBYTESWAPPING64x36
COMMERCIALTEMPERATURERANGE
PINCONFIGURATION(CONTINUED)
GND
NC
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
GND
AE
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
EF
NC
B
B
B
0
1
2
A
A
A
0
1
2
GND
GND
B
B
B
B
V
B
B
B
3
4
5
6
CC
7
8
A
A
A
A
3
4
5
6
V
CC
A
A
A
7
8
9
9
GND
GND
A
10
11
B
B
V
B
B
B
10
11
CC
12
13
14
A
V
CC
98
A
12
13
14
97
A
96
A
GND
95
GND
94
A
A
A
A
A
A
15
16
17
18
19
20
B
B
B
B
B
B
15
16
17
18
19
20
93
92
91
90
89
88
GND
GND
87
A21
A22
A23
B21
B22
B23
86
85
84
4661 drw 03
NOTES:
1. Electricalpin1incenterofbevelededge.
2. NC = No internal connection.
3. Uses Yamaichi socket IC51-1324-8283.
PQFP(3) (PQ132-1, order code: PQF)
TOP VIEW
JUNE 9, 2005
3
IDT72V36133.3V,CMOSCLOCKEDFIFOWITH
BUS-MATCHINGANDBYTESWAPPING64x36
COMMERCIALTEMPERATURERANGE
PINDESCRIPTION
Symbol
A0-A35
AE
Name
I/O
Description
Port A Data
I/O 36-bitbidirectionaldataportforsideA.
Almost-EmptyFlag
O
ProgrammableAlmost-EmptyflagsynchronizedtoCLKB. ItisLOWwhenPortBthenumberof36-bit
PortB words in the FIFO is less than or equal to the value in the offset register, X.
ProgrammableAlmost-FullflagsynchronizedtoCLKA. ItisLOWwhenthenumberof36-bitempty
AF
Almost-FullFlag
O
PortA emptylocations inthe FIFOis less thanorequaltothe value inthe offsetregister, X.
B0-B35
PortBData
I/O 36-bitbidirectionaldataportforsideB
BE
Big-EndianSelect
I
I
I
Selects the bytes on port B used during byte or word FIFO reads. A LOW on BE selects the most
significantbytes onB0-B35foruse,anda HIGHselects theleastsignificantbytes.
CLKA
CLKB
Port A Clock
PortBClock
CLKAis a continuous clockthatsynchronizes alldata transfers throughportAandcanbe asynchronous
or coincident to CLKB. FF andAF are synchronized to the LOW-to-HIGH transition of CLKA.
CLKBis a continuous clockthatsynchronizes alldata transfers throughportBandcanbe asynchronous
orcoincidenttoCLKA. Port-Bbyte swappinganddata portsizingoperations are alsosynchronous tothe
LOW-to-HIGHtransitionofCLKB.EFandAEaresynchronizedtotheLOW-to-HIGHtransitionof CLKB.
CSA
CSB
EF
PortAChipSelect
PortBChipSelect
EmptyFlag
I
I
CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write data on port A. The A0-
A35outputs are inthe high-impedance state whenCSA is HIGH.
CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port B. The B0-
B35outputs are inthe high-impedance state whenCSB is HIGH.
O
EF is synchronizedtothe LOW-to-HIGHtransitionofCLKB. WhenEF is LOW, the FIFOis empty, and
PortB reads from its memory are disabled. Data can be read fromthe FIFOtoits outputregisterwhenEFis
HIGH. EF is forced LOW when the device is reset and is set HIGH by the second LOW-to-HIGH
transitionofCLKBafterdataisloadedintoemptyFIFOmemory.
ENA
ENB
FF
Port A Enable
Port B Enable
Full Flag
I
I
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port A.
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port B.
FF is synchronizedtothe LOW-to-HIGHtransitionofCLKA. WhenFF is LOW, the FIFOis full, and
O
PortA writes to its memory are disabled. FF is forced LOW when the device is reset and is set HIGH by the
secondLOW-to-HIGHtransitionofCLKAafterreset.
FS1,FS0 FlagOffsetSelects
I
I
The LOW-to-HIGHtransitionof RST latches the values ofFS0andFS1, whichloads one offourpreset
valuesintotheAlmost-FullflagandAlmost-Emptyflagoffsets.
MBA
Port A Mailbox
Select
A high level on MBA chooses a mailbox register for a port A read or write operation. When the A0-A35
outputsareactive,mail2registerdataisoutput.
MBF1
Mail1RegisterFlag
O
MBF1issetLOWbyaLOW-to-HIGHtransitionofCLKAthatwritesdatatothemail1register. Writestothe
mail1registerare inhibitedwhile MBF1 is setLOW. MBF1 is setHIGHbya LOW-to-HIGHtransitionof
CLKB when a port B read is selected and both SIZ1 and SIZ0 are HIGH. MBF1 is set HIGH when the
deviceisreset.
MBF2
Mail2RegisterFlag
O
I
MBF2issetLOWbyaLOW-to-HIGHtransitionofCLKBthatwritesdatatothemail2register. Writestothe
mail2registerare inhibitedwhile MBF2 is setLOW. MBF2 is setHIGHbya LOW-to-HIGHtransitionof
CLKA when a port A read is selected and MBA is HIGH. MBF2 is set HIGH when the device is reset.
ODD/
EVEN
Odd/EvenParity
Select
Odd parity is checked on each port when ODD/EVEN is HIGH, and even parity is checked when
ODD/EVEN is LOW. ODD/EVEN alsoselects the type ofparitygeneratedforeachportifparity
generation is enabled for a read operation.
PEFA
Port A Parity Error
Flag
O
When any valid byte applied to terminals A0-A35 fails parity, PEFA is LOW. Bytes (PortA) are organized
as A0-A8, A9-A17, A18-A26, andA27-A35, withthe mostsignificantbitofeachbyte servingas the parity
bit.Thetypeofparitycheckedis determinedbythestateoftheODD/EVENinput.
The parity trees used to check the A0-A35 inputs are shared by the mail2 register to generate parity if
parity generation is selected by PGA. Therefore, if a mail2 read with parity generation is set up by having
CSA LOW, ENA HIGH, W/RA LOW, MBA HIGH and PGA HIGH, the PEFA flagis forcedHIGH
regardlessofthestateoftheA0-A35inputs.
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JUNE 9, 2005
IDT72V36133.3V,CMOSCLOCKEDFIFOWITH
BUS-MATCHINGANDBYTESWAPPING64x36
COMMERCIALTEMPERATURERANGE
PINDESCRIPTION(CONTINUED)
Symbol
Name
I/O
Description
PEFB
Port B Parity Error
Flag
O
Whenanyvalidbyteappliedtoterminals B0-B35fails parity,PEFB is LOW. Bytes are organized as
(PortB) B0-B8, B9-B17, B-18-B26, andB27-B35, withthe mostsignificantbitofeachbyte servingas the parity
bit. A byte is valid when it is used by the bus size selected for port B. The type of parity checked is
determinedbythestateoftheODD/EVENinput.
The parity trees used to check the B0-B35 inputs are shared by the mail1 register to generate parity if
parity generation is selected by PGB. Therefore, if a mail1 read with parity generation is set up by having
CSB LOW, ENB HIGH, W/RB LOW, SIZ1 and SIZ0 HIGH and PGB HIGH, the PEFB flag is forced HIGH
regardlessofthestateoftheB0-B35inputs.
PGA
PGB
RST
Port A Parity
Generation
I
I
I
Parity is generated for data reads from the mail2 register when PGA is HIGH. The type of parity
generatedis selectedbythe state ofthe ODD/EVEN input. Bytes are organizedatA0-A8, A9-A17, A18-
A26,andA27-A35.Thegeneratedparitybits areoutputinthemostsignificantbitofeachbyte.
Port B Parity
Generation
Parity is generated for data reads from port B when PGB is HIGH. The type of parity generated is
selected by the state of the ODD/EVEN input. Bytes are organizedas B0-B8, B9-B17, B18-B26, and
B27-B35.Thegeneratedparitybits areoutputinthemostsignificantbitofeachbyte.
Reset
To resetthedevice,fourLOW-to-HIGHtransitionsofCLKAandfourLOW-to-HIGHtransitionsofCLKB
must occur while RST is LOW. This sets the AF, MBF1, and MBF2 flags HIGH and the EF, AE, and FF
flagsLOW.TheLOW-to-HIGHtransitionofRSTlatchesthestatusoftheFS1andFS0inputstoselect
Almost-FullflagandAlmost-Emptyflagoffset.
SIZ0,
SIZ1
PortBBus Size
Selects
I
ALOW-to-HIGHtransitionofCLKBlatchesthestatesofSIZ0,SIZ1,andBE,andthefollowingLOW-to-
(PortB) HIGHtransitionofCLKBimplements thelatchedstates as aportBbus size.PortBbus sizes canbelong
word, word, or byte. AHIGH on both SIZ0 and SIZ1 chooses a mailbox register for a port B 36-bit writeor
read.
SW0,
SW1
Port B Byte Swap
Selects
I
At the beginning of each long word FIFO read, one of four modes of byte-order swapping is selected by
(PortB) SW0 and SW1. The four modes are no swap, byte swap, word swap, and byte-word swap. Byte-order
swappingispossiblewithanybus-sizeselection.
W/RA
W/RB
PortAWrite/Read
Select
I
A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-HIGH
transitionofCLKA. The A0-A35outputs are inthe high-impedance state whenW/RAis HIGH.
PortBWrite/Read
Select
I
A HIGH selects a write operation and a LOW selects a read operation on port B for a LOW-to-HIGH
transitionofCLKB.The B0-B35outputs are inthe high-impedance state whenW/RBis HIGH.
JUNE 9, 2005
5
IDT72V36133.3V,CMOSCLOCKEDFIFOWITH
BUS-MATCHINGANDBYTESWAPPING64x36
COMMERCIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGSOVEROPERATINGFREE-AIRTEMPERATURE
RANGE (unless otherwise noted)(1)
Symbol
Rating
Commercial
–0.5to+4.6
–0.5 to VCC+0.5
–0.5 to VCC+0.5
±20
Unit
V
VCC
SupplyVoltageRange
InputVoltageRange
OutputVoltageRange
(2)
VI
V
(2)
VO
V
IIK
Input Clamp Current, (VI < 0 or VI > VCC)
Output Clamp Current, (VO < 0 or VO > VCC)
Continuous Output Current, (VO = 0 to VCC)
Continuous Current Through VCC or GND
StorageTemperatureRange
mA
mA
mA
mA
°C
IOK
±50
IOUT
ICC
±50
±500
TSTG
–65 to 150
NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions
for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
RECOMMENDEDOPERATING
CONDITIONS
Symbol
Parameter
Min. Typ.
Max.
3.6
Unit
V
(1)
VCC
SupplyVoltage
3.0 3.3
VIH
VIL
IOH
IOL
TA
HIGH Level Input Voltage
LOW-LevelInputVoltage
HIGH-LevelOutputCurrent
LOW-LevelOutputCurrent
2
—
—
—
—
—
VCC+0.5
0.8
V
—
—
—
0
V
–4
mA
mA
°C
8
OperatingFree-air
Temperature
70
NOTE:
1. For 12ns (83MHz operation), Vcc=3.3V +/-0.15V, JEDEC JESD8-A compliant
ELECTRICALCHARACTERISTICSOVERRECOMMENDEDOPERATING
FREE-AIRTEMPERATURERANGE(unlessotherwisenoted)
IDT72V3613
Commercial
tCLK = 12, 15, 20 ns
Symbol
Parameter
OutputLogic"1"Voltage
Test Conditions
Min.
Typ.(1)
Max.
Unit
VOH
VCC = 3.0V,
VCC = 3.0V,
VCC = 3.6V,
VCC = 3.6V,
VCC = 3.6V,
VI = 0,
IOH = –4 mA
2.4
—
—
V
VOL
ILI
OutputLogic"0"Voltage
Input Leakage Current (Any Input)
OutputLeakageCurrent
StandbyCurrent
IOL = 8 mA
—
—
—
—
—
—
—
—
—
—
4
0.5
±5
±5
500
—
V
VI = VCC or 0
VO = VCC or 0
µA
µA
µA
pF
pF
ILO
ICC(2)
CIN
COUT
VI = VCC - 0.2V or 0
InputCapacitance
f = 1 MHz
f = 1 MHZ
OutputCapacitance
VO = 0,
8
—
NOTES:
1. All typical values are at VCC = 3.3V, TA = 25°C.
2. For additional ICC information, see Figure 1, Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS).
6
JUNE 9, 2005
IDT72V36133.3V,CMOSCLOCKEDFIFOWITH
BUS-MATCHINGANDBYTESWAPPING64x36
COMMERCIALTEMPERATURERANGE
DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION
TheICC(f)currentforthegraphinFigure1wastakenwhilesimultaneouslyreadingandwritingtheFIFOontheIDT72V3613withCLKAandCLKBset
tofS.Alldateinputsanddataoutputschangestateduringeachclockcycletoconsumethehighestsupplycurrent.Dataoutputsweredisconnectedtonormalize
thegraphtoazero-capacitanceload.Oncethecapacitiveleadperdata-outputchannelisknown,thepowerdissipationcanbecalculatedwiththeequation
below.
CALCULATING POWER DISSIPATION
WithICC(f)takenfromFigure1,themaximumpowerdissipation(PT)oftheIDT72V3613maybecalculatedby:
PT = VCC x ICC(f) + Σ(CL x (VOH - VOL)2 x fo)
N
where:
N
=
=
=
=
=
number of used outputs (36-bit (long word), 18-bit (word) or 9-bit (byte) bus-size)
outputcapacitanceload
CL
fo
switchingfrequencyofanoutput
VOH
VOL
outputhigh-levelvoltage
outputhigh-levelvoltage
WhennoreadsorwritesareoccurringontheIDT72V3613,thepowerdissipatedbyasingleclock(CLKAorCLKB)inputrunningatfrequencyfSiscalculated
PT = VCC x fS x 0.025mA/MHz
by:
Figure 1. Typical Characteristics: Supply Current (ICC) vs Clock Frequency (fS)
JUNE 9, 2005
7
IDT72V36133.3V,CMOSCLOCKEDFIFOWITH
BUS-MATCHINGANDBYTESWAPPING64x36
COMMERCIALTEMPERATURERANGE
ACELECTRICALCHARACTERISTICSOVERRECOMMENDEDRANGESOF
SUPPLYVOLTAGEANDOPERATINGFREE-AIRTEMPERATURE
Commercial: Vcc=3.3V± 0.30V; for 12ns (83MHz) operation, Vcc=3.3V ±0.15V; TA = 0°C to +70°C; JEDEC JESD8-A compliant
IDT72V3613L12
IDT72V3613L15
IDT72V3613L20
Symbol
fS
Parameter
Min.
–
Max.
83
–
Min.
–
Max.
Min.
–
Max.
50
–
Unit
MHz
ns
Clock Frequency, CLKA or CLKB
66.7
–
tCLK
tCLKH
tCLKL
tDS
Clock Cycle Time, CLKA or CLKB
12
5
15
6
20
8
Pulse Duration, CLKA and CLKB HIGH
PulseDuration, CLKAandCLKBLOW
Setup Time, A0-A35 before CLKA↑ and B0-B35 before CLKB↑
–
–
–
ns
5
–
6
–
8
–
ns
4
–
4
–
5
–
ns
tENS
Setup Time, CSA, W/RA, ENA, and MBA before CLKA↑;
CSB, W/RB, and ENB before CLKB↑
3.5
–
5
–
5
–
ns
tSZS
tSWS
tPGS
tRSTS
tFSS
tDH
Setup Time, SIZ0, SIZ1, and BE before CLKB↑
SetupTime,SW0andSW1beforeCLKB↑
3.5
4
–
–
–
–
–
–
–
4
6
4
5
5
1
1
–
–
–
–
–
–
–
5
7
5
6
6
1
1
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
(1)
SetupTime, ODD/EVEN andPGBbefore CLKB↑
Setup Time, RST LOW before CLKA↑ or CLKB↑(2)
3
4
Setup Time, FS0 and FS1 before RST HIGH
4
Hold Time, A0-A35 after CLKA↑and B0-B35 after CLKB↑
0.5
0.5
tENH
Hold Time, CSA W/RA, ENA and MBA after CLKA↑; CSB,
W/RB,andENBafterCLKB↑
tSZH
tSWH
tPGH
tRSTH
tFSH
Hold Time, SIZ0, SIZ1, and BE after CLKB↑
HoldTime,SW0andSW1afterCLKB↑
1
1
–
–
–
–
–
–
–
2
2
–
–
–
–
–
–
–
2
2
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
(1)
HoldTime, ODD/EVENandPGBafter CLKB↑
0
0
0
(2)
HoldTime, RST LOWafterCLKA↑orCLKB↑
4
5
6
Hold Time, FS0 and FS1 after RST HIGH
4
4
4
tSKEW1(3) Skew Time, between CLKA↑ and CLKB↑ for EF and FF
tSKEW2(3,4) Skew Time, between CLKA↑ and CLKB↑ for AE and AF
5.5
14
8
8
14
16
NOTES:
1. Only applies for a clock edge that does a FIFO read.
2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
4. Design simulated, not tested.
8
JUNE 9, 2005
IDT72V36133.3V,CMOSCLOCKEDFIFOWITH
BUS-MATCHINGANDBYTESWAPPING64x36
COMMERCIALTEMPERATURERANGE
SWITCHINGCHARACTERISTICSOVERRECOMMENDEDRANGESOFSUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30pF
Commercial: Vcc=3.3V± 0.30V; for 12ns (83MHz) operation, Vcc=3.3V ±0.15V; TA = 0°C to +70°C; JEDEC JESD8-A compliant
IDT72V3613L12
IDT72V3613L15
IDT72V3613L20
Symbol
tA
Parameter
Min.
1
Max.
Min.
2
Max.
10
10
10
10
10
9
Min.
2
Max.
12
Unit
ns
Access Time,CLKA↑toA0-A35andCLKB↑toB0-B35
PropagationDelayTime, CLKA↑toFF
PropagationDelayTime,CLKB↑toEF
PropagationDelayTime,CLKB↑toAE
PropagationDelayTime,CLKA↑toAF
8
8
8
8
8
8
tWFF
tREF
tPAE
tPAF
1
2
2
12
ns
1
2
2
12
ns
1
2
2
12
ns
1
2
2
12
ns
tPMF
Propagation Delay Time, CLKA↑ toMBF1 LOW orMBF2
HIGH and CLKB↑ to MBF2 LOW or MBF1 HIGH
1
1
1
12
ns
tPMR
PropagationDelayTime, CLKA↑toB0-B35(1)andCLKB↑
2
8
2
10
2
12
ns
toA0-A35(2)
(3)
tPPE
Propagationdelaytime,CLKB↑toPEFB
2
1
2
8
8
8
2
1
2
10
10
10
2
1
2
12
11.5
11
ns
ns
ns
tMDV
Propagation Delay Time, SIZ1, SIZ0 to B0-B35 valid
tPDPE
Propagation Delay Time, A0-A35 valid to PEFA valid;
B0-B35 valid to PEFB valid
tPOPE
Propagation Delay Time, ODD/EVEN to PEFA and PEFB
2
2
8
8
2
2
10
10
2
2
12
12
ns
ns
(4)
tPOPB
PropagationDelayTime, ODD/EVENtoparitybits (A8, A17,
A26, A35) and (B8, B17, B26, B35)
tPEPE
Propagation Delay Time, CSA, ENA, W/RA, MBA, or PGA
to PEFA; CSB, ENB, W/RB, SIZ1, SIZ0, or PGB to PEFB
1
2
8
8
1
2
10
10
1
2
12
12
ns
ns
(4)
tPEPB
Propagation Delay Time, CSA, ENA, W/RA, MBA, or PGA
to parity bits (A8, A17, A26, A35); CSB, ENB, W/RB, SIZ1,
SIZ0, or PGB to parity bits (B8, B17, B26, B35)
tRSF
tEN
Propagation Delay Time, RST to AE, EF LOW and AF,
MBF1, MBF2 HIGH
1
2
10
6
1
2
15
10
1
2
20
12
ns
ns
Enable Time,CSA andW/RALOWtoA0-A35
active andCSB LOWandW/RBHIGHto
B0-B35active
tDIS
Disable Time, CSA or W/RA HIGH to A0-A35 at high-
impedance andCSB HIGHorW/RBLOWtoB0-B35at
high-impedance
1
6
1
8
1
9
ns
NOTES:
1. Writing data to the mail1 register when the B0-B35 outputs are active and SIZ1 and SIZ0 are HIGH.
2. Writing data to the mail2 register when the A0-A35 outputs are active.
3. Only applies when a new port-B bus size is implemented by the rising CLKB edge.
4. Only applies when reading data from a mail register.
JUNE 9, 2005
9
IDT72V36133.3V,CMOSCLOCKEDFIFOWITH
BUS-MATCHINGANDBYTESWAPPING64x36
COMMERCIALTEMPERATURERANGE
Data is loaded into the FIFO from the A0-A35 inputs on a LOW-to-HIGH
transitionofCLKAwhenCSA is LOW, W/RAis HIGH, ENAis HIGH, MBAis
LOW,andFF isHIGH(seeTable2).TherelevantFIFOwritetimingdiagram
can found in Figure 6.
ThestateoftheportBdata(B0-B35)outputsiscontrolledbytheportB
Chip Select (CSB) and the port B Write/Read select (W/RB). The B0-B35
outputsareinthehigh-impedancestatewheneitherCSBorW/RBisHIGH.The
B0-B35outputsareactivewhenbothCSBandW/RBareLOW. Dataisread
fromtheFIFOtotheB0-B35outputsbyaLOW-to-HIGHtransitionofCLKBwhen
CSB is LOW, W/RB is LOW, ENB is HIGH, EFB is HIGH, and either SIZ0 or
SIZ1isLOW(seeTable3).RelevantFIFOreadtimingdiagramstogetherwith
Bus-Matching, EndianselectandByte-swappingoperation canbe foundin
Figures 7, 8 and 9.
FUNCTIONALDESCRIPTION
RESET (RST)
TheIDT72V3613isresetbytakingtheReset(RST)inputLOWforatleast
four port A Clock (CLKA) and four port B Clock (CLKB) LOW-to-HIGH
transitions.TheResetinputcanswitchasynchronouslytotheclocks. Adevice
resetinitializestheinternalreadandwritepointersoftheFIFOandforcesthe
FullFlag(FF)LOW,theEmptyFlag(EF)LOW,theAlmost-Emptyflag(AE)LOW,
and the Almost-Full flag (AF) HIGH. A reset also forces the Mailbox Flags
(MBF1, MBF2)HIGH. Aftera reset, FF is setHIGHaftertwoLOW-to-HIGH
transitions ofCLKA. The device mustbe resetafterpowerupbefore data is
writtentoitsmemory.
A LOW-to-HIGH transition on the RST input loads the Almost-Full and
Almost-EmptyOffsetregister(X)withthevalueselectedbytheFlagSelect(FS0,
FS1)inputs. ThevaluesthatcanbeloadedintotheregisterareshowninTable
1.SeeFigure5forrelevantFIFOResetandpresetvalueloadingtimingdiagram.
Thesetupandhold-timeconstraintstotheportclocksfortheportChipSelects
(CSA,CSB)andWrite/Readselects(W/RA,W/RB)areonlyforenablingwrite
andreadoperationsandarenotrelatedtohigh-impedancecontrolofthedata
outputs. IfaportenableisLOWduringaclockcycle,theport’sChipSelectandWrite/
Readselectcanchangestatesduringthesetupandholdtimewindowofthecycle.
FIFO WRITE/READ OPERATION
ThestateoftheportAdata(A0-A35)outputsiscontrolledbytheport-AChip
Select(CSA)andtheport-AWrite/Readselect(W/RA).TheA0-A35outputs
areinthehigh-impedancestatewheneitherCSAorW/RAis HIGH.TheA0-
A35outputs are active whenbothCSA andW/RAare LOW.
SYNCHRONIZED FIFO FLAGS
EachFIFOflagissynchronizedtoitsportclockthroughtwoflip-flopstages.
This is done to improve the flags’ reliability by reducing the probability of
metastableeventsontheiroutputswhenCLKAandCLKBoperateasynchro-
nouslytooneanother. FFandAFaresynchronizedtoCLKA. EFandAEare
synchronizedtoCLKB. Table4showstherelationshipofeachportflagtothe
levelofFIFOfill.
TABLE 1 – FLAG PROGRAMMING
ALMOST-FULL AND
FS1
FS0
RST
ALMOST-EMPTYFLAG
OFFSET REGISTER (X)
H
H
L
L
H
L
H
L
↑
↑
↑
↑
16
12
8
EMPTY FLAG (EF)
TheFIFOEmptyFlagissynchronizedtotheportclockthatreadsdatafrom
itsarray(CLKB). WhentheEFisHIGH,newdatacanbereadtotheFIFOoutput
register. WhentheEFisLOW,theFIFOisemptyandattemptedFIFOreads
4
TABLE 2 – PORT A ENABLE FUNCTION TABLE
CSA
W/RA
ENA
MBA
CLKA
Data A (A0-A35) I/O
Port Function
H
X
X
X
X
Input
None
L
L
L
L
L
L
L
H
H
H
L
L
L
L
L
H
H
L
X
L
X
↑
Input
Input
None
FIFOwrite
H
L
↑
X
↑
X
↑
Input
Mail1write
Output
Output
Output
Output
None
H
L
L
None
None
H
H
H
Mail2 read (set MBF2 HIGH)
TABLE 3 – PORT B ENABLE FUNCTION TABLE
CSB
W/RB
ENB
SIZ1, SIZ0
CLKB
Data B (B0-B35) I/O
Port Function
H
X
X
X
X
Input
None
L
L
L
L
L
L
L
H
H
H
L
L
L
L
L
H
H
L
X
X
↑
↑
X
↑
X
↑
Input
Input
None
One,bothLOW
BothHIGH
None
Mail2write
Input
One,bothLOW
One,bothLOW
BothHIGH
Output
Output
Output
Output
None
H
L
FIFO read
None
H
BothHIGH
Mail1 read (set MBF1 HIGH)
10
JUNE 9, 2005
IDT72V36133.3V,CMOSCLOCKEDFIFOWITH
BUS-MATCHINGANDBYTESWAPPING64x36
COMMERCIALTEMPERATURERANGE
are ignored. Whenreadingthe FIFOwitha byte orwordsize onportB,EFis X or less long words in memory and is HIGH when the FIFO contains (X+1)
setLOWwhenthefourthbyteorsecondwordofthelastlongwordis read.
TheFIFOreadpointerisincrementedeachtimeanewwordisclockedto
or more long words.
TwoLOW-to-HIGHtransitionsontheportBClock(CLKB)arerequiredafter
itsoutputregister. ThestatemachinethatcontrolstheEFmonitorsawrite-pointer aFIFOwritefortheAEflagtoreflectthenewleveloffill. Therefore,theAEflag
andread-pointercomparatorthatindicateswhentheFIFOmemorystatusis ofaFIFOcontaining(X+1)ormorelongwordsremainsLOWiftwoCLKBcycles
empty, empty+1, orempty+2. Awordwrittentothe FIFOcanbe readtothe havenotelapsedsincethewritethatfilledthememorytothe(X+1)level. The
FIFO output register in a minimum of three port B clock (CLKB) cycles. AEflagissetHIGHbythesecondCLKBLOW-to-HIGHtransitionaftertheFIFO
Therefore,anEFisLOWifawordinmemoryisthenextdatatobesenttothe writethatfillsmemorytothe(X+1)level. ALOW-to-HIGHtransitionofCLKB
FIFOoutputregisterandtwoCLKBcycleshavenotelapsedsincethetimethe beginsthefirstsynchronizationcycle ifitoccursattimetSKEW2orgreaterafter
wordwaswritten. TheEFoftheFIFOissetHIGHbythesecondLOW-to-HIGH thewritethatfillstheFIFOto(X+1)longwords. Otherwise,thesubsequentCLKB
transition of CLKB, and the new data word can be read to the FIFO output cycle canbe the firstsynchronizationcycle (see Figure 12).
registerinthefollowingcycle.
ALOW-to-HIGHtransitiononCLKBbeginsthefirstsynchronizationcycle ALMOST FULL FLAG (AF)
ofawriteiftheclocktransitionoccursattimetSKEW1orgreaterafterthewrite.
TheFIFOAlmost-Fullflagissynchronizedtotheportclockthatwritesdata
Otherwise,thesubsequentCLKBcyclecanbethefirstsynchronizationcycle toitsarray(CLKA). ThestatemachinethatcontrolsanAFflagmonitorsawrite-
(see Figure 10).
pointer and read-pointer comparator that indicates when the FIFO memory
statusisalmost-full,almost-full-1,oralmost-full-2. Thealmost-fullstateisdefined
bythevalueoftheAlmost-FullandAlmost-EmptyOffsetregister(X). Thisregister
FULL FLAG (FF)
TheFIFOFullFlagissynchronizedtotheportclockthatwritesdatatoits isloadedwithoneoffourpresetvaluesduringadevicereset(seeResetsection).
array(CLKA). WhentheFFisHIGH,aFIFOmemorylocationisfreetoreceive The AF flag is LOW when the FIFO contains (64-X) or more long words in
newdata. NomemorylocationsarefreewhentheFFisLOWandattempted memoryandis HIGHwhentheFIFOcontains [64-(X+1)]orless longwords.
writes to the FIFO are ignored.
TwoLOW-to-HIGHtransitionsontheportAClock(CLKA)arerequiredafter
EachtimeawordiswrittentotheFIFO,itswrite-pointerisincremented. The aFIFOreadfortheAFflagtoreflectthenewleveloffill. Therefore,theAFflag
statemachinethatcontrolstheFFmonitorsawrite-pointerandread-pointer ofaFIFOcontaining[64-(X+1)]orlesswordsremainsLOWiftwoCLKAcycles
comparatorthatindicateswhentheFIFOmemorystatusisfull,full-1,orfull-2. have not elapsed since the read that reduced the number of long words in
FromthetimeawordisreadfromtheFIFO,itspreviousmemorylocationisready memoryto[64-(X+1)]. TheAFflagissetHIGHbythesecondCLKALOW-to-
tobewritteninaminimumofthreeCLKAcycles.Therefore,aFFisLOWifless HIGHtransitionaftertheFIFOreadthatreducesthenumberoflongwordsin
thantwoCLKAcycleshaveelapsedsincethenextmemorywritelocationhas memory to [64-(X+1)]. A LOW-to-HIGH transition on CLKA begins the first
beenread.ThesecondLOW-to-HIGHtransitionontheFFsynchronizingclock synchronizationcycleifitoccurs attimetSKEW2 orgreaterafterthereadthat
afterthereadsetstheFFHIGHanddatacanbewritteninthefollowingclockcycle. reduces the number of long words in memory to [64-(X+1)]. Otherwise, the
ALOW-to-HIGHtransitiononCLKAbeginsthefirstsynchronizationcycle subsequentCLKAcyclecanbethefirstsynchronizationcycle(seeFigure13).
ofa readifthe clocktransitionoccurs attime tSKEW1 orgreaterafterthe read.
Otherwise,thesubsequentclockcyclecanbethefirstsynchronizationcycle MAILBOX REGISTERS
(see Figure 11).
Two36-bitbypassregisters(mail1,mail2)areontheIDT72V3613topass
commandandcontrolinformationbetweenportAandportBwithoutputtingit
inqueue.ALOW-to-HIGHtransitiononCLKAwritesA0-A35datatothemail1
ALMOST-EMPTYFLAG(AE)
TheFIFOAlmost-Emptyflagissynchronizedtotheportclockthatreadsdata registerwhenaportAwriteisselectedbyCSA,W/RA,andENAwithMBAHIGH.
fromitsarray(CLKB).ThestatemachinethatcontrolstheAEflagmonitorsa ALOW-to-HIGHtransitiononCLKBwritesB0-B35datatothemail2register
write-pointer and read-pointer comparator that indicates when the FIFO when a port B write is selected by CSB, W/RB and ENB, and both SIZ0 and
memory status is almost-empty, almost-empty+1, or almost-empty+2. The SIZ1areHIGH. Writingdatatoamailregistersetsitscorrespondingflag(MBF1
almost-emptystateisdefinedbythevalueoftheAlmost-FullandAlmost-Empty orMBF2)LOW. Attemptedwritestoamailregisterareignoredwhileitsmail
Offsetregister(X).Thisregisterisloadedwithoneoffourpresetvaluesduring flagisLOW.
adevicereset(seeresetabove). TheAEflagisLOWwhentheFIFOcontains
WhentheportBdata(B0-B35)outputsareactive,thedataonthebuscomes
fromtheFIFOoutputregisterwheneitheroneorbothSIZ1andSIZ0areLOW
and from the mail1 register when both SIZ1 and SIZ0 are HIGH. The Mail1
RegisterFlag(MBF1)is setHIGHbyarisingCLKBedgewhenaportBread
isselectedbyCSB,W/RB,andENB,andbothSIZ1andSIZ0HIGH. TheMail2
RegisterFlag(MBF2)is setHIGHbyarisingCLKAedgewhenaportAread
isselectedbyCSA,W/RA,andENAwithMBAHIGH. Thedatainamailregister
remainsintactafteritisreadandchangesonlywhennewdataiswrittentothe
register.SeeFigure14and15forrelevantmailregisterandmailregisterflag
timingdiagrams.
TABLE 4 – FIFO FLAG OPERATION
SYNCHRO-
NIZED
TO CLKB
SYNCHRO-
NIZED
TOCLKA
NUMBER OF 36-BIT
(1)
WORDS IN THE FIFO
EF
AE
AF
FF
0
1 to X
L
H
H
H
H
L
L
H
H
H
L
H
H
H
H
L
(X+ 1) to [64 - (X + 1)]
(64 - X) to 63
64
H
H
H
DYNAMIC BUS SIZING
The portBbus canbe configuredina 36-bitlongword, 18-bitword, or9-
bitbyteformatfordatareadfromtheFIFO.Word-andbyte-sizebusselections
canutilizethemostsignificantbytesofthebus(Big-Endian)orleastsignificant
bytesofthebus(Little-Endian).PortBbus-sizecanbechangeddynamically
andsynchronoustoCLKB tocommunicatewithperipheralsofvariousbuswidths.
L
NOTE:
1. X is the value in the Almost-Empty flag and Almost-Full flag Offset register
JUNE 9, 2005
11
IDT72V36133.3V,CMOSCLOCKEDFIFOWITH
BUS-MATCHINGANDBYTESWAPPING64x36
COMMERCIALTEMPERATURERANGE
ThelevelsappliedtotheportBbus-sizeselect(SIZ0,SIZ1)inputsandthe portBdatainputsthatarevalidforthebus-sizeimplementationisreportedby
Big-Endianselect(BE)inputarestoredoneachCLKBLOW-to-HIGHtransition. alowlevelontheportBParityErrorFlag(PEFB).OddorEvenparitychecking
ThestoredportBbus-sizeselectionisimplementedbythenextrisingedgeon can be selected, and the Parity Error Flags can be ignored if this feature is not
CLKB according to Figure 2.
desired.
ParitystatusischeckedoneachinputbusaccordingtotheleveloftheOdd/
Only36-bitlong-worddataiswrittentoorreadfromtheFIFOmemoryon
theIDT72V3613.Bus-matchingoperationsaredoneafterdataisreadfromthe Evenparity(ODD/EVEN)selectinput. Aparityerrorononeormorevalidbytes
FIFORAM. PortBbus sizingdoes notapplytomailregisteroperations.
ofaportisreportedbyaLOWlevelonthecorrespondingportParityErrorFlag
(PEFA,PEFB)output. PortAbytesarearrangedasA0-A8,A9-A17,A18-A26,
andA27-A35,andportBbytesarearrangedasB0-B8,B9-B17,B18-B26,and
BUS-MATCHING FIFO READS
DataisreadfromtheFIFORAMin36-bitlong-wordincrements.Ifalong- B27-B35,anditsvalidbytesarethoseusedinaportBbussizeimplementation.
wordbus-sizeisimplemented,theentirelongwordimmediatelyshiftstothe WhenOdd/Evenparityis selected, a portParityErrorFlag(PEFA,PEFB)is
FIFOoutputregisteruponaread.Ifbyteorwordsizeisimplementedonport LOWifanybyte onthe porthas anodd/evennumberofLOWlevels applied
B, onlythe firstone ortwobytes appearonthe selectedportionofthe FIFO toitsbits.
outputregister,withtherestofthelongwordstoredinauxiliaryregisters.In
The fourparitytrees usedtocheckthe A0-A35inputs are sharedbythe
this case, subsequent FIFO reads with the same bus-size implementation mail2registerwhenparitygenerationisselectedforport-Areads(PGA=HIGH).
outputtherestofthelongwordtotheFIFOoutputregisterintheordershown WhenaportAreadfromthemail2registerwithparitygenerationisselectedwith
by Figure 2.
CSA LOW, ENAHIGH, W/RALOW, MBAHIGH, andPGAHIGH, the portA
EachFIFOreadwithanewbus-sizeimplementationautomaticallyunloads ParityErrorFlag(PEFA)is heldHIGHregardless ofthelevels appliedtothe
datafromtheFIFORAMtoitsoutputregisterandauxiliaryregisters.Therefore, A0-A35inputs. Likewise,theparitytreesusedtochecktheB0-B35inputsare
implementinganewportBbus-sizeandperformingaFIFOreadbeforeallbytes sharedbythemail1registerwhenparitygenerationisselectedforportBreads
orwordsstoredintheauxiliaryregistershavebeenreadresultsinalossofthe (PGB=HIGH). WhenaportBreadfromthemail1registerwithparitygeneration
unreaddataintheseregisters.
isselectedwithCSBLOW,ENBHIGH,W/RBLOW,bothSIZ0andSIZ1HIGH,
WhenreadingdatafromFIFOinbyteorwordformat,theunusedB0-B35 andPGBHIGH,theportBParityErrorFlag(PEFB)isheldHIGHregardless
outputsareindeterminate.
ofthelevelsappliedtotheB0-B35inputs.
BYTE SWAPPING
PARITYGENERATION
Thebyte-orderarrangementofdatareadfromtheFIFOcanbechanged
AHIGHlevelonthe portAParityGenerate select(PGA)orportBParity
synchronoustotherisingedgeofCLKB.Byte-orderswappingisnotavailable Generateselect(PGB)enablestheIDT72V3613togenerateparitybitsforport
formailregisterdata.Fourmodesofbyte-orderswapping(includingnoswap) reads froma FIFOormailboxregister. PortAbytes are arrangedas A0-A8,
can be done with any data port size selection. The order of the bytes are A9-A17,A18-A26,andA27-A35,withthemostsignificantbitofeachbyteused
rearranged within the long word, but the bit order within the bytes remains astheparitybit. PortBbytesarearrangedasB0-B8,B9-B17,B18-B26,and
constant.
B27-B35,withthemostsignificantbitofeachbyteusedastheparitybit. Awrite
BytearrangementischosenbytheportBSwapselect(SW0,SW1)inputs toa FIFOormailregisterstores the levels appliedtoallnine inputs ofa byte
on a CLKB rising edge that reads a new long word from the FIFO. The byte regardlessofthestateoftheParityGenerateselect(PGA,PGB)inputs.When
orderchosenonthefirstbyteorfirstwordofanewlongwordreadfromtheFIFO dataisreadfromaportwithparitygenerationselected,thelowereightbitsof
ismaintaineduntiltheentirelongwordistransferred,regardlessoftheSW0and eachbyteareusedtogenerateaparitybitaccordingtothelevelontheODD/
SW1statesduringsubsequentreads.Figure4isanexampleofthebyte-order EVENselect. Thegeneratedparitybitsaresubstitutedforthelevelsoriginally
swappingavailableforlongwordreads.Performingabyteswapandbus-size writtentothemostsignificantbitsofeachbyteasthewordisreadtothedata
simultaneouslyforaFIFOreadfirstrearrangesthebytesasshowninFigure outputs.
4, then outputs the bytes as shown in Figure 2.
ParitybitsforFIFOdataaregeneratedafterthedataisreadfromtheFIFO
memoryandbeforethedataiswrittentotheoutputregister. Therefore,theport
AParityGenerateselect(PGA)andOdd/Evenparityselect(ODD/EVEN)have
PORT-B MAIL REGISTER ACCESS
InadditiontoselectingportBbussizesforFIFOreads,theportBbusSize setupandholdtimeconstraintstotheportAClock(CLKA)andtheportBParity
select(SIZ0,SIZ1)inputsalsoaccessthemailregisters.WhenbothSIZ0and Generate select (PGB) and ODD/EVEN select have setup and hold time
SIZ1areHIGH,themail1registerisaccessedforaportBlong-wordreadand constraintstotheportBClock(CLKB).Thesetimingconstraintsonlyapplyfor
themail2registerisaccessedforaportBlong-wordwrite.Themailregisteris a risingclockedge usedtoreada newlongwordtothe FIFOoutputregister
accessedimmediatelyandanybus-sizingoperationthatcanbeunderwayis (see Figure 16 and 17).
unaffectedbythemailregisteraccess.Afterthemailregisteraccessiscomplete,
Thecircuitusedtogenerateparityforthemail1dataissharedbytheport
thepreviousFIFOaccesscanresumeinthenextCLKBcycle.Thelogicdiagram Bbus(B0-B35)tocheckparityandthecircuitusedtogenerateparityforthe
inFigure3showsthepreviousbus-sizeselectionispreservedwhenthemail mail2datais sharedbytheportAbus (A0-A35)tocheckparity. Theshared
registersareaccessedfromportB.AportBbus-sizeisimplementedoneach paritytreesofaportareusedtogenerateparitybitsforthedatainamailregister
risingCLKBedgeaccordingtothestates ofSIZ0_Q,SIZ1_Q,andBE_Q.
whentheportChipSelect(CSA,CSB)isLOW,Enable(ENA,ENB)isHIGH,
andWrite/Readselect(W/RA,W/RB)inputisLOW,themailregisterisselected
(MBAHIGHforportA;bothSIZ0andSIZ1areHIGHforportB),andportParity
PARITY CHECKING
TheportAdatainputs(A0-A35) andportBdatainputs(B0-B35)eachhave Generateselect(PGA,PGB)isHIGH. Generatingparityformailregisterdata
fourparitytreestochecktheparityofincoming(oroutgoing)data. Aparityfailure doesnotchangethecontentsoftheregister. ParityGenerationtiming,when
on one or more bytes of the port A data bus is reported by a low level on the reading from a mail register, can be found in Figure 18 and 19.
port A Parity Error Flag (PEFA). A parity failure on one or more bytes of the
12
JUNE 9, 2005
IDT72V36133.3V,CMOSCLOCKEDFIFOWITH
BUS-MATCHINGANDBYTESWAPPING64x36
COMMERCIALTEMPERATURERANGE
BYTE ORDER ON PORT A:
A35 A27
A26 A18
A17 A9
A8 A0
Write to FIFO
D
A
B
C
BYTE ORDER ON PORT B:
B35 B27
B26 B18
B17 B9
B8 B0
BE SIZ1 SIZ0
Read from FIFO
A
B
D
C
X
L
L
(a) LONG WORD SIZE
B35 B27
B26 B18
B17 B9
B8 B0
B8 B0
BE SIZ1 SIZ0
A
B
1st: Read from FIFO
2nd: Read from FIFO
L
L
H
B35 B27
B26 B18
B17 B9
D
C
(b) WORD SIZE
BIG-ENDIAN
B17 B9
C
B35 B27
B35 B27
B26 B18
B8 B0
BE SIZ1 SIZ0
1st: Read from FIFO
2nd: Read from FIFO
D
H
L
H
B26 B18
B17 B9
B8 B0
A
B
(c) WORD SIZE
LITTLE-ENDIAN
B35 B27
B26 B18
B17 B9
B8 B0
B8 B0
B8 B0
B8 B0
BE SIZ1 SIZ0
1st: Read from FIFO
2nd: Read from FIFO
A
L
H
L
B35 B27
B26 B18
B26 B18
B17 B9
B17 B9
B17 B9
B
B35 B27
C
3rd: Read from FIFO
B35 B27
B26 B18
D
4th: Read from FIFO
4661 fig 01
(d) BYTE SIZE
BIG-ENDIAN
Figure 2. Dynamic Bus Sizing
JUNE 9, 2005
13
IDT72V36133.3V,CMOSCLOCKEDFIFOWITH
BUS-MATCHINGANDBYTESWAPPING64x36
COMMERCIALTEMPERATURERANGE
B35 B27 B26 B18
B17 B9
B17 B9
A17 A9
B8 B0
BE SIZ1 SIZ0
D
1st: Read from FIFO
2nd: Read from FIFO
H
H
L
B35 B27 B26 B18
A35 A27 A26 A18
B35 B27 B26 B18
B8 B0
C
A8 A0
B
3rd: Read from FIFO
B17 B9
B8 B0
A
4th: Read from FIFO
4661 fig 01a
(d) BYTE SIZE
LITTLE-ENDIAN
Figure 2. Dynamic Bus Sizing (Continued)
CLKB
MUX
G1
SIZ0 Q
SIZ1 Q
BE Q
1
D
1
Q
SIZ0
SIZ1
BE
4661 fig 02
Figure 3. Logic Diagram for SIZ0, SIZ1, and BE Register
14
JUNE 9, 2005
IDT72V36133.3V,CMOSCLOCKEDFIFOWITH
BUS-MATCHINGANDBYTESWAPPING64x36
COMMERCIALTEMPERATURERANGE
A35 A27
A26 A18
A17 A9
A8 A0
SW1 SW0
D
A
B
C
L
L
A
B
D
C
B35 B27
B26 B18
B17 B9
B8 B0
(a) NO SWAP
A35 A27
A26 A18
A17 A9
A8 A0
SW1 SW0
A
B
C
D
L
H
D
C
B
A
B35 B27
B26 B18
B17 B9
B8 B0
(b) BYTE SWAP
A35 A27
A26 A18
A17 A9
A8 A0
SW1 SW0
A
B
C
D
H
L
C
D
A
B
B35 B27
B26 B18
B17 B9
B8 B0
(c) WORD SWAP
A35 A27
A26 A18
A17 A9
A8 A0
SW1 SW0
A
B
C
D
H
H
B
A
C
D
B35 B27
B26 B18
B17 B9
B8 B0
(d) BYTE-WORD SWAP
4661 fig 03
Figure 4. Byte Swapping for FIFO Reads (Long-Word Size Example)
JUNE 9, 2005
15
IDT72V36133.3V,CMOSCLOCKEDFIFOWITH
BUS-MATCHINGANDBYTESWAPPING64x36
COMMERCIALTEMPERATURERANGE
CLKA
CLKB
tRSTH
t
RSTS
t
FSS
t
FSH
RST
FS1,FS0
FF
0,1
t
WFF
t
WFF
t
REF
EF
AE
AF
t
PAE
t
PAF
t
RSF
MBF1,
MBF2
4661 drw 05
Figure 5. FIFO Reset and Loading the X Register with the Value of Eight
tCLK
tCLKH
tCLKL
CLKA
FF HIGH
tENH
tENS
CSA
tENH
tENS
W/RA
t
ENH
t
ENS
ENS
MBA
tENH
tENH
t
ENH
t
tENS
tENS
ENA
tDH
t
DS
W1(1)
A0 - A35
W2(1)
No Operation
ODD/
EVEN
tPDPE
tPDPE
PEFA
Valid
Valid
4661 drw 06
NOTE:
1. Written to the FIFO.
Figure 6. Port A Write Cycle Timing
16
JUNE 9, 2005
IDT72V36133.3V,CMOSCLOCKEDFIFOWITH
BUS-MATCHINGANDBYTESWAPPING64x36
COMMERCIALTEMPERATURERANGE
CLKB
HIGH
EF
CSB
W/RB
tENS
tENS
tENH
tENH
ENB
No Operation
tSWS
tSWH
SW1,
SW0
t
SZS
t
t
SZH
SZH
BE
t
SZS
SIZ1,
SIZ0
(1)
NOT (1,1) (1)
(0,0)
(0,0)
NOT (1,1)
t
PGS
tPGH
PGB,
ODD/
EVEN
tDIS
tA
tEN
tA
W1(2)
W2(2)
Previous Data
B0-B35
4661 drw 07
NOTES:
1. SIZ0 = HIGH and SIZ1 = HIGH selects the mail1 register for output on B0-B35.
2. Data read from FIFO1.
DATA SWAP TABLE FOR FIFO LONG-WORD READS
FIFO DATA WRITE
SWAP MODE
FIFODATAREAD
A35-A27
A26-A18
A17-A9
A8-A0
SW1
SW0
B35-B27
B26-B18
B17-B9
B8-B0
A
A
A
A
B
B
B
B
C
C
C
C
D
D
D
D
L
L
L
H
L
A
D
C
B
B
C
D
A
C
B
A
D
D
A
B
C
H
H
H
Figure 7. Port B Long-Word Read Cycle Timing
JUNE 9, 2005
17
IDT72V36133.3V,CMOSCLOCKEDFIFOWITH
BUS-MATCHINGANDBYTESWAPPING64x36
COMMERCIALTEMPERATURERANGE
CLKB
EF HIGH
CSB
W/RB
tENS
tENH
ENB
No Operation
tSWS
tSWH
SW1,
SW0
t
SZH
t
SZS
BE
t
SZH
t
SZS
SIZ1,
SIZ0
(0,1)
NOT (1,1)(1)
NOT (1,1) (1)
(0,1)
t
PGS
tPGH
PGB,
ODD/
EVEN
t
A
tEN
t
A
A
tDIS
Little
Previous Data
Read 1
Read 1
Read 2
Read 2
B0-B17
Endian(2)
tA
t
tDIS
Big
Previous Data
Endian(2)
B18-B35
4661 drw 08
NOTES;
1. SIZ0 = HIGH and SIZ1 = HIGH selects the mail1 register for output on B0-B35.
2. Unused word B0-B17 or B18-B35 are indeterminate.
DATA SWAP TABLE FOR FIFO WORD READS
FIFODATAREAD
FIFO DATA WRITE
SWAP MODE
READ
NO.
BIG-ENDIAN
LITTLE-ENDIAN
A35-A27
A26-A18
A17-A9
A8-A0
D
SW1
L
SW0
L
B35-B27
B26-B18
B17-B9
B8-B0
1
2
A
C
B
D
C
A
D
B
A
A
B
B
C
C
1
2
D
B
C
A
B
D
A
C
D
L
H
1
2
C
A
D
B
A
C
B
D
A
A
B
B
C
C
D
D
H
H
L
1
2
B
D
A
C
D
B
C
A
H
Figure 8. Port B Word Read-Cycle Timing
18
JUNE 9, 2005
IDT72V36133.3V,CMOSCLOCKEDFIFOWITH
BUS-MATCHINGANDBYTESWAPPING64x36
COMMERCIALTEMPERATURERANGE
CLKB
EF HIGH
CSB
W/RB
tENS
tENH
ENB
No Operation
tSWH
tSWS
SW1,
SW0
t
t
SZS
SZS
tSZH
BE
t
SZH
SIZ1,
SIZ0
(1,0)
(1,0)
(1,0)
Not (1,1) (1)
(1,0)
(1)
(1)
(1)
Not (1,1)
PGS
Not (1,1)
PGH
Not (1,1)
A
t
t
PGB,
ODD/
EVEN
tDIS
tEN
t
tA
tA
tA
Previous Data
Read 1
Read 2
Read 3
Read 4
Read 4
B0-B8
tDIS
tA
tA
tA
tA
B27-B35
Previous Data
Read 1
Read 2
Read 3
4661 drw 09
NOTES:
1. SIZ0 = HIGH and SIZ1 = HIGH selects the mail1 register for output on B0-B35.
2. Unused bytes B0-B26 or B9-B35 are indeterminate.
DATA SWAP TABLE FOR FIFO BYTE READS
FIFODATAREAD
FIFO DATA WRITE
SWAP MODE
READ
NO.
BIG-
LITTLE-
ENDIAN
ENDIAN
B35-B27
A
A35-A27
A26-A18
A17-A9
A8-A0
SW1
SW0
B8-B0
1
D
2
3
4
B
C
D
C
B
A
A
B
C
D
L
L
1
2
3
4
D
C
B
A
A
B
C
D
A
A
A
B
B
B
C
C
C
D
D
D
L
H
H
H
L
1
2
3
4
C
D
A
B
B
A
D
C
1
2
3
4
B
A
D
C
C
D
A
B
H
Figure 9. Port B Byte Read-Cycle Timing
JUNE 9, 2005
19
IDT72V36133.3V,CMOSCLOCKEDFIFOWITH
BUS-MATCHINGANDBYTESWAPPING64x36
COMMERCIALTEMPERATURERANGE
t
t
CLKH CLK tCLKL
CLKA
LOW
CSA
WRA HIGH
tENS
tENH
MBA
tENS
tENH
ENA
HIGH
FF
tDS
tDH
A0 - A35
W1
t
CLKtCLKL
t
SKEW1(1)
tCLKH
1
2
CLKB
t
REF
t
REF
FIFO Empty
EF
CSB LOW
LOW
LOW
W/RB
SIZ1,
SIZ0
tENS
tENH
ENB
tA
W1
B0 -B35
4661 drw 10
NOTES:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EF to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and
rising CLKB edge is less than tSKEW1, then the transition of EF HIGH may occur one CLKB cycle later than shown.
2. Port B size of long word is selected for the FIFO read by SIZ1 = LOW, SIZ0 = LOW. If port-B size is word or byte, EF is set LOW by the last word or byte read from the FIFO,
respectively.
Figure 10. EF Flag Timing and First Data Read when the FIFO is Empty
20
JUNE 9, 2005
IDT72V36133.3V,CMOSCLOCKEDFIFOWITH
BUS-MATCHINGANDBYTESWAPPING64x36
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKB
CSB
LOW
LOW
LOW
W/RB
SIZ1,
SIZ0
tENH
tENS
ENB
EF HIGH
tA
Previous Word in FIFO Output Register
B0 -B35
Next Word From FIFO
tCLK
(1)
SKEW1
tCLKL
tCLKH
t
1
2
CLKA
t
WFF
t
WFF
FIFO Full
FF
LOW
CSA
WRA HIGH
tENS
tENH
MBA
tENS
tENH
ENA
tDS
tDH
A0 - A35
To FIFO
4661 drw 11
NOTES:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for EF to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and
rising CLKA edge is less than tSKEW1, then the transition of EF HIGH may occur one CLKA cycle later than shown.
2. Port B size of long word is selected for the FIFO read by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, tSKEW1 is referenced from the rising CLKB edge that reads the
last word or byte of the long word, respectively.
Figure 11. FF Flag Timing and First Available Write when the FIFO is Full
CLKA
tENH
tENS
ENA
(1)
tSKEW2
1
2
CLKB
t
PAE
t
PAE
AE
X Long Words in FIFO
(X+1) Long Words in FIFO
tENH
tENS
ENB
4661 drw 12
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and
rising CLKB edge is less than tSKEW2, then AE may transition HIGH one CLKB cycle later than shown.
2. FIFO write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO read (CSB = LOW, W/RB = LOW, either SIZ0 = LOW or SIZ1 = LOW).
3. Port B size of long word is selected for the FIFO read by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, tSKEW2 is referenced to the last word or byte of the long word,
respectively.
Figure 12. Timing for AE when the FIFO is Almost-Empty
JUNE 9, 2005
21
IDT72V36133.3V,CMOSCLOCKEDFIFOWITH
BUS-MATCHINGANDBYTESWAPPING64x36
COMMERCIALTEMPERATURERANGE
(1)
tSKEW2
1
2
CLKA
tENH
tENS
ENA
t
PAF
t
PAF
(64-X) Long Words in FIFO
[64-(X+1)] Long Words in FIFO
AF
CLKB
ENB
tENS
tENH
4661 drw 13
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge and
rising CLKB edge is less than tSKEW2, then AF may transition HIGH one CLKA cycle later than shown.
2. FIFO write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO read (CSB = LOW, W/RB = LOW, either SIZ0 = LOW or SIZ1 = LOW).
3. Port-B size of long word is selected for FIFO read by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, tSKEW2 is referenced from the last word or byte read of the long
word, respectively.
Figure 13. Timing for AF when the FIFO is Almost-Full
CLKA
t
ENS
t
ENH
ENH
CSA
W/RA
MBA
tENS
t
tENH
t
ENS
ENS
t
tENH
ENA
A0 - A35
CLKB
tDH
t
DS
W1
t
PMF
t
PMF
MBF1
CSB
W/RB
SIZ1, SIZ0
ENB
tENH
tENS
t
PMR
tEN
t
MDV
tDIS
FIFO Output Register
W1 (Remains valid in Mail1 Register after read)
B0 - B35
4661 drw 14
NOTE:
1. Port-B parity generation off (PGB = LOW).
Figure 14. Timing for Mail1 Register and MBF1 Flag
22
JUNE 9, 2005
IDT72V36133.3V,CMOSCLOCKEDFIFOWITH
BUS-MATCHINGANDBYTESWAPPING64x36
COMMERCIALTEMPERATURERANGE
CLKB
t
ENS
ENS
t
ENH
ENH
CSB
t
t
W/RB
t
SZS
tSZH
SIZ1,
SIZ0
tENH
t
ENS
ENB
B0 - B35
CLKA
tDH
t
DS
W1
t
PMF
tPMF
MBF2
CSA
W/RA
MBA
ENA
tENH
tENS
tEN
t
PMR
tDIS
W1 (Remains valid in Mail2 Register after read)
A0 - A35
4661 drw 15
NOTE:
1. Port-A parity generation off (PGA = LOW).
Figure 15. Timing for Mail2 Register and MBF2 Flag
ODD/
EVEN
W/RA
MBA
PGA
t
PEPE
tPEPE
tPOPE
tPOPE
Valid
Valid
PEFA
Valid
Valid
4661 drw 16
NOTE:
1. CSA = LOW and ENA = HIGH.
Figure 16. ODD/EVEN, W/RA, MBA, and PGA to PEFA Timing
JUNE 9, 2005
23
IDT72V36133.3V,CMOSCLOCKEDFIFOWITH
BUS-MATCHINGANDBYTESWAPPING64x36
COMMERCIALTEMPERATURERANGE
ODD/
EVEN
W/RB
SIZ1,
SIZ0
PGB
t
PEPE
t
PEPE
tPOPE
tPOPE
PEFB
Valid
Valid
Valid
Valid
4661 drw 17
NOTE:
1. CSB = LOW and ENB = HIGH.
Figure 17. ODD/EVEN, W/RB, SIZ1, SIZ0, and PGB to PEFB Timing
ODD/
EVEN
LOW
CSA
W/RA
MBA
PGA
t
PEPB
tPEPB
t
POPB
tEN
A8, A17,
A26, A35
Mail2 Data
Generated Parity
Generated Parity
Mail2 Data
4661 drw 18
NOTE:
1. ENA = HIGH.
Figure 18. Parity Generation Timing when Reading from the Mail2 Register
ODD/
EVEN
LOW
CSB
W/RB
SIZ1,
SIZ0
PGB
t
PEPB
tEN
t
MDV
t
POPB
tPEPB
Generated Parity
B8, B17,
B26, B35
Generated Parity
Mail1 Data
4661 drw 19
Mail1
Data
NOTE:
1. ENB = HIGH.
Figure 19. Parity Generation Timing when Reading from the Mail1 Register
24
JUNE 9, 2005
IDT72V36133.3V,CMOSCLOCKEDFIFOWITH
BUS-MATCHINGANDBYTESWAPPING64x36
COMMERCIALTEMPERATURERANGE
PARAMETER MEASUREMENT INFORMATION
3.3V
330
Ω
From Output
Under Test
30 pF (1)
510 Ω
PROPAGATION DELAY
LOAD CIRCUIT
3 V
3 V
Timing
Input
1.5 V
High-Level
1.5 V
Input
GND
1.5 V
1.5 V
GND
t
S
th
tW
3 V
3 V
1.5 V
1.5 V
Low-Level
1.5 V
GND
Input
Data,
Enable
Input
GND
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
Output
3 V
Enable
1.5 V
1.5 V
t
PZL
GND
tPLZ
3 V
≈ 3V
Input
1.5 V
1.5 V
1.5 V
Low-Level
Output
GND
V
OL
tPD
t
PZH
tPD
V
OH
V
OH
≈ OV
In-Phase
Output
1.5 V
1.5 V
High-Level
Output
1.5 V
V
t
PHZ
OL
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
4661 drw 20
NOTE:
1. Includes probe and jig capacitance.
Figure 20. Load Circuit and Voltage Waveforms
JUNE 9, 2005
25
ORDERINGINFORMATION
IDT
XXXXXX
X
XX
X
X
X
Device Type Power Speed Package
Process/
Temperature
Range
BLANK
G
Commercial (0°C to +70°C)
Green
PF
PQF
Thin Quad Flat Pack (TQFP, PN120-1)
Plastic Quad Flat Pack (PQFP, PQ132-1)
12
15
20
Clock Cycle Time (tCLK
)
Commercial Only
Speed in Nanoseconds
L
Low Power
72V3613
64 x 36 3.3V SyncFIFO
4661 drw 21
NOTES:
1. Industrial temperature range is available by special order.
2. Green parts are available. For specific speeds and packages contact your sales office.
DATASHEETDOCUMENTHISTORY
07/10/2000
05/27/2003
06/09/2005
pg. 1.
pg. 6.
pgs. 1, 2, 3 and 26.
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, Ca 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
for TECH SUPPORT:
408-360-1753
FIFOhelp@idt.com
www.idt.com
26
相关型号：
IDT72V3614L12PQFG
Bi-Directional FIFO, 64X36, 8ns, Synchronous, CMOS, PQFP132, GREEN, PLASTIC, QFP-132
IDT
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