IDT7018L20PFI8_技术文档

HIGH-SPEED

IDT7018L

64K x 9 DUAL-PORT

STATIC RAM

Features

◆

M/S = VIH for BUSY output flag on Master,

M/S = VIL for BUSY input on Slave

Interrupt Flag

True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

High-speed access

◆

On-chip port arbitration logic

– Commercial:15/20ns (max.)

Low-power operation

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

TTL-compatible, single 5V (±10%) power supply

Available in a 100-pin TQFP

– IDT7018L

◆

Active:1W(typ.)

Standby: 1mW (typ.)

◆

Dual chip enables allow for depth expansion without

external logic

IDT7018 easily expands data bus width to 18 bits or

more using the Master/Slave select when cascading more

than one device

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

FunctionalBlockDiagram

R/WL

CE0L

CE1L

R/W^R

CE0R

CE1R

OE_L

OE_R

I/O

Control

I/O

Control

I/O0-8L

I/O_0-8R

(1,2)

BUSY_L

(1,2)

BUSY_R

64Kx9

MEMORY

ARRAY

7018

A15L

A15R

A0R

Address

Decoder

Address

Decoder

A0L

16

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

CE0L

CE_0R

1L

CE

1R

CE

OEL

OER

L

R/W

R

R/W

SEML

INTL

R

SEM

INT

(2)

R

M/S⁽¹⁾

4841 drw 01

NOTES:

1. BUSY is an input as a Slave (M/S = V^IL) and an output when it is a Master (M/S = VIH).

2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).

JANUARY 2001

1

DSC-4841/2

IDT7018L

High-Speed 64K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Description

The IDT7018 is a high-speed 64K x 9 Dual-Port Static RAM. The address,andI/Opinsthatpermitindependent,asynchronousaccessfor

IDT7018isdesignedtobeusedasastand-alone576K-bitDual-PortRAM reads or writes to any location in memory. An automatic power down

orasacombinationMASTER/SLAVEDual-PortRAMfor18-bit-or-more featurecontrolledbythe chipenables(CE⁰andCE1)permittheon-chip

wordsystems.UsingtheIDTMASTER/SLAVEDual-PortRAMapproach circuitry of each port to enter a very low standby power mode.

in18-bitorwidermemorysystemapplicationsresultsinfull-speed,error-

freeoperationwithouttheneedforadditionaldiscretelogic.

FabricatedusingIDT’sCMOShigh-performancetechnology,these

devices typically operate on only 1W of power.

This device provides two independent ports with separate control,

TheIDT7018ispackagedina100-pinThinQuadFlatpack(TQFP).

PinConfigurations^(1,2,3)

Index

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

1

NC

A7L

75

NC

A7R

2

74

3

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

4

A8L

A9L

A8R

A9R

5

A10L

A11L

A12L

A13L

A14L

A15L

NC

Vcc

NC

CE0L

CE1L

SEML

6

A10R

A11R

A12R

A13R

A14R

A15R

NC

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

IDT7018PF

PN100-1

(

4)

100-Pin TQFP

GND

NC

CE0R

CE1R

SEMR

R/WR

OER

GND

NC

(

5)

Top View

WL

R/

OEL

GND

NC

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

4841 drw 02

NOTES:

1. All Vcc pins must be connected to power supply.

2. All GND pins must be connected to ground supply.

3. Package body is approximately 14mm x 14mm x 1.4mm.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part marking.

2

IDT7018L

High-Speed 64K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

PinNames

Left Port

Right Port

Names

Chip Enables

CE^0L

1L

, CE

CE^0R1R

, CE

W^L

R/

W^R

R/

Read/Write Enable

Output Enable

Address

OE^L

A^0L- A^15L

OE^R

A^0R- A^15R

0L

8L

0R

8R

I/O - I/O

Data Input/Output

Semaphore Enable

Interrupt Flag

Busy Flag

SEM^L

INT^L

SEM^R

INT^R

BUSY^R

S

BUSY^L

M/

Master or Slave Select

Power

CC

V

GND

Ground

4841 tbl 01

AbsoluteMaximumRatings⁽¹⁾

RecommendedDCOperating

Conditions

Symbol

Rating

Commercial

& Industrial

Military

Unit

Symbol

Parameter

Min.

Typ.

Max. Unit

(2)

V^TERM

Terminal Voltage

with Respect

to GND

-0.5 to +7.0

V

VCC

Supply Voltage

4.5

5.0

5.5

0

V

GND Ground

0

Temperature

Under Bias

-55 to +125

-65 to +150

50

-65 to +135

-65 to +150

50

^oC

T^BIAS

T^STG

VIH

VIL

Input High Voltage

Input Low Voltage

2.2

6.0⁽²⁾

0.8

____

Storage

Temperature

-0.5⁽¹⁾

V

____

4841 tbl 04

I^OUT

DC Output Current

mA

NOTES:

1. V^IL> -1.5V for pulse width less than 10ns.

2. V^TERMmust not exceed Vcc + 10%.

4841 tbl 02

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions above those

indicated in the operational sections of this specification is not implied. Exposure

to absolute maximum rating conditions for extended periods may affect

reliability.

Capacitance

(TA = +25°C, f = 1.0MHz)

2. V^TERMmust not exceed Vcc + 10% for more than 25% of the cycle time or 10ns

maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.

Symbol

C^IN

Parameter⁽¹⁾

Input Capacitance

Output Capacitance

Conditions⁽²⁾

V^IN= 3dV

Max. Unit

9

pF

MaximumOperatingTemperature

andSupplyVoltage⁽¹⁾

Ambient

C^OUT

V^OUT= 3dV

10

pF

4841 tbl 05

NOTES:

Grade

Temperature⁽²⁾

-55^OC to +125^OC

0^OC to +70^OC

GND

Vcc

1. This parameter is determined by device characterization but is not production

tested.

2. 3dV represents the interpolated capacitance when the input and output signals

switch from 0V to 3V or from 3V to 0V.

Military

0V

5.0V + 10%

Commercial

Industrial

0V

-40^OC to +85^OC

0V

4841 tbl 03

NOTES:

1. Industrial Temperature: for specific speeds, packages and powers contact your

sales office.

2. This is the parameter T^A. This is the "instant on" case temperature.

3

6.42

IDT7018L

High-Speed 64K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Truth Table I: Chip Enable^(1,2)

1

CE

CE⁰

Mode

V^IL

V^IH

Port Selected (TTL Active)

L

< 0.2V

V^IH

>V^CC-0.2V

X

Port Selected (CMOS Active)

Port Deselected (TTL Inactive)

Port Deselected (CMOS Inactive)

X

V^IL

H

>V^CC-0.2V

X

<0.2V

4841 tbl 06

NOTES:

1. Chip Enable references are shown above with the actual CE⁰and CE1 levels, CE is a reference only.

2. 'H' = V^IHand 'L' = VIL.

3. CMOS standby requires 'X' to be either < 0.2V or > VCC - 0.2V.

Truth Table II: Non-Contention Read/Write Control

Inputs⁽¹⁾

Outputs

CE⁽²⁾

H

OE

SEM

H

R/W

X

I/O^0-8

Mode

X

L

High-Z

DATA^IN

Deselected: Power-Down

Write to memory

L

H

L

H

DATA^OUTRead memory

High-Z Outputs Disabled

X

H

X

4841 drw 07

NOTES:

1. A^0L– A15L ≠ A0R – A15R.

2. Refer to Chip Enable Truth Table.

Truth Table III: Semaphore Read/Write Control⁽¹⁾

Inputs

Outputs

(2)

R/W

I/O^0-8

Mode

CE

OE

SEM

H

L

DATA^OUTRead Semaphore Flag Data Out

↑

IN

0

H

L

X

L

DATA

Write I/O into Semaphore Flag

______

X

Not Allowed

4841 tbl 08

NOTES:

1. There are eight semaphore flags written to via I/O⁰and read from all the I/Os (I/O0-I/O8). These eight semaphore flags are addressed by A0-A2.

2. Refer to Chip Enable Truth Table.

4

IDT7018L

High-Speed 64K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range⁽²⁾(VCC = 5.0V ± 10%)

7018L

Symbol

|I^LI|

Parameter

Test Conditions

Min.

Max.

5

Unit

µA

V

(1)

___

Input Leakage Current

V^CC= 5.5V, V^IN= 0V to V^CC

CE = V^IH, V^OUT= 0V to V^CC

I^OL= 4mA

___

|I^LO|

Output Leakage Current

Output Low Voltage

Output High Voltage

5

V^OL

0.4

___

V^OH

I^OH= -4mA

2.4

V

4841 tbl 09

NOTES:

1. At Vcc < 2.0V, input leakages are undefined.

2. Refer to Chip Enable Truth Table.

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range^(1,6,7)(VCC = 5.0V ± 10%)

7018L15

7018L20

Com'l Only

Symbol

Parameter

Test Condition

Version

COM'L

Typ.⁽¹⁾Max

Unit

mA

I^CC

Dynamic Operating

Current

(Both Ports Active)

L

220

340

200

300

CE = V^IL, Outputs Disabled

SEM = V^IH

(2)

____

IND

f = f^MAX

mA

I^SB1

I^SB2

I^SB3

Standby Current

(Both Ports - TTL Level

Inputs)

COM'L

IND

65

100

50

75

CE^L= CE^R= V^IH

SEM^R= SEM^L= V^IH

(2)

____

f = f^MAX

(4)

Standby Current

(One Port - TTL Level

Inputs)

COM'L

IND

145

225

130

195

CE^"A"= V^ILand CE^"B"= V^IH

Active Port Outputs Disabled,

(2)

____

f=f^MAX, SEM^R= SEM^L= V^IH

Full Standby Current

(Both Ports - All CMOS

Level Inputs)

Both Ports CE^Land

COM'L

IND

0.2

3.0

0.2

3.0

CE^R> V^CC- 0.2V, V^IN> V^CC- 0.2V

or V^IN< 0.2V, f = 0⁽³⁾

____

SEM^R= SEM^L> V^CC- 0.2V

mA

I^SB4

Full Standby Current

(One Port - All CMOS

Level Inputs)

COM'L

IND

L

135

220

120

190

CE^"A"< 0.2V and

(4)

CE^"B"> V^CC- 0.2V ,

SEM^R= SEM^L> V^CC- 0.2V,

____

V^IN> V^CC- 0.2V or V^IN< 0.2V, Active Port

(2)

Outputs Disabled, f = f^MAX

4841 tbl 10

NOTES:

1. V^CC= 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.)

2. At f = f^MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ tRC, and using “AC Test Conditions” of input

levels of GND to 3V.

3. f = 0 means no address or control lines change.

4. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

5. Refer to Chip Enable Truth Table.

6. Industrial Temperature: for specific speeds, packages and powers contact your sales office.

5

6.42

IDT7018L

High-Speed 64K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

5V

AC Test Conditions

Input Pulse Levels

GND to 3.0V

3ns Max.

1.5V

893Ω

Input Rise/Fall Times

OUT

DATA

DATAOUT

Input Timing Reference Levels

Output Reference Levels

BUSY

INT

1.5V

30pF

5pF*

347Ω

347

Ω

Output Load

Figures 1 and 2

4841 tbl 11

.

4841 drw 03

4841 drw 04

Figure 2. Output Test Load

(for t^LZ, tHZ, tWZ, tOW)

Figure 1. AC Output Test Load

* Including scope and jig.

Waveform of Read Cycles⁽⁵⁾

tRC

ADDR

(4)

tAA

(4)

tACE

CE⁽⁶⁾

(4)

tAOE

OE

R/W

(1)

tOH

tLZ

VALID DATA⁽⁴⁾

DATAOUT

(2)

tHZ

BUSYOUT

(3,4)

4841 drw 05

tBDD

Timing of Power-Up Power-Down

CE⁽⁶⁾

tPU

tPD

I_CC

50%

ISB

.

4841 drw 06

NOTES:

1. Timing depends on which signal is asserted last, OE or CE.

2. Timing depends on which signal is de-asserted first CE or OE.

3. t^BDDdelay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY

has no relation to valid output data.

4. Start of valid data depends on which timing becomes effective last t^AOE, tACE, tAA or tBDD.

5. SEM = V^IH.

6. Refer to Chip Enable Truth Table.

6

IDT7018L

High-Speed 64K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltageRange⁽⁵⁾

7018L15

Com'l Only

7018L20

Com'l Only

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

READ CYCLE

____

t^RC

Read Cycle Time

15

20

ns

____

t^AA

t^ACE

t^AOE

t^OH

t^LZ

Address Access Time

15

20

Chip Enable Access Time⁽⁴⁾

Output Enable Access Time

Output Hold from Address Change

Output Low-Z Time^(1,2)

____

10

12

____

3

____

3

Output High-Z Time^(1,2)

10

____

t^HZ

t^PU

t^PD

t^SOP

t^SAA

Chip Enable to Power Up Time⁽²⁾

Chip Disable to Power Down Time⁽²⁾

0

____

15

20

____

Semaphore Flag Update Pulse (OE or SEM)

10

____

Semaphore Address Access Time

15

20

ns

4841 tbl 12

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltage⁽⁵⁾

7018L15

Com'l Only

7018L20

Com'l Only

Symbol

Parameter

Min. Max.

Unit

WRITE CYCLE

____

t^WC

t^EW

t^AW

t^AS

Write Cycle Time

15

12

0

20

15

0

ns

Chip Enable to End-of-Write⁽³⁾

Address Valid to End-of-Write

Address Set-up Time⁽³⁾

Write Pulse Width

t^WP

12

0

15

0

t^WR

t^DW

t^HZ

Write Recovery Time

Data Valid to End-of-Write

Output High-Z Time^(1,2)

Data Hold Time⁽⁴⁾

10

15

____

10

____

t^DH

0

(1,2)

____

t^WZ

t^OW

t^SWRD

Write Enable to Output in High-Z

Output Active from End-of-Write^{(1, 2,4)}

SEM Flag Write to Read Time

SEM Flag Contention Window

10

____

0

5

0

5

____

t^SPS

ns

4841 tbl 13

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranted by device characterization, but is not production tested.

3. To access RAM, CE= V^ILand SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.

4. The specification for t^DHmust be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage

and temperature, the actual t^DHwill always be smaller than the actual tOW.

5. Industrial Temperature: for specific speeds, packages and powers contact your sales office.

7

6.42

IDT7018L

High-Speed 64K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Timing Waveform of Write Cycle No. 1, R/W Controlled Timing^(1,5,8)

tWC

ADDRESS

(7)

tHZ

OE

tAW

CE or SEM^(9,10)

(3)

(2)

(6)

tWP

tWR

tAS

R/W

DATAOUT

DATAIN

(7)

tWZ

tOW

(4)

tDW

tDH

4841 drw 07

Timing Waveform of Write Cycle No. 2, CE Controlled Timing^(1,5)

t_WC

ADDRESS

t_AW

(9,10)

or

CE SEM

(3)

(6)

(2)

t_WR

t_EW

t_AS

R/

W

t_DW

t_DH

DATA_IN

4841 drw 08

NOTES:

1. R/W or CE = VIH during all address transitions.

2. A write occurs during the overlap (t^EWor tWP) of a CE = VIL and a R/W = VIL for memory array writing cycle.

3. t^WRis measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the CE or SEM = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal is asserted last, CE or R/W.

7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure

2).

8. If OE = V^ILduring R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be

placed on the bus for the required t^DW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the

specified t^WP.

9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.

10. Refer to Chip Enable Truth Table.

8

IDT7018L

High-Speed 64K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Timing Waveform of Semaphore Read after Write Timing, Either Side⁽¹⁾

tSAA

tOH

A0-A2

VALID ADDRESS

tACE

tAW

tWR

tEW

SEM

tSOP

t_DW

DATA_INVALID

DATAOUT

VALID⁽²⁾

DATA0

tAS

tWP

tDH

R/W

tSWRD

tAOE

OE

tSOP

Write Cycle

Read Cycle

4841 drw 09

NOTES:

1. CE = V^IHfor the duration of the above timing (both write and read cycle) (Refer to Chip Enable Truth Table).

2. "DATA^OUTVALID" represents all I/O's (I/O0 - I/O8) equal to the semaphore value.

Timing Waveform of Semaphore Write Contention^(1,3,4)

A0"A"-A2"A"

MATCH

(2)

SIDE "A"

R/W"A"

SEM"A"

SPS

t

A0"B"-A2"B"

MATCH

(2)

SIDE

"B"

R/W

"B"

SEM"B"

4841 drw 10

NOTES:

1. D^OR= DOL = VIL, CEL = CER = VIH (Refer to Chip Enable Truth Table).

2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A".

3. This parameter is measured from R/W^"A"or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.

4. If t^SPSis not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.

9

6.42

IDT7018L

High-Speed 64K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltageRange⁽⁶⁾

7018L15

Com'l Only

7018L20

Com'l Only

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

BUSY TIMING (M/S=VIH)

____

t^BAA

t^BDA

t^BAC

t^BDC

t^APS

t^BDD

t^WH

15

20

ns

BUSY Access Time from Address Match

BUSY Disable Time from Address Not Matched

BUSY Access Time from Chip Enable Low

BUSY Access Time from Chip Enable High

Arbitration Priority Set-up Time⁽²⁾

15

17

____

5

BUSY Disable to Valid Data⁽³⁾

____

15

17

Write Hold After BUSY⁽⁵⁾

12

15

____

BUSY TIMING (M/S=VIL)

BUSY Input to Write⁽⁴⁾

Write Hold After BUSY⁽⁵⁾

PORT-TO-PORT DELAY TIMING

t^WDD

Write Pulse to Data Delay⁽¹⁾

t^DDD

Write Data Valid to Read Data Delay⁽¹⁾

____

t^WB

0

ns

t^WH

12

15

____

30

25

45

30

ns

4841 tbl 14

NOTES:

1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = V^IH)".

2. To ensure that the earlier of the two ports wins.

3. t^BDDis a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).

4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".

5. To ensure that a write cycle is completed on port "B" after contention on port "A".

6. Industrial Temperature: for specific speeds, packages and powers contact your sales office.

10

IDT7018L

High-Speed 64K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

TimingWaveformof WritewithPort-to-PortReadand BUSY(M/S = VIH)^(2,4,5)

t_WC

ADDR"A"

MATCH

tWP

R/

W"A"

t_DH

t_DW

DATA_{IN "A"}

VALID

(1)

tAPS

ADDR"B"

MATCH

tBDA

tBDD

BUSY"B"

t_WDD

DATAOUT "B"

VALID

(3)

t_DDD

NOTES:

4841 drw 11

1. To ensure that the earlier of the two ports wins. t^APSis ignored for M/S = VIL (SLAVE).

2. CE^L= CER = VIL, refer to Chip Enable Truth Table.

3. OE = V^ILfor the reading port.

4. If M/S = V^IL(SLAVE), BUSY is an input. Then for this example BUSY "A" = VIH and BUSY "B" input is shown above.

5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".

Timing Waveform of Write with BUSY (M/S = VIL)

tWP

R/W"A"

(3)

tWB

BUSY"B"

(1)

tWH

R/W_"B"

(2)

4841 drw 12

NOTES:

1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).

2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.

3. t^WBis only for the 'Slave' version.

11

6.42

IDT7018L

High-Speed 64K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Waveform of BUSY Arbitration Controlled by CE Timing(M/S = VIH)^(1,3)

ADDR"A"

ADDRESSES MATCH

and "B"

CE"A"

(2)

tAPS

CE"B"

t_BAC

t_BDC

BUSY"B"

4841 drw 13

Waveform of BUSY Arbitration Cycle Controlled by Address Match

Timing(M/S = VIH)⁽¹⁾

ADDR"A"

ADDRESS "N"

(2)

tAPS

"B"

ADDR

MATCHING ADDRESS "N"

tBAA

tBDA

"B"

BUSY

4841 drw 14

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.

2. If t^APSis not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.

3. Refer to Chip Enable Truth Table.

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltageRange⁽¹⁾

7018L15

Com'l Only

7018L20

Com'l Only

Symbol

Parameter

Min.

Max.

Min. Max.

Unit

INTERRUPT TIMING

____

t^AS

Address Set-up Time

0

ns

t^WR

t^INS

t^INR

Write Recovery Time

Interrupt Set Time

0

____

15

20

____

Interrupt Reset Time

ns

4841 tbl 15

NOTES:

1. Industrial Temperature: for specific speeds, packages and powers contact your sales office.

12

IDT7018L

High-Speed 64K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Waveform of Interrupt Timing^(1,5)

tWC

INTERRUPT SET ADDRESS⁽²⁾

ADDR"A"

(3)

(4)

tAS

tWR

CE"A"

R/W"A"

INT"B"

(3)

tINS

4841 drw 15

tRC

INTERRUPT CLEAR ADDRESS ⁽²⁾

ADDR"B"

(3)

tAS

CE"B"

"B"

OE

(3)

tINR

INT"B"

4841 drw 16

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.

2. See Interrupt Truth Table.

3. Timing depends on which enable signal (CE or R/W) is asserted last.

4. Timing depends on which enable signal (CE or R/W) is de-asserted first.

5. Refer to Chip Enable Truth Table.

Truth Table IV Interrupt Flag^(1,4,5)

Left Port

Right Port

W_L

R/

W_R

R/

A15L-A0L

FFFF

X

A15R-A0R

X

Function

CE^L

L

OE^L

X

INT^L

X

CE^R

X

OE^R

X

INT

R

(2)

L

X

L

Set Right INT Flag

R

(3)

X

L

FFFF

FFFE

X

H

Reset Right INT Flag

R

(3)

X

L

X

Set Left INT Flag

L

(2)

L

FFFE

H

X

Reset Left INT Flag

L

4841 tbl 16

NOTES:

1. Assumes BUSY^L= BUSYR =VIH.

2. If BUSY^L= VIL, then no change.

3. If BUSY^R= VIL, then no change.

4. INT^Land INTR must be initialized at power-up.

5. Refer to Chip Enable Truth Table.

13

6.42

IDT7018L

High-Speed 64K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Truth Table V Address BUSY

Arbitration⁽⁴⁾

Inputs

Outputs

0L 15L

A -A

(1)

0R 15R

A -A

Function

Normal

Write

CE_LCE_R

BUSY_L⁽¹⁾

BUSY_R

X

H

X

L

X

H

L

NO MATCH

MATCH

H

MATCH

H

MATCH

(2)

(3)

Inhibit

4841 tbl 17

NOTES:

1. Pins BUSY^Land BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT7018 are

push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.

2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address

and enable inputs of this port. If t^APSis not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.

3. Writes to the left port are internally ignored when BUSY^Loutputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored

when BUSY^Routputs are driving LOW regardless of actual logic level on the pin.

4. Refer to Chip Enable Truth Table.

Truth Table VI Example of Semaphore Procurement Sequence^(1,2,3)

Functions

D⁰- D⁸Left

D⁰- D⁸Right

Status

No Action

1

0

1

0

1

0

1

0

1

0

1

Semaphore free

Left Port Writes "0" to Semaphore

Right Port Writes "0" to Semaphore

Left Port Writes "1" to Semaphore

Left Port Writes "0" to Semaphore

Right Port Writes "1" to Semaphore

Left Port Writes "1" to Semaphore

Right Port Writes "0" to Semaphore

Right Port Writes "1" to Semaphore

Left Port Writes "0" to Semaphore

Left Port Writes "1" to Semaphore

NOTES:

Left port has semaphore token

No change. Right side has no write access to semaphore

Right port obtains semaphore token

No change. Left port has no write access to semaphore

Left port obtains semaphore token

Semaphore free

Right port has semaphore token

Semaphore free

Left port has semaphore token

Semaphore free

4841 tbl 18

1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7018.

2. There are eight semaphore flags written to via I/O⁰and read from all I/O's (I/O0-I/O8). These eight semaphores are addressed by A0-A2.

3. CE = V^IH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.

FunctionalDescription

TheIDT7018providestwoportswithseparatecontrol,addressand (INT^L) is asserted when the right port writes to memory location FFFE

I/Opinsthatpermitindependentaccessforreadsorwritestoanylocation (HEX), where a write is defined as CER = R/WR = VIL per Truth Table

inmemory.TheIDT7018hasanautomaticpowerdownfeaturecontrolled IV. The leftportclears the interruptthroughaccess ofaddress location

by CE. The CE0 and CE1 control the on-chip power down circuitry that FFFE when CEL = OEL = VIL, R/W is a "don't care". Likewise, the right

permitstherespectiveporttogointoastandbymodewhennotselected portinterruptflag(INTR)isassertedwhentheleftportwritestomemory

(CE=HIGH).Whenaportisenabled,accesstotheentirememoryarray locationFFFF(HEX)andtocleartheinterruptflag(INTR),therightport

ispermitted.

mustreadthememorylocationFFFF. Themessage(9bits)atFFFEor

FFFF is user-defined since it is an addressable SRAM location. If the

interruptfunctionisnotused,addresslocationsFFFEandFFFFarenot

usedasmailboxes,butaspartoftherandomaccessmemory.Referto

TableIVfortheinterruptoperation.

Interrupts

Iftheuserchoosestheinterruptfunction,amemorylocation(mailbox

ormessagecenter)is assignedtoeachport. Theleftportinterruptflag

14

IDT7018L

High-Speed 64K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

BusyLogic

BusyLogicprovidesahardwareindicationthatbothportsoftheRAM

haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe

twoaccessestoproceedandsignalstheothersidethattheRAMis“busy”.

TheBUSYpincanthenbeusedtostalltheaccessuntiltheoperationon

theothersideiscompleted.Ifawriteoperationhasbeenattemptedfrom

thesidethatreceivesaBUSYindication,thewritesignalisgatedinternally

topreventthewritefromproceeding.

TheuseofBUSYlogicisnotrequiredordesirableforallapplications.

InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether

anduse anyBUSYindicationas aninterruptsource toflagthe eventof

anillegalorillogicaloperation.IfthewriteinhibitfunctionofBUSYlogicis

notdesirable,theBUSYlogiccanbedisabledbyplacingthepartinslave

modewiththeM/Spin.OnceinslavemodetheBUSYpinoperatessolely

asawriteinhibitinputpin.Normaloperationcanbeprogrammedbytying

the BUSY pins HIGH. If desired, unintended write operations can be

prevented to a port by tying the BUSY pin for that port LOW.

TheBUSYoutputsontheIDT7018RAMinmastermode,arepush-

pulltypeoutputsanddonotrequirepullupresistorstooperate.Ifthese

RAMs are being expanded in depth, then the BUSY indication for the

resulting array requires the use of an external AND gate.

can result in a glitched internal write inhibit signal and corrupted data

in the slave.

Semaphores

TheIDT7018isanextremelyfastDual-Port64Kx9CMOSStaticRAM

withanadditional8addresslocationsdedicatedtobinarysemaphoreflags.

TheseflagsalloweitherprocessorontheleftorrightsideoftheDual-Port

RAMtoclaimaprivilegeovertheotherprocessorforfunctionsdefinedby

thesystemdesigner’ssoftware.Asanexample,thesemaphorecanbe

usedbyoneprocessortoinhibittheotherfromaccessingaportionofthe

Dual-Port RAM or any other shared resource.

The Dual-PortRAMfeatures a fastaccess time, andbothports are

completelyindependentofeachother.Thismeansthattheactivityonthe

leftportinnowayslows theaccess timeoftherightport.Bothports are

identicalinfunctiontostandardCMOSStaticRAMandcanbereadfrom,

orwrittento,atthesametimewiththeonlypossibleconflictarisingfromthe

simultaneous writing of, or a simultaneous READ/WRITE of, a non-

semaphorelocation.Semaphoresareprotectedagainstsuchambiguous

situationsandmaybeusedbythesystemprogramtoavoidanyconflicts

inthenon-semaphoreportionoftheDual-PortRAM.Thesedeviceshave

anautomaticpower-downfeaturecontrolledbyCE,theDual-PortRAM

enable,andSEM,thesemaphoreenable.TheCEandSEMpinscontrol

on-chippowerdowncircuitrythatpermits the respective porttogointo

standbymodewhennotselected. Thisistheconditionwhichisshownin

Truth Table II where CE and SEM are both HIGH.

16

A

CE⁰

MASTER

SLAVE

Dual Port RAM

BUSY_L

BUSY_R

BUSY_L

BUSY_R

SystemswhichcanbestusetheIDT7018containmultipleprocessors

or controllers and are typically very high-speed systems which are

software controlled or software intensive. These systems can benefit

from a performance increase offered by the IDT7018s hardware

semaphores, which provide a lockout mechanism without requiring

complexprogramming.

CE¹

MASTER

Dual Port RAM

SLAVE

Dual Port RAM

BUSY_LBUSY_R

BUSY_L

BUSY_R

,

4841 drw 17

Softwarehandshakingbetweenprocessors offers themaximumin

systemflexibilitybypermittingsharedresourcestobeallocatedinvarying

configurations.TheIDT7018doesnotuseitssemaphoreflagstocontrol

anyresourcesthroughhardware,thusallowingthesystemdesignertotal

flexibilityinsystemarchitecture.

An advantage of using semaphores rather than the more common

methodsofhardwarearbitrationisthatwaitstatesareneverincurredin

either processor. This can prove to be a major advantage in very high-

speedsystems.

Figure 3. Busy and chip enable routing for both width and depth

expansion with IDT7018 RAMs.

WidthExpansionBusyLogic

Master/SlaveArrays

WhenexpandinganIDT7018RAMarrayinwidthwhileusingBUSY

logic,onemasterpartisusedtodecidewhichsideoftheRAMsarraywill

receivea BUSYindication,andtooutputthatindication.Anynumberof

slaves to be addressed in the same address range as the master, use

the BUSYsignalasawriteinhibitsignal.ThusontheIDT7018RAMthe

BUSYpinisanoutputifthepartisusedasamaster(M/Spin=VIH),and

theBUSYpinisaninputifthepartusedasaslave(M/Spin=VIL)as shown

in Figure 3.

Iftwoormoremasterpartswereusedwhenexpandinginwidth,asplit

decisioncouldresultwithonemasterindicatingBUSYononesideofthe

arrayandanothermasterindicatingBUSYononeothersideofthearray.

Thiswouldinhibitthewriteoperationsfromoneportforpartofawordand

inhibitthewriteoperationsfromtheotherportfortheotherpartoftheword.

TheBUSYarbitration,onamaster,is basedonthechipenableand

address signals only. Itignores whetheranaccess is a readorwrite. In

a master/slave array, both address and chip enable must be valid long

enough for a BUSYflag to be output from the master before the actual

writepulsecanbeinitiatedwiththeR/Wsignal.Failuretoobservethistiming

How the Semaphore Flags Work

Thesemaphorelogicisasetofeightlatcheswhichareindependent

oftheDual-PortRAM.Theselatchescanbeusedtopassaflag,ortoken,

fromoneporttotheothertoindicatethatasharedresourceisinuse.The

semaphores provide a hardware assist for a use assignment method

called“TokenPassingAllocation.”Inthismethod,thestateofasemaphore

latchisusedasatokenindicatingthatsharedresourceisinuse.Iftheleft

processorwantstousethisresource,itrequeststhetokenbysettingthe

latch.Thisprocessorthenverifiesitssuccessinsettingthelatchbyreading

it. If it was successful, it proceeds to assume control over the shared

resource.Ifitwasnotsuccessfulinsettingthelatch,itdeterminesthatthe

rightsideprocessorhassetthelatchfirst, hasthetokenandisusingthe

sharedresource.Theleftprocessorcantheneitherrepeatedlyrequest

thatsemaphore’sstatusorremoveitsrequestforthatsemaphoretoperform

15

6.42

IDT7018L

High-Speed 64K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

anothertaskandoccasionallyattemptagaintogaincontrolofthetokenvia side during subsequent read. Had a sequence of READ/WRITE been

thesetandtestsequence.Oncetherightsidehasrelinquishedthetoken, usedinstead,systemcontentionproblemscouldhaveoccurredduringthe

theleftsideshouldsucceedingainingcontrol.

gap between the read and write cycles.

ThesemaphoreflagsareactiveLOW.Atokenisrequestedbywriting

Itisimportanttonotethatafailedsemaphorerequestmustbefollowed

azerointoasemaphorelatchandisreleasedwhenthesamesidewrites byeitherrepeatedreadsorbywritingaoneintothesamelocation.The

aonetothatlatch. reasonforthisiseasilyunderstoodbylookingatthesimplelogicdiagram

The eightsemaphore flags reside withinthe IDT7018ina separate ofthesemaphoreflaginFigure4.Twosemaphorerequestlatchesfeed

memoryspacefromtheDual-PortRAM.Thisaddressspaceisaccessed into a semaphore flag. Whichever latch is first to present a zero to the

byplacingaLOWinputontheSEMpin(whichactsasachipselectforthe semaphoreflagwillforceitssideofthesemaphoreflagLOWandtheother

semaphore flags) and using the other control pins (Address, CE, and sideHIGH.Thisconditionwillcontinueuntilaoneiswrittentothesame

R/W)as theywouldbeusedinaccessingastandardStaticRAM.Each semaphorerequestlatch.Shouldtheotherside’ssemaphorerequestlatch

oftheflagshasauniqueaddresswhichcanbeaccessedbyeitherside havebeenwrittentoazerointhemeantime,thesemaphoreflagwillflip

throughaddresspinsA0–A2.Whenaccessingthesemaphores,noneof

theotheraddresspinshasanyeffect.

L PORT

R PORT

Whenwritingtoasemaphore,onlydatapinD0isused.IfaLOWlevel

iswrittenintoanunusedsemaphorelocation,thatflagwillbesettoazero

onthatsideandaoneontheotherside(seeTableVI).Thatsemaphore

can now only be modified by the side showing the zero. When a one is

writtenintothesamelocationfromthesameside,theflagwillbesettoa

one for both sides (unless a semaphore request from the other side is

pending)andthencanbewrittentobybothsides.Thefactthattheside

whichisabletowriteazerointoasemaphoresubsequentlylocksoutwrites

fromtheothersideiswhatmakessemaphoreflagsusefulininterprocessor

communications.(Athoroughdiscussionontheuseofthisfeaturefollows

shortly.)Azerowrittenintothesamelocationfromtheothersidewillbe

storedinthesemaphorerequestlatchforthatsideuntilthesemaphoreis

freedbythefirstside.

Whenasemaphoreflagisread,itsvalueisspreadintoalldatabitsso

thataflagthatisaonereadsasaoneinalldatabitsandaflagcontaining

azeroreadsasallzeros.Thereadvalueislatchedintooneside’soutput

registerwhenthatside'ssemaphoreselect(SEM)andoutputenable(OE)

signalsgoactive.Thisservestodisallowthesemaphorefromchanging

stateinthemiddleofareadcycleduetoawritecyclefromtheotherside.

Becauseofthislatch,arepeatedreadofasemaphoreinatestloopmust

cause either signal (SEM or OE) to go inactive or the output will never

change.

AsequenceWRITE/READmustbeusedbythesemaphoreinorder

to guarantee that no system level contention will occur. A processor

requestsaccesstosharedresourcesbyattemptingtowriteazerointoa

semaphorelocation.Ifthesemaphoreisalreadyinuse,thesemaphore

requestlatchwillcontainazero,yetthesemaphoreflagwillappearasone,

afactwhichtheprocessorwillverifybythesubsequentread(seeTable

VI). As anexample, assume a processorwrites a zerotothe leftportat

afreesemaphorelocation.Onasubsequentread,theprocessorwillverify

thatithaswrittensuccessfullytothatlocationandwillassumecontrolover

the resource in question. Meanwhile, if a processor on the right side

attempts towriteazerotothesamesemaphoreflagitwillfail,as willbe

verifiedbythefactthataonewillbereadfromthatsemaphoreontheright

SEMAPHORE

REQUEST FLIP FLOP

SEMAPHORE

REQUEST FLIP FLOP

D0

D

Q

WRITE

SEMAPHORE

READ

SEMAPHORE

READ

4841 drw 18

Figure 4. IDT7018 Semaphore Logic

overtotheothersideassoonasaoneiswrittenintothefirstside’srequest

latch.Thesecondside’sflagwillnowstayLOWuntilitssemaphorerequest

latchiswrittentoaone.Fromthisitiseasytounderstandthat,ifasemaphore

is requestedandthe processorwhichrequesteditnolongerneeds the

resource, the entire system can hang up until a one is written into that

semaphorerequestlatch.

The criticalcase ofsemaphore timingis whenbothsides requesta

single token by attempting to write a zero into it at the same time. The

semaphore logic is specially designed to resolve this problem. If

simultaneousrequestsaremade,thelogicguaranteesthatonlyoneside

receives the token. If one side is earlier than the other in making the

request,thefirstsidetomaketherequestwillreceivethetoken.Ifboth

requestsarriveatthesametime,theassignmentwillbearbitrarilymade

to one port or the other.

One caution that should be noted when using semaphores is that

semaphoresalonedonotguaranteethataccesstoaresourceissecure.

Aswithanypowerfulprogrammingtechnique,ifsemaphoresaremisused

ormisinterpreted, a software errorcaneasilyhappen.

Initializationofthesemaphoresisnotautomaticandmustbehandled

viatheinitializationprogramatpower-up.Sinceanysemaphorerequest

flagwhichcontainsazeromustberesettoaone,allsemaphoresonboth

sidesshouldhaveaonewrittenintothematinitializationfrombothsides

to assure that they will be free when needed.

16

IDT7018L

High-Speed 64K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

OrderingInformation

IDT XXXXX

A

999

A

Device

Type

Power

Speed

Package

Process/

Temperature

Range

Blank

Commercial (0 C to +70 C)

°

I⁽¹⁾

Industrial (-40 C to +85 C)

°

PF

100-pin TQFP (PN100-1)

Commercial Only

15

20

Speed in

nanoseconds

Low Power

L

576K (64K x 9) Dual-Port RAM

7018

4841 drw 19

NOTE:

1. Industrial temperature range is available.

For specific speeds, packages and powers contact your sales office.

DatasheetDocumentHistory

9/30/99:

11/10/99:

1/12/01:

InitialPublicRelease

Replaced IDT logo

Page 3 Increasedstoragetemperatureparameter

ClaraifiedTAparameter

Page 5 DCElectricalparameters–changedwordingfrom"open"to"disabled"

Page 14 Added IV to Truth Table in "Interrupts" paragraph

Changed±200mVto0mVinnotes

RemovedPreliminarystatus

CORPORATE HEADQUARTERS

2975StenderWay

Santa Clara, CA 95054

for SALES:

for Tech Support:

831-754-4613

DualPortHelp@idt.com

800-345-7015 or 408-727-6116

fax: 408-492-8674

www.idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

17

6.42


型号：	IDT7018L20PFI8
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Dual-Port SRAM, 64KX9, 20ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100 静态存储器内存集成电路
文件：	总17页 (文件大小：144K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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