ICS8737-11T [IDT]
Low Skew Clock Driver, 4 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, MO-153, TSSOP-20;
| 型号： | ICS8737-11T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 4 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, MO-153, TSSOP-20 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总16页 (文件大小：216K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8737-11
Integrated
Circuit
Systems, Inc.
LOW SKEW, ÷1/÷2
DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
GENERAL DESCRIPTION
FEATURES
The ICS8737-11 is a low skew, high performance • 2 divide by 1 differential 3.3V LVPECL outputs;
ICS
Differential-to-3.3V LVPECL Clock Generator/
Divider and a member of the HiPerClockS™
family of High Performance Clock Solutions from
ICS. The ICS8737-11 has two selectable clock
2 divide by 2 differential 3.3V LVPECL outputs
HiPerClockS™
• Selectable differential CLK, nCLK or LVPECL clock inputs
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
inputs.The CLK, nCLK pair can accept most standard differ-
ential input levels. The PCLK, nPCLK pair can accept
LVPECL, CML, or SSTL input levels.The clock enable is
internally synchronized to eliminate runt pulses on the
outputs during asynchronous assertion/deassertion of the
clock enable pin.
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
• Maximum output frequency: 650MHz
• Translates any single ended input signal (LVCMOS, LVTTL,
GTL) to LVPECL levels with resistor bias on nCLK input
Guaranteed output and part-to-part skew characteristics
make the ICS8737-11 ideal for clock distribution applications
demanding well defined performance and repeatability.
• Output skew: 60ps (maximum)
• Part-to-part skew: 200ps (maximum)
• Bank skew: Bank A - 20ps (maximum),
Bank B - 35ps (maximum)
• Additive phase jitter, RMS: 0.04ps (typical)
• Propagation delay: 1.7ns (maximum)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
QA0
nQA0
VEE
CLK_EN
CLK_SEL
CLK
nCLK
PCLK
nPCLK
nc
1
2
3
4
5
6
7
8
20
19
18
17
16
15
14
13
12
11
QA0
nQA0
VCC
QA1
nQA1
QB0
nQB0
VCC
D
CLK_EN
QA1
nQA1
Q
LE
CLK
nCLK
PCLK
÷1
÷2
0
1
nPCLK
MR
VCC
9
10
QB1
nQB1
QB0
nQB0
CLK_SEL
MR
ICS8737-11
QB1
nQB1
20-LeadTSSOP
6.50mm x 4.40mm x 0.92 package body
G Package
TopView
8737AG-11
www.icst.com/products/hiperclocks.html
REV. B FEBRUARY 4, 2004
1
ICS8737-11
Integrated
Circuit
Systems, Inc.
LOW SKEW, ÷1/÷2
DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
VEE
Power
Power
Negative supply pin.
Synchronizing clock enable. When HIGH, clock outputs follow clock input.
When LOW, Q outputs are forced low, nQ outputs are forced high.
LVCMOS / LVTTL interface levels.
Clock Select input. When HIGH, selects PCLK, nPCLK inputs.
When LOW, selects CLK, nCLK inputs. LVCMOS / LVTTL interface levels.
2
CLK_EN
Pullup
Pulldown
3
CLK_SEL
Input
4
5
6
7
8
CLK
nCLK
PCLK
nPCLK
nc
Input
Input
Pulldown Non-inverting differential clock input.
Pullup Inverting differential clock input.
Pulldown Non-inverting differential LVPECL clock input.
Input
Input
Pullup
Inverting differential LVPECL clock input.
No connect.
Unused
Active HIGH Master Reset. When logic HIGH, the internal dividers
are reset causing the true outputs QXx to go low and the inverted outputs
nQXx to go high. When logic LOW, the internal dividers and the outputs
are enabled. LVCMOS / LVTTL interface levels.
9
MR
VCC
Input
Pulldown
10, 13, 18
11, 12
Power
Positive supply pins.
nQB1, QB1 Output
nQB0, QB0 Output
nQA1, QA1 Output
nQA0, QA0 Output
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
14, 15
16, 17
19, 20
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
CIN
Input Capacitance
Input Pullup Resistor
4
RPULLUP
51
51
KΩ
RPULLDOWN Input Pulldown Resistor
KΩ
8737AG-11
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REV. B FEBRUARY 4, 2004
2
ICS8737-11
Integrated
Circuit
Systems, Inc.
LOW SKEW, ÷1/÷2
DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
Outputs
MR CLK_EN CLK_SEL Selected Source
QA0, QA1
LOW
nQA0, nQA1
HIGH
QB0, QB1
LOW
nQB0, nQB1
HIGH
1
0
0
0
0
X
0
0
1
1
X
0
1
0
1
X
CLK, nCLK
PCLK, nPCLK
CLK, nCLK
PCLK, nPCLK
Disabled; LOW
Disabled; LOW
Enabled
Disabled; HIGH
Disabled; HIGH
Enabled
Disabled; LOW
Disabled; LOW
Enabled
Disabled; HIGH
Disabled; HIGH
Enabled
Enabled
Enabled
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge
as shown if Figure 1.
In the active mode, the state of the outputs are a function of the CLK , nCLK and PCLK, nPCLK inputs as described
in Table 3B.
Enabled
Disabled
nCLK, nPCLK
CLK, PCLK
CLK_EN
nQA0, nQA1,
nQB0, nQB1
QA0, QA1,
QB0, QB1
FIGURE 1. CLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Input to Output Mode
Polarity
CLK or PCLK
nCLK or nPCLK
QAx
LOW
HIGH
LOW
HIGH
HIGH
LOW
nQAx
HIGH
LOW
HIGH
LOW
LOW
HIGH
QBx
LOW
HIGH
LOW
HIGH
HIGH
LOW
nQBx
HIGH
LOW
HIGH
LOW
LOW
HIGH
0
0
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
1
1
0
Biased; NOTE 1
1
Biased; NOTE 1
Biased; NOTE 1
Biased; NOTE 1
0
1
Inverting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
8737AG-11
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REV. B FEBRUARY 4, 2004
3
ICS8737-11
Integrated
Circuit
Systems, Inc.
LOW SKEW, ÷1/÷2
DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
CC
Inputs, V
-0.5V to VCC + 0.5V
I
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
PackageThermal Impedance, θ
73.2°C/W (0 lfpm)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol
VCC
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Positive Supply Voltage
Power Supply Current
3.135
3.3
3.465
50
V
IEE
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VIH
VIL
CLK_EN, CLK_SEL, MR
CLK_EN, CLK_SEL, MR
2
3.765
0.8
V
-0.3
V
CLK_EN
VIN = VCC = 3.465V
VIN = VCC = 3.465V
5
µA
µA
µA
µA
IIH
Input High Current
Input Low Current
CLK_SEL, MR
CLK_EN
150
VIN = 0V, VCC = 3.465V
VIN = 0V, VCC = 3.465V
-150
-5
IIL
CLK_SEL,MR
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
IIH Input High Current
Test Conditions
VIN = VCC = 3.465V
VIN = VCC = 3.465V
VIN = 0V, VCC = 3.465V
Minimum Typical Maximum Units
nCLK
CLK
5
µA
µA
µA
µA
V
150
nCLK
CLK
-150
-5
IIL
Input Low Current
V
IN = 0V, VCC = 3.465V
VPP
Peak-to-Peak Input Voltage
0.15
1.3
Common Mode Input Voltage;
NOTE 1, 2
VCMR
V
EE + 0.5
VCC - 0.85
V
NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
8737AG-11
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REV. B FEBRUARY 4, 2004
4
ICS8737-11
Integrated
Circuit
Systems, Inc.
LOW SKEW,
÷1/÷2
DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
VIN = VCC = 3.465V
VIN = VCC = 3.465V
IN = 0V, VCC = 3.465V
Minimum Typical
Maximum Units
150
5
µA
µA
µA
µA
V
IIH Input High Current
V
-5
IIL
Input Low Current
VIN = 0V, VCC = 3.465V
-150
VPP
Peak-to-Peak Input Voltage
0.3
1
VCMR
VOH
Common Mode Input Voltage; NOTE 1, 2
Output High Voltage; NOTE 3
VEE + 1.5
VCC - 1.4
VCC - 2.0
0.65
VCC
V
VCC - 1.0
VCC - 1.7
0.9
V
VOL
Output Low Voltage; NOTE 3
V
VSWING
Peak-to-Peak Output Voltage Swing
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
NOTE 3: Outputs terminated with 50Ω to VCC - 2V.
TABLE 5. AC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
Output Frequency
650
1.7
1.6
60
MHz
ns
CLK, nCLK
1.3
1.2
tPD
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Bank Skew; NOTE 4
IJ 650MHz
PCLK, nPCLK
ns
tsk(o)
tsk(b)
ps
Bank A
Bank B
20
ps
35
ps
tsk(pp)
tjit
Part-to-Part Skew; NOTE 3, 4
200
ps
Buffer Additive Phase Jitter, RMS; refer to
Additive Phase Jitter Section, NOTE 5
0.04
50
ps
tR
Output Rise Time
Output Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ @ 50MHz
20ꢀ to 80ꢀ @ 50MHz
300
300
48
700
700
52
ps
ps
ꢀ
tF
odc
All parameters measured at 500MHz unless noted otherwise.
The cycle-to-cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Driving only one input clock.
8737AG-11
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REV. B FEBRUARY 4, 2004
5
ICS8737-11
Integrated
Circuit
Systems, Inc.
LOW SKEW, ÷1/÷2
DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
ADDITIVE PHASE JITTER
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental.This
ratio is expressed in decibels (dBm) or a ratio of the power in
0
Input/Output Additive
Phase Jitter at 155.52MHz
= 0.04ps typical
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements vice meets the noise floor of what is shown, but can actually be
have issues.The primary issue relates to the limitations of the lower. The phase noise is dependant on the input source and
equipment. Often the noise floor of the equipment is higher than measurement equipment.
the noise floor of the device. This is illustrated above. The de-
8737AG-11
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REV. B FEBRUARY 4, 2004
6
ICS8737-11
Integrated
Circuit
Systems, Inc.
LOW SKEW,
÷1/÷2
DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
2V
VCC
SCOPE
VCC
Qx
nCLK,
nPCLK
VPP
VCMR
Cross Points
LVPECL
CLK,
PCLK
nQx
VEE
VEE
-1.3V 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
PART 1
nQx
nQx
Qx
Qx
PART 2
nQy
nQy
Qy
Qy
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nCLK,
nPCLK
CLK,
PCLK
80ꢀ
tF
80ꢀ
VSWING
Clock
20ꢀ
20ꢀ
nQAx,
nQBx
Outputs
tR
QAx,
QBx
tPD
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
nQAx,
nQBx
QAx,
QBx
Pulse Width
tPERIOD
tPW
odc =
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
8737AG-11
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REV. B FEBRUARY 4, 2004
7
ICS8737-11
Integrated
Circuit
Systems, Inc.
LOW SKEW, ÷1/÷2
DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is
generated by the bias resistors R1, R2 and C1.This bias circuit should be located as close as possible to the input pin.The ratio of
R1 and R2 might need to be adjusted to position theV_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1
1K
CLK_IN
+
V_REF
-
C1
0.1uF
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs.The two different layouts mentioned
are recommended only as guidelines.
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 3A and 3B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs.Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
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REV. B FEBRUARY 4, 2004
8
ICS8737-11
Integrated
Circuit
Systems, Inc.
LOW SKEW,
÷1/÷2
DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL here are examples only. Please consult with the vendor of the
and other differential signals.BothVSWING andVOH must meet the driver component to confirm the driver termination requirements.
VPP and VCMR input requirements. Figures 4A to 4E show inter- For example in Figure 4A, the input termination applies for ICS
face examples for the HiPerClockS CLK/nCLK input driven by HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
the most common driver types.The input interfaces suggested from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 4A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 4B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 4C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 4D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
125
R4
125
C1
C2
LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
CLK
nCLK
HiPerClockS
Input
R5
100 - 200
R6
100 - 200
R1
84
R2
84
R5,R6 locate near the driver pin.
FIGURE 4E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
8737AG-11
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REV. B FEBRUARY 4, 2004
9
ICS8737-11
Integrated
Circuit
Systems, Inc.
LOW SKEW,
÷1/÷2
DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other here are examples only. If the driver is from another vendor,
differential signals. Both VSWING and VOH must meet the VPP and use their termination recommendation. Please consult with the
VCMR input requirements. Figures 5A to 5E show interface ex- vendor of the driver component to confirm the driver termina-
amples for the HiPerClockS PCLK/nPCLK input driven by the tion requirements.
most common driver types. The input interfaces suggested
2.5V
3.3V
3.3V
3.3V
2.5V
3.3V
R3
120
R4
120
R1
50
R2
50
SSTL
Zo = 60 Ohm
Zo = 60 Ohm
CML
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
PCLK
nPCLK
HiPerClockS
nPCLK
PCLK/nPCLK
HiPerClockS
PCLK/nPCLK
R1
120
R2
120
FIGURE 5A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A CML DRIVER
FIGURE 5B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN SSTL DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
Zo = 50 Ohm
R3
1K
R4
1K
Zo = 50 Ohm
Zo = 50 Ohm
C1
C2
LVDS
PCLK
PCLK
R5
100
nPCLK
nPCLK
Zo = 50 Ohm
HiPerClockS
PCLK/nPCLK
HiPerClockS
Input
LVPECL
R1
1K
R2
1K
R1
84
R2
84
FIGURE 5C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
FIGURE 5D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
84
R4
84
C1
C2
3.3V LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
R5
100 - 200
R6
100 - 200
R1
125
R2
125
FIGURE 5E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
8737AG-11
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REV. B FEBRUARY 4, 2004
10
ICS8737-11
Integrated
Circuit
Systems, Inc.
LOW SKEW, ÷1/÷2
DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8737-11.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8737-11 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * ICC_MAX = 3.465V * 50mA = 173.25mW
Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 30.2mW = 120.8mW
Total Power_MAX (3.465V, with all outputs switching) = 173.25mW + 120.8mW = 294.05mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total =Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W perTable 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.294W * 66.6°C/W = 89.58°C. This is well below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 20-PIN TSSOP, FORCED CONVECTION
θ
by Velocity (Linear Feet per Minute)
JA
0
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
8737AG-11
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REV. B FEBRUARY 4, 2004
11
ICS8737-11
Integrated
Circuit
Systems, Inc.
LOW SKEW,
÷1/÷2
DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in Figure 6.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage ofV - 2V.
CC
•
•
For logic high, VOUT = V
= V
– 1.0V
OH_MAX
CC_MAX
)
= 1.0V
OH_MAX
(V
- V
CC_MAX
For logic low, VOUT = V
= V
– 1.7V
OL_MAX
CC_MAX
)
= 1.7V
OL_MAX
(V
- V
CC_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
L
L
[(2V - 1V)/50Ω] * 1V = 20.0mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mWL
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
8737AG-11
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REV. B FEBRUARY 4, 2004
12
ICS8737-11
Integrated
Circuit
Systems, Inc.
LOW SKEW, ÷1/÷2
DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP
θ
by Velocity (Linear Feet per Minute)
JA
0
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8737-11 is: 510
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REV. B FEBRUARY 4, 2004
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ICS8737-11
Integrated
Circuit
Systems, Inc.
LOW SKEW,
÷1/÷2
DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
Millimeters
Minimum Maximum
SYMBOL
N
A
20
--
1.20
0.15
1.05
0.30
0.20
6.60
A1
A2
b
0.05
0.80
0.19
0.09
6.40
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
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REV. B FEBRUARY 4, 2004
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ICS8737-11
Integrated
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Systems, Inc.
LOW SKEW,
÷1/÷2
DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS8737AG-11
Marking
Package
Count
72
Temperature
0°C to 70°C
0°C to 70°C
ICS8737AG-11
ICS8737AG-11
20 lead TSSOP
ICS8737AG-11T
20 lead TSSOP on Tape and Reel
2500
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
8737AG-11
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REV. B FEBRUARY 4, 2004
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ICS8737-11
Integrated
Circuit
Systems, Inc.
LOW SKEW, ÷1/÷2
DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
REVISION HISTORY SHEET
Rev
A
Table
Page
Description of Change
Date
3
3
Updated Figure 1, CLK_EN Timing Diagram.
Revised Figure 1, CLK_EN Timing Diagram.
10/17/01
10/31/01
6/3/02
A
A
8
2
6
Added Termination for LVPECL Outputs section.
Pin Description Table - revised MR description.
1
3.3V Output Load Test Circuit Diagram, revised VEE equation from
"-1.3V 0.135V" to " -1.3V 0.165V".
A
B
8/19/02
7
2
2
4
5
Revised Output Rise/Fall Time Diagram.
T1
T2
Pin Description Table - revised MR description.
Pin Characteristics Table - changed CIN 4pF max. to 4pF typical.
Absolute Maximum Ratings, updated Output rating.
AC Characteristics Table - added Additive Phase Jitter.
Added Additive Phase Jitter Section.
T5
6
2/3/04
8
9
10
Updated LVPECL Output Termination drawings.
Added Differential Clock Input Interface section.
Added LVPECL Clock Input Interface section.
Updated format throughout the data sheet.
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REV. B FEBRUARY 4, 2004
16
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