ICS8737AGT-11LF [IDT]
Low Skew Clock Driver, 4 True Output(s), 0 Inverted Output(s), PDSO20, MO-153, TSSOP-20;
| 型号： | ICS8737AGT-11LF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 4 True Output(s), 0 Inverted Output(s), PDSO20, MO-153, TSSOP-20 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总7页 (文件大小：95K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS8737-11
Integrated
Circuit
Systems, Incꢀ
LOW SKEW
÷1/÷2
3.3V LVPECL CLOCK GENERATOR
GENERAL DESCRIPTION
FEATURES
The ICS8737-11 is very low skew, 3.3V LVPECL • 2 divide by 1 differential 3.3V LVPECL outputs;
,&6
Clock Generator/Divider and a member of the
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS8737-11 is designed
to translate any differential signal levels to 3.3V
2 divide by 2 differential 3.3V LVPECL outputs
• Selectable differential HSTL and LVPECL clock inputs
• LVCMOS / LVTTL control inputs
HiPerClockS™
LVPECL levels. The output enable is synchronous which elimi-
nates the runt clock pulses which occur during asynchro-
nous enabling and disabling of the outputs.
• Translates any differential input signal (DCM, HSTL, LVDS,
SSTL) to LVPECL levels without external bias networks
• Translates any single-ended input signal (LVCMOS, LVTTL,
GTL) to LVPECL levels with resistor bias on nCLK input
Guaranteed output and part-to-part skew characteristics
make the ICS8737-11 ideal for those clock distribution appli-
cations demanding well defined performance and repeatabil-
ity.
• Translates any single-ended input signal (LVCMOS, LVTTL,
GTL) to inverted LVPECL levels with resistor bias on CLK
input
• Output frequency up to 700MHz
• 75ps output skew
• 3.3V operating supply voltages
• 20 lead TSSOP
• 0°C to 70°C ambient operating temperature
BLOCK DIAGRAM
PIN ASSIGNMENT
QA0
nQA0
VEE
CLK_EN
CLK_SEL
HCLK
nHCLK
PCLK
nPCLK
nc
MR
VCC
1
2
3
4
5
6
7
8
20
19
18
17
16
15
14
13
12
11
QA0
nQA0
VCC
QA1
nQA1
QB0
nQB0
VCC
QB1
nD
LE
CLK_EN
QA1
nQA1
Q
HCLK
nHCLK
PCLK
0
1
÷1
÷2
nPCLK
9
10
nQB1
QB0
CLK_SEL
MR
nQB0
QB1
nQB1
ICS8737-11
20-Lead TSSOP
G Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8737-11
www.icst.com/products/hiperclocks.html
REV. B MARCH 29, 2001
1
PRELIMINARY
ICS8737-11
Integrated
Circuit
Systems, Incꢀ
LOW SKEW
÷1/÷2
3.3V LVPECL CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
VEE
Type
Description
1
2
Power
Power
Power supply pin. Connect to ground.
CLK_EN
Pullup
Output enable. Controls enabling and disabling of clock outputs.
Clock select input. When HIGH selects differential HSTL inputs.
3
CLK_SEL
Input
Pulldown When LOW selects differential PECL inputs.
LVCMOS / LVTTL interface levels.
4
5
6
7
8
9
HCLK
nHCLK
PCLK
nPCLK
nc
Input
Input
Pulldown Non-inverting differential HSTL clock input.
Pullup
Inverting differential HSTL clock input.
Input
Pulldown Non-inverting differential PECL clock input.
Input
Pullup
Inverting differential PECL clock input.
Unused pin.
Unused
Input
MR
Pulldown Resets the output divider.
10, 13,
18
VCC
Power
Input power supply pin. Connect to 3.3V.
11, 12
14, 15
16, 17
19, 20
nQB1, QB1 Output
nQB0, QB0 Output
nQA1, QA1 Output
nQA0, QA0 Output
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels
Differential clock outputs. LVPECL interface levels
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
HCLK, nHCLK
PCLK, nPCLK
pF
pF
Input
Capacitance
CIN
CLK_SEL,
CLK_EN, MR
pF
RPULLUP
Input Pullup Resistor
51
51
K
K
RPULLDOWN Input Pulldown Resistor
8737-11
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REV. B MARCH 29, 2001
2
PRELIMINARY
ICS8737-11
Integrated
Circuit
Systems, Incꢀ
LOW SKEW ÷1/÷2
3.3V LVPECL CLOCK GENERATOR
TABLE 3A. CONTROL INPUTS FUNCTION TABLE
Inputs
Outputs
MR
1
CLK_EN
CLK_SEL
QA0 thru QA1
LOW
nQA0 thru nQA1
HIGH
QB0 thru QB1
LOW
nQB0 thru nQB1
HIGH
X
0
0
1
1
X
0
1
0
1
0
LOW
HIGH
LOW
HIGH
0
LOW
HIGH
LOW
HIGH
0
Active
Active
Active
Active
0
Active
Active
Active
Active
In the active mode the state of the output is a function of the HCLK , nHCLK and PCLK, nPCLK inputs as described
in Table 3B.
TABLE 3B. CLOCK INPUTS FUNCTION TABLE
Inputs
Outputs
nQAx
Input to Output Mode
Polarity
HCLK or PCLK nHCLK or nPCLK
QAx
LOW
HIGH
LOW
HIGH
HIGH
LOW
QBx
LOW
HIGH
LOW
HIGH
HIGH
LOW
nQBx
HIGH
LOW
HIGH
LOW
LOW
HIGH
0
0
HIGH
LOW
HIGH
LOW
LOW
HIGH
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
1
1
0
Biased; NOTE 1
1
Biased; NOTE 1
Biased; NOTE 1
Biased; NOTE 1
0
1
Inverting
NOTE 1: Single ended use requires that one of the differential input be biased. The voltage at the biased input sets the
switch point for the single ended input. For LVCMOS and LVTTL levels the recommended input bias network is a 10K
resistor from the input pin to VDD, 10K resistor from the input pin to ground and a 0.1µF capacitor from the input to
ground. The resulting switch point is VDD/2 ± 300mV.
8737-11
www.icst.com/products/hiperclocks.html
REV. B MARCH 29, 2001
3
PRELIMINARY
ICS8737-11
Integrated
Circuit
Systems, Incꢀ
LOW SKEW
÷1/÷2
3.3V LVPECL CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
4.6V
Inputs
-0.5V to VDDI + 0.5V
-0.5V to VDDO + 0.5V
0°C to 70°C
Outputs
Ambient Operating Temperature
Storage Temperature
-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only and functional operation of product at these condition or any conditions beyond those listed in
the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, TA=0°C TO 70°C
Symbol
VCC
Parameter
Test Conditions
Minimum
Typical
3.3
Maximum Units
Input Power Supply Voltage
Power Supply Current
3.135
3.465
V
IEE
37
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V±5%, TA=0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum Typical
Maximum Units
CLK_SEL, CLK_EN,
MR
CLK_SEL, CLK_EN,
MR
VIH
Input High Voltage
2
3.765
0.8
V
V
VIL
IIH
Input Low Voltage
Input High Current
-0.3
CLK_EN
5
µA
µA
µA
µA
CLK_SEL, MR
CLK_EN
150
-150
-5
IIL
Input Low Current
CLK_SEL, MR
TABLE 4C. LVHSTL DC CHARACTERISTICS, VCC = 3.3V±5%, TA=0°C TO 70°C
Symbol Parameter Test Conditions
Minimum Typical Maximum Units
HCLK
150
5
µA
µA
µA
µA
V
IIH
IIL
Input High Current
nHCLK
HCLK
-5
Input Low Current
nHCLK
-150
0.1
VPP
Peak-to-Peak Input Voltage
1.3
1.3
VCMR
Common Mode Input Voltage; NOTE 1, 2
0.13
V
NOTE 1: Common mode voltage for HSTL is defined as the crossover voltage. VCMR is compatible with DCM,
LVDS, LVPECL and SSTL input levels.
NOTE 2: For single ended applications the maximum input voltage for HCLK and nHCLK is VDD + 0.3V.
8737-11
www.icst.com/products/hiperclocks.html
REV. B MARCH 29, 2001
4
PRELIMINARY
ICS8737-11
Integrated
Circuit
Systems, Incꢀ
LOW SKEW
÷1/÷2
3.3V LVPECL CLOCK GENERATOR
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5%, TA=0°C TO 70°C
Symbol
VIH
Parameter
Test Conditions
Minimum
2.135
Typical
Maximum Units
Input High Voltage PCLK, nPCLK
Input Low Voltage PCLK, nPCLK
2.42
1.825
150
5
V
V
VIL
1.49
PCLK
Input High Current
nPCLK
µA
µA
µA
µA
V
IIH
IIL
PCLK
Input Low Current
nPCLK
-5
-150
0.15
1.5
VPP
Peak-to-Peak Input Voltage
1.3
VDD
2.3
VCMR
VOH
VOL
Common Mode Input Voltage; NOTE 1
Output High Voltage; NOTE 2, 3
Output Low Voltage; NOTE 2, 3
V
VDD = 3.3V
VDD = 3.3V
1.9
V
1.2
1.6
V
VSWING Peak-to-Peak Output Voltage Swing
0.6
0.85
V
NOTE 1: Common mode input voltage for LVPECL is defined as the minimum VIH. For single ended applications,
VIHmax is VDD + 0.3V.
NOTE 2: Noted output levels are for VDD equal to 3.3V. Output levels will vary 1:1 with VDD.
NOTE 3: Outputs terminated with 50 to VDD - 2V. The power dissipation of a terminated output pair is 30mW.
TABLE 5. AC CHARACTERISTICS, VCC = 3.3V±5%, TA=0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
fMAX
tpLH
Maximum Input Frequency
700
1.6
MHz
ns
Propagation Delay, Low-to-High;
NOTE 2
Propagation Delay, High-to-Low;
NOTE 2
1.0
1.0
tpHL
1.4
ns
tsk(o)
Output Skew; NOTE 3
75
30
ps
ps
ps
ps
ps
ps
ps
ps
%
Bank A
Bank Skew
tsk(b)
Bank B
30
HCLK, nHCLK
PCLK, nPCLK
150
150
0
tsk(pp)
Part-to-Part; NOTE 4
tjit(Ø)
tR
Input-to-Output Jitter; NOTE 5
Output Rise Time
30% to 70%
30% to 70%
100
100
48
450
450
52
tF
Output Fall Time
tDC
tS
Output Pulse Width
50
Clock Enable Setup Time
Clock Enable Hold Time
1.0
0.5
ns
ns
tH
NOTE 1: All parameters measured at 500MHz unless noted otherwise.
NOTE 2: Measured from the differential input crossing point to the differential output crossing point.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured from the 50% point of the input to the differential output crossing point.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Measured from 50% of like inputs to the differential output crossing point.
NOTE 5: Measured by triggering on input signal and measuring the largest displacement between output cycles.
8737-11
www.icst.com/products/hiperclocks.html
REV. B MARCH 29, 2001
5
PRELIMINARY
ICS8737-11
Integrated
Circuit
Systems, Incꢀ
LOW SKEW ÷1/÷2
3.3V LVPECL CLOCK GENERATOR
PACKAGE OUTLINE - G SUFFIX
c
20
1
11
L
E1
E
10
α
D
A2
A
A1
-c-
e
b
SEATING
PLANE
aaa
c
TABLE 6. PACKAGE DIMENSIONS
Millimeters
Inches
SYMBOL
MIN
MAX
MIN
MAX
N
A
20
--
1.20
0.15
1.05
0.30
0.20
6.60
--
.047
.006
.041
.012
.008
.260
A1
A2
b
0.05
0.80
0.19
0.09
6.40
.002
.032
.007
.0035
.252
c
D
E
6.40 BASIC
0.252 BASIC
E1
e
4.30
4.50
.169
.177
0.65 BASIC
.0256 BASIC
L
0.45
0°
0.75
8°
.018
0°
.030
8°
a
aaa
--
0.10
--
.004
Reference Document: JEDEC Publication 95, MO-153
8737-11
www.icst.com/products/hiperclocks.html
REV. B MARCH 29, 2001
6
PRELIMINARY
ICS8737-11
Integrated
Circuit
Systems, Incꢀ
LOW SKEW
÷1/÷2
3.3V LVPECL CLOCK GENERATOR
TABLE 7. ORDERING INFORMATION
Part/Order Number
ICS8737AG-11
Marking
Package
Count
74
Temperature
0°C to 70°C
0°C to 70°C
ICS8737AG-11
ICS8737AG-11
20 lead TSSOP
ICS8737AGT-11
20 lead TSSOP on Tape and Reel
2500
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
8737-11
www.icst.com/products/hiperclocks.html
REV. B MARCH 29, 2001
7
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