ICS87366AMLF [IDT]
PLL Based Clock Driver, 87366 Series, 6 True Output(s), 0 Inverted Output(s), PDSO24, 7.50 X 15.33 MM, 2.30 MM HEIGHT, MO-119, MS-013, SOIC-24;型号: | ICS87366AMLF |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | PLL Based Clock Driver, 87366 Series, 6 True Output(s), 0 Inverted Output(s), PDSO24, 7.50 X 15.33 MM, 2.30 MM HEIGHT, MO-119, MS-013, SOIC-24 驱动 光电二极管 逻辑集成电路 |
文件: | 总10页 (文件大小:93K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PRELIMINARY
ICS87366
Integrated
Circuit
Systems, Incꢀ
1-TO-6, DIFFERENTIAL TO 3.3V LVPECL
CLOCK
G
ENERATOR W/FORWARD
E
RROR
CORRECTION
GENERAL DESCRIPTION
FEATURES
The ICS87366 is a 1-to-6, Differential to 3.3V • 6 differential LVPECL outputs
,&6
LVPECL Clock Generator and a member of the
• 1 differential CLK/nCLK input pair
HiPerClockS™
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS87366 can multiply the
reference clock times 3 or multiply times 3 * 66/64
• CLK/nCLK pair can accept the following differential input
levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
thereby applying an FEC rate to the reference clock. The
ICS87366 is an ideal device in any application requiring x3
multiplication with an 66/64 FEC option while maintaining low
jitter. Common applications may include networking and stor-
age area networks.
• Output frequency: FEC_SEL = 0, 159.375MHz
FEC_SEL = 1, 164.355MHz
• Cycle-to-cycle jitter: FEC_SEL = 0, 15ps (typical)
FEC_SEL = 1, 20ps (typical)
• Full 3.3V or 3.3V core/2.5V output supply voltage
• 0°C to 70°C ambient operating temperature
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0
nQ0
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
1
2
3
4
24
23
22
21
20
19
18
17
16
15
14
13
VCCO
FEC_SEL
nc
MR
CLK
nCLK
VEE
VCCA
VCC
Q1
nQ1
Q2
PLL_SEL
5
6
0
nQ2
Q3
CLK
nCLK
Output
Divider
0
1
7
1
nQ3
Q4
8
9
10
11
12
PLL
Input
Divider
nQ4
Q5
nQ5
PLL_SEL
VEE
VCCO
nQ4
Q5
0
1
Feedback
Divider
nQ5
ICS87366
24-Lead, 300-MIL SOIC
7.5mm x 15.33mm x 2.3mm body package
M Package
FEC_SEL
MR
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
87366AM
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 9, 2003
1
PRELIMINARY
ICS87366
Integrated
Circuit
Systems, Incꢀ
1-TO-6, DIFFERENTIAL TO 3.3V LVPECL
CLOCK
G
ENERATOR W/FORWARD
E
RROR
CORRECTION
TABLE 1. PIN DESCRIPTIONS
Number
1, 2
Name
Q0, nQ0
Q1, nQ1
Q2, nQ2
Q3, nQ3
Q4, nQ4
Q5, nQ5
VCCO
Type
Description
Output
Output
Output
Output
Output
Output
Power
Power
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Output supply pins.
3, 4
5, 6
7, 8
9, 10
11, 12
13, 24
14, 18
VEE
Negative supply pins.
Selects between the PLL and CLK, nCLK as the input to the dividers.
When HIGH, selects PLL. When LOW, selects CLK, nCLK.
LVCMOS / LVTTL interface levels.
15
PLL_SEL
Input
Pullup
16
17
VCC
Power
Power
Core supply pin.
VCCA
Analog supply pin.
Pullup/
Pulldown
19
20
nCLK
CLK
Input
Input
Inverting differential clock input. VCC/2 defaults when left floating.
Pulldown Non-inverting differential clock input.
Active High Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and the inverted outputs
nQx to go high. When logic LOW, the internal dividers and the outputs
21
MR
Input
Pulldown
are enabled. LVCMOS / LVTTL interface levels.
22
23
nc
Unused
Input
No connect.
Select pin controls the Feedback Divide value.
Pullup
FEC_SEL
LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
K
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
K
TABLE 3. FUNCTION TABLE
Inputs
MR
1
FEC_SEL
Multiplier
X
0
1
Reset: Qx = LOW, nQx = HIGH
0
3
0
3 x 33/32
87366AM
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REV. A SEPTEMBER 9, 2003
2
PRELIMINARY
ICS87366
Integrated
Circuit
Systems, Incꢀ
1-TO-6, DIFFERENTIAL TO 3.3V LVPECL
CLOCK
G
ENERATOR W/FORWARD
E
RROR
CORRECTION
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA 50°C/W (0 lfpm)
Storage Temperature, T -65°C to 150°C
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VCC
VCCA
VCCO
VCCO
IEE
Core Supply Voltage
3.465
3.465
3.465
2.625
V
V
Analog Supply Voltage
Output Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
3.135
3.3
3.135
3.3
V
2.375
2.5
V
TBD
TBD
mA
mA
ICCA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
PLL_SEL, MR,
FEC_SEL
PLL_SEL, MR,
FEC_SEL
VIH
VIL
Input High Voltage
2
V
CC + 0.3
0.8
V
V
Input Low Voltage
Input High Current
-0.3
MR
VCC = VIN = 3.465V
150
5
µA
µA
µA
µA
IIH
PLL_SEL, FEC_SEL
MR
V
CC = VIN = 3.465V
VCC = 3.465V, VIN = 0V
CC = 3.465V, VIN = 0V
-5
IIL
Input Low Current
PLL_SEL, FEC_SEL
V
-150
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter
IIH Input High Current
Test Conditions
VCC = VIN = 3.465V
VCC = VIN = 3.465V
VCC = 3.465V, VIN = 0V
VCC = 3.465V, VIN = 0V
Minimum Typical Maximum Units
CLK
150
150
µA
µA
µA
µA
V
nCLK
CLK
-5
-150
IIL
Input Low Current
nCLK
VPP
Peak-to-Peak Voltage
0.15
1.0
VCMR
Common Mode Input Voltage; NOTE 1, 2
VEE + 0.5
VCC - 0.85
V
NOTE 1: Common mode input voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V.
87366AM
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REV. A SEPTEMBER 9, 2003
3
PRELIMINARY
ICS87366
Integrated
Circuit
Systems, Incꢀ
1-TO-6, DIFFERENTIAL TO 3.3V LVPECL
CLOCK
G
ENERATOR W/FORWARD
E
RROR
CORRECTION
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOH
Output High Voltage; NOTE 1
VCCO - 1.4
VCCO - 2.0
0.6
VCCO - 1.0
VCCO - 1.7
1.0
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
µA
NOTE 1: Outputs terminated with 50 to VCCO - 2V.
TABLE 5A. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical Maximum Units
FOUT
Output Frequency
159.375
164.355
MHz
ps
FEC_SEL = 0
FEC_SEL = 1
15
20
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 3
ps
tsk(o)
tsk(pp)
tR / tF
odc
Output Skew; NOTE 1, 3
Part-to-Part Skew, NOTE 2
Output Rise/Fall Time
Output Duty Cycle
TBD
TBD
ps
ps
20% to 80%
200
700
1
ps
50
%
tLOCK
PLL Lock Time
ms
NOTE 1: Defined as skew between outputs on different devices operating at the same supply voltages and with equal
load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VCCO/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5B. AC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO = 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical Maximum Units
FOUT
Output Frequency
159.375
164.355
MHz
ps
FEC_SEL = 0
FEC_SEL = 1
TBD
TBD
TBD
TBD
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 3
ps
tsk(o)
tsk(pp)
tR / tF
odc
Output Skew; NOTE 1, 3
Part-to-Part Skew, NOTE 2
Output Rise/Fall Time
Output Duty Cycle
ps
ps
20% to 80%
200
700
1
ps
50
%
tLOCK
PLL Lock Time
ms
NOTE 1: Defined as skew between outputs on different devices operating at the same supply voltages and with equal
load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VCCO/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
87366AM
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 9, 2003
4
PRELIMINARY
ICS87366
Integrated
Circuit
Systems, Incꢀ
1-TO-6, DIFFERENTIAL TO 3.3V LVPECL
CLOCK
G
ENERATOR W/FORWARD
E
RROR
CORRECTION
PARAMETER MEASUREMENT INFORMATION
2V
2V
2.8V±0.04V
SCOPE
SCOPE
VCC
,
VCC,
Qx
Qx
VCCA, VCCO
VCCA, VCCO
LVPECL
LVPECL
VEE
nQx
nQx
VEE
-0.5V ± 0.125V
-1.3V ± 0.165V
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
VCC
nQx
Qx
nCLK
VPP
VCMR
Cross Points
nQy
CLK
Qy
tsk(o)
VEE
DIFFERENTIAL INPUT LEVEL
OUTPUT SKEW
PART 1
nQx
nQ0:nQ5
Q0:Q5
Qx
PART 2
nQy
➤
➤
tcycle n
tcycle n+1
➤
➤
tjit(cc) = tcycle n –tcycle n+1
Qy
1000 Cycles
tsk(o)
PART-TO-PART SKEW
CYCLE-TO-CYCLE JITTER
nQ0:nQ5
Q0:Q5
80%
80%
VSWING
Pulse Width
Clock
20%
20%
tPERIOD
Outputs
tF
tR
tPW
odc =
tPERIOD
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
87366AM
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REV. A SEPTEMBER 9, 2003
5
PRELIMINARY
ICS87366
Integrated
Circuit
Systems, Incꢀ
1-TO-6, DIFFERENTIAL TO 3.3V LVPECL
CLOCK
G
ENERATOR W/FORWARD
E
RROR
CORRECTION
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS87366 provides sepa-
3.3V
VCC
rate power supplies to isolate any high switching
and
.01µF
10Ω
noise from the outputs to the internal PLL. VCC, VCCA
VCCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01µF bypass
capacitor should be connected to each VCCA pin.
VCCA
.01µF
10 µF
FIGURE 1. POWER SUPPLY FILTERING
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termina- drive 50Ω transmission lines. Matched impedance techniques
tion for LVPECL outputs. The two different layouts mentioned should be used to maximize operating frequency and minimize
are recommended only as guidelines.
signal distortion. Figures 2A and 2B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
(VOH + VOL / VCC – 2) – 2
84Ω
84Ω
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
87366AM
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REV. A SEPTEMBER 9, 2003
6
PRELIMINARY
ICS87366
Integrated
Circuit
Systems, Incꢀ
1-TO-6, DIFFERENTIAL TO 3.3V LVPECL
CLOCK
G
ENERATOR W/FORWARD
E
RROR
CORRECTION
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL here are examples only. Please consult with the vendor of the
and other differential signals. Both VSWING and VOH must meet the driver component to confirm the driver termination requirements.
VPP and VCMR input requirements. Figures 3A to 3D show inter- For example in Figure 3A, the input termination applies for ICS
face examples for the HiPerClockS CLK/nCLK input driven by HiPerClockS LVHSTLdrivers. If you are using an LVHSTL driver
the most common driver types. The input interfaces suggested from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
R4
125
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
87366AM
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REV. A SEPTEMBER 9, 2003
7
PRELIMINARY
ICS87366
Integrated
Circuit
Systems, Incꢀ
1-TO-6, DIFFERENTIAL TO 3.3V LVPECL
CLOCK
G
ENERATOR W/FORWARD
E
RROR
CORRECTION
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE
θJA by Velocity (Linear Feet per Minute)
0
200
43°C/W
500
38°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
50°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS87366 is: 3069
87366AM
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REV. A SEPTEMBER 9, 2003
8
PRELIMINARY
ICS87366
Integrated
Circuit
Systems, Incꢀ
1-TO-6, DIFFERENTIAL TO 3.3V LVPECL
CLOCK
G
ENERATOR W/FORWARD
E
RROR
CORRECTION
PACKAGE OUTLINE - M SUFFIX
TABLE 7. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
24
--
2.65
--
A1
A2
B
0.10
2.05
0.33
0.18
15.20
7.40
2.55
0.51
0.32
15.85
7.60
C
D
E
e
1.27 BASIC
H
h
10.00
0.25
0.40
0°
10.65
0.75
1.27
8°
L
Reference Document: JEDEC Publication 95, MS-013, MO-119
87366AM
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REV. A SEPTEMBER 9, 2003
9
PRELIMINARY
ICS87366
Integrated
Circuit
Systems, Incꢀ
1-TO-6, DIFFERENTIAL TO 3.3V LVPECL
CLOCK
G
ENERATOR W/FORWARD
E
RROR
CORRECTION
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS87366AM
Marking
Package
Count
30 per tube
1000
Temperature
0°C to 70°C
0°C to 70°C
ICS87366AM
ICS87366AM
24 Lead SOIC
ICS87366AMT
24 Lead SOIC on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
87366AM
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REV. A SEPTEMBER 9, 2003
10
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