ICS8543BGILF [IDT]
Low Skew, 1-to-4, Differential-to-LVDS Fanout Buffer; 低偏移， 1至4 ，差分至LVDS扇出缓冲器
| 型号： | ICS8543BGILF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew, 1-to-4, Differential-to-LVDS Fanout Buffer |
| 文件： | 总18页 (文件大小：902K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8543
Low Skew, 1-to-4,
Differential-to-LVDS Fanout Buffer
DATA SHEET
General Description
Features
The ICS8543 is a low skew, high performance 1-to-4
• Four differential LVDS output pairs
Differential-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage
Differential Signaling (LVDS) the ICS8543 provides a low power, low
noise, solution for distributing clock signals over controlled
impedances of 100Ω. The ICS8543 has two selectable clock inputs.
The CLK, nCLK pair can accept most standard differential input
levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL
input levels. The clock enable is internally synchronized to eliminate
runt pulses on the outputs during asynchronous
• Selectable differential CLK, nCLK or LVPECL clock inputs
• CLK, nCLK pair can accept the following differential input levels:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
• PCLK, nPCLK pair can accept the following differential input
levels: LVPECL, CML, SSTL
• Maximum output frequency: 800MHz
• Translates any single-ended input signals to LVDS levels with
resistor bias on nCLK input
assertion/deassertion of the clock enable pin.
• Additive phase jitter, RMS: 0.164ps (typical)
• Output skew: 40ps (maximum)
Guaranteed output and part-to-part skew characteristics make the
ICS8543 ideal for those applications demanding well defined
performance and repeatability.
• Part-to-part skew: 500ps (maximum)
• Propagation delay: 2.6ns (maximum)
• Full 3.3V supply mode
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Pin Assignment
Block Diagram
GND
CLK_EN
CLK_SEL
CLK
1
2
20 Q0
Pullup
CLK_EN
D
19
nQ0
Q
3
4
18
17
VDD
Q1
LE
Pulldown
Pullup
CLK
nCLK
0
nCLK
PCLK
nPCLK
5
6
7
8
9
16 nQ1
Q0
15
14
13
Q2
nQ2
GND
nQ0
Pulldown
Pullup
PCLK
nPCLK
1
Q1
nQ1
OE
GND
VDD 10
12 Q3
11
nQ3
Pulldown
CLK_SEL
Q2
nQ2
ICS8543
Q3
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm
package body
nQ3
Pullup
OE
G Package
Top View
ICS8543BG REVISION E DECEMBER 17, 2010
1
©2010 Integrated Device Technology, Inc.
ICS8543 Data Sheet
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 9, 13
GND
Power
Input
Power supply ground.
Synchronizing clock enable. When HIGH, clock outputs follows clock input. When
LOW, Qx outputs are forced low, nQx outputs are forced high.
LVCMOS / LVTTL interface levels.
2
CLK_EN
Pullup
Clock select input. When HIGH, selects PCLK, nPCLK inputs.
When LOW, selects CLK, nCLK inputs. LVCMOS / LVTTL interface levels.
3
4
CLK_SEL
CLK
Input
Input
Pulldown
Pulldown
Non-inverting differential clock input.
5
6
7
nCLK
PCLK
Input
Input
Input
Pullup
Pulldown
Pullup
Inverting differential clock input.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input.
nPCLK
Output enable. Controls enabling and disabling of outputs Q[0:3], nQ[0:3].
LVCMOS/LVTTL interface levels.
8
OE
Input
Pullup
10, 18
11, 12
14, 15
16, 17
19, 20
VDD
Power
Output
Output
Output
Output
Positive supply pins.
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
4
RPULLUP
RPULLDOWN
51
51
kΩ
kΩ
ICS8543BG REVISION E DECEMBER 17, 2010
2
©2010 Integrated Device Technology, Inc.
ICS8543 Data Sheet
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Function Tables
Table 3A. Control Input Function Table
Inputs
Outputs
OE
0
CLK_EN
CLK_SEL
Selected Source
Q[0:3]
Hi-Z
nQ[0:3]
Hi-Z
X
0
0
1
1
X
0
1
0
1
1
CLK, nCLK
PCLK, nPCLK
CLK, nCLK
Disabled; Low
Disabled; Low
Enabled
Disabled; High
Disabled; High
Enabled
1
1
1
PCLK, nPCLK
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK/nCLK and PCLK/nPCLK inputs as described in Table 3B.
Enabled
Disabled
nCLK, nPCLK
CLK, PCLK
CLK_EN
nQ0:nQ3
Q0:Q3
Figure 1. CLK_EN Timing Diagram
Table 3B. Clock Input Function Table
Inputs
Outputs
CLK or PCLK
nCLK or nPCLK
Q[0:3]
nQ[0:3]
HIGH
LOW
Input to Output Mode
Differential to Differential
Differential to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Polarity
Non-Inverting
Non-Inverting
Non-Inverting
Non-Inverting
Inverting
0
1
LOW
HIGH
LOW
HIGH
HIGH
LOW
1
0
0
Biased; NOTE 1
HIGH
LOW
1
Biased; NOTE 1
Biased; NOTE 1
Biased; NOTE 1
0
1
LOW
HIGH
Inverting
NOTE 1: Please refer to the Application Information section, Wiring the Differential Input to Accept Single-Ended Levels.
ICS8543BG REVISION E DECEMBER 17, 2010
3
©2010 Integrated Device Technology, Inc.
ICS8543 Data Sheet
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
Outputs, IO
Continuos Current
Surge Current
10mA
15mA
Package Thermal Impedance, θJA
73.2°C/W (0 lfpm)
-65°C to 150°C
Storage Temperature, TSTG
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 3.3V 5%, TA = 0°C to 70°C
Symbol
VDD
Parameter
Test Conditions
Minimum
Typical
Maximum
3.465
50
Units
V
Positive Supply Voltage
Power Supply Current
3.135
3.3
IDD
mA
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V 5%, TA = 0°C to 70°C
Symbol
VIH
Parameter
Test Conditions
Minimum
Typical
Maximum
3.765
0.8
Units
V
Input High Voltage
Input Low Voltage
2
VIL
V
OE, CLK_EN
CLK_SEL
V
DD = VIN = 3.465V
VDD = VIN = 3.465V
DD = 3.465V, VIN = 0V
5
µA
µA
µA
µA
IIH
Input High Current
Input Low Current
150
OE, CLK_EN
CLK_SEL
V
-150
-5
IIL
VDD = 3.465V, VIN = 0V
ICS8543BG REVISION E DECEMBER 17, 2010
4
©2010 Integrated Device Technology, Inc.
ICS8543 Data Sheet
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Table 4C. Differential DC Characteristics, VDD = 3.3V 5%, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
µA
µA
µA
µA
V
CLK
V
DD = VIN = 3.465V
VDD = VIN = 3.465V
DD = 3.465V, VIN = 0V
150
5
IIH Input High Current
nCLK
CLK
V
-5
IIL
Input Low Current
nCLK
VDD = 3.465V, VIN = 0V
-150
0.15
VPP
Peak-to-Peak Voltage; NOTE 1
1.3
Common Mode Input Voltage;
NOTE 1, 2
VCMR
0.5
VDD – 0.85
V
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as VIH.
Table 4D. LVPECL DC Characteristics, VDD = 3.3V 5%, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
VDD = VIN = 3.465V
VDD = VIN = 3.465V
DD = 3.465V, VIN = 0V
DD = 3.465V, VIN = 0V
Minimum
Typical
Maximum
Units
µA
µA
µA
µA
V
PCLK
150
5
IIH Input High Current
nPCLK
PCLK
V
V
-5
IIL
Input Low Current
nPCLK
-150
0.3
VPP
Peak-to-Peak Voltage
1.0
Common Mode Input Voltage;
NOTE 1
VCMR
1.5
VDD
V
NOTE 1: Common mode input voltage is defined as VIH.
Table 4E. LVDS DC Characteristics, VDD = 3.3V 5%, TA = 0°C to 70°C
Symbol
VOD
Parameter
Test Conditions
Minimum
Typical
280
0
Maximum
360
40
Units
mV
mV
V
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
200
∆VOD
VOS
1.125
1.25
5
1.375
25
∆VOS
IOz
VOS Magnitude Change
High Impedance Leakage
Power Off Leakage
mV
µA
µA
mA
mA
V
-10
-20
+10
+20
-5
IOFF
IOSD
IOS
1
Differential Output Short Circuit Current
Output Short Circuit Current
Output Voltage High
-3.5
-3.5
1.34
1.06
-5
VOH
1.6
VOL
Output Voltage Low
0.9
V
ICS8543BG REVISION E DECEMBER 17, 2010
5
©2010 Integrated Device Technology, Inc.
ICS8543 Data Sheet
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
AC Electrical Characteristics
Table 5. AC Characteristics, VDD = 3.3V 5%, TA = 0°C to 70°C
Symbol Parameter
fMAX Maximum Output Frequency
tPD
Test Conditions
Minimum
Typical
Maximum
800
Units
MHz
ns
Propagation Delay; NOTE 1
IJ 800MHz
1.7
2.6
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
153.6MHz, Integration Range:
12kHz – 20MHz
tjit
0.164
ps
tsk(o)
tsk(pp)
tR / tF
odc
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise/Fall Time
40
500
350
55
ps
ps
ps
%
20% to 80% @ 50MHz
150
45
Output Duty Cycle odc
50
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters measured at 500MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential output
cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
ICS8543BG REVISION E DECEMBER 17, 2010
6
©2010 Integrated Device Technology, Inc.
ICS8543 Data Sheet
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 153.6MHz
12kHz to 20MHz = 0.164ps (typical)
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
ICS8543BG REVISION E DECEMBER 17, 2010
7
©2010 Integrated Device Technology, Inc.
ICS8543 Data Sheet
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Parameter Measurement Information
V
DD
SCOPE
Qx
nCLK,
nPCLK
V
DD
3.3V 5%
POWER SUPPLY
VPP
VCMR
Cross Points
+
Float GND –
LVDS
CLK,
PCLK
nQx
GND
3.3V LVDS Output Load AC Test Circuit
Differential Input Level
V
DD
nQx
Qx
nQ[0:3]
VOD
Cross Points
nQy
Q[0:3]
GND
Qy
VOS
tsk(o)
Differential Output Level
Output Skew
Part 1
nQx
nCLK,
nPCLK
Qx
CLK,
PCLK
Part 2
nQy
nQ[0:3]
Qy
Q[0:3]
tsk(pp)
tPD
Part-to-Part Skew
Propagation Delay
ICS8543BG REVISION E DECEMBER 17, 2010
8
©2010 Integrated Device Technology, Inc.
ICS8543 Data Sheet
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Parameter Measurement Information, continued
nQ[0:3]
Q[0:3]
nQ[0:3]
80%
tF
80%
tR
tPW
VOD
20%
tPERIOD
20%
Q[0:3]
tPW
odc =
x 100%
tPERIOD
Output Rise/Fall Time
Output Duty Cycle/Pulse Width/Period
VDD
VDD
out
➤
out
out
➤
DC Input
LVDS
LVDS
V
OD/∆ VOD
DC Input
100
out
➤
VOS/∆ VOS
➤
Offset Voltage Setup
Differential Output Voltage Setup
VDD
out
out
IOZ
3.3V 5% POWER SUPPLY
Float GND
DC Inpu
t
LVDS
_
+
IOSD
DC Input
LVDS
out
out
IOZ
High Impedance Leakage Current Setup
Differential Output Short Circuit Setup
ICS8543BG REVISION E DECEMBER 17, 2010
9
©2010 Integrated Device Technology, Inc.
ICS8543 Data Sheet
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Parameter Measurement Information, continued
VDD
out
IOS
DC Input
LVDS
LVDS
VDD
IOSB
out
IOFF
Output Short Circuit Current Setup
Power Off Leakage Setup
Applications Information
Wiring the Differential Input to Accept Single-Ended Levels
Figure 2 shows how a differential input can be wired to accept single
ended levels. The reference voltage VREF = VCC/2 is generated by
the bias resistors R1 and R2. The bypass capacitor (C1) is used to
help filter noise on the DC bias. This bias circuit should be located as
close to the input pin as possible. The ratio of R1 and R2 might need
to be adjusted to position the VREF in the center of the input voltage
swing. For example, if the input clock swing is 2.5V and VDD = 3.3V,
R1 and R2 value should be adjusted to set VREF at 1.25V. The values
below are for when both the single ended swing and VDD are at the
same voltage. This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the input will attenuate the signal in half. This can be done in one of
two ways. First, R3 and R4 in parallel should equal the transmission
line impedance. For most 50Ω applications, R3 and R4 can be 100Ω.
The values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than VDD + 0.3V. Though some
of the recommended components might not be used, the pads
should be placed in the layout. They can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a differential signal.
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
ICS8543BG REVISION E DECEMBER 17, 2010
10
©2010 Integrated Device Technology, Inc.
ICS8543 Data Sheet
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
3.3V Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and
other differential signals. Both VSWING and VOH must meet the VPP
and VCMR input requirements. Figures 3A to 3F show interface
examples for the CLK/nCLK input driven by the most common driver
types. The input interfaces suggested here are examples only.
Please consult with the vendor of the driver component to confirm the
driver termination requirements. For example, in Figure 3A, the input
termination applies for IDT open emitter LVHSTL drivers. If you are
using an LVHSTL driver from another vendor, use their termination
recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50Ω
Zo = 50Ω
CLK
CLK
Zo = 50Ω
Zo = 50Ω
nCLK
nCLK
Differential
Input
LVPECL
Differential
Input
LVHSTL
R1
50Ω
R2
50Ω
R1
50Ω
R2
50Ω
IDT
LVHSTL Driver
R2
50Ω
Figure 3A. CLK/nCLK Input Driven by an
IDT Open Emitter LVHSTL Driver
Figure 3B. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
3.3V
3.3V
3.3V
3.3V
R3
R4
3.3V
125Ω
125Ω
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
CLK
CLK
R1
100Ω
nCLK
nCLK
Differential
Input
Zo = 50Ω
LVPECL
Receiver
LVDS
R1
84Ω
R2
84Ω
Figure 3C. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 3D. CLK/nCLK Input Driven by a 3.3V LVDS Driver
2.5V
3.3V
3.3V
3.3V
2.5V
R3
R4
120Ω
120Ω
Zo = 50Ω
Zo = 60Ω
Zo = 60Ω
*R3
*R4
33Ω
33Ω
CLK
CLK
Zo = 50Ω
nCLK
nCLK
Differential
Input
Differential
Input
SSTL
HCSL
R1
50Ω
R2
50Ω
R1
120Ω
R2
120Ω
*Optional – R3 and R4 can be 0Ω
Figure 3E. CLK/nCLK Input Driven by a
3.3V HCSL Driver
Figure 3F. CLK/nCLK Input Driven by a 2.5V SSTL Driver
ICS8543BG REVISION E DECEMBER 17, 2010
11
©2010 Integrated Device Technology, Inc.
ICS8543 Data Sheet
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
3.3V LVPECL Clock Input Interface
The PCLK/nPCLK accepts LVPECL, CML, SSTL and other
The input interfaces suggested here are examples only. If the driver
is from another vendor, use their termination recommendation.
Please consult with the vendor of the driver component to confirm the
driver termination requirements.
differential signals. Both VSWING and VOH must meet the VPP and
VCMR input requirements. Figures 4A to 4E show interface examples
for the PCLK/nPCLK input driven by the most common driver types.
3.3V
3.3V
3.3V
3.3V
Zo = 50Ω
3.3V
R1
R2
50Ω
50Ω
PCLK
Zo = 50Ω
Zo = 50Ω
R1
100Ω
PCLK
nPCLK
Zo = 50Ω
LVPECL
nPCLK
CML Built-In Pullup
Input
LVPECL
Input
CML
Figure 4B. PCLK/nPCLK Input Driven by a
Built-In Pullup CML Driver
Figure 4A. PCLK/nPCLK Input Driven by a CML Driver
3.3V
3.3V
3.3V
3.3V
3.3V
R3
R4
C1
C2
Zo = 50Ω
Zo = 50Ω
125Ω
125Ω
3.3V LVPECL
PCLK
Zo = 50Ω
Zo = 50Ω
PCLK
VBB
nPCLK
LVPECL
Input
nPCLK
R5
R6
R1
50Ω
R2
50Ω
LVPECL
Input
100Ω - 200Ω 100Ω - 200Ω
LVPECL
R1
R2
84Ω
84Ω
Figure 4D. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver with AC Couple
Figure 4C. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver
2.5V
3.3V
2.5V
R3
R4
120
120
Zo = 60Ω
Zo = 60Ω
PCLK
nPCLK
LVPECL
Input
SSTL
R1
120
R2
120
Figure 4E. PCLK/nPCLK Input Driven by a
2.5V SSTL Driver
ICS8543BG REVISION E DECEMBER 17, 2010
12
©2010 Integrated Device Technology, Inc.
ICS8543 Data Sheet
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
CLK/nCLK INPUTS
LVDS Outputs
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from CLK to ground.
All unused LVDS outputs should be terminated with 100Ω resistor
between the differential pair.
PCLK/nPCLK INPUTS
For applications not requiring the use of the differential input, both
PCLK and nPCLK can be left floating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from PCLK to
ground.
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
LVDS Driver Termination
A general LVDS interface is shown in Figure 5. Standard termination
for LVDS type output structure requires both a 100Ω parallel resistor
at the receiver and a 100Ω differential transmission line environment.
In order to avoid any transmission line reflection issues, the 100Ω
resistor must be placed as close to the receiver as possible. IDT
offers a full line of LVDS compliant devices with two types of output
structures: current source and voltage source. The standard
termination schematic as shown in Figure 5 can be used with either
type of output structure. If using a non-standard termination, it is
recommended to contact IDT and confirm if the output is a current
source or a voltage source type structure. In addition, since these
outputs are LVDS compatible, the amplitude and common mode
input range of the input receivers should be verified for compatibility
with the output.
+
LVDS
Receiver
–
LVDS Driver
100Ω
100Ω Differential Transmission Line
Figure 5. Typical LVDS Driver Termination
ICS8543BG REVISION E DECEMBER 17, 2010
13
©2010 Integrated Device Technology, Inc.
ICS8543 Data Sheet
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS8543.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8543 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
•
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 50mA = 173.25mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 73.2°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.173W * 73.2°C/W = 82.7°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resitance θJA for 20 Lead TSSOP, Forced Convection
θJA by Velocity
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
98.0°C/W
66.6°C/W
88.0°C/W
63.5°C/W
ICS8543BG REVISION E DECEMBER 17, 2010
14
©2010 Integrated Device Technology, Inc.
ICS8543 Data Sheet
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Reliability Information
Table 7. θJA vs. Air Flow Table for a 20 Lead TSSOP
θJA by Velocity
0
Linear Feet per Minute
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
98.0°C/W
66.6°C/W
88.0°C/W
63.5°C/W
Transistor Count
The transistor count for ICS8543 is: 636
Package Outline and Package Dimensions
Package Outline - G Suffix for 20 Lead TSSOP
Table 8. Package Dimensions
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
A
20
1.20
0.15
1.05
0.30
0.20
6.60
A1
A2
b
0.05
0.80
0.19
0.09
6.40
c
D
E
6.40 Basic
E1
e
4.30
4.50
0.65 Basic
L
0.45
0°
0.75
8°
α
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
ICS8543BG REVISION E DECEMBER 17, 2010
15
©2010 Integrated Device Technology, Inc.
ICS8543 Data Sheet
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Ordering Information
Table 9. Ordering Information
Part/Order Number
8543BG
8543BGT
8543BGLF
8543BGLFT
Marking
ICS8543BG
ICS8543BG
ICS8543BGLF
ICS8543BGLF
Package
20 Lead TSSOP
20 Lead TSSOP
Shipping Packaging
Tube
2500 Tape & Reel
Tube
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
“Lead-Free” 20 Lead TSSOP
“Lead-Free” 20 Lead TSSOP
2500 Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product
for use in life support devices or critical medical instruments.
ICS8543BG REVISION E DECEMBER 17, 2010
16
©2010 Integrated Device Technology, Inc.
ICS8543 Data Sheet
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Revision History Sheet
Rev
A
Table
Page
Description of Change
Date
T4E
5
3
3
In the VOL row, 1.06 has been moved to the Typical column from the maximum column.
Updated Figure 1, CLK_EN Timing Diagram.
9/18/01
10/17/01
11/2/01
A
A
Updated Figure 1, CLK_EN Timing Diagram.
1
Features section, Bullet 6 to read 3.3V LVDS levels instead of LVPECL.
Updated Parameter Measurement Information figures.
A
B
5/6/02
6/5/02
6 - 10
T5
5
1
AC Characteristics table - revised Output Frequency from 650MHz to 800MHz.
Features - deleted bullet "Designed to meet or exceed the requirements of
ANSI TIA/EIA-644".
C
9/19/02
4E
T2
5
LVDS Table - changed VOD typical value from 350mV to 280mV.
2
4
Pin Characteristics - changed CIN 4pF max. to 4pF typical.
Absolute Maximum Ratings - changed Output rating.
Added Differential Clock Input Interface section.
Added LVPECL Clock Input Interface section.
Added LVDS Driver Termination section.
9
D
12/31/03
10
11
Updated format throughout data sheet.
D
D
T1
T8
2
Pin Description table - added function description to the OE pin.
4/7/04
10
13
Updated LVPECL Clock Input Interface section.
6/16/04
Added Lead Free part number to Ordering Information table.
3
Updated Figure 1, CLK_EN Timing Diagram.
Updated Differential Clock Input Interface section.
Updated LVPECL Clock Input Interface section.
Added Recommendation for Unused Input and Output Pins section.
Added Power Considerations section.
10
11
12
13
D
2/27/08
Updated format throughout the datasheet.
1
Features section - added Additive Phase Jitter bullet.
AC Characteristics Table - added Added Phase Jitter spec and thermal note.
Added Additive Phase Jitter plot.
T5
T9
6
7
10
11
12
13
16
Updated Wiring the Differential Input to Accept Single-ended Levels section.
Updated 3.3V Differential Clock Input Interface section.
Updated 3.3V LVPECL Clock Input Interface section.
Updated LVDS Driver Termination section.
E
E
11/12/10
12/17/10
Ordering Information Table - deleted “ICS” prefix from Part/Order Number column.
Updated datasheet header/footer style.
1
Page 1, corrected Header Title.
14
Power Considerations - corrected typo for junction temperature from 827.7°C to 82.7°C.
ICS8543BG REVISION E DECEMBER 17, 2010
17
©2010 Integrated Device Technology, Inc.
ICS8543 Data Sheet
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
We’ve Got Your Timing Solution
6024 Silver Creek Valley Road Sales
Technical Support
800-345-7015 (inside USA)
netcom@idt.com
San Jose, California 95138
+408-284-8200 (outside USA) +480-763-2056
Fax: 408-284-2775
www.IDT.com/go/contactIDT
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any
license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT
product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third
party owners.
Copyright 2010. All rights reserved.
相关型号：
ICS8543BGIT
Low Skew Clock Driver, 4 True Output(s), 0 Inverted Output(s), PDSO20, 4.40 X 6.50 MM, 0.92 MM HEIGHT, MO-153, TSSOP-20
IDT
ICS85454-01LF
Low Skew Clock Driver, 85454 Series, 3 True Output(s), 0 Inverted Output(s), 3 X 3 MM, 0.95 MM HEIGHT, ROHS COMPLIANT, MO-220, VFQFN-32
IDT
ICS85454-01T
Low Skew Clock Driver, 85454 Series, 3 True Output(s), 0 Inverted Output(s), 3 X 3 MM, 0.95 MM HEIGHT, MO-220, VFQFN-32
IDT
ICS85454AK
Low Skew Clock Driver, 85454 Series, 3 True Output(s), 0 Inverted Output(s), 3 X 3 MM, 0.95 MM HEIGHT, MO-220, VFQFN-16
IDT
©2020 ICPDF网 联系我们和版权申明