ICS8543BGT [ICSI]
LOW SKEW, 1-TO-4 LVDS FANOUT BUFFER; 低偏移， 1到4 LVDS扇出缓冲器
| 型号： | ICS8543BGT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-4 LVDS FANOUT BUFFER |
| 文件： | 总7页 (文件大小：94K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS8543
LOW SKEW, 1-TO-4
LVDS FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
GENERAL DESCRIPTION
FEATURES
The ICS8543 is a low skew, high performance • 4 LVDS outputs
,&6
1-to-4 clock fanout buffer and a member of
• Designed to meet or exceed the requirements of ANSI
TIA/EIA-644
HiPerClockS™
the HiPerClockS™ family of High Performance
Clock Solutions from ICS. Utilizing Low Voltage
Differential Signaling (LVDS) the ICS8543
• Selectable differential HSTL or LVPECL clock inputs
• LVCMOS / LVTTL control inputs
• 3.3V operating supply
provides a low power, low noise, solution for distributing clock
signals over controlled impedances of 100Ω. The ICS8543
accepts any differential input level and translates it to 3.3V
LVDS output levels.
• 20 lead TSSOP
Guaranteed output and part-to-part skew characteristics
make the ICS8543 ideal for those applications demanding
well defined performance and repeatability.
• 0°C to 70°C ambient operating temperature
BLOCK DIAGRAM
PIN ASSIGNMENT
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
VEE
CLK_EN
CLK_SEL
HCLK
nHCLK
PCLK
nPCLK
OE
VEE
nD
LE
CLK_EN
nQ0
VDD
Q1
nQ1
Q2
nQ2
VEE
Q3
Q
HCLK
nHCLK
PCLK
0
1
Q0
nQ0
nPCLK
Q1
nQ1
CLK_SEL
VDD
nQ3
Q2
nQ2
ICS8543
Q3
nQ3
20-Lead TSSOP
G Package
Top View
OE
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
ICS8543BG
www.icst.com/products/hiperclocks.html
REV. C MAY 21, 2001
1
PRELIMINARY
ICS8543
LOW SKEW, 1-TO-4
LVDS FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 9, 13
VEE
Power
Input
Power supply ground. Connect to ground.
Synchronous clock enable. When HIGH clock outputs follows clock
input. When LOW, Q outputs are force low, nQ outputs are force high.
LVCMOS / LVTTL interface levels.
2
3
CLK_EN
Pullup
Clock select input. When HIGH selects differential PECL inputs.
CLK_SEL
Input
Pulldown When LOW selects differential HSTL inputs.
LVCMOS / LVTTL interface levels.
4
5
6
7
HCLK
nHCLK
PCLK
Input
Input
Input
Input
Pulldown Non-inverting differential HSTL clock input.
Pullup
Inverting differential HSTL clock input.
Pulldown Non-inverting differential PECL clock input.
nPCLK
Pullup
Pullup
Inverting differential PECL clock input.
Output enable. Controls enabling and disabling of outputs Q0, nQ0
thru Q3, nQ3
8
OE
Input
10, 18
11, 12
14, 15
16, 17
19, 20
VDD
Power
Output
Output
Output
Output
Power supply pin. Connect to 3.3V.
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
Differential clock outputs. LVDS interface levels.
Differential clock outputs. LVDS interface levels.
Differential clock outputs. LVDS interface levels.
Differential clock outputs. LVDS interface levels.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
HCLK, nHCLK
PCLK, nPLCK
4
4
pF
pF
CIN
Input Capacitance
CLK_EN,
CLK_SEL
4
pF
RPULLUP
Input Pullup Resistor
51
51
KΩ
KΩ
RPULLDOWN Input Pulldown Resistor
ICS8543BG
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REV. C MAY 21, 2001
2
PRELIMINARY
ICS8543
LOW SKEW, 1-TO-4
LVDS FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 3A. CONTROL INPUTS FUNCTION TABLE
Inputs
Outputs
nQ1 thru nQ3
Hi Z
OE
0
CLK_EN
CLK_SEL
Q1 thru Q3
X
0
0
1
1
X
0
1
0
1
Hi Z
Low
1
High
1
Low
High
1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
1
In the active mode the state of the output is a function of the HCLK, nHCLK and PCLK, nPCLK inputs as described in
Table 3B.
TABLE 3B. CLOCK INPUTS FUNCTION TABLE
Inputs
Outputs
nQ0 thru nQ3
Input to Output Mode
Polarity
HCLK, PCLK
nHCLK, nPCLK
Q0 thru Q3
LOW
0
1
HIGH
LOW
HIGH
LOW
LOW
HIGH
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
1
0
HIGH
0
Biased; NOTE 1
LOW
1
Biased; NOTE 1
HIGH
Biased; NOTE 1
Biased; NOTE 1
0
1
HIGH
LOW
Inverting
NOTE 1: Single ended use requires that one of the differential inputs be biased. The voltage at the biased input sets the
switch point for the single ended input. For LVCMOS and LVTTL levels the recommended input bias network is a resistor to
VCC, a resistor of equal value to ground and a 0.1µF capacitor from the input to ground. The resulting switch point is
approximately VCC/2 ± 300mV.
ICS8543BG
www.icst.com/products/hiperclocks.html
REV. C MAY 21, 2001
3
PRELIMINARY
ICS8543
LOW SKEW, 1-TO-4
LVDS FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
4.6V
Inputs
Outputs
Ambient Operating Temperature
Storage Temperature
-0.5V to VDD + 0.5V
-0.5V to VDD + 0.5V
0°C to 70°C
-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of product at these condition or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, TA=0°C TO 70°C
Symbol
VDD
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Power Supply Voltage
Power Supply Current
3.135
3.3
3.465
50
V
IEE
mA
TABLE 4B. LVPECL DC CHARACTERISTICS, VDD = 3.3V±5%, TA=0°C TO 70°C
Symbol Parameter Test Conditions
Minimum
Typical Maximum Units
PCLK
150
5
µA
µA
µA
µA
V
IIH
IIL
Input High Current
nPCLK
PCLK
-5
Input Low Current
nPCLK
-150
0.15
1.5
VPP
Peak-to-Peak Input Voltage
1.3
3.3
VCMR
Common Mode Input Voltage; NOTE 1
V
NOTE 1: Common mode voltage for LVPECL is defined as the minimum VIH.
TABLE 4C. LVHSTL DC CHARACTERISTICS, VDD = 3.3V±5%, TA=0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
HCLK
3.135V ≤ VDDI ≤ 3.465V
3.135V ≤ VDDI ≤ 3.465V
3.135V ≤ VDDI ≤ 3.465V
3.135V ≤ VDDI ≤ 3.465V
150
5
µA
µA
µA
µA
V
IIH
IIL
Input High Current
nHCLK
HCLK
-5
Input Low Current
nHCLK
-150
0.15
0.5
VPP
Peak-to-Peak Input Voltage
1.3
VCMR
Common Mode Input Voltage; NOTE 1
VDD - 0.85
V
NOTE 1: Common mode voltage for HSTL is defined as the crossover voltage. VCMR is compatible with DCM, LVDS and
SSTL inputs.
ICS8543BG
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REV. C MAY 21, 2001
4
PRELIMINARY
ICS8543
LOW SKEW, 1-TO-4
LVDS FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 4D. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, TA=0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH
VIL
Input High Voltage CLK_EN, CLK_SEL, OE
2
V
Input Low Voltage CLK_EN, CLK_SEL, OE
0.8
5
V
CLK_EN, OE
Input High Current
µA
µA
µA
µA
IIH
IIL
CLK_SEL
150
CLK_EN, OE
Input Low Current
-150
-5
CLK_SEL
TABLE 4E. LVDS DC CHARACTERISTICS, VDD = 3.3V±5%, TA=0°C TO 70°C
Symbol
VOD
Parameter
Test Conditions
Minimum
Typical
350
4
Maximum Units
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
250
450
35
mV
mV
V
∆ VOD
VOS
1.125
1.25
5
1.375
25
∆ VOS
IOZ
VOS Magnitude Change
High Impedance Leakage Current
Power Off Leakage
mV
µA
µA
mA
mA
-10
-20
±1
+10
+20
IOFF
IOSD
IOS
±1
Differential Output Short Circuit Current
Output Short Circuit Current
3.0
3.0
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V±5%, TA=0°C TO 70°C
Symbol
fMAX
tpLH
tsk(o)
tsk(pp)
tR
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
MHz
ns
Maximum Input Frequency
Propagation Delay, Low-to-High
Output Skew; NOTE 2
Part-to-Part Skew; NOTE 3
Output Rise Time
650
0 ≤ f ≤ 650MHz
1.8
2.4
50
ps
300
ps
RL = 100Ω
RL = 100Ω
200
200
400
400
600
600
ps
tF
Output Fall Time
ps
tPW
Output Pulse Width
Output Enable Time
Output Disable Time
tCYCLE/2 - TBD
tCYCLE/2 + TBD
TBD
ns
tEN
ns
tDIS
TBD
ns
NOTE 1: All parameters measured at fMAX unless noted otherwise.
NOTE 2: Defined as skew across outputs at the same supply voltages and with equal load conditions.
Measured from the 50% point of the input to the differential output crossing point.
NOTE 3: Defined as skew at different outputs on different devices operating at the same supply voltages
and with equal load conditions. Measured from 50% of like inputs to the differential output crossing point.
ICS8543BG
www.icst.com/products/hiperclocks.html
REV. C MAY 21, 2001
5
PRELIMINARY
ICS8543
LOW SKEW, 1-TO-4
LVDS FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
PACKAGE OUTLINE - G SUFFIX
c
N
20
11
10
L
E1
E
1
α
D
A2
A
-C-
e
A1
SEATING
PLANE
b
aaa
C
TABLE 6. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Inches
MIN
MAX
MIN
MAX
N
A
20
--
1.20
0.15
1.05
0.30
0.20
6.60
--
0.047
0.006
0.041
0.012
0.008
0.260
A1
A2
b
0.05
0.80
0.19
0.09
6.40
0.002
0.032
0.007
0.0035
0.252
c
D
E
6.40 BASIC
0.252 BASIC
0.169 0.177
0.0256 BASIC
E1
e
4.30
4.50
0.65 BASIC
L
0.45
0°
0.75
8°
0.018
0.030
8°
α
0°
aaa
--
0.10
--
0.004
Reference Document: JEDEC Publication 95, MO-153
ICS8543BG
www.icst.com/products/hiperclocks.html
REV. C MAY 21, 2001
6
PRELIMINARY
ICS8543
LOW SKEW, 1-TO-4
LVDS FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 7. ORDERING INFORMATION
Part/Order Number
ICS8543BG
Marking
Package
Count
72 per tube
2500
Temperature
0°C to 70°C
0°C to 70°C
ICS8543BG
ICS8543BG
20 lead TSSOP
ICS8543BGT
20 lead TSSOP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
ICS8543BG
www.icst.com/products/hiperclocks.html
REV. C MAY 21, 2001
7
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