ICS853L022AGLF [IDT]
TTL/CMOS to PECL Translator, 2 Func, Complementary Output, PDSO8, 3 X 3 MM, 0.95 MM HEIGHT, LEAD FREE, MO-187, TSSOP-8;
| 型号： | ICS853L022AGLF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | TTL/CMOS to PECL Translator, 2 Func, Complementary Output, PDSO8, 3 X 3 MM, 0.95 MM HEIGHT, LEAD FREE, MO-187, TSSOP-8 光电二极管 接口集成电路 锁存器 |
| 文件： | 总11页 (文件大小：264K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS853L022
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
3.3V LVPECL TRANSLATOR
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS853L022 is a Dual LVCMOS / LVTTL-to- • 2 differential LVPECL outputs
ICS
Differential 3.3V LVPECL translator and a mem-
ber of the HiPerClocks™ family of High
Performance Clocks Solutions from ICS. The
ICS853L022 has single ended clock inputs. The
• LVCMOS/LVTTL clock inputs
HiPerClockS™
• Output frequency: 350MHz (typical)
• Part-to-part skew: 400 (maximum)
• Propagation Delay: 450ps (typical)
• Additive phase jitter, RMS: 0.03ps (typical)
single ended clock input accepts LVCMOS or LVTTL input lev-
els and translate them to LVPECL levels. The small outline 8-
pin TSSOP package makes this device ideal for applications
where space, high performance and low power are important.
• LVPECL mode operating voltage supply range:
VCC = 3.0V to 3.8V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.8V to -3.0V
• -40°C to 85°C ambient operating temperature
• Lead-Free package RoHS compliant
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0
nQ0
D0
Q0
nQ0
Q1
VCC
D0
D1
VEE
1
2
3
4
8
7
6
5
Q1
nQ1
D1
nQ1
ICS853L022
8-LeadTSSOP, 118 mil
3mm x 3mm x 0.95mm package body
G Package
TopView
8-Lead SOIC, 150 mil
3.90mm x 4.90mm x 1.37mm package body
M Package
TopView
853L022AG
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 29, 2008
1
ICS853L022
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
3.3V LVPECL TRANSLATOR
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
Name
Q0, nQ0
Q1, nQ1
VEE
Type
Description
1, 2
3, 4
5
Output
Output
Power
Input
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Negative supply pin.
6
D1
LVCMOS / LVTTL clock input.
LVCMOS / LVTTL clock input.
Positive supply pin.
7
D0
Input
8
VCC
Power
853L022AG
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 29, 2008
2
ICS853L022
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
3.3V LVPECL TRANSLATOR
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, VCC
4.6V (LVPECL mode, VEE = 0) NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
Negative Supply Voltage, VEE
Inputs, VI (LVPECL mode)
Inputs, VI (ECL mode)
-4.6V (ECL mode, VCC = 0)
-0.5V to VCC + 0.5 V
0.5V to VEE - 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
OperatingTemperature Range, TA -40°C to +85°C
StorageTemperature,TSTG -65°C to 150°C
PackageThermal Impedance, θJA 101.7°C/W (0 m/s)TSSOP
112.7°C/W (0 lfpm) SOIC
(Junction-to-Ambient)
TABLE 2A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.0V TO 3.8V; VEE = 0V
Symbol Parameter Test Conditions
Minimum Typical Maximum Units
VCC
IEE
Positive Supply Voltage
Power Supply Current
3.0
3.3
3.8
30
V
mA
TABLE 2B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = 3.0V TO 3.8V; VEE = 0V
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VIH
VIL
IIH
Input High Voltage
0.7 * VCC
V
Input Low Voltage
Input High Current
Input Low Current
0.3 * VCC
100
V
VCC = VIN = 3.8V
µA
mA
IIL
VCC = 3.8V, VIN = 0V
-0.6
TABLE 2C. LVPECL DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V
-40°C
25°C
85°C
Symbol Parameter
Units
Min
2.175
1.405
Typ
Max
2.38
1.68
Min
2.225 2.295
1.425 1.52
Typ
Max
Min
2.295
1.44
Typ
2.33
Max
2.365
1.63
2.275
1.545
2.37
V
V
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
1.615
1.535
Output parameters vary 1:1 with VCC. VCC can vary 3.8V to 3.0V.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
853L022AG
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 29, 2008
3
ICS853L022
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
3.3V LVPECL TRANSLATOR
Integrated
Circuit
Systems, Inc.
TABLE 2D. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -3.8V TO -3.0V
-40°C
25°C
Typ
85°C
Typ
Symbol Parameter
Units
Min
Typ
Max
Min
Max
Min
Max
-1.125 -1.025 -0.92 -1.075 -1.005 -0.93 -1.005 -0.97 -0.935
-1.895 -1.755 -1.62 -1.875 -1.78 -1.685 -1.86 -1.765 -1.67
VOH
VOL
VPP
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Input Voltage
V
V
150
800
1200
150
800
1200
150
800
1200
mV
Output parameters vary 1:1 with VCC.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
TABLE 3. AC CHARACTERISTICS, VCC = 0V; VEE = -3.8V TO -3.0V OR VCC = 3.0V TO 3.8V; VEE = 0V
-40°C 25°C
Min Typ Max Min Typ
85°C
Symbol Parameter
Units
Max Min Typ
Max
fMAX
Output Frequency
350
300 525
10
350
300 450
10
350
MHz
ps
Propagation Delay, Low to High;
NOTE 1
tpLH
750
600
300 450
10
600
tsk(o)
Output Skew; NOTE 2, 4
45
45
45
ps
ps
tsk(pp)
Part-to-Part Skew; NOTE 3, 4
225
225
225
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section
tjit
0.03
0.03
0.03
ps
ps
tR/tF
Output Rise/Fall Time
20% to 80%
100 325
550
100 325
550
100 325
550
All parameters are measured ≤ 350MHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
853L022AG
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 29, 2008
4
ICS853L022
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
3.3V LVPECL TRANSLATOR
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
2V
nQx
Qx
SCOPE
VCC
Qx
nQy
Qy
LVPECL
nQx
VEE
tsk(o)
-1.8V to -1.0V
OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
nQx
PART 1
Qx
D0, D1
nQy
PART 2
Qy
nQ0, nQ1
Q0, Q1
tsk(pp)
tpLH
PROPAGATION DELAY
PART-TO-PART SKEW
80%
tF
80%
VSWING
20%
Clock
20%
Outputs
tR
OUTPUT RISE/FALL TIME
853L022AG
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 29, 2008
5
ICS853L022
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
3.3V LVPECL TRANSLATOR
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs.The two different layouts mentioned
are recommended only as guidelines.
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 1A and 1B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs.Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 1A. LVPECL OUTPUT TERMINATION
FIGURE 1B. LVPECL OUTPUT TERMINATION
853L022AG
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 29, 2008
6
ICS853L022
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
3.3V LVPECL TRANSLATOR
Integrated
Circuit
Systems, Inc.
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853L022.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853L022 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.8V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 30mA = 114mW
Power (outputs)MAX = 30.94mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30.94mW = 61.88mW
Total Power_MAX (3.8V, with all outputs switching) = 114mW + 61.88mW = 175.88mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total =Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 1 meters per second and a multi-layer board, the appropriate value is 90.5°C/W perTable 4A below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.176W * 90.5°C/W = 100.9°C. This is below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 4A. THERMAL RESISTANCE θJA FOR 8-PIN TSSOP, FORCED CONVECTION
θJA byVelocity (Meters per Second)
0
1
2
Multi-Layer PCB, JEDEC StandardTest Boards
101.7°C/W
90.5°C/W
89.8°C/W
TABLE 4B. THERMAL RESISTANCE θJA FOR 8 LEAD SOIC
θJA byVelocity (Linear Feet per Minute)
0
200
128.5°C/W
103.3°C/W
500
115.5°C/W
97.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
153.3°C/W
112.7°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
853L022AG
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 29, 2008
7
ICS853L022
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
3.3V LVPECL TRANSLATOR
Integrated
Circuit
Systems, Inc.
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in Figure 4.
VCC
Q1
VOUT
RL
50
VCC - 2V
Figure 4. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage ofV - 2V.
CCO
•
•
For logic high, VOUT = V
= V
– 0.935V
OH_MAX
CCO_MAX
)
= 0.935V
OH_MAX
(V
- V
CC_MAX
For logic low, VOUT = V
= V
– 1.67V
CCO_MAX
OL_MAX
)
= 1.67V
OL_MAX
(V
- V
CCO_MAX
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
_MAX
CCO
OH_MAX
CCO _MAX
OH_MAX
L
L
[(2V - 0.935V)/50Ω] * 0.935V = 19.92mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
- V
/R ] * (V
- V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
_MAX
OL_MAX
CCO_MAX
OL_MAX
L
CCO
L
[(2V - 1.67V)/50Ω] * 1.67V = 11.02mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
853L022AG
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 29, 2008
8
ICS853L022
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
3.3V LVPECL TRANSLATOR
Integrated
Circuit
Systems, Inc.
RELIABILITY INFORMATION
TABLE 5A. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP
θJA byVelocity (Meters per Second)
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards
101.7°C/W
90.5°C/W
89.8°C/W
TABLE 5B. θJAVS. AIR FLOW TABLE FOR 8 LEAD SOIC
θJA byVelocity (Linear Feet per Minute)
0
200
128.5°C/W
103.3°C/W
500
115.5°C/W
97.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
153.3°C/W
112.7°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS853L022 is: 92
Pin compatible with MC100LVELT22
853L022AG
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 29, 2008
9
ICS853L022
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
3.3V LVPECL TRANSLATOR
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP
PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC
TABLE 6A. PACKAGE DIMENSIONS
TABLE 6B. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Millimeters
SYMBOL
Minimum
Maximum
MINIMUN
MAXIMUM
N
A
8
N
A
A1
B
C
D
E
e
8
--
1.10
0.15
0.97
0.38
0.23
1.35
0.10
0.33
0.19
4.80
3.80
1.75
0.25
0.51
0.25
5.00
4.00
A1
A2
b
0
0.79
0.22
0.08
c
D
3.00 BASIC
4.90 BASIC
3.00 BASIC
0.65 BASIC
1.95 BASIC
E
1.27 BASIC
E1
e
H
h
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
e1
L
L
0.40
0°
0.80
8°
α
α
Reference Document: JEDEC Publication 95, MS-012
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-187
853L022AG
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 29, 2008
10
ICS853L022
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
3.3V LVPECL TRANSLATOR
Integrated
Circuit
Systems, Inc.
TABLE 7. ORDERING INFORMATION
Part/Order Number
853L022AG
Marking
Package
8 lead TSSOP
Shipping Packaging
tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
022A
022A
853L022AGT
8 lead TSSOP
2500 tape & reel
tube
853L022AGLF
853L022AGLFT
853L022AM
L2AL
8 lead "Lead-Free" TSSOP
8 lead "Lead-Free" TSSOP
8 lead SOIC
L2AL
2500 tape & reel
tube
53L022A
53L022A
53L022AL
53L022AL
853L022AMT
853L022AMLF
853L022AMLFT
8 lead SOIC
2500 tape & reel
tube
8 lead "Lead-Free" SOIC
8 lead "Lead-Free" SOIC
2500 tape & reel
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
853L022AG
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 29, 2008
11
相关型号：
ICS853L022AGLFT
TTL/CMOS to PECL Translator, 2 Func, Complementary Output, PDSO8, 3 X 3 MM, 0.95 MM HEIGHT, LEAD FREE, MO-187, TSSOP-8
IDT
ICS853L022AGT
TTL/CMOS to PECL Translator, 2 Func, Complementary Output, PDSO8, 3 X 3 MM, 0.95 MM HEIGHT, MO-187, TSSOP-8
IDT
ICS853L022AM
TTL/CMOS to PECL Translator, 2 Func, Complementary Output, PDSO8, 3.90 X 4.90 MM, 1.37 MM HEIGHT, MS-012, SOIC-8
IDT
ICS853L022AMLF
TTL/CMOS to PECL Translator, 2 Func, Complementary Output, PDSO8, 3.90 X 4.90 MM, 1.37 MM HEIGHT, LEAD FREE, MS-012, SOIC-8
IDT
ICS853L022AMLFT
TTL/CMOS to PECL Translator, 2 Func, Complementary Output, PDSO8, 3.90 X 4.90 MM, 1.37 MM HEIGHT, LEAD FREE, MS-012, SOIC-8
IDT
ICS853L022AMT
TTL/CMOS to PECL Translator, 2 Func, Complementary Output, PDSO8, 3.90 X 4.90 MM, 1.37 MM HEIGHT, MS-012, SOIC-8
IDT
ICS853P022AGT
TTL/CMOS to PECL Translator, 2 Func, Complementary Output, PDSO8, 3 X 3 MM, 0.95 MM HEIGHT, MO-187, TSSOP-8
IDT
ICS853P022AM
TTL/CMOS to PECL Translator, 2 Func, Complementary Output, PDSO8, 3.90 X 4.90 MM, 1.37 MM HEIGHT, SOIC-8
IDT
ICS853P022AMT
TTL/CMOS to PECL Translator, 2 Func, Complementary Output, PDSO8, 3.90 X 4.90 MM, 1.37 MM HEIGHT, SOIC-8
IDT
ICS853S012AKI
Low Skew Clock Driver, 853S Series, 1 True Output(s), 0 Inverted Output(s), 5 MM X 5 MM, 0.75 MM HEIGHT, MO-220VHHD-2, VFQFN-32
IDT
ICS853S012AKILF
Low Skew Clock Driver, 853S Series, 1 True Output(s), 0 Inverted Output(s), 5 MM X 5 MM, 0.75 MM HEIGHT, ROHS COMPLIANT, MO-220VHHD-2, VFQFN-32
IDT
©2020 ICPDF网 联系我们和版权申明