ICS853111BY-02T [IDT]
Low Skew Clock Driver, 10 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1 MM HEIGHT, TQFP-32;
| 型号： | ICS853111BY-02T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 10 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1 MM HEIGHT, TQFP-32 驱动 逻辑集成电路 |
| 文件： | 总10页 (文件大小：151K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS853111-02
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS853111-02 is a low skew, high per- • 10 differential 2.5V/3.3V LVPECL / ECLoutputs
formance 1-to-10 Differential-to-2.5V/3.3V
LVPECL/ECL Fanout Buffer and a mem-
• 2 selectable differential input pairs
HiPerClockS™
ber of the HiPerClockS™ family of High
Performance Clock Solutions from ICS.
• PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
The ICS853111-02 is characterized to operate from
either a 2.5V or a 3.3V power supply. Guaranteed
output and part-to-part skew characteristics make
the ICS853111-02 ideal for those clock distribution
applications demanding well defined performance
and repeatability.
• Maximum output frequency: >3GHz
• Translates any single ended input signal to 3.3V
LVPECLlevels with resistor bias on nPCLK input
• Output skew: 20ps (typical)
• Part-to-part skew: 85ps (typical)
• Propagation delay: TBD
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.8V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -2.375V to -3.8V
• -40°C to 85°C ambient operating temperature
• Pin compatible with MC100EP111 and MC100LVEP111
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0
nQ0
PCLK0
nPCLK0
0
1
PCLK1
nPCLK1
Q1
nQ1
24 23 22 21 20 19 18 17
VCCO
nQ2
Q2
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
VCCO
Q7
Q2
nQ2
nQ7
Q8
CLK_SEL
VBB
Q3
nQ3
nQ1
Q1
ICS853111-02
nQ8
Q9
Q4
nQ4
nQ0
Q0
nQ9
Q5
nQ5
VCCO
VCCO
1
2
3
4
5
6
7
8
Q6
nQ6
Q7
nQ7
32-Lead TQFP
Q8
7mm x 7mm x 1.0mm package body
nQ8
Y Package
Top View
Q9
nQ9
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
853111BY-02
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 27, 2003
1
PRELIMINARY
ICS853111-02
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
VCC
Power
Core supply pin.
Clock select input. When HIGH, selects PCLK1, nPCLK1 inputs. When
LOW, selects PCLK0, nPCLK0 inputs. LVCMOS / LVTTL interface levels.
2
CLK_SEL
Input Pulldown
3
4
PCLK0
nPCLK0
VBB
Input Pulldown Non-inverting differential clock input.
Input
Clock input. VCC/2 default when left floating.
Bias voltage.
5
Output
6
PCLK1
nPCLK1
VEE
Input Pulldown Non-inverting differential clock input.
7
Input
Power
Power
Clock input. VCC/2 default when left floating.
Negative supply pin.
8
9, 16, 25, 32
10, 11
12, 13
14, 15
17, 18
19, 20
21, 22
23, 24
26, 27
28, 29
30, 31
VCCO
Output supply pins.
nQ9, Q9 Output
nQ8, Q8 Output
nQ7, Q7 Output
nQ6, Q6 Output
nQ5, Q5 Output
nQ4, Q4 Output
nQ3, Q3 Output
nQ2, Q2 Output
nQ1, Q1 Output
nQ0, Q0 Output
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
4
RPULLUP
37.5
75
KΩ
RPULLDOWN Input Pulldown Resistor
KΩ
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
CLK_SEL
Selected Source
0
1
CLK0, nCLK0
CLK1, nCLK1
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Input to Output Mode
Polarity
CLK0 or CLK1
nCLK0 or nCLK1
Q0:Q9
nQ0:Q9
HIGH
LOW
0
1
LOW
HIGH
LOW
HIGH
HIGH
LOW
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
1
0
0
Biased; NOTE 1
HIGH
LOW
1
Biased; NOTE 1
Biased; NOTE 1
Biased; NOTE 1
0
1
LOW
HIGH
Inverting
NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to Accept Single Ended Levels".
853111BY-02
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REV. A FEBRUARY 27, 2003
2
PRELIMINARY
ICS853111-02
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
Negative Supply Voltage, VEE
Inputs, VI
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
4.6V
-4.6V
-0.5V to VCC + 0.5 V
0.5V to VEE - 0.5V
± 0.5mA
Outputs, VO
VBB Sink/Source, IBB
Operating Temperature Range, TA -40°C to +85°C
Storage Temperature, TSTG -65°C to 150°C
Package Thermal Impedance, θJA 49.5°C/W (0 lfpm)
(Junction-to-Ambient)
Package Thermal Impedance, θJC 12°C/W to 17°C/W
(Junction-to-Case)
Wave Solder, TSOL
265°C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375 TO 3.8V; VEE = 0V
Symbol Parameter Test Conditions
Minimum Typical Maximum Units
VCC
IEE
Positive Supply Voltage
Power Supply Current
2.375
3.3
3.8
V
TBD
mA
TABLE 4B. LVPECL DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V
-40°C
25°C
Typ
85°C
Symbol Parameter
Units
Min Typ Max Min
Max Min Typ Max
VOH
VOL
VSWING
VIH
Output High Voltage; NOTE 1
2280
1480
800
mV
mV
mV
mV
mV
mV
mV
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Input High Voltage(Single-Ended)
Input Low Voltage(Single-Ended)
Output Voltage Reference; NOTE 2
Peak-to-Peak Input Voltage
TBD
TBD
TBD
VIL
VBB
VPP
150
1.2
TBD
3.3
Input High Voltage
Common Mode Range; NOTE 3, 4
VCMR
IIH
V
PCLK0, PCLK1
Input High Current
150
µA
nPCLK0, nPCLK1
PCLK0, PCLK1
Input Low Current
-10
-150
IIL
µA
nPCLK0, nPCLK1
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
NOTE 2: Single-ended input operation is limited VCC ≥ 3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as VIH.
NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1
is VCC + 0.3V.
853111BY-02
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REV. A FEBRUARY 27, 2003
3
PRELIMINARY
ICS853111-02
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 2.5V; VEE = 0V
-40°C
25°C
Typ
85°C
Symbol Parameter
Units
Min Typ Max Min
Max
Min Typ Max
VOH
Output High Voltage; NOTE 1
1480
680
mV
mV
mV
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
800
Input High Voltage(Single-Ended);
NOTE 2
Input Low Voltage(Single-Ended);
NOTE 2
VIH
VIL
TBD
mV
mV
TBD
TBD
VBB
VPP
Output Voltage Reference; NOTE 3
Peak-to-Peak Input Voltage
mV
mV
150
1.2
TBD
2.5
Input High Voltage
Common Mode Range; NOTE 4, 5
VCMR
IIH
V
PCLK0, PCLK1
Input High Current
150
µA
nPCLK0, nPCLK1
PCLK0, PCLK1
Input Low Current
-10
-150
IIL
µA
nPCLK0, nPCLK1
Input and output parameters vary 1:1 with VCC. VEE can vary +0.125V to -1.3V.
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
NOTE 2: Do not use VBB at VCC < 3V.
NOTE 3: Single-ended input operation is limited VCC ≥ 3V in LVPECL mode.
NOTE 4: Common mode voltage is defined as VIH.
NOTE 5: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1
is VCC + 0.3V.
TABLE 4C. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -2.375V TO -3.8V
-40°C
25°C
Typ
85°C
Symbol Parameter
Units
Min Typ Max
Min
Max Min Typ Max
VOH
VOL
VSWING
VIH
Output High Voltage; NOTE 1
-1020
-1820
800
mV
mV
mV
mV
mV
mV
mV
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Input High Voltage(Single-Ended)
Input Low Voltage(Single-Ended)
Output Voltage Reference; NOTE 2
Peak-to-Peak Input Voltage
TBD
TBD
TBD
VIL
VBB
VPP
150
TBD
150
Input High Voltage
Common Mode Range; NOTE 3, 4
PCLK0, PCLK1
VCMR
VEE + 1.2
V
IIH
Input High Current
nPCLK0,
µA
nPCLK1
PCLK0, PCLK1
nPCLK0,
nPCLK1
-10
-150
IIL
Input Low Current
µA
Input and output parameters vary 1:1 with VCC.
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
NOTE 2: Single-ended input operation is limited VEE ≤ -3V in ECL mode.
NOTE 3: Common mode voltage is defined as VIH.
NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1
is VCC + 0.3V.
853111BY-02
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REV. A FEBRUARY 27, 2003
4
PRELIMINARY
ICS853111-02
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -2.375V TO -3.8V OR VCC = 2.375 TO 3.8V; VEE = 0V
-40°C 25°C
Min Typ Max Min Typ
85°C
Max Min Typ
Symbol Parameter
Units
Max
fMAX
Output Frequency
>3
TBD
20
GHz
ps
tPD
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
tsk(o)
tsk(pp)
tR/tF
ps
Part-to-Part Skew; NOTE 3, 4
85
ps
Output Rise/Fall Time
20% to 80%
TBD
ps
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
853111BY-02
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REV. A FEBRUARY 27, 2003
5
PRELIMINARY
ICS853111-02
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
VCC, VCCO = 2V
VCC
SCOPE
Qx
nCLK0, nCLK1
VPP
LVPECL
VCMR
Cross Points
CLK0, CLK1
nQx
VEE
VEE = -0.375V to -1.8V
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx
PART 1
Qx
nQx
Qx
nQy
nQy
PART 2
Qy
Qy
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nCLK0,
nCLK1
80%
80%
CLK0,
CLK1
VSWING
20%
20%
nQ0:nQ9
Clock Outputs
t
t
F
R
Q0:Q9
tPD
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
853111BY-02
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REV. A FEBRUARY 27, 2003
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PRELIMINARY
ICS853111-02
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows an example of the differential input that can
be wired to accept single ended levels. The reference voltage
level VBB generated from the device is connected to the
negative input. The C1 capacitor should be located as close
as possible to the input pin.
VDD(or VCC)
CLK_IN
+
VBB
-
C1
0.1uF
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termina-
50Ω transmission lines. Matched impedance techniques should
tion for LVPECL outputs. The two different layouts mentioned be used to maximize operating frequency and minimize signal
are recommended only as guidelines.
distortion. Figures 3A and 3B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECLcompatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Zo = 50Ω
5
2
5
Zo
Zo
2
FIN
FOUT
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
➤
V
CC - 2V
Zo = 50Ω
RTT
1
3
2
3
2
Zo
RTT =
Zo
Zo
(VOH + VOL / VCC –2) –2
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
853111BY-02
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REV. A FEBRUARY 27, 2003
7
PRELIMINARY
ICS853111-02
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
69.3°C/W
57.8°C/W
52.1°C/W
49.5°C/W
43.8°C/W
41.3°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS853111-02 is: 1340
853111BY-02
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REV. A FEBRUARY 27, 2003
8
PRELIMINARY
ICS853111-02
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TQFP PACKAGE OUTLINE - Y SUFFIX
-HD VERSION
HEAT SLUG DOWN
TABLE 7. TQFP PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
ABA-HD
SYMBOL
MINIMUM
NOMINAL
32
MAXIMUM
N
A
--
--
1.20
0.15
1.05
0.40
0.20
A1
A2
b
0.05
0.95
0.30
0.09
0.10
1.0
0.35
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
4.00 BASIC
9.00 BASIC
7.00 BASIC
5.60 Ref.
4.00 BASIC
0.80 BASIC
0.60
D1
D2
D3
E
E1
E2
E3
e
L
0.45
0.75
q
--
0
°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
www.icst.com/products/hiperclocks.html
853111BY-02
REV. A FEBRUARY 27, 2003
9
PRELIMINARY
ICS853111-02
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS853111BY-02
ICS853111BY-02T
Marking
Package
32 lead TQFP
Count
250 per tray
1000
Temperature
-40°C to 85°C
-40°C to 85°C
ICS853111B02
ICS853111B02
32 lead TQFP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
853111BY-02
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REV. A FEBRUARY 27, 2003
10
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IDT
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IDT
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