ICS853111Y_技术文档

PRELIMINARY

ICS853111

Integrated

Circuit

Systems, Incꢀ

LOW SKEW, 1-TO-10

DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER

GENERAL DESCRIPTION

FEATURES

The ICS853111 is a low skew, high perfor- • 10 differential 2.5V/3.3V LVPECL / ECLoutputs

mance 1-to-10 Differential-to-2.5V/3.3V LVPECL/

ECL Fanout Buffer and a member of the

• 2 selectable differential input pairs

HiPerClockS™

HiPerClockS™ family of High Performance

Clock Solutions from ICS. The ICS853111

• PCLKx, nPCLKx pairs can accept the following differential

input levels: LVPECL, LVDS, CML, SSTL

is characterized to operate from either a 2.5V or a 3.3V

power supply. Guaranteed output and part-to-part skew

characteristics make the ICS853111 ideal for those clock

distribution applications demanding well defined perfor-

mance and repeatability.

• Maximum output frequency: >3GHz

• Translates any single ended input signal to 3.3V

LVPECLlevels with resistor bias on nPCLK input

• Output skew: 20ps (typical)

• Part-to-part skew: 85ps (typical)

• Propagation delay: TBD

• LVPECL mode operating voltage supply range:

V_CC= 2.375V to 3.8V, V_EE= 0V

• ECL mode operating voltage supply range:

V_CC= 0V, V_EE= -2.375V to -3.8V

• -40°C to 85°C ambient operating temperature

• Pin compatible with MC100EP111 and MC100LVEP111

BLOCK DIAGRAM

PIN ASSIGNMENT

Q0

nQ0

PCLK0

nPCLK0

0

1

PCLK1

nPCLK1

Q1

nQ1

24 23 22 21 20 19 18 17

VCCO

nQ2

Q2

25

26

27

28

29

30

31

32

16

15

14

13

12

11

10

9

VCCO

Q7

Q2

nQ2

nQ7

Q8

CLK_SEL

V_BB

Q3

nQ3

nQ1

Q1

ICS853111

nQ8

Q9

Q4

nQ4

nQ0

Q0

nQ9

Q5

nQ5

V^CCO

1

2

3

4

5

6

7

8

Q6

nQ6

Q7

nQ7

32-Lead LQFP

7mm x 7mm x 1.4mm package body

Q8

nQ8

Y Package

Top View

Q9

nQ9

The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial

product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.

853111AY

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REV. A NOVEMBER 14, 2002

1

PRELIMINARY

ICS853111

Integrated

Circuit

Systems, Incꢀ

LOW SKEW, 1-TO-10

DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER

TABLE 1. PIN DESCRIPTIONS

Number

Name

Type

Description

1

V_CC

Power

Core supply pin.

Clock select input. When HIGH, selects PCLK1, nPCLK1 inputs. When

LOW, selects PCLK0, nPCLK0 inputs. LVCMOS / LVTTL interface levels.

2

CLK_SEL

Input Pulldown

3

4

PCLK0

nPCLK0

V_BB

Input Pulldown Non-inverting differential clock input.

Input

Clock input. V_CC/2 default when left floating.

Bias voltage.

5

Output

6

PCLK1

nPCLK1

V_EE

Input Pulldown Non-inverting differential clock input.

7

Input

Power

Clock input. V_CC/2 default when left floating.

Negative supply pin.

8

9, 16, 25, 32

10, 11

12, 13

14, 15

17, 18

19, 20

21, 22

23, 24

26, 27

28, 29

30, 31

V_CCO

Output supply pins.

nQ9, Q9 Output

nQ8, Q8 Output

nQ7, Q7 Output

nQ6, Q6 Output

nQ5, Q5 Output

nQ4, Q4 Output

nQ3, Q3 Output

nQ2, Q2 Output

nQ1, Q1 Output

nQ0, Q0 Output

Differential output pair. LVPECL interface levels.

NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.

TABLE 2. PIN CHARACTERISTICS

Symbol

C_IN

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

pF

Input Capacitance

Input Pullup Resistor

4

R_PULLUP

37.5

75

KΩ

R_PULLDOWNInput Pulldown Resistor

KΩ

TABLE 3A. CONTROL INPUT FUNCTION TABLE

Inputs

CLK_SEL

Selected Source

0

1

CLK0, nCLK0

CLK1, nCLK1

TABLE 3B. CLOCK INPUT FUNCTION TABLE

Inputs

Outputs

Input to Output Mode

Polarity

CLK0 or CLK1

nCLK0 or nCLK1

Q0:Q9

nQ0:Q9

HIGH

LOW

0

1

LOW

HIGH

LOW

HIGH

LOW

Differential to Differential

Single Ended to Differential

Non Inverting

Inverting

1

0

Biased; NOTE 1

HIGH

LOW

1

Biased; NOTE 1

0

1

LOW

HIGH

Inverting

NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to Accept Single Ended Levels".

853111AY

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REV. A NOVEMBER 14, 2002

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PRELIMINARY

ICS853111

Integrated

Circuit

Systems, Incꢀ

LOW SKEW, 1-TO-10

DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER

ABSOLUTE MAXIMUM RATINGS

Supply Voltage, V_CC

Negative Supply Voltage, V_EE

Inputs, V_I

NOTE: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent damage

to the device. These ratings are stress specifi-

cations only. Functional operation of product at

these conditions or any conditions beyond those

listed in the DC Characteristics or AC Character-

istics is not implied. Exposure to absolute maxi-

mum rating conditions for extended periods may

affect product reliability.

4.6V

-4.6V

-0.5V to V_CC+ 0.5 V

0.5V to V_EE- 0.5V

± 0.5mA

Outputs, V_O

V_BBSink/Source, I_BB

Operating Temperature Range, TA -40°C to +85°C

Storage Temperature, T_STG-65°C to 150°C

Package Thermal Impedance, θ_JA47.9°C/W (0 lfpm)

(Junction-to-Ambient)

Package Thermal Impedance, θ_JC12°C/W to 17°C/W

(Junction-to-Case)

Wave Solder, T_SOL

265°C

TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V_CC= 2.375 TO 3.8V; V_EE= 0V

Symbol

V_CC

Parameter

Test Conditions

Minimum

Typical

3.3

Maximum Units

Positive Supply Voltage

Power Supply Current

2.375

3.8

V

I_EE

TBD

mA

TABLE 4B. LVPECL DC CHARACTERISTICS, V_CC= 3.3V; V_EE= 0V

-40°C

25°C

Typ

85°C

Symbol Parameter

Units

Min Typ Max Min

Max Min Typ Max

V_OH

V_OL

V_SWING

V_IH

Output High Voltage; NOTE 1

2280

1480

800

mV

Output Low Voltage; NOTE 1

Peak-to-Peak Output Voltage Swing

Input High Voltage(Single-Ended)

Input Low Voltage(Single-Ended)

Output Voltage Reference; NOTE 2

Peak-to-Peak Input Voltage

TBD

V_IL

V_BB

V_PP

150

1.2

TBD

3.3

Input High Voltage

Common Mode Range; NOTE 3, 4

V_CMR

I_IH

V

PCLK0, PCLK1

Input High Current

150

µA

nPCLK0, nPCLK1

PCLK0, PCLK1

Input Low Current

-10

-150

I_IL

µA

nPCLK0, nPCLK1

Input and output parameters vary 1:1 with V_CC. V_EEcan vary +0.925V to -0.5V.

NOTE 1: Outputs terminated with 50Ω to V_CCO- 2V.

NOTE 2: Single-ended input operation is limited V_CC≥ 3V in LVPECL mode.

NOTE 3: Common mode voltage is defined as V_IH.

NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1

is V_CC+ 0.3V.

853111AY

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REV. A NOVEMBER 14, 2002

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PRELIMINARY

ICS853111

Integrated

Circuit

Systems, Incꢀ

LOW SKEW, 1-TO-10

DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER

TABLE 4C. LVPECL DC CHARACTERISTICS, V_CC= 2.5V; V_EE= 0V

-40°C

25°C

Typ

85°C

Symbol Parameter

Units

Min Typ Max Min

Max

Min Typ Max

V_OH

Output High Voltage; NOTE 1

1480

680

mV

V_OL

Output Low Voltage; NOTE 1

V_SWING

Peak-to-Peak Output Voltage Swing

800

Input High Voltage(Single-Ended);

NOTE 2

Input Low Voltage(Single-Ended);

NOTE 2

V_IH

V_IL

TBD

mV

TBD

V_BB

V_PP

Output Voltage Reference; NOTE 3

Peak-to-Peak Input Voltage

mV

150

1.2

TBD

2.5

Input High Voltage

Common Mode Range; NOTE 4, 5

V_CMR

I_IH

V

PCLK0, PCLK1

Input High Current

150

µA

nPCLK0, nPCLK1

PCLK0, PCLK1

Input Low Current

-10

-150

I_IL

µA

nPCLK0, nPCLK1

Input and output parameters vary 1:1 with V_CC. V_EEcan vary +0.125V to -1.3V.

NOTE 1: Outputs terminated with 50Ω to V_CCO- 2V.

NOTE 2: Do not use V_BBat V_CC< 3V.

NOTE 3: Single-ended input operation is limited V_CC≥ 3V in LVPECL mode.

NOTE 4: Common mode voltage is defined as V_IH.

NOTE 5: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1

is V_CC+ 0.3V.

TABLE 4C. ECL DC CHARACTERISTICS, V_CC= 0V; V_EE= -2.375V TO -3.8V

-40°C

25°C

Typ

85°C

Symbol Parameter

Units

Min Typ Max

Min

Max Min Typ Max

V_OH

V_OL

V_SWING

V_IH

Output High Voltage; NOTE 1

-1020

-1820

800

mV

Output Low Voltage; NOTE 1

Peak-to-Peak Output Voltage Swing

Input High Voltage(Single-Ended)

Input Low Voltage(Single-Ended)

Output Voltage Reference; NOTE 2

Peak-to-Peak Input Voltage

TBD

V_IL

V_BB

V_PP

150

TBD

150

Input High Voltage

Common Mode Range; NOTE 3, 4

PCLK0, PCLK1

V_CMR

V_EE+ 1.2

V

I_IH

Input High Current

nPCLK0,

µA

nPCLK1

PCLK0, PCLK1

nPCLK0,

nPCLK1

-10

-150

I_IL

Input Low Current

µA

Input and output parameters vary 1:1 with V_CC

.

NOTE 1: Outputs terminated with 50Ω to V_CCO- 2V.

NOTE 2: Single-ended input operation is limited V_EE≤ -3V in ECL mode.

NOTE 3: Common mode voltage is defined as V_IH.

NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1

is V_CC+ 0.3V.

853111AY

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REV. A NOVEMBER 14, 2002

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PRELIMINARY

ICS853111

Integrated

Circuit

Systems, Incꢀ

LOW SKEW, 1-TO-10

DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER

TABLE 5. AC CHARACTERISTICS, V_CC= 0V; V_EE= -2.375V TO -3.8V OR V_CC= 2.375 TO 3.8V; V_EE= 0V

-40°C 25°C

Min Typ Max Min Typ

85°C

Max Min Typ

Symbol Parameter

Units

Max

f_MAX

Output Frequency

>3

TBD

20

GHz

ps

t_PD

Propagation Delay; NOTE 1

Output Skew; NOTE 2, 4

tsk(o)

tsk(pp)

t_R/t_F

ps

Part-to-Part Skew; NOTE 3, 4

85

ps

Output Rise/Fall Time

20% to 80%

TBD

ps

NOTE 1: Measured from the differential input crossing point to the differential output crossing point.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.

Measured at the output differential cross points.

NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages

and with equal load conditions. Using the same type of inputs on each device, the outputs are measured

at the differential cross points.

NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

853111AY

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REV. A NOVEMBER 14, 2002

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PRELIMINARY

ICS853111

Integrated

Circuit

Systems, Incꢀ

LOW SKEW, 1-TO-10

DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER

PARAMETER MEASUREMENT INFORMATION

V_CC, V_CCO= 2V

V_CC

SCOPE

Qx

nCLK0, nCLK1

V_PP

LVPECL

V_CMR

Cross Points

CLK0, CLK1

nQx

V_EE

V_EE= -0.375V to -1.8V

3.3V OUTPUT LOAD AC TEST CIRCUIT

DIFFERENTIAL INPUT LEVEL

nQx

PART 1

Qx

nQx

Qx

nQy

PART 2

Qy

tsk(pp)

tsk(o)

PART-TO-PART SKEW

OUTPUT SKEW

nCLK0,

nCLK1

80%

CLK0,

CLK1

V_SWING

20%

nQ0:nQ9

Clock Outputs

t

F

R

Q0:Q9

t_PD

OUTPUT RISE/FALL TIME

PROPAGATION DELAY

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REV. A NOVEMBER 14, 2002

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PRELIMINARY

ICS853111

Integrated

Circuit

Systems, Incꢀ

LOW SKEW, 1-TO-10

DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER

APPLICATION INFORMATION

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

Figure 2 shows an example of the differential input that can

be wired to accept single ended levels. The reference voltage

level V_BBgenerated from the device is connected to the

negative input. The C1 capacitor should be located as close

as possible to the input pin.

VDD(or VCC)

CLK_IN

+

VBB

-

C1

0.1uF

FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

TERMINATION FOR LVPECL OUTPUTS

The clock layout topology shown below is a typical termina-

50Ω transmission lines. Matched impedance techniques should

tion for LVPECL outputs. The two different layouts mentioned be used to maximize operating frequency and minimize signal

are recommended only as guidelines.

distortion. Figures 3A and 3B show two different layouts which

are recommended only as guidelines. Other suitable clock lay-

outs may exist and it would be recommended that the board

designers simulate to guarantee compatibility across all printed

circuit and clock component process variations.

FOUT and nFOUT are low impedance follower outputs that gen-

erate ECL/LVPECLcompatible outputs. Therefore, terminating

resistors (DC current path to ground) or current sources must

be used for functionality. These outputs are designed to drive

3.3V

Z_o= 50Ω

5

2

5

Z_o

2

F_IN

F_OUT

Z_o= 50Ω

F_OUT

F_IN

50Ω

➤

V

_CC- 2V

Z_o= 50Ω

RTT

1

3

2

3

2

Z_o

RTT =

Z_o

(V_OH+ V_OL/ V_CC–2) –2

FIGURE 3A. LVPECL OUTPUT TERMINATION

FIGURE 3B. LVPECL OUTPUT TERMINATION

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REV. A NOVEMBER 14, 2002

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PRELIMINARY

ICS853111

Integrated

Circuit

Systems, Incꢀ

LOW SKEW, 1-TO-10

DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER

POWER CONSIDERATIONS

This section provides information on power dissipation and junction temperature for the ICS853111.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the ICS853111 is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for V_CC= 3.8V, which gives worst case results.

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

•

Power (core)_MAX= V_{CC_MAX}* I_{EE_MAX}= 3.8V * TBDmA = TBDmW

Power (outputs)_MAX= 30.2mW/Loaded Output pair

If all outputs are loaded, the total power is 10 * 30.2mW = 302mW

Total Power_{_MAX}(3.8V, with all outputs switching) = TBDmW + 302mW = TBDmW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the

device. The maximum recommended junction temperature for HiPerClockS^TMdevices is 125°C.

The equation for Tj is as follows: Tj = θ_JA* Pd_total + T_A

Tj = Junction Temperature

θ_JA= Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

T_A=Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ_JAmust be used. Assuming a

moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 6 below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.TBDW * 42.1°C/W = TBD°C. This is well below the limit of 125°C

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,

and the type of board (single layer or multi-layer).

TABLE 6. THERMAL RESISTANCE q_JAFOR 32-PIN LQFP, FORCED CONVECTION

q by Velocity (Linear Feet per Minute)

JA

0

200

500

Single-Layer PCB, JEDEC Standard Test Boards

Multi-Layer PCB, JEDEC Standard Test Boards

67.8°C/W

55.9°C/W

50.1°C/W

47.9°C/W

42.1°C/W

39.4°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

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REV. A NOVEMBER 14, 2002

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PRELIMINARY

ICS853111

Integrated

Circuit

Systems, Incꢀ

LOW SKEW, 1-TO-10

DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER

3. Calculations and Equations.

LVPECL output driver circuit and termination are shown in Figure 4.

VCCO

Q1

VOUT

RL

50

VCCO - 2V

Figure 4. LVPECL Driver Circuit and Termination

To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination

voltage of V - 2V.

CCO

•

For logic high, V = V

= V

– 1.0V

OUT

OH_MAX

CCO_MAX

)

= 1.0V

OH_MAX

(V

- V

CC_MAX

For logic low, V = V

= V

– 1.7V

OUT

OL_MAX

CCO_MAX

)

= 1.7V

OL_MAX

(V

- V

CCO_MAX

))

/R ] * (V

Pd_H = [(V

– (V

- 2V))/R ] * (V

- V

) = [(2V - (V

- V

) =

OH_MAX

CCO_MAX

OH_MAX

_MAX

OH_MAX

CCO _MAX

OH_MAX

L

CCO

L

[(2V - 1V)/50Ω] * 1V = 20.0mW

))

/R ] * (V

Pd_L = [(V

– (V

- 2V))/R ] * (V

- V

) =

OL_MAX

CCO_MAX

OL_MAX

_MAX

OL_MAX

CCO_MAX

OL_MAX

L

CCO

L

[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW

Total Power Dissipation per output pair = Pd_H + Pd_L= 30.2mW

853111AY

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REV. A NOVEMBER 14, 2002

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PRELIMINARY

ICS853111

Integrated

Circuit

Systems, Incꢀ

LOW SKEW, 1-TO-10

DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER

RELIABILITY INFORMATION

TABLE 7. θ_JA^VS. AIR FLOW TABLE

q by Velocity (Linear Feet per Minute)

JA

0

200

500

Single-Layer PCB, JEDEC Standard Test Boards

Multi-Layer PCB, JEDEC Standard Test Boards

67.8°C/W

55.9°C/W

50.1°C/W

47.9°C/W

42.1°C/W

39.4°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

TRANSISTOR COUNT

The transistor count for ICS853111 is: 1340

853111AY

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REV. A NOVEMBER 14, 2002

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PRELIMINARY

ICS853111

Integrated

Circuit

Systems, Incꢀ

LOW SKEW, 1-TO-10

DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER

PACKAGE OUTLINE - Y SUFFIX

TABLE 8. PACKAGE DIMENSIONS

JEDEC VARIATION

ALL DIMENSIONS IN MILLIMETERS

BBA

SYMBOL

MINIMUM

NOMINAL

MAXIMUM

N

A

32

--

1.60

0.15

1.45

0.45

0.20

A1

A2

b

0.05

1.35

0.30

0.09

1.40

0.37

c

--

D

9.00 BASIC

7.00 BASIC

5.60 Ref.

9.00 BASIC

7.00 BASIC

5.60 Ref.

0.80 BASIC

0.60

D1

D2

E

E1

E2

e

L

0.45

0.75

q

--

0

°

7°

ccc

--

0.10

Reference Document: JEDEC Publication 95, MS-026

853111AY

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REV. A NOVEMBER 14, 2002

11

PRELIMINARY

ICS853111

Integrated

Circuit

Systems, Incꢀ

LOW SKEW, 1-TO-10

DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER

TABLE 9. ORDERING INFORMATION

Part/Order Number

Marking

Package

32 lead LQFP

Count

250 per tray

1000

Temperature

-40°C to 85°C

ICS853111Y

ICS853111AY

ICS853111AYT

32 lead LQFP on Tape and Reel

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use

or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use

in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not

recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product

for use in life support devices or critical medical instruments.

853111AY

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REV. A NOVEMBER 14, 2002

12


型号：	ICS853111Y
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Low Skew Clock Driver, 10 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, LQFP-32 驱动逻辑集成电路
文件：	总12页 (文件大小：161K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ICS853111Y [IDT]

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