ICS840002AG-01LFT [IDT]
Clock Generator, 175MHz, PDSO16, 4.40 X 5 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-16;
| 型号： | ICS840002AG-01LFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 175MHz, PDSO16, 4.40 X 5 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-16 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总13页 (文件大小：446K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
ICS840002-01
FemtoClock , Crystal-to-LVCMOS/LVTTL
Frequency Synthesizer
DATA SHEET
General Description
Features
The ICS840002-01 is a two output LVCMOS/LVTTL Synthesizer
optimized to generate Ethernet reference clock frequencies. Using a
25MHz 18pF parallel resonant crystal, the following frequencies can
be generated based on the two frequency select pins (F_SEL[1:0]):
156.25MHz, 125MHz, and 62.5MHz. The ICS840002-01 uses IDT’s
3RD generation low phase noise VCO technology and can achieve
1ps or lower typical random rms phase jitter, easily meeting Ethernet
jitter requirements. The ICS840002-01 is packaged in a small 16-pin
TSSOP package.
• Two LVCMOS/LVTTL outputs@ 3.3V,
17 typical output impedance
• Selectable crystal oscillator interface or LVCMOS/LVTTL
single-ended TEST_CLK
• Output frequency range: 56MHz to 175MHz
• VCO range: 560MHz to 700MHz
• Output skew: 12ps (maximum)
• RMS phase jitter at 156.25MHz, (1.875MHz to 20MHz):
0.47ps (typical)
Phase Noise:
Offset
Noise Power
100Hz.................-97.4 dBc/Hz
1kHz...................-120.2 dBc/Hz
10kHz.................-127.6 dBc/Hz
100kHz...............-126.1 dBc/Hz
• Full 3.3V or mixed 3.3V core/2.5V output supply modes
• -30°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Frequency Select Function Table
Inputs
F_SEL1
F_SEL0
M Divider Value
N Divider Value
Output Frequency (25MHz Ref.)
0
0
1
1
0
1
0
1
25
25
25
25
4
5
156.25
125
10
5
62.5
125
Pin Assignment
Block Diagram
F_SEL1
GND
GND
Q0
F_SEL0
nXTAL_SEL
TEST_CLK
OE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
Pullup
OE
2
Pullup:Pullup
F_SEL1:0
MR
Q1
Pulldown
nPLL_SEL
nPLL_SEL
VDDA
VDDO
10 XTAL_IN
XTAL_OUT
Pulldown
nXTAL_SEL
9
VDD
XTAL_IN
ICS840002-01
F_SEL1:0
N
0
Q0
Q1
OSC
1
0
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm
package body
XTAL_OUT
TEST_CLK
0 0 ÷4
0 1 ÷5
1 0 ÷10
1 1 ÷5
Phase
Detector
Pulldown
1
VCO
G Package
Top View
M = ÷25 (fixed)
Pulldown
MR
ICS840002AG-01 REVISION D SEPTEMBER 28, 2012
1
©2012 Integrated Device Technology, Inc.
ICS840002-01 Data Sheet
FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Table 1. Pin Descriptions
Number
Name
Type
Description
1
F_SEL0
Input
Input
Input
Input
Pullup
Pulldown
Pulldown
Pullup
Frequency select pin. LVCMOS/LVTTL interface levels.
Selects between crystal or TEST_CLK inputs as the PLL reference
source. When HIGH, selects TEST_CLK. When LOW, selects XTAL
inputs. LVCMOS/LVTTL interface levels.
2
3
4
nXTAL_SEL
TEST_CLK
OE
Single-ended test clock input. LVCMOS/LVTTL interface levels.
Output enable. When logic HIGH, the outputs are active.
When LOW, the outputs are in high-impedance state.
LVCMOS/LVTTL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers
are reset causing the active outputs to go low. When Logic LOW,
the internal dividers and the outputs are enabled. LVCMOS/LVTTL
5
6
MR
Input
Input
Pulldown
Pulldown
interface levels.
PLL Bypass. When LOW, the output is driven from the VCO output. When
HIGH, the PLL is bypassed and the output frequency = reference clock
frequency/N output divider. LVCMOS/LVTTL interface levels.
nPLL_SEL
7
8
VDDA
VDD
Power
Power
Analog supply pin.
Core supply pin.
9,
10
XTAL_OUT
XTAL_IN
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the
output.
Input
11
VDDO
Power
Output
Power
Input
Output supply pin.
12, 13
14, 15
16
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Power supply ground.
Q1, Q0
GND
F_SEL1
Pullup
Frequency select pin. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
4
CPD
Power Dissipation Capacitance
Input Pullup Resistor
Input Pulldown Resistor
8
pF
RPULLUP
RPULLDOWN
51
51
17
21
k
k
V
DDO = 3.3V 5ꢀ
14
16
21
25
ROUT
Output Impedance
VDDO = 2.5V 5ꢀ
ICS840002AG-01 REVISION D SEPTEMBER 28, 2012
2
©2012 Integrated Device Technology, Inc.
ICS840002-01 Data Sheet
FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
4.6V
Inputs, VI
XTAL_IN
0V to VDD
Other Inputs
-0.5V to VDD + 0.5V
Outputs, VO
-0.5V to VDDO + 0.5V
89C/W (0 lfpm)
-65C to 150C
Package Thermal Impedance, JA
Storage Temperature, TSTG
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics, VDD = VDDA = 3.3V 5ꢀ, VDDO = 3.3V 5ꢀ or 2.5V 5ꢀ, TA = -30°C to 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VDD
Core Supply Voltage
3.465
3.465
3.465
2.625
100
V
V
VDDA
Analog Supply Voltage
3.135
3.3
3.135
3.3
V
VDDO
Output Supply Voltage
2.375
2.5
V
IDD
Power Supply Current
Analog Supply Current
Output Supply Current
mA
mA
mA
IDDA
IDDO
12
5
Table 3B. LVCMOS/LVTTL DC Characteristics, VDD = VDDA = 3.3V 5ꢀ, VDDO = 3.3V 5ꢀ or 2.5V 5ꢀ, TA = -30°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VIH
VIL
Input High Voltage
Input Low Voltage
2
VDD + 0.3
V
V
-0.3
0.8
5
OE, F_SEL0, F_SEL1
V
DD = VIN = 3.465V or 2.625V
µA
Input
High Current
IIH
MR, TEST_CLK,
nXTAL_SEL, nPLL_SEL
VDD = VIN =3.465V or 2.625V
150
µA
µA
µA
VDD = 3.465V or 2.625V,
VIN = 0V
OE, F_SEL0, F_SEL1
-150
-5
Input
IIL
Low Current
MR, TEST_CLK,
VDD = 3.465V or 2.625V,
nXTAL_SEL, nPLL_SEL
VIN = 0V
VDDO = 3.3V 5ꢀ
VDDO = 2.5V 5ꢀ
2.6
1.8
V
V
V
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
VDDO = 3.3V 5ꢀ or 2.5V 5ꢀ
0.5
NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information section, Output Load Test Circuit diagrams.
ICS840002AG-01 REVISION D SEPTEMBER 28, 2012
3
©2012 Integrated Device Technology, Inc.
ICS840002-01 Data Sheet
FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Table 4. Crystal Characteristics
Parameter
Test Conditions
Minimum
Typical
Fundamental
25
Maximum
Units
Mode of Oscillation
Frequency
MHz
Equivalent Series Resistance (ESR)
Shunt Capacitance (CO)
Drive Level
50
7
pF
1
mW
NOTE: Characterized using an 18pF parallel resonant crystal.
AC Electrical Characteristics
Table 5A. AC Characteristics, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = -30°C to 85°C
Symbol Parameter
Test Conditions
F_SEL[1:0] = 00
Minimum
140
Typical
Maximum
175
Units
MHz
MHz
MHz
ps
fOUT
Output Frequency
F_SEL[1:0] = 01 or 11
F_SEL[1:0] = 10
112
140
56
70
tsk(o)
tjit(Ø)
Output Skew; NOTE 1, 2
12
156.25MHz, (1.875MHz - 20MHz)
125MHz, (1.875MHz - 20MHz)
62.5MHz, (1.875MHz - 20MHz)
20ꢀ to 80ꢀ
0.47
0.57
0.51
ps
RMS Phase Jitter, Random;
NOTE 3
ps
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
200
46
700
54
ps
ꢀ
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Refer to Phase Noise Plot.
Table 5B. AC Characteristics, VDD = VDDA = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ, TA = -30°C to 85°C
Symbol Parameter
Test Conditions
F_SEL[1:0] = 00
Minimum
140
Typical
Maximum
175
Units
MHz
MHz
MHz
ps
fOUT
Output Frequency
F_SEL[1:0] = 01 or 11
F_SEL[1:0] = 10
112
140
56
70
tsk(o)
tjit(Ø)
Output Skew; NOTE 1, 2
12
156.25MHz, (1.875MHz - 20MHz)
125MHz, (1.875MHz - 20MHz)
62.5MHz, (1.875MHz - 20MHz)
20ꢀ to 80ꢀ
0.47
0.55
0.49
ps
RMS Phase Jitter, Random;
NOTE 3
ps
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
200
46
700
54
ps
ꢀ
fOUT = 125MHz
47
53
ꢀ
For NOTES, see Table 5A above.
ICS840002AG-01 REVISION D SEPTEMBER 28, 2012
4
©2012 Integrated Device Technology, Inc.
ICS840002-01 Data Sheet
FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Typical Phase Noise at 62.5MHz (3.3V)
1Gb Ethernet Filter
62.5MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.51ps (typical)
Raw Phase Noise Data
Phase Noise Result by adding a
1Gb Ethernet filter to raw data
Offset Frequency (Hz)
Typical Phase Noise at 156.25MHz (3.3V)
10Gb Ethernet Filter
156.25MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.47ps (typical)
Raw Phase Noise Data
Phase Noise Result by adding a
10Gb Ethernet filter to raw data
Offset Frequency (Hz)
ICS840002AG-01 REVISION D SEPTEMBER 28, 2012
5
©2012 Integrated Device Technology, Inc.
ICS840002-01 Data Sheet
FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Parameter Measurement Information
2.05V 5ꢀ
1.25V 5ꢀ
1.65V 5ꢀ
SCOPE
SCOPE
V
V
V
DD,
V
DD,
DDA,
V
DDA
V
Qx
DDO
DDO
Qx
LVCMOS
GND
GND
VDDO
2
-1.65V 5ꢀ
-1.25V 5ꢀ
3.3V Core/3.3V Output Load AC Test Circuit
3.3V Core/2.5V Output Load AC Test Circuit
Phase Noise Plot
VDDO
Qx
Qy
2
Phase Noise Mask
VDDO
2
tsk(o)
Offset Frequency
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS Phase Jitter
Output Skew
VDDO
2
Q[0:1]
80ꢀ
tF
80ꢀ
tR
tPW
tPERIOD
20ꢀ
20ꢀ
Q[0:1]
tPW
x 100ꢀ
odc =
tPERIOD
Output Skew
Output Duty Cycle/Pulse Width/Period
ICS840002AG-01 REVISION D SEPTEMBER 28, 2012
6
©2012 Integrated Device Technology, Inc.
ICS840002-01 Data Sheet
FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Applications Information
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
Crystal Inputs
LVCMOS Outputs
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1k resistor can be tied from
XTAL_IN to ground.
All unused LVCMOS outputs can be left floating. We recommend that
there is no trace attached.
TEST_CLK Input
For applications not requiring the use of the test clock, it can be left
floating. Though not required, but for additional protection, a 1k
resistor can be tied from the TEST_CLK to ground.
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
ICS840002AG-01 REVISION D SEPTEMBER 28, 2012
7
©2012 Integrated Device Technology, Inc.
ICS840002-01 Data Sheet
FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Overdriving the XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 1A. The XTAL_OUT pin can be left floating. The
maximum amplitude of the input signal should not exceed 2V and the
input edge rate can be as slow as 10ns. This configuration requires
that the output impedance of the driver (Ro) plus the series
resistance (Rs) equals the transmission line impedance. In addition,
matched termination at the crystal input will attenuate the signal in
half. This can be done in one of two ways. First, R1 and R2 in parallel
should equal the transmission line impedance. For most 50
applications, R1 and R2 can be 100. This can also be
accomplished by removing R1 and making R2 50. By overdriving
the crystal oscillator, the device will be functional, but note, the device
performance is guaranteed by using a quartz crystal.
VCC
XTAL_OUT
R1
100
C1
Rs
Zo = 50 ohms
Ro
XTAL_IN
.1uf
R2
100
Zo = Ro + Rs
LVCMOS Driver
Figure 1A. General Diagram for LVCMOS Driver to XTAL Input Interface
XTAL_OUT
C2
Zo = 50 ohms
XTAL_I N
.1uf
Zo = 50 ohms
R1
50
R2
50
LVPECL Driver
R3
50
Figure 1B. General Diagram for LVPECL Driver to XTAL Input Interface
ICS840002AG-01 REVISION D SEPTEMBER 28, 2012
8
©2012 Integrated Device Technology, Inc.
ICS840002-01 Data Sheet
FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Layout Guideline
Figure 2 shows a schematic example of the ICS840002-01
application schematic. In this example, the device is operated at VDD
= VDDA = VDDO = 3.3V. The 18pF parallel resonant 25MHz crystal is
used. The load capacitance C1 = 22pF and C2 = 22pF are
recommended for frequency accuracy. Depending on the parasitic of
the printed circuit board layout, these values might require a slight
adjustment to optimize the frequency accuracy. Crystals with other
load capacitance specifications can be used. This will required
adjusting C1 and C2.
0.1uF capacitor in each power pin filter should be placed on the
device side of the PCB and the other components can be placed on
the opposite side.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supply frequencies, it is recommended that component values
be adjusted and if required, additional filtering be added. Additionally,
good general design practices for power plane voltage stability
suggests adding bulk capacitances in the local area of all devices.
As with any high speed analog circuitry, the power supply pins are
vulnerable to noise. To achieve optimum jitter performance, power
supply isolation is required. The ICS840002-01 provides separate
power supplies to isolate from coupling into the internal PLL.
The schematic example focuses on functional connections and is not
configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure the logic control inputs are properly
set.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
Logic Control Input Examples
3.3V
Set Logic
Input to
'1'
Set Logic
Input to
'0'
BLM18BB221SN1
VDD
VDD
VDD
1
2
R1
33
Zo = 50 Ohm
RU1
1K
RU2
Not Install
C6
Ferrite Bead
C7
10uF
0.1uF
To Logic
Input
pins
To Logic
Input
pins
U1
LVCMOS
RD1
Not Install
RD2
1K
1
16
FSEL0
FSEL1
GND
GND
Q0
Q1
2
3
4
5
6
7
8
15
14
13
12
11
10
9
XTAL_SEL
TEST_CLK
OE
MR
nPLL_SEL
VDDA
VDDO
VDDO
VDDO
XTAL_IN
XTAL_OUT
VDD
VDDA
R3
VDD
R2
10
C3
10uF
100
C4
0.1u
C5
0.1u
Zo = 50 Ohm
R4
100
XTAL_IN
X1
If not using the crystal input, it can be left floating.
For additional protection the XTAL_IN pin can be
tied to ground.
18pF
LVCMOS
C1
22pF
25MHz
XTAL_OUT
Optional Termination
C2
22pF
Unused output can be left floating. There should
no trace attached to unused output. Device
characterized with all outputs terminated.
3.3V
BLM18BB221SN2
1
2
VDDO
Ferrite Bead
C9
C8
0.1uF
C10
0.1u
10uF
Figure 2. ICS840002-01 Application Schematic Example
ICS840002AG-01 REVISION D SEPTEMBER 28, 2012
9
©2012 Integrated Device Technology, Inc.
ICS840002-01 Data Sheet
FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Reliability Information
Table 6. JA vs. Air Flow Table for a 16 Lead TSSOP
JA by Velocity
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
137.1°C/W
89.0°C/W
118.2°C/W
81.8°C/W
106.8°C/W
78.1°C/W
Transistor Count
The transistor count for ICS840002-01 is: 3085
Package Outline and Package Dimensions
Package Outline - G Suffix for 16 Lead TSSOP
Table 7. Package Dimensions for 16 Lead TSSOP
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
A
16
1.20
0.15
1.05
0.30
0.20
5.10
A1
A2
b
0.5
0.80
0.19
0.09
4.90
c
D
E
6.40 Basic
E1
e
4.30
4.50
0.65 Basic
L
0.45
0°
0.75
8°
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
ICS840002AG-01 REVISION D SEPTEMBER 28, 2012
10
©2012 Integrated Device Technology, Inc.
ICS840002-01 Data Sheet
FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Ordering Information
Table 8. Ordering Information
Part/Order Number
840002AG-01
840002AG-01T
840002AG-01LF
840002AG-01LFT
Marking
Package
16 Lead TSSOP
16 Lead TSSOP
Shipping Packaging
Tube
Temperature
-30C to 85C
-30C to 85C
-30C to 85C
-30C to 85C
40002A01
40002A01
0002A01L
0002A01L
Tape & Reel
Tube
Tape & Reel
“Lead-Free”, 16 Lead TSSOP
“Lead-Free”, 16 Lead TSSOP
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
ICS840002AG-01 REVISION D SEPTEMBER 28, 2012
11
©2012 Integrated Device Technology, Inc.
ICS840002-01 Data Sheet
FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Revision History Sheet
Rev
Table
Page
Description of Change
Date
1
Features Section - corrected the integration range from 1.875MHz - 175MHz to 1.875MHz -
20MHz in the RMS phase jitter bullet.
T4
T8
4
8
Crystal Characteristics Table - added Drive Level.
B
1/13/06
Added Recommendations for Unused Input and Output Pins.
Ordering Information Table - corrected standard marking and
added Lead-Free part number, marking and note.
11
T5A
T5B
4
4
3.3V AC Characteristics Table - added thermal note.
3.3V/2.5V AC Characteristics Table -corrected FOUT from 56MHz min - 68MHz max to
56MHz min - 70MHz max.
7
7
8
Deleted Power Supply Filtering Techniques section, added to schematic layout.
Deleted Crystal Input Interface section.
C
D
2/3/11
T6
T8
Added Overdriving the XTAL Interface section.
9
11
Updated Layout Guideline and diagram.
Ordering Information Table - deleted “ICS” prefix in Part/Order Number column.
Converted datasheet format.
T5B
T8
4
AC Characteristics Table - updated odc to include spec at 125MHz.
2/29/12
9/28/12
11
Ordering Information Table - corrected Package column to replace LQFP with TSSOP.
D
D
5A, 5B
8
4
AC Table; fOUT = F_SEL[1:0] = 01 or 11, F_SEL[1:0] = 10
Deleted Quantity from Tape and Reel
11
ICS840002AG-01 REVISION D SEPTEMBER 28, 2012
12
©2012 Integrated Device Technology, Inc.
ICS840002-01 Data Sheet
FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
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including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
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