ICS840002AGI-01 [ICSI]
FEMTOCLOCKS⑩ CRYSTAL-TO LVCMOS/LVTTL FREQUENCY SYNTHESIZER; FEMTOCLOCKS⑩ CRYSTAL -TO LVCMOS / LVTTL频率合成器型号: | ICS840002AGI-01 |
厂家: | INTEGRATED CIRCUIT SOLUTION INC |
描述: | FEMTOCLOCKS⑩ CRYSTAL-TO LVCMOS/LVTTL FREQUENCY SYNTHESIZER |
文件: | 总12页 (文件大小:207K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ICS840002I-01
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
• Two LVCMOS/LVTTL outputs @ 3.3V,
The ICS840002I-01 is a 2 output LVCMOS/LVTTL
17Ω typical output impedance
• Selectable crystal oscillator interface
or LVCMOS single-ended input
ICS
Synthesizer optimized to generate Ethernet
reference clock frequencies and is a member of
the HiPerClocksTM family of high performance
clock solutions from ICS. Using a 25MHz 18pF
HiPerClockS™
• Supports the following output frequencies:
156.25MHz, 125MHz and 62.5MHz
parallel resonant crystal, the following frequencies can be
generated based on the 2 frequency select pins (F_SEL1:0):
156.25MHz, 125MHz, and 62.5MHz.The ICS840002I-01 uses
ICS’ 3rd generation low phase noise VCO technology and can
achieve 1ps or lower typical random rms phase jitter, easily
meeting Ethernet jitter requirements. The ICS840002I-01 is
packaged in a small 16-pin TSSOP package.
• Output frequency range: 56MHz - 175MHz
• VCO range: 560MHz - 700MHz
• Output skew: 12ps (maximum)
• RMS phase jitter at 156.25MHz (1.875MHz - 20MHz):
0.47ps (typical)
Phase noise:
Offset
Noise Power
100Hz ............... -97.4 dBc/Hz
1KHz ..............-120.2 dBc/Hz
10KHz ..............-127.6 dBc/Hz
100KHz ..............-126.1 dBc/Hz
• Power supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• -40°C to 85°C ambient operating temperature
• Lead-Free package RoHS compliant
FREQUENCY SELECT FUNCTION TABLE
Inputs
Output Frequency
(25MHz Ref.)
F_SEL1 F_SEL0 M Divider Value N Divider Value
0
0
1
1
0
1
0
1
25
25
25
25
4
5
156.25
125
10
5
62.5
125
BLOCK DIAGRAM
PIN ASSIGNMENT
Pullup
OE
1
2
3
4
5
6
7
8
F_SEL0
nXTAL_SEL
TEST_CLK
OE
MR
nPLL_SEL
VDDA
16
15
14
13
12
11
10
9
F_SEL1
GND
GND
Q0
Q1
VDDO
XTAL_IN
XTAL_OUT
2
Pullup:Pullup
F_SEL1:0
Pulldown
nPLL_SEL
Pulldown
nXTAL_SEL
25MHz
XTAL_IN
VDD
F_SEL1:0
N
0
Q0
Q1
OSC
1
0
ICS840002I-01
16-LeadTSSOP
4.4mm x 5.0mm x 0.92mm
package body
0 0 ÷4
XTAL_OUT
0 1 ÷5
1 0 ÷10
1 1 ÷5
Phase
Detector
Pulldown
1
TEST_CLK
VCO
G Package
Top View
M = ÷25 (fixed)
Pulldown
MR
840002AGI-01
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ICS840002I-01
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
F_SEL0,
F_SEL1
1, 16
Input
Input
Pullup
Frequency select pin. LVCMOS/LVTTL interface levels.
Selects between the crystal or TEST_CLK inputs as the PLL reference
2
nXTAL_SEL
Pulldown source. When HIGH, selects TEST_CLK. When LOW, selects XTAL
inpus. LVCMOS/LVTTL interface levels.
3
4
TEST_CLK
OE
Input
Input
Pulldown Single-ended LVCMOS/LVTTL clock input.
Output enable pin. When HIGH, the outputs are active. When LOW, the
Pullup
outputs are in a high impedance state. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
Pulldown reset causing active outputs to go low. When logic LOW, the internal
dividers and the outputs are enabled. LVCMOS/LVTTL interface levels.
PLL Bypass. When LOW, the output is driven from the VCO output.
5
6
MR
Input
Input
When HIGH, the PLL is bypassed and the output frequency =
nPLL_SEL
Pulldown
reference clock frequency/N output divider.
LVCMOS/LVTTL interface levels.
7
8
VDDA
VDD
Power
Power
Analog supply pin.
Core supply pin.
9,
10
XTAL_OUT,
XTAL_IN
Input
Crystal oscillator interface.
11
VDDO
Q1, Q0
GND
Power
Output
Power
Output supply pin.
12, 13
14, 15
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Power supply ground.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
pF
pF
kΩ
kΩ
Ω
CPD
Power Dissipation Capacitance
Input Pullup Resistor
8
RPULLUP
51
51
17
21
RPULLDOWN Input Pulldown Resistor
3.3V 5%
2.5V 5%
14
16
21
25
ROUT
Output Impedance
Ω
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ICS840002I-01
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDD + 0.5V
89°C/W (0 lfpm)
-65°C to 150°C
I
Outputs, VO
PackageThermal Impedance, θ
JA
StorageTemperature, T
STG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V 5%, VDDO = 3.3V 5% OR 2.5V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VDD
Core Supply Voltage
3.465
3.465
3.465
2.625
100
V
V
VDDA
Analog Supply Voltage
3.135
3.3
3.135
3.3
V
VDDO
Output Supply Voltage
2.375
2.5
V
IDD
Power Supply Current
Analog Supply Current
Output Supply Current
mA
mA
mA
IDDA
IDDO
12
5
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
2.375
Typical
2.5
Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
2.625
2.625
2.625
95
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
2.375
2.5
2.375
2.5
V
mA
mA
mA
IDDA
IDDO
12
5
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ICS840002I-01
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5% OR 2.5V 5%, OR
VDD = VDDA = 3.3V 5%, VDDO = 2.5V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
VDD = 3.3V
Minimum Typical Maximum Units
2
VDD + 0.3
VDD + 0.3
0.8
V
V
V
V
VIH
VIL
Input High Voltage
VDD = 2.5V
1.7
-0.3
-0.3
V
DD = 3.3V
Input Low Voltage
VDD = 2.5V
DD = VIN = 3.465V or
2.625V
0.7
V
OE, F_SEL0, F_SEL1
5
µA
µA
µA
µA
Input
High Current
IIH
VDD = VIN = 3.465V or
nPLL_SEL, MR,
nXTAL_SEL, TEST_CLK
150
2.625V
VDD = 3.465V or 2.625V,
OE, F_SEL0, F_SEL1
-150
-5
V
IN = 0V
Input
Low Current
IIL
nPLL_SEL, MR,
nXTAL_SEL, TEST_CLK
VDD = 3.465V or 2.625V,
VIN = 0V
V
DDO = 3.3V 5%
2.6
1.8
V
V
V
VOH
VOL
Output High Voltage; NOTE 1
VDDO = 2.5V 5%
Output Low Voltage; NOTE 1
VDDO = 3.3V or 2.5V 5%
0.5
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information, Output Load Test Circuit.
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Fundamental
25
Typical Maximum Units
Mode of Oscillation
Frequency
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
50
7
pF
NOTE: Characterized using an 18pF parallel resonant crystal.
TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
F_SEL[1:0] = 00
Minimum Typical Maximum Units
140
112
56
175
140
70
MHz
MHz
MHz
ps
fOUT
Output Frequency
F_SEL[1:0] = 01
F_SEL[1:0] = 10 or 11
tsk(o)
tjit(Ø)
Output Skew; NOTE 1, 3
12
156.25MHz (1.875MHz - 20MHz)
125MHz (1.875MHz - 20MHz)
62.5MHz (1.875MHz - 20MHz)
20% to 80%
0.47
0.57
0.51
ps
RMS Phase Jitter (Random);
NOTE 2
ps
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
200
46
700
54
ps
%
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
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ICS840002I-01
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Integrated
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Systems, Inc.
TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 3.3V 5%, VDDO = 2.5V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
F_SEL[1:0] = 00
Minimum Typical Maximum Units
140
112
56
175
140
68
MHz
MHz
MHz
ps
fOUT
Output Frequency
F_SEL[1:0] = 01
F_SEL[1:0] = 10 or 11
tsk(o)
tjit(Ø)
Output Skew; NOTE 1, 3
12
156.25MHz (1.875MHz - 20MHz)
125MHz (1.875MHz - 20MHz)
62.5MHz (1.875MHz - 20MHz)
20% to 80%
0.47
0.55
0.49
ps
RMS Phase Jitter (Random);
NOTE 2
ps
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
200
46
700
54
ps
%
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5C. AC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
F_SEL[1:0] = 00
Minimum Typical Maximum Units
140
112
56
175
140
68
MHz
MHz
MHz
ps
fOUT
Output Frequency
F_SEL[1:0] = 01
F_SEL[1:0] = 10 or 11
tsk(o)
tjit(Ø)
Output Skew; NOTE 1, 3
12
156.25MHz (1.875MHz - 20MHz)
125MHz (1.875MHz - 20MHz)
62.5MHz (1.875MHz - 20MHz)
20% to 80%
0.49
0.56
0.52
ps
RMS Phase Jitter (Random);
NOTE 2
ps
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
200
46
700
54
ps
%
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
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FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Integrated
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Systems, Inc.
TYPICAL PHASE NOISE AT 62.5MHZ @3.3V
0
-10
-20
-30
-40
-50
-60
1Gb Ethernet Filter
62.5MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.51ps (typical)
-70
-80
-90
Raw Phase Noise Data
-100
-110
-120
-130
-140
-150
-160
-170
-180
Phase Noise Result by adding
1Gb Ethernet Filter to raw data
-190
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 156.25MHZ @3.3V
0
-10
-20
-30
10Gb Ethernet Filter
-40
-50
156.25MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.47ps (typical)
-60
-70
-80
-90
Raw Phase Noise Data
-100
-110
-120
-130
-140
-150
-160
-170
-180
Phase Noise Result by adding
10Gb Ethernet Filter to raw data
-190
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
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ICS840002I-01
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Integrated
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Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
2.05V 5% 1.25V 5%
1.65V 5%
SCOPE
SCOPE
VDD
VDDA
,
VDD
VDDA, VDDO
,
VDDO
Qx
Qx
LVCMOS
LVCMOS
GND
GND
-1.25V 5%
-1.65V 5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
1.25V 5%
Phase Noise Plot
SCOPE
VDD
,
VDDA, VDDO
Phase Noise Mask
Qx
LVCMOS
GND
Offset Frequency
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
-1.25V 5%
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
VDDO
80%
tF
80%
tR
Qx
2
20%
20%
Clock
Outputs
VDDO
2
Qy
tsk(o)
OUTPUT SKEW
OUTPUT RISE/FALL TIME
VDDO
2
Q0, Q1
Pulse Width
tPERIOD
tPW
odc =
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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ICS840002I-01
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise.The ICS840002I-01 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VDD, VDDA, and VDDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01μF bypass
3.3V or 2.5V
VDD
.01μF
.01μF
10Ω
VDDA
10μF
capacitor should be connected to each VDDA
.
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS840002I-01 has been characterized with 18pF paral- below were determined using a 25MHz 18pF parallel reso-
lel resonant crystals.The capacitor values shown in Figure 2 nant crystal and were chosen to minimize the ppm error.
XTAL_IN
C1
22p
X1
18pF Parallel Crystal
XTAL_OUT
C2
22p
ICS840002I-01
Figure 2. CRYSTAL INPUt INTERFACE
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ICS840002I-01
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
LAYOUT GUIDELINE
C2=22pF are recommended for frequency accuracy. For differ-
ent board layout, the C1 and C2 may be slightly adjusted for
optimizing frequency accuracy. 1KΩ pullup or pulldown resis-
tors can be used for the logic control input pins.
Figure 3 shows a schematic example of the ICS840002I-01. An
example of LVCMOS termination is shown in this schematic.
Additional LVCMOS termination approaches are shown in the
LVCMOS Termination Application Note. In this example, an 18
pF parallel resonant 25MHz crystal is used.The C1=22pF and
Logic Control Input Examples
Set Logic
Input to
'1'
Set Logic
Input to
'0'
VDD
VDD
R2
33
Zo = 50 Ohm
RU1
1K
RU2
Not Install
VDD
To Logic
Input
pins
To Logic
Input
pins
U1
LVCMOS
RD1
Not Install
RD2
1K
1
16
15
14
13
12
11
10
9
FSEL0
XTAL_SEL
TEST_CLK
OE
MR
nPLL_SEL
VDDA
FSEL1
GND
GND
Q0
Q1
VDDO
XTAL_IN
XTAL_OUT
2
3
4
5
6
7
8
VDD
VDD
VDDA
R3
VDD
R1
10
C3
10uF
100
C4
0.01u
C6
0.1u
Zo = 50 Ohm
C5
0.1u
ICS840002I-01
R4
100
XTAL2
If not using the crystal input, it can be left floating.
For additional protection the XTAL_IN pin can be
tied to ground.
LVCMOS
C2
22pF
X1
XTAL1
Optional Termination
C1
22pF
Unused output can be left floating. There should
no trace attached to unused output. Device
characterized with all outputs terminated.
FIGURE 3. ICS840002I-01 SCHEMATIC EXAMPLE
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FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP
θJA byVelocity (Linear Feet per Minute)
0
200
118.2°C/W
81.8°C/W
500
106.8°C/W
78.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
137.1°C/W
89.0°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS840002I-01 is: 3356
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FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Integrated
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PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
Millimeters
Minimum Maximum
SYMBOL
N
A
16
--
1.20
0.15
1.05
0.30
0.20
5.10
A1
A2
b
0.05
0.80
0.19
0.09
4.90
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
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LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Integrated
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Systems, Inc.
TABLE 8. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging Temperature
ICS840002AGI-01
ICS840002AGI-01T
ICS840002AGI-01LF
ICS840002AGI-01LFT
ICS840002AI01
ICS840002AI01
TBD
16 Lead TSSOP
tube
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
16 Lead TSSOP
2500 tape & reel
tube
16 Lead "Lead-Free" TSSOP
16 Lead "Lead-Free" TSSOP
TBD
2500 tape & reel
The aforementioned trademarks, HiPerClockS™ and FEMTOCLOCKS™ are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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