ICS501DLF [IDT]
Clock Generator, 160MHz, CMOS, DIE;
| 型号： | ICS501DLF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 160MHz, CMOS, DIE 时钟 外围集成电路 晶体 |
| 文件： | 总4页 (文件大小：68K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS501
LOCO™ PLL Clock Multiplier
Description
Features
• Packaged as 8 pin SOIC or die
The ICS501 LOCO™ is the most cost effective
way to generate a high quality, high frequency
clock output from a lower frequency crystal or
clock input. The name LOCO stands for LOw
Cost Oscillator, as it is designed to replace crystal
oscillators in most electronic systems. Using Phase-
Locked-Loop (PLL) techniques, the device uses a
standard fundamental mode, inexpensive crystal
to produce output clocks up to 160 MHz.
• ICS’ lowest cost PLL clock
• Zero ppm multiplication error
• Input crystal frequency of 5 - 27 MHz
• Input clock frequency of 2 - 50 MHz
• Output clock frequencies up to 160 MHz
• Extremely low jitter - 25 ps one sigma
• Compatible with all popular CPUs
• Duty cycle of 45/55 up to 160 MHz
• Mask option for 9 selectable frequencies
• Operating voltages of 3.0 to 5.5V
• Tri-state output for board level testing
• 25mA drive capability at TTL levels
• Ideal for oscillator replacement
Stored in the chip’s ROM is the ability to generate
9 different multiplication factors, allowing one
chip to output many common frequencies (see
page 2).
The device also has an Output Enable pin that tri-
states the clock output when the OE pin is taken
low.
• Industrial temperature version available
• Advanced, low power CMOS process
Block Diagram
VDD GND
S0
S1
PLL
Clock Multiplier
Circuitry
and
Crystal or
clock input
Output
Buffer
X1/ICLK
CLK
Crystal
Oscillator
ROM
X2
Output Enable
Optional crystal capacitors
MDS 501 F
1
Revision 111000
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126•(408) 295-9800tel • www.icst.com
ICS501
LOCO™ PLL Clock Multiplier
Pin Assignment
Clock Output Table
S1
0
S0
0
CLK
4X input
Minimum Input
per page 3
20MHz
1
2
3
4
8
7
6
5
X1/ICLK
VDD
GND
S1
X2
OE
S0
0
M
1
5.3125X input
5X input
0
per page 3
4MHz
M
M
M
1
0
6.25X input
2X input
M
1
per page 3
8MHz
3.125X input
6X input
CLK
0
per page 3
per page 3
per page 3
1
M
1
3X input
1
8X input
0 = connect directly to ground.
1 = connect directly to VDD.
M = leave unconnected (floating).
Common Output Frequencies Examples (MHz)
Output
20
10
24
12
30
10
32
16
33.33
16.66
M, M
37.5
12
40
10
48
12
50
60
10
62.5
20
Input
16.66
1, M
Selection (S1, S0)
M, M
M, M
1, M
M, M
M, 1
0, 0
0, 0
1, 0
M, 1
Output
64
16
66.66
16.66
0, 0
72
12
75
12
80
10
83.33
16.66
0, 1
90
15
100
20
106.25
20
120
15
125
20
Input
Selection (S1, S0)
0, 0
1, 0
M, 0
1, 1
1, 0
0, 1
0, M
1, 1
M, 0
Note that all of the above outputs are achieved by using a common, inexpensive 10MHz to 20MHz crystal.
Consult MicroClock/ICS on how to achieve other output frequencies.
Pin Descriptions
Number
Name
X1/ICLK
VDD
GND
S1
Type Description
1
2
3
4
5
6
7
8
I
P
Crystal connection or clock input.
Connect to +3.3V or +5V.
P
Connect to ground.
TI
O
TI
I
Select 1 for output clock. Connect to GND or VDD or float.
Clock output per Table above.
CLK
S0
Select 0 for output clock. Connect to GND or VDD or float.
Output Enable. Tri-states CLK output when low. Internal pull-up.
Crystal connection. Leave unconnected for clock input.
OE
X2
O
Key: I = Input, TI = Tri-Level Input, O = output, P = power supply connection
MDS 501 F
2
Revision 111000
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126•(408) 295-9800tel • www.icst.com
ICS501
LOCO™ PLL Clock Multiplier
Electrical Specifications
Parameter
Conditions
Minimum
Typical
Maximum
Units
ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)
Supply Voltage, VDD
Inputs
Referenced to GND
Referenced to GND
Referenced to GND
7
VDD+0.5
VDD+0.5
70
V
V
V
C
C
C
C
-0.5
-0.5
0
Clock Output
Ambient Operating Temperature
ICS501MI only
-40
85
Soldering Temperature
Storage temperature
Max of 10 seconds
260
-65
150
DC CHARACTERISTICS (VDD = 5.0V unless otherwise noted)
Operating Voltage, VDD
3
5.5
(VDD/2)-1
0.8
V
V
Input High Voltage, VIH, ICLK only
Input Low Voltage, VIL, ICLK only
Input High Voltage, VIH
ICLK (Pin 1)
ICLK (Pin 1)
OE (Pin 7)
OE (Pin 7)
S0, S1
(VDD/2)+1
VDD/2
VDD/2
V
2
V
Input Low Voltage, VIL
V
Input High Voltage, VIH
VDD-0.5
2.4
V
Input Low Voltage, VIL
S0, S1
0.5
V
Output High Voltage, VOH
Output Low Voltage, VOL
IOH=-25mA
IOL=25mA
V
0.4
V
IDD Operating Supply Current, 20 MHz crystal No Load, 100MHz
20
±70
270
4
mA
mA
kW
pF
Short Circuit Current
CLK output
Pin 7
On-Chip Pull-up Resistor
Input Capacitance, S1, S0 , and OE
Pins 4, 6, 7
AC CHARACTERISTICS (VDD = 5.0V unless otherwise noted)
Input Frequency, crystal input
5
27
50
MH z
MH z
MH z
MH z
MH z
MH z
ns
Input Frequency, clock input
2
Output Frequency, VDD = 4.5 to 5.5V
0 C to +70 C
14
14
14
14
160
140
100
90
-40 C to +85 C
0 C to +70 C
Output Frequency, VDD = 3.0 to 3.6V
-40 C to +85 C
0.8 to 2.0V
Output Clock Rise Time
1
1
Output Clock Fall Time
2.0 to 0.8V
ns
Output Clock Duty Cycle
1.5V, up to 160 MHz
45
10
49 to 51
55
%
PLL Bandwidth
kHz
ns
Output Enable Time, OE high to output on
Output Disable Time, OE low to tri-state
Absolute Clock Period Jitter
One Sigma Clock Period Jitter
50
50
ns
Deviation from mean
±70
25
ps
ps
MDS 501 F
3
Revision 111000
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126•(408) 295-9800tel • www.icst.com
ICS501
LOCO™ PLL Clock Multiplier
External Components / Crystal Selection
The ICS501 requires a 0.01µF decoupling capacitor to be connected between VDD and GND. It must be
connected close to the ICS501 to minimize lead inductance. No external power supply filtering is required
for this device. A 33Wterminating resistor can be used next to the CLK pin. The total on-chip capacitance
is approximately 12 pF, so a parallel resonant, fundamental mode crystal should be used. For crystals with
a specified load capacitance greater than 12 pF, crystal capacitors should be connected from each of the
pins X1 and X2 to Ground as shown in the Block Diagram on page 1. The value (in pF) of these crystal
caps should be = (C -12)*2, where C is the crystal load capacitance in pF. These external capacitors are
L
L
only required for applications where the exact frequency is critical. For a clock input, connect to X1 and
leave X2 unconnected (no capacitors on either).
Package Outline and Package Dimensions
8 pin SOIC
E
H
Inches
Millimeters
Min Max
0.055 0.068 1.397 1.7272
Pin 1
Symbol Min
Max
A
b
0.013 0.019 0.330
0.185 0.200 4.699
0.150 0.160 3.810
0.225 0.245 5.715
0.483
5.080
4.064
6.223
D
E
H
e
h x 45°
D
.050 BSC
0.015
0.01
1.27 BSC
A
Q
h
0.381
0.254
c
Q
0.004
0.102
b
e
Ordering Information
Part/Order Number
ICS501M
Marking
ICS501M
ICS501M
ICS501I
ICS501I
-
Package
8 pin SOIC
8 pin SOIC on tape and reel
8 pin SOIC
8 pin SOIC on tape and reel -40 to +85 C
Die on uncut, probed wafers
Tested die in waffle pack
Temperature
0 to 70 C
0 to 70 C
ICS501MT
ICS501MI
ICS501MIT
ICS501D
-40 to +85 C
0 to 70 C
0 to 70 C
ICS501DW
-
While the information presented herein has been checked for both accuracy and reliability, ICS/MicroClock assumes no responsibility for either its use or for the infringement of
any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS/MicroClock. ICS/MicroClock reserves the right to change any circuitry or specifications without notice. ICS/MicroClock
does not authorize or warrant any ICS/MicroClock product for use in life support devices or critical medical instruments.
LOCO is a trademark of ICS
MDS 501 F
4
Revision 111000
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126•(408) 295-9800tel • www.icst.com
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