FICS951601FLF [IDT]
Clock Generator;
| 型号： | FICS951601FLF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator |
| 文件： | 总10页 (文件大小：137K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS951601
Preliminary Product Preview
Integrated
Circuit
Systems,Inc.
General Purpose Frequency Timing Generator
RecommendedApplication:
KeySpecifications:
GeneralPurposeClockGenerator
•
PCI – PCI output skew within same bank @
33MHz:<170ps
OutputFeatures:
•
PCI – PCI output skew within same bank@ 66MHz:
<340ps
•
17 - PCI clocks selectable,
either 33.33MHz or 66.6MHz @ 3.3V
•
•
•
•
•
Cycle to Cycle Jitter PCI @ 33MHz: <200ps
Cycle to Cycle Jitter PCI @ 66MHz: <200ps
Cycle to Cycle Jitter 48MHz: <350ps
Cycle to Cycle Jitter REF: <500ps
•
•
1 - 48MHz @ 3.3V
1 - REF @ 3.3V, 14.318MHz.
Features:
Slew Rate: 1.5 - 4 V/ns. (PCI spec.)
•
Programable Spread spectrum precentage for EMI
control
•
•
Uses external 14.318MHz crystal
Select pins for frequency select
Pin Configuration
Block Diagram
REF0
VDD
X1
X2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
48MHz
GND
VDD48
SPREAD
VDDA
PLL2
48MHz
REF0
SDATA
SCLK
GNDA
VDDA
SEL1A
PCI1A_0
PCI1A_1
VDD33
GND
PCI1A_2
PCI1A_3
GND
VDD33
PCI1A_4
PCI1A_5
VDD33
GND
GNDA
X1
X2
XTAL
OSC
SEL2B
PCI2B_2
PCI2B_1
GND
VDD66
PCI2B_0
SEL2A
PCI2A_2
PCI2A_1
VDD2A
GND
PCI2A_0
SEL1B
PCI1B_2
PCI1B_1
GND
PLL1
Spread
Spectrum
PCI
DIVDER
PCI1A (7:0)
PCI2A (2:0)
PCI1B (2:0)
PCI2B (2:0)
8
3
3
3
PCI
DIVDER
Control
Logic
SDATA
SCLK
PCI
DIVDER
SELA (2:1)
SELB (2:1)
PCI1A_6
PCI1A_7
VDD1B
PCI1B_0
Config.
Reg.
PCI
DIVDER
SPREAD
48-pin SSOP
*120Kohmpull-uptoVDDonindicatedinputs.
Power Groups:
VDDA = Analog Power
GNDA = Analog Ground
0663C—10/04/05
PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to
changewithoutnotice.
ICS951601
Preliminary Product Preview
Pin Descriptions
Pin number
Pin name
Type
Description
1
REF0
VDD
OUT
Reference output
3.3V Power supply
2, 13, 18, 21, 26,
PWR
33, 38, 46
3
4
X1
IN
Crystal input,nominally 14.318MHz.
Crystal output, nominally 14.318MHz.
Analog 3.3V Power supply
X2
OUT
PWR
IN
9, 44
VDDA
10, 30, 36, 42 SELxx
Real time PCI output frequency selection pins
5, 14, 17, 22, 27,
GND
PWR
Ground pins
32, 39, 47
Data pin for I2C circuitry 5V tolerant
6
SDATA
I/O
IN
Clock input of I2C input
7
SCLK
GNDA
8, 43
PWR
Analog ground pins
24, 23, 20, 19,
16, 15, 12, 11,
PCI clock outputs, selectable to be either
33.33 or 66.66MHz at 3.3V.
PCI clock outputs, selectable to be either
33.33 or 66.66MHz at 3.3V.
PCI clock outputs, selectable to be either
33.33 or 66.66MHz at 3.3V.
PCI clock outputs, selectable to be either
33.33 or 66.66MHz at 3.3V.
PCI1A (7:0)
PCI1B (2:0)
PCI2A (2:0)
PCI2B (2:0)
OUT
OUT
OUT
OUT
29, 28, 25
35, 34, 31
41, 40, 37
45
48
SPREAD
48MHz
IN
Enables Spread Spectrum, default is on.
OUT
Fixed 48MHz clock output for USB.
0663C—10/04/05
2
ICS951601
Preliminary Prouct Preview
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
How toWrite:
How to Read:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2(H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• Controller (host) will send start bit.
• Controller (host) sends the read address D3(H)
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• ICS clock sends first byte (Byte 0) through byte
5
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) will need to acknowledge each
byte
• Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock will acknowledge each byte one at a
time.
How to Write:
Controller (Host)
ICS (Slave/Receiver)
How to Read:
Start Bit
Address
Controller (Host)
ICS (Slave/Receiver)
Start Bit
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Byte Count
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
Stop Bit
Stop Bit
Notes:
1.
TheICSclockgeneratorisaslave/receiver, I2Ccomponent.Itcanreadbackthedatastoredinthelatches
for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
2.
3.
4.
5.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the
controller.The bytes must be accessed in sequential order from lowest to highest byte with the ability to
stop after any complete byte has been transferred. The Command code and Byte count shown above
must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is
issued.
6.
At power-on, all registers are set to a default condition, as shown.
0663C—10/04/05
3
ICS951601
Preliminary Product Preview
Serial Configuration Command Bitmap
Byte 0: Functionality and frequency select register (Default = 0)
Bit Bit2 Bit7 Bit6 Bit5 Bit4 66MHZ 33MHz
FS4 FS3 FS2 FS1 FS0
FEATURES
PWD
00000
0
66
66
33
33
-0.25 % down spread
-0.5 % down spread
-1.0 % down spread
-1.5 % down spread
+ 0.25 % center spread
+0.5 % center spread
+ 1.0 % center spread
+1.5 % center spread
2% over-clocking
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
66
66
33
33
66
66
33
33
66
33
66.6
67.32
68.64
69.96
72.6
65.27
63.96
62.6
60
33.3
33.66
34.32
34.98
36.3
32.63
31.97
31.3
30
4% over-clocking
6% over-clocking
Bit
2,7:4
10% over-clocking
2% under- clocking
2% under- clocking
2% under- clocking
2% under- clocking
-1.4 % down spread
-1.6 % down spread
-1.8 % down spread
-2.0 % down spread
+ 1.4 % center spread
+ 1.6 % center spread
+ 1.8 % center spread
+ 2.0 % center spread
66.6
66.6
66.6
66.6
66.6
66.6
66.6
66.6
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
0-Frequency and Spread is seleced by hardware select. Latched input
1-Frequency is seleced by Bit2, 7:4
Bit3
Bit1 0-Normal 1-Spread spectrum Enabled
Bit0 0-Running 1-Tristate all outputs
0
0
0663C—10/04/05
4
ICS951601
Preliminary Prouct Preview
Byte1:PCI1AStopClocksRegister
(1 = enable, 0 = disable)
Byte 2: PCI2A Stop Clocks
Register (1 = enable, 0 = disable)
Bit
Pin #
24
23
20
19
16
15
12
11
PWD
Description
PCI1A_7
PCI1A_6
PCI1A_5
PCI1A_4
PCI1A_3
PCI1A_2
PCI1A_1
PCI1A_0
Bit
Pin # PWD
Description
PCI2A_2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
35
34
31
29
28
25
-
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
X
X
PCI2A_1
PCI2A_0
PCI1B_2
PCI1B_1
PCI1B_0
Reserved
Reserved
-
Byte 3: PCI2B Stop Clocks Register
(1 = enable, 0 = disable)
Byte4:ReservedRegister
(1 = enable, 0 = disable)
Bit
Pin #
PWD
1
1
Description
PCI2B_2
Bit
Pin #
PWD
1
1
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
41
40
37
-
-
-
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
48
1
-
-
-
-
-
-
48MHz
REF0
PCI2B_1
PCI2B_0
Reserved
Reserved
Reserved
Reserved
Reserved
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
X
X
X
X
X
-
-
Byte 5: Latched Input Read Back Register
(1= enable, 0 = disable)
Byte 6: Reserved for Byte Count Register
(1= enable, 0 = disable)
Bit
Pin #
PWD
X
X
X
X
X
X
X
X
Description
Bit
Pin #
PWD
Description
Reserved for read
byte count
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
-
-
-
-
-
-
-
-
SEL2B
SEL1B
SEL2A
SEL1A
Reserved
Reserved
Reserved
Reserved
Bit7
-
0
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
-
-
-
-
-
-
-
0
0
0
0
1
1
0
Note: PWD = Power-Up Default
0663C—10/04/05
5
ICS951601
Preliminary Product Preview
Absolute Maximum Ratings
SupplyVoltage . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient OperatingTemperature . . . . . . . . . . 0°C to +70°C
StorageTemperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
CaseTemperature . . . . . . . . . . . . . . . . . . . . . 115°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratingsarestressspecificationsonlyandfunctionaloperationofthedeviceattheseoranyotherconditionsabovethose
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; VDD, VDDL = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX
VDD + 0.3
0.8
UNITS
V
VIL
VSS - 0.3
V
IIH
VIN = VDD
5
mA
mA
mA
mA
mA
MHz
pF
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
IIL2
-200
Operating Supply
Current
IDD3.3OP100 CL = 0 pF; Select @ 100 MHz
IDD3.3OP133 CL = 0 pF; Select @ 133 MHz
160
160
16
5
Input frequency
Fi
VDD = 3.3 V;
11
27
14.318
CIN
Logic Inputs
Input Capacitance1
CINX
Ttrans
Ts
X1 & X2 pins
45
3
pF
Transition Time1
Settling Time1
Clk Stabilization1
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From VDD = 3.3 V to 1% target Freq.
ms
ms
ms
3
TSTAB
3
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; VDD = 3.3 V +/-5%; VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
16
MAX UNITS
Operating
Supply Current
Power Down Supply
Current
IDD2.5OP100 CL = 0 pF; Select @ 100 MHz
IDD2.5OP133 CL = 0 pF; Select @ 133 MHz
75
mA
mA
19
90
IDD2.5PD
CL = 0 pF; PWRDWN# = 0
0.1
100
µA
1Guaranteed by design, not 100% tested in production.
0663C—10/04/05
6
ICS951601
Preliminary Prouct Preview
Electrical Characteristics - PCI
TA = 0 - 70°C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
Fall Time1
Duty Cycle1
Skew1
Skew1
Jitter, Cycle-to-cycle1
SYMBOL
VOH1
VOL1
IOH1
IOL1
tr1
CONDITIONS
MIN
2.4
TYP
MAX UNITS
V
IOH = -11 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
0.4
-22
V
mA
mA
ns
ns
%
16
45
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
2
tf1
2
dt1
55
tsk1
VT = 1.5 V @ 33.33
VT = 1.5 V @ 66.66
170
340
500
ps
ps
ps
tsk2
Tjcyc-cyc1 VT = 1.5 V
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 48 MHz
TA = 0 - 70°C; VDD = 3.3 V +/-5%; VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
Fall Time1
Duty Cycle1
Jitter, Cycle-to-cycle1
SYMBOL
VOH5
VOL5
IOH5
IOL5
CONDITIONS
MIN
2.4
TYP
MAX UNITS
V
IOH = -16 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
0.4
-22
V
mA
mA
ns
16
45
tr5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
4
4
tf5
ns
dt5
55
350
%
Tjcyc-cyc5 VT = 1.5 V
ps
1Guaranteed by design, not 100% tested in production.
0663C—10/04/05
7
ICS951601
Preliminary Product Preview
Electrical Characteristics - REF
TA = 0 - 70°C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
Fall Time1
Duty Cycle1
Jitter, Cycle-to-cycle1
SYMBOL
VOH5
VOL5
IOH5
IOL5
CONDITIONS
MIN
2.4
TYP
MAX UNITS
V
IOH = -16 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
0.4
-22
V
mA
mA
ns
16
45
tr5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
4
4
tf5
ns
dt5
55
500
%
Tjcyc-cyc5 VT = 1.5 V
ps
1Guaranteed by design, not 100% tested in production.
0663C—10/04/05
8
ICS951601
Preliminary Prouct Preview
c
In Millimeters
In Inches
N
SYMBOL
COMMON DIMENSIONS COMMON DIMENSIONS
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
L
A
A1
b
E1
E
INDEX
AREA
c
D
E
E1
e
SEE VARIATIONS
SEE VARIATIONS
10.03
7.40
10.68
7.60
.395
.291
.420
.299
1
2
a
hh xx 4455°°
0.635 BASIC
0.025 BASIC
D
h
L
0.38
0.50
0.64
1.02
.015
.020
.025
.040
N
α
SEE VARIATIONS
SEE VARIATIONS
A
0°
8°
0°
8°
A1
VARIATIONS
- CC --
D mm.
D (inch)
e
SEATING
PLANE
N
b
MIN
MAX
MIN
MAX
48
15.75
16.00
.620
.630
.10 (.004)
C
Reference Doc.: JEDEC Publication 95, M O-118
10-0034
300 mil SSOP Package
Ordering Information
ICS951601yFLF
Example:
ICS XXXX y F - PPP LF
Lead Free, RoHS Compliant (Optional)
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator
Device Type
Prefix
ICS = Standard Device
0663C—10/04/05
9
ICS951601
Preliminary Product Preview
Revision History
Rev.
Issue Date Description
Page #
C
10/4/2005 Added LF to Ordering Information
9
0663C—10/04/05
10
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