F2977NEGK8 [IDT]

High Linearity Broadband SP2T 30MHz to 6GHz;
F2977NEGK8
型号: F2977NEGK8
厂家: INTEGRATED DEVICE TECHNOLOGY    INTEGRATED DEVICE TECHNOLOGY
描述:

High Linearity Broadband SP2T 30MHz to 6GHz

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中文:  中文翻译
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High Linearity Broadband SP2T  
30MHz to 6GHz  
F2977  
Datasheet  
Description  
Features  
The F2977 is a 50ꢀ singleꢁpole doubleꢁthrow (SP2T) reflective RF  
switch featuring high linearity and wide bandwidth. This device is  
optimized from 30MHz to 6GHz to support a multitude of wireless  
RF applications. The F2977 uses a single positive supply voltage  
of either +3.3V or +5.0V and is compatible with either 1.8V or 3.3V  
control logic.  
Low insertion loss:  
0.38dB at 2.4GHz  
0.45dB at 6GHz  
High Isolation:  
39dB at 2.4GHz  
High Linearity:  
IIP2 +125dBm at 2.4GHz  
IIP3 +77dBm at 2.4GHz  
P0.1dB compression of +40dBm at 2.4GHz  
Second Harmonic: ꢁ95dBc at 900MHz  
Third Harmonic: ꢁ90dBc at 900MHz  
Supply voltage: +2.7V to +5.25V  
1.8V and 3.3V compatible control logic  
Competitive Advantage  
The F2977 provides extremely low insertion loss across the entire  
bandwidth while providing superb distortion performance.  
Low insertion loss  
High isolation  
Low distortion  
Fast switching  
No external matching required  
ꢁ40°C to +105°C operating temperature range  
2mm x 2mm, 12ꢁpin VFQFPꢁN package  
Typical Applications  
Block Diagram  
Cellular BTS  
Figure 1. Block Diagram  
Cellular BTS small cell  
Transmit / Receive switching  
Post PA switching  
General purpose  
RFC  
RF1  
RF2  
EN  
VCTL  
© 2017 Integrated Device Technology, Inc.  
1
Rev O May 19, 2017  
F2977 Datasheet  
Pin Assignments  
Figure 2. Pin Assignments for 2mm x 2mm x 0.5mm 12ꢀpin VFQFPꢀN, NEG12 – Top View  
RF2  
GND  
GND  
12  
11  
10  
GND  
1
VCC  
9
RFC  
GND  
2
3
EN  
F2977  
8
7
VCTL  
EP  
4
5
6
RF1  
GND  
GND  
Pin Descriptions  
Table 1.  
Pin Descriptions  
Number  
Name  
Description  
1
2
3
4
5
6
7
GND  
RFC  
GND  
GND  
RF1  
Internally grounded. Connect pin directly to paddle ground or as close as possible to pin with thru vias.  
RF Common Port. If this pin is not 0V DC, then an external coupling capacitor must be used.  
Internally grounded. Connect pin directly to paddle ground or as close as possible to pin with thru vias.  
Internally grounded. Connect pin directly to paddle ground or as close as possible to pin with thru vias.  
RF1 Port. If this pin is not 0V DC, then an external coupling capacitor must be used.  
Internally grounded. Connect pin directly to paddle ground or as close as possible to pin with thru vias.  
Logic control pin.  
GND  
VCTL  
Active HIGH enable pin. If LOW, neither RF1 nor RF2 are connected to RFC. Pin is internally pulled up to  
2.5V through a 500kꢂ resistor.  
8
9
EN  
Power supply. Bypass to GND with capacitors shown in the Typical Application Circuit as close as  
possible to pin.  
VCC  
10  
11  
12  
GND  
RF2  
Internally grounded. Connect pin directly to paddle ground or as close as possible to pin with thru vias.  
RF2 Port. If this pin is not 0V DC, then an external coupling capacitor must be used.  
GND  
Internally grounded. Connect pin directly to paddle ground or as close as possible to pin with thru vias.  
Exposed Pad. Internally connected to GND. Solder this exposed pad to a PCB pad that uses multiple  
ground vias to provide heat transfer out of the device into the PCB ground planes. These multiple ground  
vias are also required to achieve the specified RF performance.  
EP  
© 2017 Integrated Device Technology, Inc.  
2
Rev O May 19, 2017  
F2977 Datasheet  
Absolute Maximum Ratings  
Stresses beyond those listed below may cause permanent damage to the device. Functional operation of the device at these or any other  
conditions beyond those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions  
for extended periods may affect device reliability.  
Table 2.  
Absolute Maximum Ratings  
Parameter  
Symbol  
Minimum  
Maximum  
Units  
VCC to GND  
VCTL, EN  
VCC  
ꢁ0.3  
+5.5  
V
Lower of  
(VCC + 0.3, 3.9)  
VLOGIC  
VRF  
ꢁ0.3  
ꢁ0.3  
V
V
RF1, RF2, RFC  
+0.3  
Maximum Input CW  
Power, 50ꢂ, TEP = 25°C,  
30MHz ≤ fRF ≤ 200MHz  
200MHz < fRF ≤ 6000MHz  
30MHz ≤ fRF ≤ 200MHz  
200MHz < fRF ≤ 6000MHz  
PABSCW1  
33  
dBm  
dBm  
V
CC = 5.25V (any port,  
PABSCW2  
PABSPK1  
PABSPK2  
34  
38  
39  
insertion loss state) [a]  
Maximum Peak Power,  
50ꢂ, TEP = 25°C,  
V
CC = 5.25V (any port,  
insertion loss state) [a, b]  
Maximum Junction Temperature  
Storage Temperature Range  
TJMAX  
TST  
+140  
+150  
+260  
°C  
°C  
°C  
ꢁ65  
Lead Temperature (soldering, 10s)  
TLEAD  
Electrostatic Discharge – HBM  
(JEDEC/ESDA JSꢁ001ꢁ2012)  
2500  
(Class 2)  
VESDHBM  
VESDCDM  
V
V
Electrostatic Discharge – CDM  
(JEDEC 22ꢁC101F)  
1000  
(Class C3)  
a. TEP = Temperature of the exposed paddle.  
b. 5% duty cycle of a 4.6ms period.  
© 2017 Integrated Device Technology, Inc.  
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Rev O May 19, 2017  
F2977 Datasheet  
Recommended Operating Conditions  
Table 3.  
Recommended Operating Conditions  
Parameter  
Symbol  
Condition  
Minimum  
Typical  
Maximum  
Units  
Supply Voltage  
VCC  
TEP  
fRF  
2.7  
ꢁ40  
3.3  
5.25  
+105  
6
V
Operating Temperature Range  
RF Frequency Range  
Exposed Paddle  
°C  
0.030  
GHz  
Insertion Loss State  
ZS = ZL = 50ꢂ  
Maximum Operating Input Power  
Port Impedance (RFC, RF1, RF2)  
PMAX  
ZRF  
See Figure 3  
dBm  
Insertion Loss State  
50  
Figure 3. Maximum Operating RF Input Power (ZS = ZL = 50ꢁ)  
© 2017 Integrated Device Technology, Inc.  
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Rev O May 19, 2017  
F2977 Datasheet  
General Specifications  
Table 4.  
General Specifications  
See F2977 Typical Application Circuit. Specifications apply when operated with VCC = +3.3V, TEP = +25°C, EN = HIGH, single tone signal  
applied at RF1 or RF2 and measured at RFC, unless otherwise noted.  
Parameter  
Symbol  
Condition  
VCTL, EN pins  
Minimum  
Typical  
Maximum  
Units  
Lower of  
(VCC, 3.6)  
Logic Input HIGH Threshold  
VIH  
1.17 [b]  
V
Logic Input LOW Threshold  
Logic Current  
VIL  
VCTL, EN pins  
ꢁ0.3  
-10 [a]  
0.6  
+10  
150  
35  
V
IIH, IIL  
VCTL, EN pins (each pin)  
Normal Operation  
Standby (EN = LOW)  
ꢃA  
80  
20  
DC Current (VCC)  
Switching Rate  
ICC  
ꢃA  
SWRATE  
25  
kHz  
No Change  
in RF Path  
1.0  
1.6  
From Standby  
State, 50% EN  
to 90% RF  
Startup Time  
TSTRTUP  
ꢃs  
Change in  
RF Path  
Peak transient during  
switching. ZS = ZL = 50ꢂ.  
Measured with 20ns rise time,  
0V to 3.3V (3.3V to 0V)  
Maximum Video FeedꢁThrough,  
RFC Port  
VIDFT  
12  
mVpꢁp  
ꢃs  
control pulse applied to VCTL.  
Switching Time [c]  
SWTIME  
50% VCTL to 90% or 10% RF  
1.5  
3
a. Items in min/max columns in bold italics are guaranteed by test.  
b. Items in min/max columns that are not bold italics are guaranteed by design characterization.  
c. Measured at fRF = 1GHz.  
© 2017 Integrated Device Technology, Inc.  
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Rev O May 19, 2017  
F2977 Datasheet  
Electrical Characteristics  
Table 5.  
Electrical Characteristics  
See F2977 Typical Application Circuit. Specifications apply when operated with VCC = +3.3V, TEP = +25°C, ZS = ZL = 50ꢂ, EN = HIGH, single  
tone signal applied at RF1 or RF2 and measured at RFC, EVKit trace and connector losses are deꢁembedded, unless otherwise noted.  
Parameter  
Symbol  
Condition  
Minimum  
Typical  
Maximum  
Units  
30MHz < fRF ≤ 1GHz  
1GHz < fRF ≤ 2GHz [c]  
2GHz < fRF ≤ 3GHz  
3GHz < fRF ≤ 6GHz  
30MHz < fRF ≤ 1GHz  
1GHz < fRF ≤ 2GHz  
2GHz < fRF ≤ 3GHz  
3GHz < fRF ≤ 6GHz  
30MHz < fRF ≤ 1GHz  
1GHz < fRF ≤ 2GHz  
2GHz < fRF ≤ 3GHz  
3GHz < fRF ≤ 6GHz  
30MHz < fRF ≤ 1GHz  
1GHz < fRF ≤ 2GHz  
2GHz < fRF ≤ 3GHz  
3GHz < fRF ≤ 6GHz  
0.33  
0.36  
0.40  
0.45  
48  
0.53 [b]  
0.56 [a]  
Insertion Loss  
(RFC to RF1, RF2)  
IL  
dB  
43  
36  
31  
42  
Isolation  
(RFC to RF1, RF2)  
ISO1  
ISO2  
RL  
dB  
dB  
dB  
37  
27  
40  
33  
29  
45  
38  
Isolation  
(RF1 to RF2, RF2 to RF1)  
34  
26  
28  
26  
Return Loss (RFC, RF1, RF2)  
(Insertion loss states)  
26  
25  
a. Items in min/max columns in bold italics are guaranteed by test.  
b. Items in min/max columns that are not bold italics are guaranteed by design characterization.  
c. Minimum or maximum specification guaranteed by test at 2GHz and by design characterization over the whole  
frequency range.  
© 2017 Integrated Device Technology, Inc.  
6
Rev O May 19, 2017  
F2977 Datasheet  
Electrical Characteristics  
Table 6.  
Electrical Characteristics  
See F2977 Application Circuit. Specifications apply when operated with VCC = +3.3V, TEP = +25°C, ZS = ZL = 50ꢂ, EN = HIGH, single tone  
signal applied at RF1 or RF2 and measured at RFC, EVKit trace and connector losses are deꢁembedded, unless otherwise noted.  
Parameter  
Symbol  
Condition  
fRF = 30MHz  
Minimum  
Typical  
Maximum  
Units  
40  
40  
40  
Input 0.1dB Compression [c]  
P0.1dB  
fRF = 2.4GHz  
fRF = 6.0GHz  
dBm  
fRF = 2.4GHz  
PIN = +24dBm/tone  
100MHz spacing  
Input IP3  
(RF1, RF2 to RFC)  
IIP3  
IIP2  
77  
dBm  
dBm  
f1 = 700MHz  
f2 = 1.7GHz  
PIN = +24dBm/tone  
Measure 2.4GHz product  
125  
Input IP2  
(RF1, RF2 to RFC)  
f1 = 2.4GHz  
f2 = 3.5GHz  
PIN = +24dBm/tone  
Measure 5.9GHz product  
120  
fIN = 900MHz, PIN = +35dBm  
fIN = 1.8GHz, PIN = +33dBm  
fIN = 900MHz, PIN = +35dBm  
fIN = 1.8GHz, PIN = +33dBm  
ꢁ95  
ꢁ86  
ꢁ90  
ꢁ89  
ꢁ85 [b]  
ꢁ76  
Second Harmonic  
(RF1, RF2 to RFC)  
H2  
H3  
dBc  
dBc  
ꢁ75  
Third Harmonic  
(RF1, RF2 to RFC)  
ꢁ74  
fOUT ≥ 5MHz  
All unused ports terminated  
PSPUR1  
PSPUR2  
ꢁ133  
ꢁ120  
Spurious Output  
(No RF Applied)  
dBm  
fOUT < 5MHz  
All unused ports terminated  
a. Items in min/max columns in bold italics are guaranteed by test.  
b. Items in min/max columns that are not bold italics are guaranteed by design characterization.  
c. The input 0.1dB compression point is a linearity figure of merit. Refer to Figure 3 for the maximum RF operating input  
power levels.  
© 2017 Integrated Device Technology, Inc.  
7
Rev O May 19, 2017  
F2977 Datasheet  
Thermal Characteristics  
Table 7.  
Package Thermal Characteristics  
Parameter  
Symbol  
Value  
Units  
Junction to Ambient Thermal Resistance  
θJA  
102  
°C/W  
Junction to Case Thermal Resistance  
(Case is defined as the exposed paddle)  
θJC_BOT  
56  
°C/W  
Moisture Sensitivity Rating (Per JꢁSTDꢁ020)  
MSL 1  
Typical Operating Conditions (TOCs)  
Unless otherwise noted:  
VCC = +3.3V  
TEP = 25°C  
EN = HIGH  
ZS = ZL = 50ꢂ  
All temperatures are referenced to the exposed paddle  
Evaluation Kit traces and connector losses are deꢁembedded  
© 2017 Integrated Device Technology, Inc.  
8
Rev O May 19, 2017  
F2977 Datasheet  
Typical Performance Characteristics [1]  
Figure 4. RF1 to RFC Insertion Loss  
Figure 5. RF2 to RFC Insertion Loss  
0.0  
0.0  
-0.1  
-0.2  
-0.3  
-0.4  
-0.5  
-0.6  
-0.7  
-0.8  
-0.9  
-1.0  
-40 C / 2.7 V  
25 C / 2.7 V  
105 C / 2.7 V  
-40 C / 3.3 V  
25 C / 3.3 V  
105 C / 3.3 V  
-40 C / 5.25 V  
25 C / 5.25 V  
105 C / 5.25 V  
-40 C / 2.7 V  
25 C / 2.7 V  
105 C / 2.7 V  
-40 C / 3.3 V  
25 C / 3.3 V  
105 C / 3.3 V  
-40 C / 5.25 V  
25 C / 5.25 V  
105 C / 5.25 V  
-0.1  
-0.2  
-0.3  
-0.4  
-0.5  
-0.6  
-0.7  
-0.8  
-0.9  
-1.0  
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Frequency (GHz)  
Frequency (GHz)  
Figure 6. RF1 to RFC Isolation [RF2 On State]  
Figure 7. RF2 to RFC Isolation [RF1 On State]  
0
0
-40 C / 2.7 V  
25 C / 2.7 V  
105 C / 2.7 V  
-40 C / 3.3 V  
25 C / 3.3 V  
105 C / 3.3 V  
-40 C / 5.25 V  
25 C / 5.25 V  
105 C / 5.25 V  
-40 C / 2.7 V  
25 C / 2.7 V  
105 C / 2.7 V  
-40 C / 3.3 V  
25 C / 3.3 V  
105 C / 3.3 V  
-40 C / 5.25 V  
25 C / 5.25 V  
105 C / 5.25 V  
-10  
-20  
-30  
-40  
-50  
-60  
-70  
-80  
-90  
-10  
-20  
-30  
-40  
-50  
-60  
-70  
-80  
-90  
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Frequency (GHz)  
Frequency (GHz)  
Figure 8. RF1 to RF2 Isolation [RF1 On State]  
Figure 9. RF2 to RF1 Isolation [RF2 On State]  
0
0
-40 C / 2.7 V  
25 C / 2.7 V  
105 C / 2.7 V  
-40 C / 3.3 V  
25 C / 3.3 V  
105 C / 3.3 V  
-40 C / 5.25 V  
25 C / 5.25 V  
105 C / 5.25 V  
-40 C / 2.7 V  
25 C / 2.7 V  
105 C / 2.7 V  
-40 C / 3.3 V  
25 C / 3.3 V  
105 C / 3.3 V  
-40 C / 5.25 V  
25 C / 5.25 V  
105 C / 5.25 V  
-10  
-20  
-30  
-40  
-50  
-60  
-70  
-80  
-90  
-10  
-20  
-30  
-40  
-50  
-60  
-70  
-80  
-90  
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Frequency (GHz)  
Frequency (GHz)  
© 2017 Integrated Device Technology, Inc.  
9
Rev O May 19, 2017  
F2977 Datasheet  
Typical Performance Characteristics [2]  
Figure 10. RFC Return Loss [RF1 On State]  
Figure 11. RFC Return Loss [RF2 On State]  
0
0
-40 C / 2.7 V  
25 C / 2.7 V  
105 C / 2.7 V  
-40 C / 3.3 V  
25 C / 3.3 V  
105 C / 3.3 V  
-40 C / 5.25 V  
25 C / 5.25 V  
105 C / 5.25 V  
-40 C / 2.7 V  
25 C / 2.7 V  
105 C / 2.7 V  
-40 C / 3.3 V  
25 C / 3.3 V  
105 C / 3.3 V  
-40 C / 5.25 V  
25 C / 5.25 V  
105 C / 5.25 V  
-5  
-10  
-15  
-20  
-25  
-30  
-35  
-40  
-45  
-50  
-5  
-10  
-15  
-20  
-25  
-30  
-35  
-40  
-45  
-50  
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Frequency (GHz)  
Frequency (GHz)  
Figure 12. RF1 Return Loss [RF1 On State]  
Figure 13. RF2 Return Loss [RF2 On State]  
0
0
-40 C / 2.7 V  
25 C / 2.7 V  
105 C / 2.7 V  
-40 C / 3.3 V  
25 C / 3.3 V  
105 C / 3.3 V  
-40 C / 5.25 V  
25 C / 5.25 V  
105 C / 5.25 V  
-40 C / 2.7 V  
25 C / 2.7 V  
105 C / 2.7 V  
-40 C / 3.3 V  
25 C / 3.3 V  
105 C / 3.3 V  
-40 C / 5.25 V  
25 C / 5.25 V  
105 C / 5.25 V  
-5  
-10  
-15  
-20  
-25  
-30  
-35  
-40  
-45  
-50  
-5  
-10  
-15  
-20  
-25  
-30  
-35  
-40  
-45  
-50  
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Frequency (GHz)  
Frequency (GHz)  
Figure 14. Switching Time  
Figure 15. Switching Time  
[Isolation to Insertion Loss State]  
[Insertion Loss to Isolation State]  
© 2017 Integrated Device Technology, Inc.  
10  
Rev O May 19, 2017  
F2977 Datasheet  
Control Mode  
Table 8.  
Switch Control Truth Table  
VCTL (pin 7)  
EN (pin 8)  
HIGH  
Switch State  
RFC to RF1 Insertion Loss State  
RFC to RF2 Insertion Loss State  
Standby  
LOW  
HIGH  
HIGH  
Don’t Care  
LOW  
Application Information  
Power Supplies  
A common VCC power supply should be used for all pins requiring DC power. All supply pins should be bypassed with external capacitors to  
minimize noise and fast transients. Supply noise can degrade noise figure and fast transients can trigger ESD clamps and cause them to fail.  
Supply voltage change or transients should have a slew rate smaller than 1V / 20ꢃs. In addition, all control pins should remain at 0V (+/ꢁ 0.3V)  
while the supply voltage ramps up or while it returns to zero.  
Control Pin Interface  
If control signal integrity is a concern and clean signals cannot be guaranteed due to overshoot, undershoot, ringing, etc., the following circuit  
at the input of each control pin is recommended. This applies to control pins 7 and 8 as shown below.  
Figure 16. Control Pin Interface Schematic  
12  
11  
5
10  
GND  
1
VCC  
9
5k  
RFC  
GND  
2
3
EN  
8
7
2 pF  
2 pF  
EP  
4
6
5k  
VCTL  
© 2017 Integrated Device Technology, Inc.  
11  
Rev O May 19, 2017  
F2977 Datasheet  
Evaluation Kit Picture  
Figure 17. Top View  
Figure 18. Bottom View  
© 2017 Integrated Device Technology, Inc.  
12  
Rev O May 19, 2017  
F2977 Datasheet  
Evaluation Kit / Applications Circuit  
Figure 19. Electrical Schematic  
© 2017 Integrated Device Technology, Inc.  
13  
Rev O May 19, 2017  
F2977 Datasheet  
Table 9.  
Bill of Material (BOM)  
Part Reference  
C1 – C7  
QTY  
Description  
Manufacturer Part #  
Manufacturer  
0
3
5
1
Not Installed (0402)  
R1 – R3  
J1 – J5  
J6  
0ꢀ 1/10W, Resistor (0402)  
SMA Edge Mount  
ERJꢁ2GE0R00X  
142ꢁ0761ꢁ881  
68602ꢁ210HLF  
Panasonic  
Cinch Connectivity  
Amphenol FCI  
Conn Header 10 Pos 0.100” Str 15 Au  
TP1, TP2, TP3, TP4,  
TP5  
0
Not Installed Test Point Loop  
U1  
1
1
SP2T Switch 2mm x 2mm 12ꢁpin TQFN  
Printed Circuit Board  
F2977NEGK  
IDT  
IDT  
F2972 50ꢀ PCB  
Evaluation Kit (EVKit) Operation  
External Supply Setup  
Set up a VCC power supply in the voltage range of +2.7V to +5.25V with the power supply output disabled.  
Connect the disabled VCC supply connection to J6 pin 3 and GND to J6 pin 1, 2, 4, 6, 8, 9, or 10.  
Logic Control Setup  
With the logic control lines disabled, set the HIGH and LOW logic levels to satisfy the levels stated in the electrical specifications table.  
Connect the disabled logic control lines to J6 EN / LS (pin 5) and VCTL (pin 7).  
See Table 8 for the logic truth table.  
Turn On Procedure  
Setup the supplies and EVKit as noted in the External Supply Setup and Logic Control Setup sections above.  
Enable the VCC supply.  
Enable the logic control signals.  
Set the logic setting to achieve the desired Table 8 configuration. Note that external control logic should not be applied without VCC being  
present.  
Turn Off Procedure  
Set the logic control pins to a logic LOW.  
Disable the VCC supply.  
© 2017 Integrated Device Technology, Inc.  
14  
Rev O May 19, 2017  
F2977 Datasheet  
Package Drawings  
Figure 20. Package Outline Drawing NEG12 PSCꢀ4642  
© 2017 Integrated Device Technology, Inc.  
15  
Rev O May 19, 2017  
F2977 Datasheet  
Recommended Land Pattern  
Figure 21. Recommended Land Pattern NEG12 PSCꢀ4642  
© 2017 Integrated Device Technology, Inc.  
16  
Rev O May 19, 2017  
F2977 Datasheet  
Marking Diagram  
Line 1 ꢁ 2977 = Abbreviated part number.  
Line 2 ꢁ Y = Year code.  
Line 2 ꢁ W = Work week code.  
2977  
YW**  
Line 2 ꢁ ** = Sequential alpha for lot traceability.  
Ordering Information  
Orderable Part Number  
Package  
MSL Rating  
Shipping Packaging  
Temperature  
F2977NEGK  
F2977NEGK8  
F2977EVBI  
2mm x 2mm x 0.5mm 12ꢁVFQFPꢁN  
2mm x 2mm x 0.5mm 12ꢁVFQFPꢁN  
Evaluation Board  
MSL1  
MSL1  
Cut Reel  
ꢁ40°C to +105°C  
ꢁ40°C to +105°C  
Tape and Reel  
© 2017 Integrated Device Technology, Inc.  
17  
Rev O May 19, 2017  
F2977 Datasheet  
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2017ꢁMayꢁ19  
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© 2017 Integrated Device Technology, Inc.  
18  
Rev O May 19, 2017  

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