F29C51001B [ETC]
1MEGABIT(131,072 x 8 BIT) 5 VOLT CMOS FLASH MEMORY; 1MEGABIT （ 131,072 ×8位）的5伏CMOS FLASH MEMORY
| 型号： | F29C51001B |
| 厂家： | 
ETC |
| 描述： | 1MEGABIT(131,072 x 8 BIT) 5 VOLT CMOS FLASH MEMORY |
| 文件： | 总16页 (文件大小：144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SyncMOS
F29C51001T/F29C51001B
Functional Block Diagram
1,048,576 Bit
Memory Cell Array
X-Decoder
A0–A16
Address buffer & latches
Y-Decoder
CE
OE
WE
Control Logic
I/O Buffer & Data Latches
I/O0–I/O7
51001-05
Capacitance (1,2)
Symbol
Parameter
Test mSetup
Typ.
Max.
8
Units
pF
C
C
C
Input Capacitance
V
= 0
6
8
8
IN
IN
Output Capacitance
Control Pin Capacitance
V
= 0
12
pF
OUT
IN2
OUT
V
= 0
10
pF
IN
NOTE:
1. Capacitance is sampled and not 100% tested.
2.
T
= 25°C, V = 5V ± 10%, f = 1 MHz.
A
CC
(1)
Latch Up Characteristics
Parameter
Min.
-1
Max.
Unit
V
Input Voltage with Respect to GND on A , OE
+13
+ 1
9
Input Voltage with Respect to GND on I/O, address or control pins
Current
-1
V
V
CC
V
-100
+100
mA
CC
NOTE:
1. Includes all pins except V . Test conditions: V = 5V, one pin at a time.
CC
CC
AC Test Load
+5.0 V
IN3064
or Equivalent
2.7 kΩ
Device Under
Test
IN3064 or Equivalent
IN3064 or Equivalent
IN3064 or Equivalent
51001-06
CL = 100 pF
6.2 kΩ
F29C51001T/F29C51001B V1.0 May 1999
3
SyncMOS
F29C51001T/F29C51001B
(1)
Absolute Maximum Ratings
Symbol
Parameter
Commercial
-2 to +7
Extended
-2 to +7
Unit
V
V
V
Input Voltage (input or I/O pins)
IN
IN
Input Voltage (A pin, OE)
-2 to +13
-2 to +13
V
9
V
Power Supply Voltage
-0.5 to +5.5
-65 to +125
0 to +70
-0.5 to +5.5
-65 to +150
-40 to + 125
200 (Max.)
V
CC
T
Storage Temerpature (Plastic)
Operating Temperature
°C
°C
mA
STG
OPR
OUT
T
(2)
I
Short Circuit Current
200 (Max.)
NOTE:
1. Stress greater than those listed unders “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. No more than one output maybe shorted at a time and not exceeding one second long.
DC Electrical Characteristics
(over the commercial operating range)
Parameter
Name
Parameter
Test Conditions
Min.
—
Max.
0.8
—
Unit
V
V
V
Input LOW Voltage
Input HIGH Voltage
Input Leakage Current
Output Leakage Current
Output LOW Voltage
Output HIGH Voltage
Read Current
V
V
V
V
V
V
= V Min.
CC
IL
CC
= V Max.
2
V
IH
CC
CC
I
I
= GND to V , V = V Max.
—
±1
µA
µA
V
IL
OL
IN
CC
CC
CC
= GND to V , V = V Max.
—
±1
OUT
CC
CC
CC
V
V
= V Min., I = 2.1mA
—
0.4
—
OL
CC
CC
CC
OL
= V Min, I = -400µA
2.4
—
V
OH
CC
OH
I
CE = OE = V , WE = V , all I/Os open,
40
mA
CC1
IL
IH
Address input = V /V , at f = 1/t Min.,
IL IH
RC
V
= V Max.
CC
CC
I
I
I
Program Current
CE = WE = VIL, OE = V , V = V Max.
—
—
50
2
mA
mA
µA
V
CC2
IH
CC
CC
TTL Standby Current
CMOS Standby Current
CE = OE = WE = V , V = V Max.
IH CC CC
SB
CE = OE = WE = V – 0.3V, V = V Max.
—
100
12.5
50
SB1
CC
CC
CC
V
Device ID Voltage for A
CE = OE = V , WE = V
IH
11.5
—
H
9
9
IL
I
Device ID Current for A
CE = OE = V , WE = V , A9 = V Max.
µA
H
IL
IH
H
F29C51001T/F29C51001B V1.0 May 1999
4
SyncMOS
F29C51001T/F29C51001B
AC Electrical Characteristics
(over all temperature ranges)
Read Cycle
-45
-70
-90
Parameter
Name
Parameter
Min.
45
—
—
—
0
Max.
—
Min.
70
—
—
—
0
Max.
—
Min.
90
—
—
—
0
Max.
—
Unit
ns
t
Read Cycle Time
RC
t
Address Access Time
Chip Enable Access Time
Output Enable Access Time
CE Low to Output Active
OE Low to Output Active
45
70
90
ns
AA
t
45
70
90
ns
ACS
t
25
35
45
ns
OE
t
—
—
—
ns
CLZ
t
0
—
0
—
0
—
ns
OLZ
t
Output Enable or Chip Disable to Output
in High Z
0
15
0
20
0
30
ns
DF
t
Output Hold from Address Change
0
—
0
—
0
—
ns
OH
Program (Erase/Program) Cycle
Parameter
-45
-70
-90
Name
Parameter
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
t
Program Cycle Time
Address Setup Time
Address Hold Time
CE Setup Time
45
0
—
—
—
—
—
—
—
—
—
—
—
—
—
500
—
—
—
—
—
—
—
—
—
—
—
20
10
—
70
0
—
—
—
—
—
—
—
—
—
—
—
—
—
500
—
—
—
—
—
—
—
—
—
—
—
20
10
—
90
0
—
—
—
—
—
—
—
—
—
—
—
—
—
500
—
—
—
—
—
—
—
—
—
—
—
20
10
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ms
ms
WC
t
AS
t
35
0
45
0
45
0
AH
t
CS
t
CE Hold Time
0
0
0
CH
t
OE Setup Time
0
0
0
OES
t
OE High Hold Time
WE Pulse Width
WE Pulse Width High
Data Setup Time
Data Hold Time
0
0
0
OEH
t
25
20
20
0
35
35
25
0
45
38
30
0
WP
t
WPH
t
DS
t
DH
t
t
t
Programming Cycle
Sector Erase Cycle
Chip Erase Cycle
—
—
—
—
—
—
—
—
—
WHWH1
WHWH2
WHWH3
F29C51001T/F29C51001B V1.0 May 1999
5
SyncMOS
F29C51001T/F29C51001B
Waveforms of Read Cycle
tRC
ADDRESS
CE
tAA
tCE
tOE
tDF
OE
tOLZ
WE
tCLZ
tOH
HIGH-Z
I/O
HIGH-Z
VALID DATA OUT
tAA
VALID DATA OUT
51001-07
Waveforms of WE Controlled-Program Cycle
3rd bus cycle
tWC
tAS
PA(2)
5555H
PA
ADDRESS
tRC
tCH
tAH
CE
OE
tWHWH1
tWP
tOES
WE
tDF
tWPH
tDS
tCS
tOE
tDH
PD(3)
(1)
DOUT
I/O
A0H
I/O7
tOH
51001-08
NOTES:
1. I/O : The output is the complement of the data written to the device.
7
2. PA: The address of the memory location to be programmed.
3. PD: The data at the byte address to be programmed.
F29C51001T/F29C51001B V1.0 May 1999
6
SyncMOS
F29C51001T/F29C51001B
Waveforms of CE Controlled-Program Cycle
tWC
5555H
PA
tAS
tAH
PA(1)
ADDRESS
tRC
WE
OE
tWP
tWHWH1
CE
I/O
tDF
tWPH
tDS
tOES
tOE
tDH
PD(2)
DOUT
A0H
I/O7
tOH
51001-09
(1)
Waveforms of Erase Cycle
tWC
tAS
2AAAH
5555H
5555H
tAH
5555H
2AAAH
SA
ADDRESS
CE
OE
WE
tWP
tWPH
tCS
tDS
10H for
tDH
Chip Erase
AAH
55H
80H
AAH
55H
30H
I/O
51001-10
NOTES:
1. PA: The address of the memory location to be programmed.
2. PD: The data at the byte address to be programmed.
3. SA: The sector address for Sector Erase. Address = don’t care for Chip Erase.
F29C51001T/F29C51001B V1.0 May 1999
7
SyncMOS
F29C51001T/F29C51001B
Waveforms of DATA Polling Cycle
tCH
CE
tDF
tOE
OE
tOEH
tCE
WE
tOH
tWHWH1
HIGH-Z
VALID DATA OUT
I/O7
I/O7
I/O7
HIGH-Z
VALID DATA OUT
INVALID
I/O0-I/O6
I/O0-I/O6
51001-11
Waveforms of Toggle Bit Cycle
CE
tOEH
WE
OE
I/O6
51001-12
F29C51001T/F29C51001B V1.0 May 1999
8
SyncMOS
F29C51001T/F29C51001B
Functional Description
F29C51001T
F29C51001B
The F29C51001T/F29C51001B consists of 256
equally-sized sectors of 512 bytes each. The 8 KB
lockable Boot Block is intended for storage of the
system BIOS boot code. The boot code is the first
piece of code executed each time the system is
powered on or rebooted.
The F29C51001 is available in two versions: the
F29C51001T with the Boot Block address starting
from 1E000H to 1FFFFH, and the F29C51001B
with the Boot Block address starting from 00000H
to 1FFFFH.
1FFFFH
512
8KB Boot Block
1E000H
512
512
512
•
•
•
•
•
•
512
512
512
512
01FFFH
8KB Boot Block
00000H
00000H
Read Cycle
51001-13
A read cycle is performed by holding both CE
and OE signals LOW. Data Out becomes valid only
when these conditions are met. During a read cycle
WE must be HIGH prior to CE and OE going LOW.
WE must remain HIGH during the read operation
for the read to complete (see Table 1).
8KB Boot Block = 16 Sectors
During the byte program cycle, addresses are
latched on the falling edge of either CE or WE,
whichever is last. Data is latched on the rising edge
of CE or WE, whichever is first. The byte program
cycle can be CE controlled or WE controlled.
Output Disable
Sector Erase Cycle
Returning OE or CE HIGH, whichever occurs first
will terminate the read operation and place the l/O
pins in the HIGH-Z state.
The F29C51001T/F29C51001B features a
sector erase operation which allows each sector to
be erased and reprogrammed without affecting
data stored in other sectors. Sector erase operation
is initiated by using a specific six-bus-cycle
sequence: Two unlock program cycles, a setup
command, two additional unlock program cycles,
and the sector erase command (see Table 2). A
sector must be first erased before it can be
reprogrammed. While in the internal erase mode,
the device ignores any program attempt into the
device. The internal erase completion can be
determined via DATA polling or toggle bit.
Standby
The device will enter standby mode when the CE
signal is HIGH. The l/O pins are placed in the
HIGH-Z, independent of the OE signal.
Byte Program Cycle
The F29C51001T/F29C51001B is programmed
on a byte-by-byte basis. The byte program
operation is initiated by using a specific four-bus-
cycle sequence: two unlock program cycles, a
program setup command and program data
program cycles (see Table 2).
The F29C51001T/F29C51001B is shipped with
pre-erased sectors (all bits = 1).
Table 1. Operation Modes Decoding
Decoding Mode
Read
CE
OE
WE
A
A
A
I/O
READ
PD
0
0
0
1
1
1
9
9
9
V
V
V
IH
A
A
A
A
A
A
IL
IL
IH
IL
Byte Write
V
V
V
IH
IL
Standby
V
X
X
X
X
X
HIGH-Z
CODE
CODE
X
Autoselect Device ID
Autoselect Manufacture ID
Enabling Boot Block Protection Lock
V
V
V
V
V
V
V
V
V
V
V
V
V
IL
IL
IL
IL
IL
IH
IH
IH
IL
IL
H
H
H
V
IL
V
V
X
X
H
IL
F29C51001T/F29C51001B V1.0 May 1999
9
SyncMOS
F29C51001T/F29C51001B
Decoding Mode
CE
OE
WE
A
A
A
I/O
X
0
1
9
Disabling Boot Block Protection Lock
V
V
V
X
X
V
H
H
IL
H
Output Disable
V
V
V
X
X
X
HIGH-Z
IL
IH
IH
NOTES:
1. X = Don’t Care, V = HIGH, V = LOW. V = 12.5V Max.
IH
IL
H
2. PD: The data at the byte address to be programmed.
Table 2. Command Codes
First Bus
Program Cycle
Second Bus
Program Cycle
Third Bus
Program Cycle
Fourth Bus
Program Cycle
Fifth Bus
Program Cycle
Six Bus
Program Cycle
Command
Sequence
Address Data Address Data Address Data Address Data
Address Data Address Data
Read
XXXXH
5555H
5555H
F0H
Read
AAH 2AAAH
AAH 2AAAH
55H
55H
5555H
5555H
F0H RA
RD
Autoselect
90H
00H
01H
40H
01H
(1)
(2)
A1H
Byte
5555H
5555H
AAH 2AAAH
55H
5555H
A0H PA
PD(4)
Program
Chip Erase
AAH 2AAAH
AAH 2AAAH
55H
55H
5555H
5555H
80H
80H
5555H
5555H
AAH
AAH
2AAAH
2AAAH
55H
55H
5555H
PA(3)
10H
30H
Sector Erase 5555H
NOTES:
1. Top Boot Sector
2. Bottom Boot Sector
3. PA: The address of the memory location to be programmed.
4. PD: The data at the byte address to be programmed.
Chip Erase Cycle
DATA Polling (I/O )
7
The F29C51001T/F29C51001B features a chip-
erase operation. The chip erase operation is
initiated by using a specific six-bus-cycle
sequence: two unlock program cycles, a setup
command, two additional unlock program cycles,
and the chip erase command (see Table 2).
The chip erase operation is performed
sequentially, one sector at a time. When the
automated on chip erase algorithm is requested
with the chip erase command sequence, the device
automatically programs and verifies the entire
memory array for an all zero pattern prior to erasure
The automatic erase begins on the rising edge of
the last WE or CE pulse in the command sequence
and terminates when the data on DQ7 is “1”.
The F29C51001T/F29C51001B features DATA
polling to indicate the end of a program cycle.
When the device is in the program cycle, any
attempt to read the device will received the
complement of the loaded data on I/O . Once the
7
program cycle is completed, I/O will show true
7
data, and the device is then ready for the next
cycle.
Toggle Bit (I/O )
6
The F29C51001T/F29C51001B also features
another method for determining the end of a
program cycle. When the device is in the program
cycle, any attempt to read the device will result in
l/O toggling between 1 and 0. Once the program is
6
completed, the toggling will stop. The device is then
ready for the next operation. Examining the toggle
bit may begin at any time during a program cycle.
Program Cycle Status Detection
There are two methods for determining the state
of the F29C51001T/F29C51001B during a
program (erase/program) cycle: DATA Polling
(I/O ) and Toggle Bit (I/O ).
7
6
F29C51001T/F29C51001B V1.0 May 1999
10
SyncMOS
F29C51001T/F29C51001B
Boot Block Protection
Device ID
The F29C51001T/F29C51001B features
hardware Boot Block Protection. The boot block
sector protection is enabled when high voltage
(12.5V) is applied to OE and A9 pins with CE pin
LOW and WE pin lOW. The sector protection is
desabled when high voltage is applied to OE, CE
and A9 pins with WE pin LOW. Other pins can be
HIGH or LOW. This is shown in table 1.
In Autoselect mode, performing a read at
address XXXXH will determine whether the device
is a Top Boot Block device or a Bottom Boot Block
device. If the data is 01H, the device is a Top Boot
Block. If the data is A1H, the device is a Bottom
Boot Block device (see Table 3).
In addition, the device ID can also be read via the
command register when the device is erased or
programmed in a system without applying high
Autoselect
voltage to the A pin. When A is HIGH, the device
9
0
The F29C51001T/F29C51001B features an
Autoselect mode to identify the Boot Block
(protected/unprotected), the Device (Top/Bottom),
and the manufacturer ID.
ID is presented at the outputs.
Manufacturer ID
In Autoselect mode, performing a read at
address. XXXX0H will determine the manufacturer
ID. 40H is the manufacturer code for SyncMOS
Flash.
In addition the manufacturer ID can also be read
via the command register when the device is
erased or programmed in a system without
To get to the Autoselect mode, a high voltage
(V ) must be applied to the A pin. Once the A
H
9
9
signal is returned to LOW or HIGH, the device will
return to the previous mode.
Boot Block Protection Status
In Autoselect mode, performing a read at
address 3CXX2H or address 0CXX2H will indicate
if the Top Boot Block sector or the Bottom Boot
Block sector is locked out. If the data is 01H, the
Top/Bottom Boot Block is protected. If the data is
00H, the Top/Bottom Boot Block is unprotected.
(see Table 3.)
applying high voltage to the A pin. when A is
LOW, the manufacturer ID is presented at the
outputs.
9
0
Hardware Data Protection
V
Sense Protection: the program operation is
CC
inhibited when VCC is less than 2.5V.
Noise Protection: a CE or WE pulse of less than
5ns will not initiate a program cycle.
Program Inhibit Protection: holding any one of
OE LOW, CE HIGH or WE HIGH inhibits a program
cycle.
Table 3. Autoselect Decoding
Address
Decoding Mode
Boot Block
Top
A
A
A –A
A
–A
Data I/O –I/O
0
IL
IL
IH
1
IH
IH
2
13
14
16
0
7
Boot Block Protection
V
V
V
V
X
X
X
V
01H: protected
IH
Bottom
Top
V
00H: unprotected
IL
Device ID
V
V
X
01H
A1H
40H
IL
Bottom
Manufacture ID
V
V
X
X
IL
IL
NOTE:
1. X = Don’t Care, V = HIGH, V = LOW.
IH
IL
F29C51001T/F29C51001B V1.0 May 1999
11
SyncMOS
F29C51001T/F29C51001B
Byte Program Algorithm
Chip/Sector Erase Algorithm
Write Program
Write Erase
Command Sequence
Command Sequence
Add/Data
Add/Data
5555H/AAH
5555H/AAH
2AAAH/55H
5555H/A0H
PA/PD
2AAAH/55H
5555H/80H
5555H/AAH
2AAAH/55H
Four Bus
Cycle
Sequence
Six Bus
Cycle
Sequence
DATA Polling (I/O7)
or Toggle Bit (I/O6)
5555H/10H (Chip Erase)
PA/30H (Sector Erase
No
Verify Byte?
Yes
DATA Polling or Toggle Bit
Successfully Completed
Programming
Completed
Erase Complete
51001-14
F29C51001T/F29C51001B V1.0 May 1999
12
SyncMOS
F29C51001T/F29C51001B
DATA Polling Algorithm
Toggle Bit Algorithm
Read I/O7
Read I/O6
Read I/O6
Address = PBA(1)
No
I/O7 = Data
Yes
Yes
I/O6 Toggle
No
Program
Done
Program
Done
51002-17
NOTE:
1. PBA: The byte address to be programmed.
F29C51001T/F29C51001B V1.0 May 1999
13
SyncMOS
F29C51001T/F29C51001B
Package Diagrams
32-pin Plastic DIP
1.660 MAX.
15° MAX
INDEX-1
INDEX-2
EJECTOR MARK
.600 TYP
0.545/0.555
+.004
– .0004
.010
.050 MAX
0.210 MAX
0.120 MIN
.100
TYP
+.006
– .002
+.012
– 0
0.010 MIN
.018
.047
+.012
.032
– 0
32-pin PLCC
20 19 18 17 16 15 14
21
22
23
13
12
11
.590 ± .005
24
25
26
27
28
29
10
9
.550 ± .003
8
7
6
5
30 31 32
1
2
3
4
.045X45°
.450 ± .003
.490 ± .005
.136 ± .003
.110
.046 ± .003
.025
.050 TYP
30°
.017
3° - 6°
.420 ± .003
3° - 6°
3° - 6°
F29C51001T/F29C51001B V1.0 May 1999
14
SyncMOS
32-pin TSOP-I
Units in inches
F29C51001T/F29C51001B
Detail “A”
0.787 ± 0.008
0.010
0.315 TYP.
(0.319 MAX.)
0.024 ± 0.004
0.724 TYP. (0.728 MAX.)
0.035 ± 0.002
0.047 MAX.
SEATING
PLANE
0.032 TYP.
See Detail “A”
0.020 MAX.
0.020 SBC
0.009 ± 0.002
0.005 MIN.
0.007 MAX.
0.003 MAX
F29C51001T/F29C51001B V1.0 May 1999
15
SyncMOS Technology Inc.
Sales Office :
No. 1, Creation Rd. 1,
Science-Based Industrial Park,
Hsinchu, Taiwan, R.O.C.
Tel : 886-3-5792926
Fax : 886-3-5792953
Note 1 : publication date : May 1999. Rev. A
Note 2 : all data and specification are subject to change without notice.
F29C51001T/F29C51001B V1.0 May 1999
16
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