9FG830 [IDT]
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI; 八个输出差分频率发生器为PCIe 3代和QPI
| 型号： | 9FG830 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Eight Output Differential Frequency Generator for PCIe Gen3 and QPI |
| 文件： | 总19页 (文件大小：223K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
Eight Output Differential Frequency Generator
for PCIe Gen3 and QPI
9FG830
Features/Benefits:
GeneralDescription:
•
•
Pin-to-Pin with 9FG108D; Easy upgrade to PCIe Gen3
The 9FG830 is a Frequency Timing Generator that provides 8
HCSL differential output pairs. These outputs support PCI-Express
Gen3, and QPI applications. The part supports Spread Spectrum
and synthesizes several additional output frequencies from either
a 14.31818 MHz crystal, a 25 MHz crystal or reference input clock.
The 9FG830 also outputs a copy of the reference clock. Complete
control of the device is available via strapping pins or via the
SMBus interface.
Generates common frequencies from 14.318 MHz or 25
MHz; single part supports mulitple applications
•
•
•
•
Provides copy of reference output; eleminates need for
additional crystal or oscillator
Three spread spectrum modes: -0.5%, +/-0.25%, and off;
EMI reduction
Unused outputs may be disabled in Hi-Z; save system
power
RecommendedApplication:
Device may be configured by SMBus and/or strap pins;
can be used in systems without SMBus
8 Output Differential Output Frequency Generator for PCIe Gen3
and QPI
KeySpecifications:
OutputFeatures:
•
•
•
•
•
Cycle-to-cycle jitter: < 50ps with 25MHz input
Output-to-output skew: <50ps
•
•
8 - 0.7V current mode differential HCSL output pairs
1 - 3.3V LVTTL REF output
Phase jitter: PCIe Gen3 < 1ps rms
Phase jitter: QPI 9.6GB/s < 0.2ps rms
10 ppm synthesis error with 25MHz input and Spread Off
Functional Block Diagram
XIN/CLKIN
REFOUT
OSC
X2
OE(7:0)
8
STOP
LOGIC
PROGRAMMABLE
SPREAD PLL
DIF(7:0)
SPREAD
SEL14M_25M#
DIF_STOP#
FS(2:0)
CONTROL
LOGIC
SDATA
SCLK
IREF
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
1680C—08/26/10
1
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
Pin Configuration
XIN/CLKIN
X2
1
2
3
4
5
6
7
8
9
48 VDDA
47 GNDA
46 IREF
VDD
GND
45 vFS0
REFOUT
vFS2
44 vFS1
43 vOE_0
42 DIF_0
41 DIF_0#
40 VDD
vOE_7
DIF_7
DIF_7#
VDD 10
DIF_6 11
DIF_6# 12
^OE_6 13
VDD 14
39 DIF_1
38 DIF_1#
37 ^OE_1
36 VDD
35 GND
GND 15
34 ^OE_2
33 DIF_2
32 DIF_2#
31 VDD
^OE_5 16
DIF_5 17
DIF_5# 18
VDD 19
30 DIF_3
29 DIF_3#
28 vOE_3
27 ^SEL14M_25M#
26 vSPREAD
25 DIF_STOP#
DIF_4 20
DIF_4# 21
vOE_4 22
SDATA 23
SCLK 24
^ indicates internal 120K pull up
v indicates internal 120K pull down
Frequency Select Table
Power Groups
Pin Number
SEL14M_25M#
FS2 FS1 FS0 OUTPUT(MHz)
VDD
GND
4
Description
REFOUT, Digital Inputs, SMBus
DIF Outputs
(FS3)
3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
100.00
125.00
133.33
166.67
200.00
266.67
333.33
400.00
100.00
125.00
133.33
166.67
200.00
266.67
333.33
400.00
10,14,19,31,36,40
15,35
47
N/A
48
IREF
47
Analog VDD & GND for PLL Core
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
1680C—08/26/10
2
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
Pin Description
PIN #
PIN NAME
XIN/CLKIN
X2
PIN TYPE
IN
DESCRIPTION
Crystal input or Reference Clock input
1
2
3
4
5
6
OUT
PWR
PWR
OUT
IN
Crystal output, Nominally 14.318MHz
VDD
Power supply, nominal 3.3V
GND
Ground pin.
REFOUT
vFS2
Reference Clock output
Frequency select pin. This pin has an internal 120k pull down resistor
Active high input for enabling output 7. This pin has a 120kohm pull down.
0 =disable outputs, 1= enable outputs
7
vOE_7
IN
8
9
DIF_7
DIF_7#
VDD
OUT
OUT
PWR
OUT
OUT
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
10
11
12
DIF_6
DIF_6#
0.7V differential true clock output
0.7V differential Complementary clock output
Active high input for enabling output 6. This pin has an internal 120kohm pull up.
0 = disable outputs, 1= enable outputs
13
^OE_6
IN
14
15
VDD
GND
PWR
PWR
Power supply, nominal 3.3V
Ground pin.
Active high input for enabling output 5. This pin has an internal 120kohm pull up.
0 = disable outputs, 1= enable outputs
16
^OE_5
IN
17
18
19
20
21
DIF_5
DIF_5#
VDD
OUT
OUT
PWR
OUT
OUT
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
DIF_4
DIF_4#
0.7V differential true clock output
0.7V differential Complementary clock output
Active high input for enabling output 4. This pin as an internal 120kohm pull down.
0 =disable outputs, 1= enable outputs
22
vOE_4
IN
23
24
25
SDATA
I/O
IN
Data pin for SMBus circuitry, 5V tolerant.
Clock pin of SMBus circuitry, 5V tolerant.
Active low input to stop differential output clocks.
Asynchronous, active high input to enable spread spectrum functionality. This pin has
a 120Kohm pull down resistor.
SCLK
DIF_STOP#
IN
26
vSPREAD
IN
IN
Select 14.31818 MHz or 25 Mhz input frequency. This pin has an internal 120kohm
pull up resistor.
27
^SEL14M_25M#
1 = 14.31818 MHz, 0 = 25 MHz
Active high input for enabling output 3. This pin has an internal 120kohm pull down
resistor.
28
vOE_3
IN
0 =disable outputs, 1= enable outputs
29
30
DIF_3#
DIF_3
OUT
OUT
0.7V differential Complementary clock output
0.7V differential true clock output
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
1680C—08/26/10
3
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
Pin Description (Continued)
31
32
33
VDD
PWR
OUT
OUT
Power supply, nominal 3.3V
DIF_2#
DIF_2
0.7V differential Complementary clock output
0.7V differential true clock output
Active high input for enabling output 2. This pin has in internal 120kohm pull up
resistor.
34
^OE_2
IN
0 = disable outputs, 1= enable outputs
35
36
GND
VDD
PWR
PWR
Ground pin.
Power supply, nominal 3.3V
Active high input for enabling output 1. This pin has an internal 120kohm pull up
resistor.
37
^OE_1
IN
0 = disable outputs, 1= enable outputs
38
39
40
41
42
DIF_1#
DIF_1
VDD
OUT
OUT
PWR
OUT
OUT
0.7V differential Complementary clock output
0.7V differential true clock output
Power supply, nominal 3.3V
DIF_0#
DIF_0
0.7V differential Complementary clock output
0.7V differential true clock output
Active high input for enabling output 0. This pin has an internal 120kohm pull down
resistor.
43
vOE_0
IN
0 =disable outputs, 1= enable outputs
44
45
vFS1
vFS0
IN
IN
3.3V Frequency select latched input pin with internal 120kohm pull down resistor.
3.3V Frequency select latched input pin with internal 120kohm pull down resistor.
This pin establishes the reference current for the differential current-mode output pairs.
This pin requires a fixed precision resistor tied to ground in order to establish the
appropriate current. 475 ohms is the standard value.
Ground pin for the PLL core.
46
IREF
OUT
47
48
GNDA
VDDA
PWR
PWR
3.3V power for the PLL core.
Note:
^ indicates internal 120K pull up
v indicates internal 120K pull down
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
1680C—08/26/10
4
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
Electrical Characteristics - Absolute Maximum Ratings
PARAMETER
SYMBOL
CONDITIONS
UNITS NOTES
MIN
TYP
MAX
4.6
3.3V Core Supply Voltage
3.3V Logic Supply Voltage
Input Low Voltage
VDDA
VDD
VIL
V
V
V
1,2
1,2
1
4.6
GND-0.5
Input High Voltage
Input High Voltage
VIH
Except for SMBus interface
SMBus clock and data pins
VDD+0.5V
5.5V
V
V
1
1
VIHSMB
°C
°C
V
1
1
1
Storage Temperature
Junction Temperature
Input ESD protection
Ts
Tj
-65
150
125
ESD prot
Human Body Model
2000
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor guaranteed.
Electrical Characteristics - Input/Supply/Common Parameters
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
TCOM
TIND
Commmercial range
0
70
85
°C
°C
1
1
Ambient Operating
Temperature
Industrial range
-40
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
Input High Voltage
Input Low Voltage
VIH
2
VDD + 0.3
V
1
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
VIL
IIN
GND - 0.3
-5
0.8
5
V
1
1
Single-ended inputs, VIN = GND, VIN = VDD
uA
Single-ended inputs
Input Current
VIN = 0 V; Inputs with internal pull-up resistors
VIN = VDD; Inputs with internal pull-down resistors
IINP
-200
200
uA
1
SEL14M_25M# = 0
SEL14M_25M# = 1
25
MHz
MHz
nH
1
1
1
Input Frequency
Pin Inductance
Fin
14.31818
Lpin
CIN
7
5
6
6
Logic Inputs
Crystal inputs
1.5
pF
pF
pF
1
1
1
Capacitance
CINXTAL
COUT
Output pin capacitance
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
Allowable Frequency
Clk Stabilization
SS Modulation Frequency
OE# Latency
TSTAB
fMODIN
tLATOE#
tDRVDS
2.5
33
ms
kHz
1,2
1
30
1
(Triangular Modulation)
DIF start after OE# assertion
DIF stop after OE# deassertion
DIF output enable after
3
cycles
us
1,3
1,3
Tdrive_STOP#
300
DIF_STOP# de-assertion
Tfall
tF
Fall time of control inputs
5
5
ns
ns
V
1,2
1,2
1
Trise
tR
Rise time of control inputs
SMBus Input Low Voltage
SMBus Input High Voltage
VILSMB
VIHSMB
0.8
2.1
VDDSMB
0.4
V
1
SMBus Output Low Voltage VOLSMB
@ IPULLUP
@ VOL
V
1
SMBus Sink Current
Nominal Bus Voltage
SCLK/SDATA Rise Time
IPULLUP
VDDSMB
tRSMB
4
mA
V
1
3V to 5V +/- 10%
2.7
5.5
1000
300
1
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
ns
ns
1
SCLK/SDATA Fall Time
SMBus Operating
Frequency
tFSMB
1
fMAXSMB
Maximum SMBus operating frequency
100
kHz
1
1Guaranteed by design and characterization, not 100% tested in production.
2Control input must be monotonic from 20% to 80% of input swing.
3Time from deassertion until outputs are >200 mV
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
1680C—08/26/10
5
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
Electrical Characteristics - DIF 0.7V Current Mode Differential Outputs
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%, See Test Loads for loading conditions
PARAMETER
SYMBOL
Trf
CONDITIONS
MIN
1
TYP MAX UNITS NOTES
V/ns
%
Slew rate
Scope averaging on
4
1, 2, 3
1, 2, 4
∆
Slew rate matching
Trf
Slew rate matching, Scope averaging on
20
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
Voltage High
Voltage Low
VHigh
VLow
660
850
1
1
mV
-150
150
Max Voltage
Min Voltage
Vmax
Vmin
Measurement on single ended signal using
absolute value. (Scope averaging off)
Scope averaging off
1150
1
mV
-300
300
250
1
Vswing
Vswing
mV
mV
mV
1, 2
1, 5
1, 6
Crossing Voltage (abs)
Crossing Voltage (var)
Vcross_abs
∆
Scope averaging off
550
140
-Vcross
Scope averaging off
1
Ω
Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA.
Ω
Ω
IOH = 6 x IREF and VOH = 0.7V @ ZO=50 (100 differential impedance).
2 Measured from differential waveform
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4 Matching applies to rising edge rate of Clock / falling edge rate of Clock#. It is measured in a +/-75mV window centered on the
average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope uses for the edge rate calculations.
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6 The total variation of all Vcross measurements in a particular system. This is a subset of V_cross_min/max (V_cross absolute)
allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolute.
Electrical Characteristics - Current Consumption
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%, See Test Loads for loading conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
IDD3.3
IDDA3.3OP
IDD3.3
VDD, All outputs active @100MHz
VDDA, All outputs active @100MHz
VDD, All outputs active @400MHz
VDDA, All outputs active @400MHz
VDD, All DIF pairs stopped driven
VDDA, All DIF pairs stopped driven
VDD, All DIF pairs stopped Hi-Z
VDDA, All DIF pairs stopped Hi-Z
mA
mA
mA
mA
mA
mA
mA
mA
1
1
1
1
1
1
1
1
250
28
Operating Supply Current
200
28
IDDA3.3OP
IDD3.3DS
IDDA3.3DS
IDD3.3DZ
IDDA3.3DZ
190
28
DIF_STOP# Current
38
28
1Guaranteed by design and characterization, not 100% tested in production.
2
Ω
Ω
IREF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50 .
Electrical Characteristics - Output Duty Cycle, Jitter, and Skew Characterisitics
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
45
TYP
MAX
UNITS NOTES
Duty Cycle
tDC
Measured differentially, PLL Mode
VT = 50%
55
50
50
60
%
ps
ps
ps
1
Skew, Output to Output
Jitter, Cycle to cycle
Jitter, Cycle to cycle
tsk3
1
tjcyc-cyc
25M input
1,3
1,3
tjcyc-cyc
14.318M input
1Guaranteed by design and characterization, not 100% tested in production.
2 IREF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50 .
3 Measured from differential waveform
Ω
Ω
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
1680C—08/26/10
6
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
Electrical Characteristics - Phase Jitter Parameters
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%, See Test Loads for loading conditions
PARAMETER
SYMBOL
tjphPCIeG1
CONDITIONS
PCIe Gen 1
MIN
TYP
MAX
86
UNITS Notes
ps (p-p) 1,2,3,6
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
ps
3
3.1
1
1,2,6
(rms)
tjphPCIeG2
Phase Jitter, PCI Express
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
PCIe Gen 3
ps
1,2,6
(rms)
ps
(rms)
ps
1,2,4,5,
6
tjphPCIeG3
(PLL BW of 2-4MHz, CDR = 10MHz)
QPI & SMI
0.5
0.3
0.2
1,5,6
1,5,6
1,5,6
(100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI)
QPI & SMI
(rms)
ps
Phase Jitter, QPI/SMI
tjphQPI_SMI
(100MHz, 8.0Gb/s, 12UI)
QPI & SMI
(rms)
ps
(100MHz, 9.6Gb/s, 12UI)
1 Guaranteed by design and characterization, not 100% tested in production.
2 See http://www.pcisig.com for complete specs
(rms)
3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
4 Subject to final radification by PCI SIG.
5 Calculated from Intel-supplied Clock Jitter Tool v 1.6.3
6 Applies to all differential outputs
Electrical Characteristics - REF-14.318/25 MHz
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%; See Test Loads for Loads for loading conditions.
PARAMETER
Long Accuracy
Clock period
SYMBOL
ppm
CONDITIONS
MIN
TYP
0
MAX
UNITS Notes
see Tperiod min-max values
14.318MHz output nominal
ppm
ns
ns
V
1,2
1,2
1,2
1
Tperiod
69.8413
Clock period
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise/Fall Time
Duty Cycle
Tperiod
VOH
VOL
IOH
25.000MHz output nominal
IOH = -1 mA
40
2.4
IOL = 1 mA
0.4
-23
27
V
1
VOH @MIN = 1.0 V, VOH@MAX = 3.135 V
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VT = 1.5 V
-29
29
mA
mA
ns
%
1
IOL
1
trf1
0.5
45
2
1
dt1
55
1
Jitter
tjcyc-cyc
VT = 1.5 V
100
250
ps
1
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 14.31818 or 25.00 MHz
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
1680C—08/26/10
7
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
SRC Reference Clock
Common Recommendations for Differential Routing
Dimension or Value
0.5 max
Unit Notes
L1 length, route as non-coupled 50ohm trace
inch
inch
inch
ohm
ohm
1
1
1
1
1
L2 length, route as non-coupled 50ohm trace
0.2 max
0.2 max
33
L3 length, route as non-coupled 50ohm trace
Rs
Rt
49.9
Down Device Differential Routing
L4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max
inch
inch
1
1
L4 length, route as coupled stripline 100ohm differential trace
1.8 min to 14.4 max
Differential Routing to PCI Express Connector
L4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max
inch
inch
2
2
L4 length, route as coupled stripline 100ohm differential trace
0.225 min to 12.6 max
Figure 1: Down Device Routing
(Test Load)
L2
L1
Rs
Rs
L4
L4'
L2'
L1'
Rt
Rt
HCSL Output Buffer
PCI Express
Down Device
REF_CLK Input
L3' L3
Figure 2: PCI Express Connector Routing
L2
L1
Rs
L4
L4'
L2'
L1'
Rs
Rt
Rt
HCSL Output Buffer
PCI Express
Add-in Board
REF_CLK Input
L3' L3
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
1680C—08/26/10
8
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
Alternative Termination for LVDS and other Common Differential Signals (Figure 3)
Vdiff
0.45v
0.58
0.80
0.60
Vp-p
0.22v
0.28
0.40
0.3
Vcm
1.08
0.6
R1
33
33
33
33
R2
R3
R4
Note
150
78.7
78.7
174
100
137
none
140
100
100
100
100
0.6
ICS874003i-02 input compatible
Standard LVDS
1.2
R1a = R1b = R1
R2a = R2b = R2
Figure 3
L2
L1
R3
R4
R1a
R1b
L4
L4'
L2'
L1'
R2a
R2b
HCSL Output Buffer
Down Device
REF_CLK Input
L3'
L3
Cable Connected AC Coupled Application (figure 4)
Component
Value
Note
R5a, R5b
R6a, R6b
Cc
8.2K 5%
1K 5%
0.1 µF
Vcm
0.350 volts
Figure 4
3.3 Volts
R5a
R5b
Cc
L4
L4'
Cc
R6a
R6b
PCIe Device
REF_CLK Input
Figure 5. REF Output Test Load
Zo = 50 ohms
33
5pF
9FGxxx REF Output
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
1680C—08/26/10
9
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
Differential Clock Tolerances x1 - 25MHz
Clock Periods - Differential Outputs with Spread Spectrum Disabled
Measurement Window
SSC OFF
1 Clock
1us
0.1s
0.1s
0.1s
1us
1 Clock
or SSC +/- Synthesis
Center
Freq.
MHz
+SSC
Units Notes
Short- +c2c jitter
-SSC
- ppm
+ ppm
Long-Term
Average
Max
0.25%
Center
Spread
Error
-c2c jitter
AbsPer
Min
0 ppm
Period
Short-Term Long-Term
(ppm)
Term
Average
Max
AbsPer
Max
Average
Min
Average
Min
Nominal
0
0
100.00
125.00
133.33
166.67
200.00
266.67
333.33
400.00
9.95000
7.95000
7.45000
5.94994
4.95000
3.69998
2.94997
2.45000
10.00000
8.00000
7.50000
5.99994
5.00000
3.74998
2.99997
2.50000
10.00000
8.00000
7.50000
6.00000
5.00000
3.75000
3.00000
2.50000
10.00000
8.00000
7.50000
6.00006
5.00000
3.75002
3.00003
2.50000
10.05000
8.05000
7.55000
6.05006
5.05000
3.80002
3.05003
2.55000
ns
ns
ns
ns
ns
ns
ns
ns
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
0
10
0
DIF
6
10
0
Clock Periods - Differential Outputs with Spread Spectrum Enabled
Measurement Window
1 Clock
1us
0.1s
0.1s
0.1s
1us
1 Clock
SSC ON
-0.5%
Synthesis
Error
Center
Freq.
MHz
+SSC
Units Notes
Short- +c2c jitter
-SSC
- ppm
+ ppm
Long-Term
Average
Max
-c2c jitter
AbsPer
Min
0 ppm
Period
Down
Short-Term Long-Term
(ppm)
Term
Average
Max
AbsPer
Max
Spread
Average
Min
Average
Min
Nominal
96
19
96
10
96
-98
10
96
99.75
124.69
133.00
166.25
199.50
266.00
332.50
399.00
9.94910
7.94990
7.44933
5.94998
4.94955
3.70039
2.94999
2.44978
9.99910
7.99990
7.49933
5.99998
4.99955
3.75039
2.99999
2.49978
10.02410
8.01990
7.51808
6.01498
5.01205
3.75977
3.00749
2.50603
10.02506
8.02005
7.51880
6.01504
5.01253
3.75940
3.00752
2.50627
10.02603 10.05103 10.10103
ns
ns
ns
ns
ns
ns
ns
ns
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
8.02020
7.51952
6.01510
5.01301
3.75903
3.00755
2.50651
8.04020
7.53827
6.03010
5.02551
3.76841
3.01505
2.51276
8.09020
7.58827
6.08010
5.07551
3.81841
3.06505
2.56276
DIF
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy specifications are guaranteed with the assumption that the REF output is tuned to the exact target XTAL
frequency.
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
1680C—08/26/10
10
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
Differential Clock Tolerances x1 - 14.31818MHz
Clock Periods - Differential Outputs with Spread Spectrum Disabled
Measurement Window
SSC OFF
1 Clock
1us
0.1s
0.1s
0.1s
1us
1 Clock
or SSC +/- Synthesis
Center
Freq.
MHz
+SSC
Units Notes
Short- +c2c jitter
-SSC
- ppm
+ ppm
Long-Term
Average
Max
0.25%
Center
Spread
Error
-c2c jitter
AbsPer
Min
0 ppm
Period
Short-Term Long-Term
(ppm)
Term
Average
Max
AbsPer
Max
Average
Min
Average
Min
Nominal
35
-114
35
100.00
125.00
133.33
166.67
200.00
266.67
333.33
400.00
9.94965
7.95091
7.44974
5.95062
4.94983
3.69984
2.95031
2.44991
9.99965
8.00091
7.49974
6.00062
4.99983
3.74984
3.00031
2.49991
10.00000
8.00000
7.50000
6.00000
5.00000
3.75000
3.00000
2.50000
10.00035
7.99909
7.50026
5.99937
5.00018
3.75016
2.99969
2.50009
10.05035
8.04909
7.55026
6.04937
5.05018
3.80016
3.04969
2.55009
ns
ns
ns
ns
ns
ns
ns
ns
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
-104
35
DIF
42
-104
35
Clock Periods - Differential Outputs with Spread Spectrum Enabled
Measurement Window
1 Clock
1us
0.1s
0.1s
0.1s
1us
1 Clock
SSC ON
-0.5%
Synthesis
Error
Center
Freq.
MHz
+SSC
Units Notes
Short- +c2c jitter
-SSC
- ppm
+ ppm
Long-Term
Average
Max
-c2c jitter
AbsPer
Min
0 ppm
Period
Down
Short-Term Long-Term
(ppm)
Term
Average
Max
AbsPer
Max
Spread
Average
Min
Average
Min
Nominal
199
-100
199
10
99.75
124.69
133.00
166.25
199.50
266.00
332.50
399.00
9.94807
7.95085
7.44855
5.94998
4.94903
3.70055
2.94999
2.44952
9.99807
8.00085
7.49855
5.99998
4.99903
3.75055
2.99999
2.49952
10.02307
8.02085
7.51730
6.01498
5.01153
3.75992
3.00749
2.50577
10.02506
8.02005
7.51880
6.01504
5.01253
3.75940
3.00752
2.50627
10.02706 10.05206 10.10206
ns
ns
ns
ns
ns
ns
ns
ns
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
8.01925
7.52029
6.01510
5.01353
3.75887
3.00755
2.50676
8.03925
7.53904
6.03010
5.02603
3.76825
3.01505
2.51301
8.08925
7.58904
6.08010
5.07603
3.81825
3.06505
2.56301
DIF
199
-140
10
199
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy specifications are guaranteed with the assumption that the REF output is tuned to the exact target XTAL
frequency.
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
1680C—08/26/10
11
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
General SMBus serial interface information for the 9FG830
How to Write:
How to Read:
• Controller (host) sends a start bit.
• Controller (host) sends the write address DC(H)
• IDT clock will acknowledge
• Controller (host) will send start bit.
• Controller (host) sends the write address DC(H)
• IDT clock will acknowledge
• Controller (host) sends the begining byte location = N
• IDT clock will acknowledge
• Controller (host) sends the begining byte
location = N
• Controller (host) sends the data byte count = X
• IDT clock will acknowledge
• IDT clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address DD(H)
• IDT clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
(see Note 2)
• IDT clock will send the data byte count = X
• IDT clock sends Byte N + X -1
• IDT clock will acknowledge each byte one at a time
• IDT clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
• Controller (host) sends a Stop bit
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host)
Index Block Read Operation
Controller (Host)
IDT (Slave/Receiver)
IDT (Slave/Receiver)
starT bit
T
T
starT bit
Slave Address DC(H)
Slave Address DC(H)
WR
WRite
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
WR
WRite
ACK
ACK
ACK
ACK
ACK
ACK
Beginning Byte = N
RT
Repeat starT
Slave Address DD(H)
RD
ReaD
ACK
Data Byte Count = X
Beginning Byte N
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
Byte N + X - 1
N
P
Not acknowledge
stoP bit
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
1680C—08/26/10
12
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
SMBus Table: Device Control Register, READ/WRITE ADDRESS (DC/DD)
Byte 0
Bit 7
Pin #
Name
Control Function
FS31
FS21
FS11
FS01
Type
RW
RW
RW
RW
RW
0
1
Default
Pin 27
Pin 5
27
5
See Frequency
Selection Table.
Bit 6
Bit 5
Bit 4
Bit 3
44
7
Pin 44
Pin 7
Spread Enable1
26
Off
On
Pin 26
Enable Software Control of Frequency,
Spread Enable (Spread Type always
Software Control)
Hardware Software
-
RW
0
Bit 2
Select
Select
-
-
DIF_STOP# drive mode
Spread Type
RW
RW
Driven
Down
Hi-Z
0
0
Bit 1
Bit 0
Center
Notes:
1. These bits reflect the state of the corresponding pins at power up, but may be written to
if Byte 0, bit 2 is set to '1'. FS3 is the SEL14M_25M# pin.
SMBus Table: Output Enable Register
Byte 1
Bit 7
Pin #
Name
Control Function
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
Default
-
-
-
-
-
-
-
-
DIF_7 EN
DIF_6 EN
DIF_5 EN
DIF_4 EN
DIF_3 EN
DIF_2 EN
DIF_1 EN
DIF_0 EN
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
1
1
1
1
1
1
1
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Note:
Byte 1 sets outputs active or inactive, not the conditons set by the OE inputs.
SMBus Table: Output Stop Mode Register
Byte 2 Pin # Name
Bit 7
Control Function
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
Default
-
-
-
-
-
-
-
-
DIF_7 STOP EN Free Run/ Stop Enable
DIF_6 STOP EN Free Run/ Stop Enable
DIF_5 STOP EN Free Run/ Stop Enable
DIF_4 STOP EN Free Run/ Stop Enable
DIF_3 STOP EN Free Run/ Stop Enable
DIF_2 STOP EN Free Run/ Stop Enable
DIF_1 STOP EN Free Run/ Stop Enable
DIF_0 STOP EN Free Run/ Stop Enable
Free-run Stop-able
Free-run Stop-able
Free-run Stop-able
Free-run Stop-able
Free-run Stop-able
Free-run Stop-able
Free-run Stop-able
Free-run Stop-able
0
0
0
0
0
0
0
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
1680C—08/26/10
13
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
SMBus Table: Frequency Select Readback Register
Byte 3
Pin #
Name
SEL14M_25M#1
(FS3)
Control Function
Type
0
1
Default
27
State of pin 27
R
Pin 27
Bit 7
See Frequency
Selection Table.
FS21
FS11
FS01
6
State of pin 6
State of pin 44
State of pin 45
State of pin 26
R
R
R
Pin 6
Pin 44
Pin 45
Bit 6
Bit 5
Bit 4
44
45
26
SPREAD1
R
R
R
R
Off
On
Pin 26
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
X
X
X
Reserved
Reserved
Reserved
Reserved
Notes:
1. These bits reflect the state of the corresponding pins, regardless of whether software
programming is enabled or not.
SMBus Table: Vendor & Revision ID Register
Byte 4
Bit 7
Pin #
Name
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
Control Function
Type
R
0
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
Default
-
-
-
-
-
-
-
-
X
X
X
X
0
0
0
1
R
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REVISION ID
R
R
R
R
VENDOR ID
R
R
SMBus Table: DEVICE ID
Byte 5 Pin #
Bit 7
Name
Control Function
Type
R
0
1
Default
-
-
-
-
-
-
-
-
DEVID7
DEVID6
DEVID5
DEVID4
DEVID3
DEVID2
DEVID1
DEVID0
Reserved
1
0
0
0
0
0
1
1
R
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
Device ID = 83 hex
R
R
R
R
SMBus Table: Byte Count Register
Byte 6
Bit 7
Pin #
Name
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
Control Function
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
-
-
-
-
-
-
-
1
Default
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
0
1
1
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Writing to this register
will configure how many
bytes will be read back,
default is 07 = 7 bytes.
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
1680C—08/26/10
14
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
SMBus Table: Reserved Register
Byte 7
Bit 7
Pin #
Name
Control Function
Reserved
Type
0
1
Default
X
X
X
X
X
X
X
X
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SMBus Table: Reserved Register
Byte 8 Pin # Name
Bit 7
Control Function
Type
0
1
Default
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
X
X
X
X
X
X
X
X
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SMBus Table: M/N Programming Enable
Byte 9
Pin #
Name
Control Function
Type
0
1
Default
PLL M/N Programming
Enable
-
M/N_EN
RW
Disable
Enable
0
Bit 7
Select Polarity of OE
inputs
RW
RW
OE#
OE
-
OE_Polarity
REFOUT_En
1
Bit 6
Enables/Disables REF
Disable
Enable
5
1
0
0
0
0
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
Reserved
SMBus Table: PLL Frequency Control Register
Byte 10
Bit 7
Pin #
Name
Control Function
Type
0
1
Default
-
-
-
-
-
-
-
-
PLL N Div8
N Divider Prog bit 8
RW
X
The decimal
PLL N Div9
PLL M Div5
PLL M Div4
PLL M Div3
PLL M Div2
PLL M Div1
PLL M Div0
N Divider Prog bit 9
RW
RW
RW
RW
RW
RW
RW
X
X
X
X
X
X
X
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
representation of M and
N Divider in Byte 11 and
12 will configure the PLL
VCO frequency.
Default at power up =
latch-in or Byte 0 Rom
table. VCO Frequency
= fXTAL x [NDiv(9:0)+8]
/ [MDiv(5:0)+2]
M Divider Programming
bit (5:0)
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
1680C—08/26/10
15
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
SMBus Table: PLL Frequency Control Register
Byte 11
Bit 7
Pin #
Name
Control Function
Type
0
1
Default
-
-
-
-
PLL N Div7
RW
X
The decimal
PLL N Div6
PLL N Div5
RW
RW
representation of M and
N Divider in Byte 11 and
12 will configure the PLL
VCO frequency.
X
X
Bit 6
Bit 5
N Divider Programming
Byte11 bit(7:0) and
Byte10 bit(7:6)
PLL N Div4
PLL N Div3
PLL N Div2
PLL N Div1
PLL N Div0
RW
RW
RW
RW
RW
X
X
X
X
X
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default at power up =
latch-in or Byte 0 Rom
table. VCO Frequency
= fXTAL x [NDiv(9:0)+8]
/ [MDiv(5:0)+2]
-
-
-
-
SMBus Table: PLL Spread Spectrum Control Register
Byte 12
Bit 7
Pin #
Name
Control Function
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
Default
-
-
-
-
-
-
-
-
PLL SSP7
PLL SSP6
PLL SSP5
PLL SSP4
PLL SSP3
PLL SSP2
PLL SSP1
PLL SSP0
X
X
X
X
X
X
X
X
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
These Spread
Spectrum bits in
Byte 13 and 14 will
program the spread
pecentage of PLL
Spread Spectrum
Programming bit(7:0)
SMBus Table: PLL Spread Spectrum Control Register
Byte 13
Bit 7
Pin #
Name
Control Function
Reserved
Type
0
1
Default
-
-
-
-
-
-
-
-
0
X
X
X
X
X
X
X
PLL SSP14
PLL SSP13
PLL SSP12
PLL SSP11
PLL SSP10
PLL SSP9
PLL SSP8
RW
RW
RW
RW
RW
RW
RW
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
These Spread
Spectrum bits in
Byte 13 and 14 will
program the spread
pecentage of PLL
Spread Spectrum
Programming bit(14:8)
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
1680C—08/26/10
16
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
300 mil SSOP
In Millimeters
COMMON DIMENSIONS
In Inches
SYMBOL
COMMON DIMENSIONS
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
A
A1
b
.016
.0135
.010
c
D
E
SEE VARIATIONS
SEE VARIATIONS
10.03
7.40
10.68
7.60
.395
.420
.299
E1
e
.291
0.635 BASIC
0.025 BASIC
h
0.38
0.50
0.64
1.02
.015
.020
.025
.040
L
N
a
SEE VARIATIONS
SEE VARIATIONS
0°
8°
0°
8°
VARIATIONS
D mm.
D (inch)
N
MIN
MAX
MIN
.620
MAX
.630
48
15.75
16.00
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
1680C—08/26/10
17
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
c
6.10 mm. Body, 0.50 mm. Pitch TSSOP
N
(240 mil)
(20 mil)
In Millimeters
In Inches
SYMBOL
COMMON DIMENSIONS COMMON DIMENSIONS
L
MIN
--
MAX
1.20
0.15
1.05
0.27
0.20
MIN
--
MAX
.047
.006
.041
.011
.008
A
A1
A2
b
E1
E
0.05
0.80
0.17
0.09
.002
.032
.007
.0035
INDEX
AREA
c
D
E
SEE VARIATIONS
8.10 BASIC
SEE VARIATIONS
0.319 BASIC
1
2
E1
e
6.00
6.20
.236
.244
α
0.50 BASIC
0.020 BASIC
D
L
0.45
0.75
.018
.030
N
α
SEE VARIATIONS
SEE VARIATIONS
0°
--
8°
0°
--
8°
aaa
0.10
.004
A
A2
VARIATIONS
A1
D mm.
D (inch)
N
- C-
MIN
MAX
MIN
.488
MAX
.496
48
12.40
12.60
e
SEATING
PLANE
Reference Doc.: JEDEC Publication 95, M O-153
b
10-0039
aaa C
Ordering Information
Part / Order Number Shipping Packaging
Package
Temperature
0 to +70°C
9FG830AFLF
9FG830AFLFT
9FG830AFILF
9FG830AFILFT
9FG830AGLF
9FG830AGLFT
9FG830AGILF
9FG830AGILFT
Tubes
Tape and Reel
Tubes
48-pin SSOP
48-pin SSOP
48-pin SSOP
48-pin SSOP
48-pin TSSOP
48-pin TSSOP
48-pin TSSOP
48-pin TSSOP
0 to +70°C
-40 to +85°C
-40 to +85°C
0 to +70°C
Tape and Reel
Tubes
Tape and Reel
Tubes
0 to +70°C
-40 to +85°C
-40 to +85°C
Tape and Reel
“LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
“A” is the device revision designator (will not correlate with the datasheet revision).
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
1680C—08/26/10
18
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
Revision History
Rev. Originator Issue Date Rev X.3
Page #
A
7/13/2010
RDW
Initial release. Move to final
1. Added PPM tables to DS for both 25M and 14.318M inputs
2. Added Test load figures
B
7/20/2010
RDW
1. Updated/reformatted Electrical Tables
2. Corrected Features/Benefits and General Description
3. Updated termination figures to include Fig 5. for REF output
C
8/25/2010
RDW
1, Various
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www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
408-284-6578
pcclockhelp@idt.com
Corporate Headquarters
Asia Pacific and Japan
Europe
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800 345 7015
+408 284 8200 (outside U.S.)
IDT Singapore Pte. Ltd.
1 Kallang Sector #07-01/06
KolamAyer Industrial Park
Singapore 349276
Phone: 65-6-744-3356
Fax: 65-6-744-1764
IDT Europe Limited
321 Kingston Road
Leatherhead, Surrey
KT22 7TU
England
Phone: 44-1372-363339
Fax: 44-1372-378851
© 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks
are or may be trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
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